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From: Greg KH <gregkh@linuxfoundation.org>
To: shenwei.wang@nxp.com
Cc: linux-serial@vger.kernel.org
Subject: Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode
Date: Thu, 14 Jul 2022 16:32:08 +0200	[thread overview]
Message-ID: <YtAo6LNRnErheW2a@kroah.com> (raw)
In-Reply-To: <20220708195800.325933-1-shenwei.wang@nxp.com>

On Fri, Jul 08, 2022 at 02:58:00PM -0500, shenwei.wang@nxp.com wrote:
> The LPUART hardware doesn't zero out the parity bit on the received
> characters. This behavior won't impact the use cases of CS8 because
> the parity bit is the 9th bit which is not currently used by software.
> But the parity bit for CS7 must be zeroed out by software in order to
> get the correct raw data.
> 
> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>

Also, please fix your email client so that your name shows up in the
 From: line.

thanks,

greg k-h

      parent reply	other threads:[~2022-07-14 14:32 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-08 19:58 [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode shenwei.wang
2022-07-14 14:31 ` Greg KH
2022-07-14 14:53   ` [EXT] " Shenwei Wang
2022-07-14 14:31 ` Greg KH
2022-07-14 15:11   ` [EXT] " Shenwei Wang
2022-07-14 15:24     ` Greg KH
2022-07-14 15:26       ` Shenwei Wang
2022-07-14 15:30         ` Greg KH
2022-07-14 15:50           ` Shenwei Wang
2022-07-14 15:56             ` Greg KH
2022-07-14 14:32 ` Greg KH [this message]

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