[PATCH 0/2] serial: 8250_of: RS-485 on Microchip Core16550

[PATCH 0/2] serial: 8250_of: RS-485 on Microchip Core16550

[Kohei Otsuka via B4 Relay]

Core16550 is a 16550-compatible UART soft IP for Microchip FPGAs. We use
four of them in the fabric of a PolarFire SoC Icicle Kit as RS-485
ports, described as "ns16550a" with linux,rs485-enabled-at-boot-time.
With RS-485 enabled, RTS (the transceiver's driver enable) goes high at
the start of the first transmission and never drops, and the port stops
receiving. Core16550, like the original 16550A, raises no interrupt on
TEMT, so __stop_tx() waits for one forever unless the port has
UART_CAP_NOTEMT, which 8250_of never sets.

Testing, on a PolarFire SoC Icicle Kit with four Core16550 instances
on FIC3 (PCLK 50 MHz), linux-mchp 6.18.17 with this series applied,
115200 8N1, against USB-RS485 (2-wire, half duplex) and USB-RS422
(4-wire) converters:
- All four ports transmit and receive correctly with both converters.
- On RS-485, each port keeps receiving after transmitting, across
  repeated request/response exchanges in both directions.
- Without the series, RTS stays high after the first transmission and
  nothing more is received.

This series was prepared with the help of an AI coding assistant
(Claude, Anthropic): the analysis of __stop_tx(), both patches and
these messages. I reviewed and tested the result and take
responsibility for it.
Link: https://github.com/linux4microchip/meta-mchp/issues/5

Signed-off-by: Kohei Otsuka <kohei@spacemachines.com>
---
Kohei Otsuka (2):
      dt-bindings: serial: 8250: add Microchip Core16550
      serial: 8250_of: drop RS-485 RTS on Microchip Core16550

 Documentation/devicetree/bindings/serial/8250.yaml | 1 +
 drivers/tty/serial/8250/8250_of.c                  | 9 +++++++++
 2 files changed, 10 insertions(+)
---
base-commit: c339f4010dea8b0d754f84ace70cd1b089878ef8
change-id: 20261103-core16550-rs485-505af0ffaeeb

Best regards,
--  
Kohei Otsuka <kohei@spacemachines.com>

[PATCH 1/2] dt-bindings: serial: 8250: add Microchip Core16550

[Kohei Otsuka via B4 Relay]

From: Kohei Otsuka <kohei@spacemachines.com>

Core16550 is a 16550-compatible UART soft IP core for Microchip FPGAs,
including the fabric of PolarFire SoC. Its registers follow the 16550A,
so ns16550a stays the fallback, but it raises no interrupt on TEMT,
which the driver has to know about to support RS-485 on it.

Add microchip,core16550 with ns16550a as the fallback.

Link: https://github.com/linux4microchip/meta-mchp/issues/5
Signed-off-by: Kohei Otsuka <kohei@spacemachines.com>
---
 Documentation/devicetree/bindings/serial/8250.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
index 50d5c977afa3..33a5929bdaa6 100644
--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -137,6 +137,7 @@ properties:
               - ti,da830-uart
               - loongson,ls2k0500-uart
               - loongson,ls2k1500-uart
+              - microchip,core16550
           - const: ns16550a
       - items:
           - enum:

-- 
2.53.0

[PATCH 2/2] serial: 8250_of: drop RS-485 RTS on Microchip Core16550

[Kohei Otsuka via B4 Relay]

From: Kohei Otsuka <kohei@spacemachines.com>

Core16550, a 16550-compatible UART for Microchip FPGAs, interrupts on
THRE but not on TEMT. When the last character moves from the FIFO into
the shift register, the THRE interrupt calls __stop_tx(), which finds
TEMT clear and, without UART_CAP_NOTEMT, returns to wait for a TEMT
interrupt that never comes. RTS, and with it the RS-485 driver enable,
then stays asserted after the frame, and receive interrupts, disabled
for the half-duplex transmission, stay off.

Set UART_CAP_NOTEMT for nodes compatible with "microchip,core16550",
so em485 drops RTS from its stop timer one frame time (plus 1/7) after
THRE, as it does for DesignWare UARTs.

Set UART_CAP_FIFO as well: with the capabilities already non-zero,
serial8250_do_startup() no longer fills in the PORT_16550A default,
and without UART_CAP_FIFO serial8250_clear_fifos() does nothing, so
the RX FIFO is not flushed at the end of a half-duplex transmission.

Link: https://github.com/linux4microchip/meta-mchp/issues/5
Signed-off-by: Kohei Otsuka <kohei@spacemachines.com>
---
 drivers/tty/serial/8250/8250_of.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_of.c b/drivers/tty/serial/8250/8250_of.c
index b41ca604083f..2f1f505501a2 100644
--- a/drivers/tty/serial/8250/8250_of.c
+++ b/drivers/tty/serial/8250/8250_of.c
@@ -278,6 +278,15 @@ static int of_platform_serial_probe(struct platform_device *ofdev)
 	if (port8250.port.fifosize)
 		port8250.capabilities = UART_CAP_FIFO;
 
+	/*
+	 * Core16550 has no TEMT interrupt: without UART_CAP_NOTEMT the em485
+	 * code waits for one after the last THRE interrupt and never drops RTS.
+	 * Set UART_CAP_FIFO too, because a non-zero value stops
+	 * serial8250_do_startup() filling in the PORT_16550A default.
+	 */
+	if (of_device_is_compatible(ofdev->dev.of_node, "microchip,core16550"))
+		port8250.capabilities |= UART_CAP_FIFO | UART_CAP_NOTEMT;
+
 	/* Check for TX FIFO threshold & set tx_loadsz */
 	if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold",
 				  &tx_threshold) == 0) &&

-- 
2.53.0

Re: [PATCH 2/2] serial: 8250_of: drop RS-485 RTS on Microchip Core16550

[sashiko-bot]

> From: Kohei Otsuka <kohei@spacemachines.com>
> 
> Core16550, a 16550-compatible UART for Microchip FPGAs, interrupts on
> THRE but not on TEMT. When the last character moves from the FIFO into
> the shift register, the THRE interrupt calls __stop_tx(), which finds
> TEMT clear and, without UART_CAP_NOTEMT, returns to wait for a TEMT
> interrupt that never comes. RTS, and with it the RS-485 driver enable,
> then stays asserted after the frame, and receive interrupts, disabled
> for the half-duplex transmission, stay off.
> 
> Set UART_CAP_NOTEMT for nodes compatible with "microchip,core16550",
> so em485 drops RTS from its stop timer one frame time (plus 1/7) after
> THRE, as it does for DesignWare UARTs.
> 
> Set UART_CAP_FIFO as well: with the capabilities already non-zero,
> serial8250_do_startup() no longer fills in the PORT_16550A default,
> and without UART_CAP_FIFO serial8250_clear_fifos() does nothing, so
> the RX FIFO is not flushed at the end of a half-duplex transmission.
> 
> Link: https://github.com/linux4microchip/meta-mchp/issues/5
> Signed-off-by: Kohei Otsuka <kohei@spacemachines.com>

Sashiko has reviewed this patch and found no issues.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261103-core16550-rs485-v1-0-6d15ebe1e5b9@spacemachines.com?part=2

Re: [PATCH 1/2] dt-bindings: serial: 8250: add Microchip Core16550

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dt-bindings: serial: 8250: missing RTL version in microchip,core16550
--

commit de9364d94e19f22c5fdbfabf92e9c1ea40cb4c1e
Author: Kohei Otsuka <kohei@spacemachines.com>

dt-bindings: serial: 8250: add Microchip Core16550

This commit adds the microchip,core16550 compatible string with ns16550a as a
fallback to the 8250 serial Devicetree binding for the Microchip Core16550
FPGA soft IP core.

Link: https://github.com/linux4microchip/meta-mchp/issues/5

> diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
> index 50d5c977afa3d..33a5929bdaa69 100644
> --- a/Documentation/devicetree/bindings/serial/8250.yaml
> +++ b/Documentation/devicetree/bindings/serial/8250.yaml
> @@ -137,6 +137,7 @@ properties:
>                - ti,da830-uart
>                - loongson,ls2k0500-uart
>                - loongson,ls2k1500-uart
> +              - microchip,core16550

[Severity: Medium]
Should this compatible string include the RTL version suffix (for example,
microchip,core16550-rtl-vN matching the Libero Core16550 major RTL release)
rather than using an unversioned microchip,core16550 name?

Unlike hard SoC peripherals whose IP revision is fixed by an SoC-specific
compatible string, Core16550 is a synthesizable soft IP core from Microchip's
Libero catalog that can be instantiated in FPGA fabric across different chip
families and IP revisions.

Existing Microchip FPGA soft IP core bindings follow the
microchip,<ip>-rtl-v<N> naming convention:

  Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml:
    - microchip,coreqspi-rtl-v2 # FPGA QSPI
    - microchip,corespi-rtl-v5 # FPGA CoreSPI

  Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml:
    - microchip,coregpio-rtl-v3

  Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml:
    - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core

  Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml:
    - const: microchip,corepwm-rtl-v4

Other soft 16550 IP cores in Documentation/devicetree/bindings/serial/8250.yaml
also include their RTL or IP version (opencores,uart16550-rtlsvn105 and
xlnx,xps-uart16550-2.00.b). Including the RTL version suffix would keep the
binding consistent with other Microchip soft IP cores and allow software to
distinguish between revisions if behavior (such as TEMT interrupt generation
or FIFO handling) changes across RTL releases.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261103-core16550-rs485-v1-0-6d15ebe1e5b9@spacemachines.com?part=1