[PATCH 2/2] ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock

[PATCH 2/2] ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock

[Geert Uytterhoeven]

According to the datasheet, the operating clock for IIC0 is the HPP
(RT Peri) clock, not the SUB (Peri) clock. Both clocks run at the same
speed (50 Mhz).

This is consistent with IIC0 being located in the A4R PM domain, and
IIC1 in the A3SP PM domain.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm/boot/dts/r8a7740.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 20d2b56773fbf069..e2c9496c2c325a1f 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -497,7 +497,7 @@
 			clocks = <&cpg_clocks R8A7740_CLK_S>,
 				 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
 				 <&cpg_clocks R8A7740_CLK_B>,
-				 <&sub_clk>, <&sub_clk>,
+				 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
 				 <&cpg_clocks R8A7740_CLK_B>;
 			#clock-cells = <1>;
 			renesas,clock-indices = <
-- 
1.9.1

Re: [PATCH 2/2] ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock

[Simon Horman]

On Wed, Nov 05, 2014 at 11:04:34AM +0100, Geert Uytterhoeven wrote:
> According to the datasheet, the operating clock for IIC0 is the HPP
> (RT Peri) clock, not the SUB (Peri) clock. Both clocks run at the same
> speed (50 Mhz).
> 
> This is consistent with IIC0 being located in the A4R PM domain, and
> IIC1 in the A3SP PM domain.

Thanks, I have queued this up.

Re: [PATCH 2/2] ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock

[Simon Horman]

On Mon, Nov 10, 2014 at 09:57:46AM +0900, Simon Horman wrote:
> On Wed, Nov 05, 2014 at 11:04:34AM +0100, Geert Uytterhoeven wrote:
> > According to the datasheet, the operating clock for IIC0 is the HPP
> > (RT Peri) clock, not the SUB (Peri) clock. Both clocks run at the same
> > speed (50 Mhz).
> > 
> > This is consistent with IIC0 being located in the A4R PM domain, and
> > IIC1 in the A3SP PM domain.
> 
> Thanks, I have queued this up.

Hi Geert,

As this appears to be a bug fix I would like to accompany this patch with
some text describing when the problem was introduced and what its effects
are. In short a rough guide to if it should be applied to -stable. To that
end I prepared the following which I would appreciate your feedback on.

* ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock  

  This problem was introduced when clock support was added DT for the
  r8a7740 by d9ffd583bf345e2ea ("ARM: shmobile: r8a7740: add SoC clocks to
  DTS") in v3.17.

  I am not aware of any run-time effect of this problem.

Re: [PATCH 2/2] ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock

[Simon Horman]

On Wed, Nov 12, 2014 at 09:57:02AM +0900, Simon Horman wrote:
> On Mon, Nov 10, 2014 at 09:57:46AM +0900, Simon Horman wrote:
> > On Wed, Nov 05, 2014 at 11:04:34AM +0100, Geert Uytterhoeven wrote:
> > > According to the datasheet, the operating clock for IIC0 is the HPP
> > > (RT Peri) clock, not the SUB (Peri) clock. Both clocks run at the same
> > > speed (50 Mhz).
> > > 
> > > This is consistent with IIC0 being located in the A4R PM domain, and
> > > IIC1 in the A3SP PM domain.
> > 
> > Thanks, I have queued this up.
> 
> Hi Geert,
> 
> As this appears to be a bug fix I would like to accompany this patch with
> some text describing when the problem was introduced and what its effects
> are. In short a rough guide to if it should be applied to -stable. To that
> end I prepared the following which I would appreciate your feedback on.
> 
> * ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock  
> 
>   This problem was introduced when clock support was added DT for the
>   r8a7740 by d9ffd583bf345e2ea ("ARM: shmobile: r8a7740: add SoC clocks to
>   DTS") in v3.17.

s/v3.17/v3.18-rc1/

>   I am not aware of any run-time effect of this problem.

Re: [PATCH 2/2] ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock

[Geert Uytterhoeven]

Hi Simon,

On Wed, Nov 12, 2014 at 3:25 AM, Simon Horman <horms@verge.net.au> wrote:
> On Wed, Nov 12, 2014 at 09:57:02AM +0900, Simon Horman wrote:
>> On Mon, Nov 10, 2014 at 09:57:46AM +0900, Simon Horman wrote:
>> > On Wed, Nov 05, 2014 at 11:04:34AM +0100, Geert Uytterhoeven wrote:
>> > > According to the datasheet, the operating clock for IIC0 is the HPP
>> > > (RT Peri) clock, not the SUB (Peri) clock. Both clocks run at the same
>> > > speed (50 Mhz).
>> > >
>> > > This is consistent with IIC0 being located in the A4R PM domain, and
>> > > IIC1 in the A3SP PM domain.
>>
>> As this appears to be a bug fix I would like to accompany this patch with
>> some text describing when the problem was introduced and what its effects
>> are. In short a rough guide to if it should be applied to -stable. To that
>> end I prepared the following which I would appreciate your feedback on.
>>
>> * ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock
>>
>>   This problem was introduced when clock support was added DT for the
>>   r8a7740 by d9ffd583bf345e2ea ("ARM: shmobile: r8a7740: add SoC clocks to
>>   DTS") in v3.17.
>
> s/v3.17/v3.18-rc1/

Correct, thanks!

>>   I am not aware of any run-time effect of this problem.

Indeed. Both clocks run at the same frequency, and TTBOMK the HPP clock
cannot be disabled (is that correct?), so the IIC0 clock cannot be inadvertently
be disabled because the common part is disabled through another clock.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/2] ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock

[Geert Uytterhoeven]

On Wed, Nov 12, 2014 at 10:09 AM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>>>   I am not aware of any run-time effect of this problem.
>
> Indeed. Both clocks run at the same frequency, and TTBOMK the HPP clock
> cannot be disabled (is that correct?), so the IIC0 clock cannot be inadvertently
> be disabled because the common part is disabled through another clock.

I have to correct myself: this patch does fix something visible.
With CONFIG_DEBUG_LL=y, there's no longer a periof of garbage output
on the serial console, when the i2c driver disables the IIC0 clock.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[GIT PULL] Renesas ARM Based SoC DT Fixes for v3.18

[Simon Horman]

Hi Olof, Hi Kevin, Hi Arnd,

Please consider these Renesas ARM based SoC DT fixes for v3.18.
Or alternatively for v3.19 if you feel they are too late for v3.18.


* ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock

  This problem was introduced when clock support was added DT for the
  r8a7740 by d9ffd583bf345e2ea ("ARM: shmobile: r8a7740: add SoC clocks to
  DTS") in v3.18-rc1.

  I am not aware of any run-time effect of this problem.

* ARM: shmobile: r8a7790: Fix SD3CKCR address to device tree

  This problem was introduced when clock support was added DT for the
  r8a7790 by 22a1f59547e1e63cd ("ARM: shmobile: r8a7790: Add clocks")
  in v3.13.

  As there is no SD card slot for SDHI3 on the lager board there is no
  run-time effect of this problem on boards supported in mainline.


The following changes since commit f114040e3ea6e07372334ade75d1ee0775c355e1:

  Linux 3.18-rc1 (2014-10-19 18:08:38 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-dt-fixes-for-v3.18

for you to fetch changes up to b89ff7c3c2dee189489a5f45eb8d72e106179299:

  ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock (2014-11-10 09:56:01 +0900)

----------------------------------------------------------------
Renesas ARM Based SoC DT Fixes for v3.18

* Correct IIC0 parent clock on r8a7740
* Correct SD3CKCR address to device tree on r8a7790

----------------------------------------------------------------
Geert Uytterhoeven (1):
      ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock

Shinobu Uehara (1):
      ARM: shmobile: r8a7790: Fix SD3CKCR address to device tree

 arch/arm/boot/dts/r8a7740.dtsi | 2 +-
 arch/arm/boot/dts/r8a7790.dtsi | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

[PATCH 2/2] ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock

[Simon Horman]

From: Geert Uytterhoeven <geert+renesas@glider.be>

According to the datasheet, the operating clock for IIC0 is the HPP
(RT Peri) clock, not the SUB (Peri) clock. Both clocks run at the same
speed (50 Mhz).

This is consistent with IIC0 being located in the A4R PM domain, and
IIC1 in the A3SP PM domain.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm/boot/dts/r8a7740.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index d46c213..eed697a 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -433,7 +433,7 @@
 			clocks = <&cpg_clocks R8A7740_CLK_S>,
 				 <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
 				 <&cpg_clocks R8A7740_CLK_B>,
-				 <&sub_clk>, <&sub_clk>,
+				 <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
 				 <&cpg_clocks R8A7740_CLK_B>;
 			#clock-cells = <1>;
 			renesas,clock-indices = <
-- 
2.1.1