* [PATCH 02/08] clocksource: sh_cmt: Initialize 'max_match_value' and 'lock' in sh_cmt_setup()
From: Magnus Damm @ 2012-12-14 5:53 UTC (permalink / raw)
To: linux-kernel
Cc: linux-sh, johnstul, horms, shinya.kuribayashi.px, Magnus Damm,
tglx
In-Reply-To: <20121214055323.10081.12056.sendpatchset@w520>
From: Magnus Damm <damm@opensource.se>
Move the setup of spinlock and max_match_value to sh_cmt_setup().
There's no need to defer those steps until sh_cmt_register().
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
---
drivers/clocksource/sh_cmt.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--- 0002/drivers/clocksource/sh_cmt.c
+++ work/drivers/clocksource/sh_cmt.c 2012-12-14 12:52:35.000000000 +0900
@@ -625,14 +625,6 @@ static int sh_cmt_register(struct sh_cmt
unsigned long clockevent_rating,
unsigned long clocksource_rating)
{
- if (p->width = (sizeof(p->max_match_value) * 8))
- p->max_match_value = ~0;
- else
- p->max_match_value = (1 << p->width) - 1;
-
- p->match_value = p->max_match_value;
- raw_spin_lock_init(&p->lock);
-
if (clockevent_rating)
sh_cmt_register_clockevent(p, name, clockevent_rating);
@@ -703,6 +695,14 @@ static int sh_cmt_setup(struct sh_cmt_pr
p->clear_bits = ~0xc000;
}
+ if (p->width = (sizeof(p->max_match_value) * 8))
+ p->max_match_value = ~0;
+ else
+ p->max_match_value = (1 << p->width) - 1;
+
+ p->match_value = p->max_match_value;
+ raw_spin_lock_init(&p->lock);
+
ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev),
cfg->clockevent_rating,
cfg->clocksource_rating);
^ permalink raw reply
* [PATCH 01/08] clocksource: sh_cmt: Take care of clk_put() when setup_irq() fails
From: Magnus Damm @ 2012-12-14 5:53 UTC (permalink / raw)
To: linux-kernel
Cc: linux-sh, johnstul, horms, shinya.kuribayashi.px, tglx,
Magnus Damm
In-Reply-To: <20121214055323.10081.12056.sendpatchset@w520>
From: Magnus Damm <damm@opensource.se>
Make sure clk_put() is called in case of failure in sh_cmt_setup().
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
---
drivers/clocksource/sh_cmt.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
--- 0001/drivers/clocksource/sh_cmt.c
+++ work/drivers/clocksource/sh_cmt.c 2012-12-14 12:50:02.000000000 +0900
@@ -708,17 +708,19 @@ static int sh_cmt_setup(struct sh_cmt_pr
cfg->clocksource_rating);
if (ret) {
dev_err(&p->pdev->dev, "registration failed\n");
- goto err1;
+ goto err2;
}
p->cs_enabled = false;
ret = setup_irq(irq, &p->irqaction);
if (ret) {
dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
- goto err1;
+ goto err2;
}
return 0;
+err2:
+ clk_put(p->clk);
err1:
iounmap(p->mapbase);
^ permalink raw reply
* [PATCH 00/08] clocksource: sh_cmt: CMT driver update
From: Magnus Damm @ 2012-12-14 5:53 UTC (permalink / raw)
To: linux-kernel
Cc: linux-sh, johnstul, horms, shinya.kuribayashi.px, Magnus Damm,
tglx
clocksource: sh_cmt: CMT driver update
[PATCH 01/08] clocksource: sh_cmt: Take care of clk_put() when setup_irq() fails
[PATCH 02/08] clocksource: sh_cmt: Initialize 'max_match_value' and 'lock' in sh_cmt_setup()
[PATCH 03/08] clocksource: sh_cmt: Consolidate platform_set_drvdata() call
[PATCH 04/08] clocksource: sh_cmt: Introduce per-register functions
[PATCH 05/08] clocksource: sh_cmt: CMSTR and CMCSR register access update
[PATCH 06/08] clocksource: sh_cmt: CMCNT and CMCOR register access update
[PATCH 07/08] clocksource: sh_cmt: Add control register callbacks
[PATCH 08/08] clocksource: sh_cmt: Add CMT register layout comment
This patch series contains a couple of driver updates from Kuribayashi-san
together with some register access changes from me. The register access
changes work towards adding support for 32-bit only CMT hardware, but
the final bits are not yet included in this series due to lack of hardware.
Patches 1-3:
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Signed-off-by: Magnus Damm <damm@opensource.se>
Patches 4-8:
Signed-off-by: Magnus Damm <damm@opensource.se>
---
drivers/clocksource/sh_cmt.c | 257 ++++++++++++++++++++++++------------------
1 file changed, 152 insertions(+), 105 deletions(-)
^ permalink raw reply
* [PATCH] ARM: mach-shmobile: sh73a0 external IRQ wake update
From: Magnus Damm @ 2012-12-14 3:43 UTC (permalink / raw)
To: linux-sh
From: Magnus Damm <damm@opensource.se>
Use sh73a0_set_wake() for external IRQ signals on sh73a0.
The sh73a0 IRQ hardware for external IRQ pins consists of
the INTCA interrupt controller and the GIC together doing
their best to limp along. These external IRQ pins are
treated as a special case where interrupts need to be
managed in both interrupt controllers in parallel.
The ->irq_set_wake() callback for the external IRQ pins
can be dealt with in the same way as INTCA-only without
involving the GIC. So this patch updates the external
IRQ pin code for sh73a0 to no longer involve the GIC.
Signed-off-by: Magnus Damm <damm@opensource.se>
---
arch/arm/mach-shmobile/intc-sh73a0.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
--- 0001/arch/arm/mach-shmobile/intc-sh73a0.c
+++ work/arch/arm/mach-shmobile/intc-sh73a0.c 2012-12-14 12:29:17.000000000 +0900
@@ -315,11 +315,6 @@ static int intca_gic_set_type(struct irq
return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
}
-static int intca_gic_set_wake(struct irq_data *data, unsigned int on)
-{
- return irq_cbp(irq_set_wake, to_intca_reloc_irq(data), on);
-}
-
#ifdef CONFIG_SMP
static int intca_gic_set_affinity(struct irq_data *data,
const struct cpumask *cpumask,
@@ -339,7 +334,7 @@ struct irq_chip intca_gic_irq_chip = {
.irq_disable = intca_gic_disable,
.irq_shutdown = intca_gic_disable,
.irq_set_type = intca_gic_set_type,
- .irq_set_wake = intca_gic_set_wake,
+ .irq_set_wake = sh73a0_set_wake,
#ifdef CONFIG_SMP
.irq_set_affinity = intca_gic_set_affinity,
#endif
^ permalink raw reply
* Re: [PATCH 1/2] ARM: shmobile: sh73a0: Add CPU sleep suspend
From: Magnus Damm @ 2012-12-14 3:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1354709587-25288-1-git-send-email-hechtb+renesas@gmail.com>
On Wed, Dec 5, 2012 at 9:13 PM, Bastian Hecht <hechtb@gmail.com> wrote:
> From: Bastian Hecht <hechtb@gmail.com>
>
> Add the lighest possible sleep mode on Cortex-A9 cores: CPU sleep. It is
> entered by a simple dsb and wfi instruction via cpu_do_idle(). As just
> clocks are stopped there is no need to save or restore any state of the
> system.
>
> Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Acked-by: Magnus Damm <damm@opensource.se>
^ permalink raw reply
* Re: [PATCH 2/2] ARM: shmobile: r8a7740: Add CPU sleep suspend
From: Magnus Damm @ 2012-12-14 3:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1354709587-25288-2-git-send-email-hechtb+renesas@gmail.com>
On Wed, Dec 5, 2012 at 9:13 PM, Bastian Hecht <hechtb@gmail.com> wrote:
> From: Bastian Hecht <hechtb@gmail.com>
>
> Add the lighest possible sleep mode on Cortex-A9 cores: CPU sleep.
> It is entered by a simple dsb and wfi instruction via cpu_do_idle(). As
> just clocks are stopped there is no need to save or restore any state of
> the system.
>
> Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Acked-by: Magnus Damm <damm@opensource.se>
^ permalink raw reply
* Re: [PATCH 2/2] ARM: SH-Mobile: sh73a0: Add CPU Hotplug
From: Magnus Damm @ 2012-12-14 3:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1354795719-5578-2-git-send-email-hechtb+renesas@gmail.com>
On Thu, Dec 6, 2012 at 9:08 PM, Bastian Hecht <hechtb@gmail.com> wrote:
> From: Bastian Hecht <hechtb@gmail.com>
>
> Add the capability to add and remove CPUs on the fly.
> The Cortex-A9 offers the possibility to take single cores out of the
> MP Core. We add this capabilty taking care that caches are kept
> coherent. For the actual shutdown via a WFI instruction, a code snippet
> from the omap2 code tree is copied. Thanks for that! For verifying the
> shutdown we rely on the internal SH73A0 Power Status Register
> PSTR.
>
> Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Acked-by: Magnus Damm <damm@opensource.se>
^ permalink raw reply
* Re: [PATCH 1/2] ARM: SH-Mobile: sh73a0: Secondary CPUs handle own SCU flags
From: Magnus Damm @ 2012-12-14 3:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1354795719-5578-1-git-send-email-hechtb+renesas@gmail.com>
On Thu, Dec 6, 2012 at 9:08 PM, Bastian Hecht <hechtb@gmail.com> wrote:
> From: Bastian Hecht <hechtb@gmail.com>
>
> When booting secondary CPUs we have used the main CPU to set up the
> Snoop Control Unit flags of these CPUs. It is a cleaner approach
> if every CPU takes care of its own flags. We avoid the need for
> locking and the program logic is more concise. With this patch the file
> headsmp-sh73a0.S is added that contains a startup vector for secondary CPUs
> that sets up its own SCU flags.
> Further in sh73a0_smp_prepare_cpus() we can rely on the generic ARM helper
> scu_power_mode(). This is possible as we don't cross borders anymore (every
> CPU handles its own flags) and need no locking. So we can throw out the
> needless function modify_scu_cpu_psr().
>
> Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com>
Acked-by: Magnus Damm <damm@opensource.se>
^ permalink raw reply
* Re: [PATCH] ARM: shmobile: sh73a0: fixup div4_clks bitmap
From: Simon Horman @ 2012-12-14 0:57 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <87ehj5nuip.wl%kuninori.morimoto.gx@renesas.com>
On Tue, Dec 04, 2012 at 05:43:29PM -0800, Kuninori Morimoto wrote:
> div4_clks's bitmap of sh73a0 was wrong.
> This patch is based on v2.0 datasheet.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks applied.
I have applied this to a temporary 'soc5' branch which is based on 3.7-rc1.
I will rebase this on 3.8-rc1 once it is released and rename the branch
to the more sane 'soc'.
I have also merged this change into the next branch.
^ permalink raw reply
* Re: [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations
From: Will Deacon @ 2012-12-13 14:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <Pine.LNX.4.64.1212131522430.18586@axis700.grange>
On Thu, Dec 13, 2012 at 02:32:46PM +0000, Guennadi Liakhovetski wrote:
> On Thu, 13 Dec 2012, Will Deacon wrote:
>
> > On Thu, Dec 13, 2012 at 08:09:33AM +0000, Guennadi Liakhovetski wrote:
> > > On Wed, 12 Dec 2012, Will Deacon wrote:
> > > > Back to the case in hand.... Lorenzo just pointed out to me that the
> > > > finished in question (sh7372_do_idle_sysc) calls v7_flush_dcache_all, so
> > > > the louis stuff should be irrelevant. The problem may actually be that the
> > > > finisher disables the L2 cache prior to cleaning/invalidating it, which is
> > > > the opposite order to that described by the A8 TRM.
> > > >
> > > > Guennadi -- can you try moving the kernel_flush call before the L2 disable
> > > > in sh7372_do_idle_sysc please?
> > >
> > > Yes, this works too.
> >
> > That's good to know. Please can you send a patch for that? The sequence
> > currently being used by the finisher *is* buggy, and should be fixed
> > independently of the louis stuff.
>
> Well, the fix is yours, so, it should be "From: you." I can certainly send
> it just copying your description above, but I'd also need your Sob.
> Something like the below (feel free to improve the subject line and the
> description):
No, I didn't send any code for this so you should be the author. I can
review/possibly ack it if you like (please send a v2 addressing Santosh's
comments).
Will
^ permalink raw reply
* Re: [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations
From: Santosh Shilimkar @ 2012-12-13 14:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <Pine.LNX.4.64.1212131522430.18586@axis700.grange>
On Thursday 13 December 2012 03:32 PM, Guennadi Liakhovetski wrote:
> On Thu, 13 Dec 2012, Will Deacon wrote:
>
>> On Thu, Dec 13, 2012 at 08:09:33AM +0000, Guennadi Liakhovetski wrote:
>>> On Wed, 12 Dec 2012, Will Deacon wrote:
>>>> Back to the case in hand.... Lorenzo just pointed out to me that the
>>>> finished in question (sh7372_do_idle_sysc) calls v7_flush_dcache_all, so
>>>> the louis stuff should be irrelevant. The problem may actually be that the
>>>> finisher disables the L2 cache prior to cleaning/invalidating it, which is
>>>> the opposite order to that described by the A8 TRM.
>>>>
>>>> Guennadi -- can you try moving the kernel_flush call before the L2 disable
>>>> in sh7372_do_idle_sysc please?
>>>
>>> Yes, this works too.
>>
>> That's good to know. Please can you send a patch for that? The sequence
>> currently being used by the finisher *is* buggy, and should be fixed
>> independently of the louis stuff.
>
> Well, the fix is yours, so, it should be "From: you." I can certainly send
> it just copying your description above, but I'd also need your Sob.
> Something like the below (feel free to improve the subject line and the
> description):
>
> From: Will Deacon <will.deacon@arm.com>
> Subject: [PATCH] ARM: sh7372: fix cache clean / invalidate order
>
> According to the Cortex A8 TRM the L2 cache should be first cleaned and
> then disabled. Fix the swapped order on sh7372.
>
> Signed-off-by: <you>
> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
> (or even just)
> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
>
> diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
> index 1d56467..df15d8a 100644
> --- a/arch/arm/mach-shmobile/sleep-sh7372.S
> +++ b/arch/arm/mach-shmobile/sleep-sh7372.S
> @@ -59,16 +59,16 @@ sh7372_do_idle_sysc:
> mcr p15, 0, r0, c1, c0, 0
> isb
>
> - /* disable L2 cache in the aux control register */
> - mrc p15, 0, r10, c1, c0, 1
> - bic r10, r10, #2
> - mcr p15, 0, r10, c1, c0, 1
> -
> /*
> * Invalidate data cache again.
> */
kernel_flush does "Clean and Invalidate"
> ldr r1, kernel_flush
> blx r1
> +
> + /* disable L2 cache in the aux control register */
> + mrc p15, 0, r10, c1, c0, 1
> + bic r10, r10, #2
> + mcr p15, 0, r10, c1, c0, 1
An isb will be make it safe.
Otherwise patch looks good to me.
Feel free to add my review-by tag if you need one.
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
^ permalink raw reply
* Re: [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations
From: Guennadi Liakhovetski @ 2012-12-13 14:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121213105109.GB26540@mudshark.cambridge.arm.com>
On Thu, 13 Dec 2012, Will Deacon wrote:
> On Thu, Dec 13, 2012 at 08:09:33AM +0000, Guennadi Liakhovetski wrote:
> > On Wed, 12 Dec 2012, Will Deacon wrote:
> > > Back to the case in hand.... Lorenzo just pointed out to me that the
> > > finished in question (sh7372_do_idle_sysc) calls v7_flush_dcache_all, so
> > > the louis stuff should be irrelevant. The problem may actually be that the
> > > finisher disables the L2 cache prior to cleaning/invalidating it, which is
> > > the opposite order to that described by the A8 TRM.
> > >
> > > Guennadi -- can you try moving the kernel_flush call before the L2 disable
> > > in sh7372_do_idle_sysc please?
> >
> > Yes, this works too.
>
> That's good to know. Please can you send a patch for that? The sequence
> currently being used by the finisher *is* buggy, and should be fixed
> independently of the louis stuff.
Well, the fix is yours, so, it should be "From: you." I can certainly send
it just copying your description above, but I'd also need your Sob.
Something like the below (feel free to improve the subject line and the
description):
From: Will Deacon <will.deacon@arm.com>
Subject: [PATCH] ARM: sh7372: fix cache clean / invalidate order
According to the Cortex A8 TRM the L2 cache should be first cleaned and
then disabled. Fix the swapped order on sh7372.
Signed-off-by: <you>
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
(or even just)
Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
index 1d56467..df15d8a 100644
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -59,16 +59,16 @@ sh7372_do_idle_sysc:
mcr p15, 0, r0, c1, c0, 0
isb
- /* disable L2 cache in the aux control register */
- mrc p15, 0, r10, c1, c0, 1
- bic r10, r10, #2
- mcr p15, 0, r10, c1, c0, 1
-
/*
* Invalidate data cache again.
*/
ldr r1, kernel_flush
blx r1
+
+ /* disable L2 cache in the aux control register */
+ mrc p15, 0, r10, c1, c0, 1
+ bic r10, r10, #2
+ mcr p15, 0, r10, c1, c0, 1
/*
* The kernel doesn't interwork: v7_flush_dcache_all in particluar will
* always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
^ permalink raw reply related
* Re: [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations
From: Will Deacon @ 2012-12-13 10:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <Pine.LNX.4.64.1212130909190.18586@axis700.grange>
On Thu, Dec 13, 2012 at 08:09:33AM +0000, Guennadi Liakhovetski wrote:
> On Wed, 12 Dec 2012, Will Deacon wrote:
> > Back to the case in hand.... Lorenzo just pointed out to me that the
> > finished in question (sh7372_do_idle_sysc) calls v7_flush_dcache_all, so
> > the louis stuff should be irrelevant. The problem may actually be that the
> > finisher disables the L2 cache prior to cleaning/invalidating it, which is
> > the opposite order to that described by the A8 TRM.
> >
> > Guennadi -- can you try moving the kernel_flush call before the L2 disable
> > in sh7372_do_idle_sysc please?
>
> Yes, this works too.
That's good to know. Please can you send a patch for that? The sequence
currently being used by the finisher *is* buggy, and should be fixed
independently of the louis stuff.
Cheers,
Will
^ permalink raw reply
* Re: [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations
From: Guennadi Liakhovetski @ 2012-12-13 8:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121212133650.GJ6195@mudshark.cambridge.arm.com>
On Wed, 12 Dec 2012, Will Deacon wrote:
> On Wed, Dec 12, 2012 at 10:33:38AM +0000, Lorenzo Pieralisi wrote:
> > On Tue, Dec 11, 2012 at 11:27:39PM +0000, Stephen Boyd wrote:
> > > On 12/11/12 08:38, Will Deacon wrote:
> > > > diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> > > > index cd95664..f58248f 100644
> > > > --- a/arch/arm/mm/cache-v7.S
> > > > +++ b/arch/arm/mm/cache-v7.S
> > > > @@ -44,7 +44,8 @@ ENDPROC(v7_flush_icache_all)
> > > > ENTRY(v7_flush_dcache_louis)
> > > > dmb @ ensure ordering with previous memory accesses
> > > > mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
> > > > - ands r3, r0, #0xe00000 @ extract LoUIS from clidr
> > > > + ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr
> > > > + ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr
> > > > mov r3, r3, lsr #20 @ r3 = LoUIS * 2
> > >
> > > You need to fix this mov as well, right?
> >
> > And after doing that I think the suspend finisher will still have
> > to call flush_cache_all() since LoUU = 1 on A8, L2 is not cleaned
> > and that's probably what we want if it can be retained.
>
> At some point we probably want to describe the level of flushing required in
> the device tree as a property of the CPU node (or something similar). That
> would allow us to have *one* function for flushing,
> e.g. cpu_suspend_flush_cache which flushes to the appropriate level. Then
> we could remove the louis flush from the CPU suspend code and instead make
> it the finisher's responsibility to call our flushing function when it's
> done, which helps to avoid over/under-flushing the cache.
>
> In the meantime, fixing louis as we've suggested should work.
>
> Back to the case in hand.... Lorenzo just pointed out to me that the
> finished in question (sh7372_do_idle_sysc) calls v7_flush_dcache_all, so
> the louis stuff should be irrelevant. The problem may actually be that the
> finisher disables the L2 cache prior to cleaning/invalidating it, which is
> the opposite order to that described by the A8 TRM.
>
> Guennadi -- can you try moving the kernel_flush call before the L2 disable
> in sh7372_do_idle_sysc please?
Yes, this works too.
Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
^ permalink raw reply
* Re: [PATCH] ARM: shmobile: r8a7740: add TMU timer support
From: Simon Horman @ 2012-12-13 1:29 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <871uevinw9.wl%kuninori.morimoto.gx@renesas.com>
On Wed, Dec 12, 2012 at 02:08:09AM -0800, Kuninori Morimoto wrote:
> This patch enabled TMU0 timer on r8a7740.
> But TMU1 timer is not supported yet
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks applied.
I have applied this to a temporary 'soc5' branch which is based on 3.7-rc1.
I will rebase this on 3.8-rc1 once it is released and rename the branch
to the more sane 'soc'.
I have also merged this change into the next branch.
^ permalink raw reply
* Re: [PATCH v2 00/77] SH pin control and GPIO rework with OF support
From: Simon Horman @ 2012-12-13 0:55 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <1353974596-30033-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com>
On Wed, Dec 12, 2012 at 02:43:24AM +0100, Laurent Pinchart wrote:
> Hi Linus,
>
> On Friday 07 December 2012 19:35:33 Laurent Pinchart wrote:
> > On Thursday 06 December 2012 02:34:39 Laurent Pinchart wrote:
> > > On Saturday 01 December 2012 23:55:35 Linus Walleij wrote:
> > > > On Tue, Nov 27, 2012 at 1:01 AM, Laurent Pinchart wrote:
> > > > > Here's the second version of the SH pin control and GPIO rework
> > > > > patches.
> > > > > I've added OF support for PFC instantiation and GPIO mappings that was
> > > > > missing from v1. PINCTRL bindings are still missing and will come
> > > > > soon.
> > > >
> > > > So I've tried the only way I could to review this by cloning your tree
> > > > and actually inspecting the end result ... overall it's looking very
> > > > good!
> >
> > > > Here are assorted comments:
> > [snip]
> >
> > > > - You're using the method to add ranges from the pinctrl side of
> > > > things. This is basically deprecated with the changes to gpiolib
> > > > I make in this merge window. If you study the way I changed
> > > > the pinctrl-u300.c and pinctrl-coh901.c to switch the registration
> > > > from being done in the pin controller to being done in the
> > > > gpiolib part, you will get the picture. The big upside is that
> > > > (A) makes the pin and GPIO references to the local GPIO
> > > > chip and pin controller and (B) that this supports adding ranges
> > > > from the device tree, which is probably what you want in the
> > > > end...
> > >
> > > OK, I will have a look at the code.
> >
> > Do you have a tree with those patches ?
>
> I should have looked myself for the tree before asking, sorry. I'll have a
> look at the changes you've added there and will rework the PFC driver
> accordingly.
>
> I will send a v3 with fixes based on your comments. I might omit the DT
> patches this time and send a pull request, as the patch set is getting too big
> for my taste. Even though the result won't be perfect (yet :-)), it's still an
> improvement, and I'll send additional patches on top of that.
FWIW, I am quite comfortable with this approach.
>
> > > > - This stuff in setup_data_regs():
> > > > rp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg, drp->reg_width);
> > > >
> > > > You know, I think shadow registers is just another name for
> > > > regmap-mmio. Please consult drivers/base/regmap/regmap-mmio.c and
> > > > tell me if I'm wrong. It's not like I'm going to require you to
> > > > convert this to regmap from day 1 if this is legacy stuff but it's
> > > > probably the same thing.
> > >
> > > I'll have a look at it.
> >
> > I've considered regmap but I think it's a bit overkill. True, the reg_shadow
> > is a different name for regmap-mmio (or rather for a small subset of it),
> > but I already have a data structure instance for each register due to other
> > requirements of the driver, so storing the cached value there is pretty
> > much free.
> >
> > I might end up reworking the data registers related code in which case I
> > will try to use regmap.
>
> --
> Regards,
>
> Laurent Pinchart
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH] ARM: clocksource: Initialise early (repost)
From: Simon Horman @ 2012-12-13 0:46 UTC (permalink / raw)
To: linux-arm-kernel
Initialise clock sources early, since some subsystems rely on them to initialize
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
Repost to add LKML to CC list.
v3
* Initial post
---
drivers/Makefile | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/Makefile b/drivers/Makefile
index a16a8d0..eba9b58 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -37,6 +37,11 @@ obj-$(CONFIG_XEN) += xen/
# regulators early, since some subsystems rely on them to initialize
obj-$(CONFIG_REGULATOR) += regulator/
+# clocksource early, since some subsystems rely on them to initialize
+ifndef CONFIG_ARCH_USES_GETTIMEOFFSET
+obj-y += clocksource/
+endif
+
# tty/ comes before char/ so that the VT console is the boot-time
# default.
obj-y += tty/
@@ -114,9 +119,6 @@ obj-y += firmware/
obj-$(CONFIG_CRYPTO) += crypto/
obj-$(CONFIG_SUPERH) += sh/
obj-$(CONFIG_ARCH_SHMOBILE) += sh/
-ifndef CONFIG_ARCH_USES_GETTIMEOFFSET
-obj-y += clocksource/
-endif
obj-$(CONFIG_DCA) += dca/
obj-$(CONFIG_HID) += hid/
obj-$(CONFIG_PPC_PS3) += ps3/
--
1.7.10.4
^ permalink raw reply related
* Re: [PATCH 1/6] ARM: clocksource: Initialise early
From: Simon Horman @ 2012-12-13 0:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <19362966.Oyuy1aUOFc@avalon>
On Tue, Dec 11, 2012 at 01:51:27PM +0100, Laurent Pinchart wrote:
> Hi Simon,
>
> Thanks for the patch.
>
> Could you please CC LKML on this one ? It targets a wider audience than the
> SH-specific patches.
Sure, good thinking.
>
> On Tuesday 11 December 2012 12:07:29 Simon Horman wrote:
> > Initialise clock sources early, since some subsystems rely on them to
> > initialize
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> >
> > ---
> >
> > v3
> > * Initial post
> > ---
> > drivers/Makefile | 8 +++++---
> > 1 file changed, 5 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/Makefile b/drivers/Makefile
> > index a16a8d0..eba9b58 100644
> > --- a/drivers/Makefile
> > +++ b/drivers/Makefile
> > @@ -37,6 +37,11 @@ obj-$(CONFIG_XEN) += xen/
> > # regulators early, since some subsystems rely on them to initialize
> > obj-$(CONFIG_REGULATOR) += regulator/
> >
> > +# clocksource early, since some subsystems rely on them to initialize
> > +ifndef CONFIG_ARCH_USES_GETTIMEOFFSET
> > +obj-y += clocksource/
> > +endif
> > +
> > # tty/ comes before char/ so that the VT console is the boot-time
> > # default.
> > obj-y += tty/
> > @@ -114,9 +119,6 @@ obj-y += firmware/
> > obj-$(CONFIG_CRYPTO) += crypto/
> > obj-$(CONFIG_SUPERH) += sh/
> > obj-$(CONFIG_ARCH_SHMOBILE) += sh/
> > -ifndef CONFIG_ARCH_USES_GETTIMEOFFSET
> > -obj-y += clocksource/
> > -endif
> > obj-$(CONFIG_DCA) += dca/
> > obj-$(CONFIG_HID) += hid/
> > obj-$(CONFIG_PPC_PS3) += ps3/
> --
> Regards,
>
> Laurent Pinchart
>
^ permalink raw reply
* Re: [PATCH v2] ARM: shmobile: r8a7779: Fix GPIO input reg addresses
From: Simon Horman @ 2012-12-13 0:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <OF613746CC.4E3EB4D0-ON80257AD2.0038052F-80257AD2.00381232@eu.necel.com>
On Wed, Dec 12, 2012 at 10:12:27AM +0000, phil.edworthy@renesas.com wrote:
> Hi Simon, Laurent,
>
> (resend as plain text)
>
> > From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > To: Phil Edworthy <phil.edworthy@renesas.com>,
> > Cc: Simon <horms@verge.net.au>, linux-sh@vger.kernel.org, linux-arm-
> > kernel@lists.infradead.org, Magnus <magnus.damm@gmail.com>, Laurent
> > Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> > Date: 11/12/2012 11:39
> > Subject: Re: [PATCH v2] ARM: shmobile: r8a7779: Fix GPIO input reg
> addresses
> >
> > On Tuesday 11 December 2012 11:34:17 Phil Edworthy wrote:
> > > The INDTx register addresses were wrong.
> > >
> > > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> >
> > You can add
> >
> > Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>
> Please scrap this patch. I just found out that it screws up the GPIO
> outputs. The current code assumes the same register is used for both input
> and output, which is not the case. It needs a bit of work to fix this.
Thanks, I have marked v1 and v2 as Rejected in patchwork.
^ permalink raw reply
* Re: [PATCH] ARM: shmobile: sh73a0: fixup div4_clks bitmap
From: Simon Horman @ 2012-12-13 0:17 UTC (permalink / raw)
To: linux-sh
In-Reply-To: <87ehj5nuip.wl%kuninori.morimoto.gx@renesas.com>
On Tue, Dec 04, 2012 at 05:43:29PM -0800, Kuninori Morimoto wrote:
> div4_clks's bitmap of sh73a0 was wrong.
> This patch is based on v2.0 datasheet.
Magnus, could you check this?
Or alternatively, could someone point me to the appropriate
pages of the data sheet?
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> ---
> arch/arm/mach-shmobile/clock-sh73a0.c | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
> index 516ff7f..5f57701 100644
> --- a/arch/arm/mach-shmobile/clock-sh73a0.c
> +++ b/arch/arm/mach-shmobile/clock-sh73a0.c
> @@ -264,17 +264,17 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
> SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
>
> static struct clk div4_clks[DIV4_NR] = {
> - [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
> - [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
> - [DIV4_M3] = DIV4(FRQCRA, 12, 0xfff, CLK_ENABLE_ON_INIT),
> - [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
> - [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
> - [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
> - [DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0),
> - [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0),
> - [DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0),
> - [DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0),
> - [DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0),
> + [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
> + [DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
> + [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
> + [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
> + [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
> + [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
> + [DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0),
> + [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
> + [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
> + [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
> + [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0),
> };
>
> enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [TRIVIAL PATCH 13/26] sh: Convert print_symbol to %pSR
From: Joe Perches @ 2012-12-12 18:19 UTC (permalink / raw)
To: Jiri Kosina; +Cc: Paul Mundt, linux-sh, linux-kernel
In-Reply-To: <cover.1355335227.git.joe@perches.com>
Use the new vsprintf extension to avoid any possible
message interleaving.
Signed-off-by: Joe Perches <joe@perches.com>
---
arch/sh/kernel/process_32.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index 73eb66f..a0837ba 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -38,8 +38,8 @@ void show_regs(struct pt_regs * regs)
(int)strcspn(init_utsname()->version, " "),
init_utsname()->version);
- print_symbol("PC is at %s\n", instruction_pointer(regs));
- print_symbol("PR is at %s\n", regs->pr);
+ printk("PC is at %pSR\n", (void *)instruction_pointer(regs));
+ printk("PR is at %pSR\n", (void *)regs->pr);
printk("PC : %08lx SP : %08lx SR : %08lx ",
regs->pc, regs->regs[15], regs->sr);
--
1.7.8.112.g3fd21
^ permalink raw reply related
* [TRIVIAL PATCH 00/26] treewide: Add and use vsprintf extension %pSR
From: Joe Perches @ 2012-12-12 18:18 UTC (permalink / raw)
To: linux-arm-kernel
Remove the somewhat awkward uses of print_symbol and convert all the
existing uses to a new vsprintf pointer type of %pSR.
print_symbol can be interleaved when it is used in a sequence like:
printk("something: ...");
print_symbol("%s", addr);
printk("\n");
Instead use:
printk("something: %pSR\n", (void *)addr);
Add a new %p[SsFf]R vsprintf extension that can perform the same
symbol function/address/offset formatting as print_symbol to
reduce the number and styles of message logging functions.
print_symbol used __builtin_extract_return_addr for those architectures
like S/390 and SPARC that have offset or masked addressing.
%p[FfSs]R uses the same gcc __builtin
Joe Perches (26):
vsprintf: Add extension %pSR - print_symbol replacement
alpha: Convert print_symbol to %pSR
arm: Convert print_symbol to %pSR
arm64: Convert print_symbol to %pSR
avr32: Convert print_symbol to %pSR
c6x: Convert print_symbol to %pSR
ia64: Convert print_symbol to %pSR
m32r: Convert print_symbol to %pSR
mn10300: Convert print_symbol to %pSR
openrisc: Convert print_symbol to %pSR
powerpc: Convert print_symbol to %pSR
s390: Convert print_symbol to %pSR
sh: Convert print_symbol to %pSR
um: Convert print_symbol to %pSR
unicore32: Convert print_symbol to %pSR
x86: Convert print_symbol to %pSR
xtensa: Convert print_symbol to %pSR
drivers: base: Convert print_symbol to %pSR
gfs2: Convert print_symbol to %pSR
sysfs: Convert print_symbol to %pSR
irq: Convert print_symbol to %pSR
smp_processor_id: Convert print_symbol to %pSR
mm: Convert print_symbol to %pSR
xtensa: Convert print_symbol to %pSR
x86: head_64.S: Use vsprintf extension %pSR not print_symbol
kallsyms: Remove print_symbol
Documentation/filesystems/sysfs.txt | 4 +-
Documentation/printk-formats.txt | 2 +
Documentation/zh_CN/filesystems/sysfs.txt | 4 +-
arch/alpha/kernel/traps.c | 8 ++----
arch/arm/kernel/process.c | 4 +-
arch/arm64/kernel/process.c | 4 +-
arch/avr32/kernel/process.c | 25 ++++++-----------------
arch/c6x/kernel/traps.c | 3 +-
arch/ia64/kernel/process.c | 13 ++++-------
arch/m32r/kernel/traps.c | 6 +---
arch/mn10300/kernel/traps.c | 8 +++---
arch/openrisc/kernel/traps.c | 7 +----
arch/powerpc/platforms/cell/spu_callbacks.c | 12 ++++------
arch/s390/kernel/traps.c | 28 +++++++++++++++-----------
arch/sh/kernel/process_32.c | 4 +-
arch/um/kernel/sysrq.c | 6 +---
arch/unicore32/kernel/process.c | 5 ++-
arch/x86/kernel/cpu/mcheck/mce.c | 13 ++++++-----
arch/x86/kernel/dumpstack.c | 5 +--
arch/x86/kernel/head_64.S | 4 +-
arch/x86/kernel/process_32.c | 2 +-
arch/x86/mm/mmio-mod.c | 4 +-
arch/x86/um/sysrq_32.c | 9 ++-----
arch/xtensa/kernel/traps.c | 6 +---
drivers/base/core.c | 4 +-
fs/gfs2/glock.c | 4 +-
fs/gfs2/trans.c | 3 +-
fs/sysfs/file.c | 4 +-
include/linux/kallsyms.h | 18 -----------------
kernel/irq/debug.h | 15 ++++++-------
kernel/kallsyms.c | 11 ----------
lib/smp_processor_id.c | 2 +-
lib/vsprintf.c | 18 ++++++++++++----
mm/memory.c | 8 +++---
mm/slab.c | 8 ++----
35 files changed, 117 insertions(+), 164 deletions(-)
--
1.7.8.112.g3fd21
^ permalink raw reply
* Re: [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations
From: Guennadi Liakhovetski @ 2012-12-12 16:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121212103119.GA6195@mudshark.cambridge.arm.com>
Hi Will
On Wed, 12 Dec 2012, Will Deacon wrote:
> On Tue, Dec 11, 2012 at 11:27:39PM +0000, Stephen Boyd wrote:
> > On 12/11/12 08:38, Will Deacon wrote:
> > > diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> > > index cd95664..f58248f 100644
> > > --- a/arch/arm/mm/cache-v7.S
> > > +++ b/arch/arm/mm/cache-v7.S
> > > @@ -44,7 +44,8 @@ ENDPROC(v7_flush_icache_all)
> > > ENTRY(v7_flush_dcache_louis)
> > > dmb @ ensure ordering with previous memory accesses
> > > mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
> > > - ands r3, r0, #0xe00000 @ extract LoUIS from clidr
> > > + ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr
> > > + ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr
> > > mov r3, r3, lsr #20 @ r3 = LoUIS * 2
> >
> > You need to fix this mov as well, right?
>
> Ha, nice catch. So the original patch ended up with a ridiculously high
> level number and would've flushed L2, hence we will need to retest with the
> fix below...
Had to apply manually, but it worked too.
Thanks
Guennadi
>
> Will
>
> --->8
>
> diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> index cd95664..7539ec2 100644
> --- a/arch/arm/mm/cache-v7.S
> +++ b/arch/arm/mm/cache-v7.S
> @@ -44,8 +44,10 @@ ENDPROC(v7_flush_icache_all)
> ENTRY(v7_flush_dcache_louis)
> dmb @ ensure ordering with previous memory accesses
> mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
> - ands r3, r0, #0xe00000 @ extract LoUIS from clidr
> - mov r3, r3, lsr #20 @ r3 = LoUIS * 2
> + ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr
> + ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr
> + ALT_SMP(mov r3, r3, lsr #20) @ r3 = LoUIS * 2
> + ALT_UP(mov r3, r3, lsr #26) @ r3 = LoUU * 2
> moveq pc, lr @ return if level = 0
> mov r10, #0 @ r10 (starting level) = 0
> b flush_levels @ start flushing cache levels
>
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
^ permalink raw reply
* Re: [RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations
From: Guennadi Liakhovetski @ 2012-12-12 16:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20121212103338.GB23022@e102568-lin.cambridge.arm.com>
Hi Lorenzo
On Wed, 12 Dec 2012, Lorenzo Pieralisi wrote:
> On Tue, Dec 11, 2012 at 11:27:39PM +0000, Stephen Boyd wrote:
> > On 12/11/12 08:38, Will Deacon wrote:
> > > diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> > > index cd95664..f58248f 100644
> > > --- a/arch/arm/mm/cache-v7.S
> > > +++ b/arch/arm/mm/cache-v7.S
> > > @@ -44,7 +44,8 @@ ENDPROC(v7_flush_icache_all)
> > > ENTRY(v7_flush_dcache_louis)
> > > dmb @ ensure ordering with previous memory accesses
> > > mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
> > > - ands r3, r0, #0xe00000 @ extract LoUIS from clidr
> > > + ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr
> > > + ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr
> > > mov r3, r3, lsr #20 @ r3 = LoUIS * 2
> >
> > You need to fix this mov as well, right?
>
> And after doing that I think the suspend finisher will still have
> to call flush_cache_all() since LoUU = 1 on A8, L2 is not cleaned
> and that's probably what we want if it can be retained.
>
> What about this (compile tested) ?
Works too.
Thanks
Guennadi
>
> Lorenzo
>
> --->8
>
> diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
> index cd95664..036f80f 100644
> --- a/arch/arm/mm/cache-v7.S
> +++ b/arch/arm/mm/cache-v7.S
> @@ -44,8 +44,9 @@ ENDPROC(v7_flush_icache_all)
> ENTRY(v7_flush_dcache_louis)
> dmb @ ensure ordering with previous memory accesses
> mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
> - ands r3, r0, #0xe00000 @ extract LoUIS from clidr
> - mov r3, r3, lsr #20 @ r3 = LoUIS * 2
> + ALT_SMP(lsr r3, r0, #20) @ r3 = clidr[31:20]
> + ALT_UP(lsr r3, r0, #26) @ r3 = clidr[31:26]
> + ands r3, r3, #0xe @ r3 = LoUIS/LoUU * 2
> moveq pc, lr @ return if level = 0
> mov r10, #0 @ r10 (starting level) = 0
> b flush_levels @ start flushing cache levels
>
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
^ permalink raw reply
* [FWIW:-)] comparing bonnie++ output
From: Guennadi Liakhovetski @ 2012-12-12 15:40 UTC (permalink / raw)
To: linux-sh
[-- Attachment #1: Type: TEXT/PLAIN, Size: 952 bytes --]
Hi all
I've been asked to prepare and publish some simple scripts / programs to
measure block device performance with a possibility to compare results.
There are a lot of programs available to benchmark block IO, but comparing
results of multiple runs is not always easy.
The expected use is, that you run the attached bash script bonnie_do.sh
several times in each configuration, that you want to benchmark. For
example, if a performance regression is suspected between kernel versions
X and Y, you collect output of this script in two log files X.log and
Y.log.
Then you use the attached bonnie_diff.c to compare the two log files. The
program calculates averages of each of several parameters, that I chose to
compare in each file. Then it compares calculated averages and prints out
absolute and percentual diffs.
Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
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/*
* (C) 2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
* License: Public domain
*
* This program can be used to compare logfiles, produced by bonnie_do.sh
*
* Running:
* ./bonnie_diff <logfile1> <logfile2>
*/
#include <sys/types.h>
#include <sys/stat.h>
#include <unistd.h>
#include <stdio.h>
#include <errno.h>
static const int index[] = {3, 5, 7, 9, 11, 13};
#define N (sizeof(index) / sizeof(index[0]))
static const char *name[] = {
"Character Output",
"Block Output",
"Rewrite",
"Character Input",
"Block Input",
"Random Seek",
};
static void avg(FILE *fd, float *val)
{
int i, j;
for (i = 0; i < N; i++)
val[i] = 0.;
for (j = 0; ; j++) {
float v[N];
int ret = fscanf(fd, "%*s %*s %f %*f %f %*f %f %*f %f %*f %f %*f %f %*f",
v, v + 1, v + 2, v + 3, v + 4, v + 5);
if (ret < 6 || ret == EOF)
break;
for (i = 0; i < N; i++)
val[i] += v[i];
}
if (!j)
return;
for (i = 0; i < N; i++)
val[i] /= j;
}
int main(int argc, char *argv[])
{
FILE *fd1, *fd2;
int i;
float val1[N], val2[N];
if (argc != 3) {
errno = -EINVAL;
return 1;
}
fd1 = fopen(argv[1], "r");
if (!fd1)
return 1;
fd2 = fopen(argv[2], "r");
if (!fd2)
return 1;
avg(fd1, val1);
avg(fd2, val2);
for (i = 0; i < N; i++) {
float delta, pdelta;
char *s = "+";
delta = val2[i] - val1[i];
if (delta < 0)
s = "";
pdelta = delta * 100 / val1[i];
printf("%s: %s%f (%s%f%%)\n", name[i], s, delta, s, pdelta);
}
return 0;
}
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