timer on just one cpu in linux mp-system

timer on just one cpu in linux mp-system

[Klaas Zweck]

hi,

my question is how to make a linux mp-kernel
react on timer interrupts on just _one_ cpu?

my system is a pentium3 smp computer with
a serverworks chipset.

boot.msg says:

 >Intel MultiProcessor Specification v1.4
<4>    Virtual Wire compatibility mode.
<4>OEM ID: OEM00000 Product ID: PROD00000000 APIC at: 0xFEE00000
<4>Processor #3 Pentium(tm) Pro APIC version 17
<4>    Floating point unit present.
<4>    Machine Exception supported.
<4>    64 bit compare & exchange supported.
<4>    Internal APIC present.
<4>    SEP present.
<4>    MTRR  present.
<4>    PGE  present.
<4>    MCA  present.
<4>    CMOV  present.
<4>    PAT  present.
<4>    PSE  present.
<4>    PSN  present.
<4>    MMX  present.
<4>    FXSR  present.
<4>    XMM  present.
<4>    Bootup CPU

and so for the second cpu (except for the bootup cpu line)
cat /proc/interrupts says that timer interrupt
is number 0 and it is always counted on both cpus.
(they diifer slightly but both counters are updated )

example of cat /proc/interrupts

           CPU0       CPU1
  0:     105123      96263    IO-APIC-edge  timer  

in the function setup_local_APIC() in arch/i386/kernel/apic.c
i did the following to (try) to disable timer interrupt on cpu1:

if ( smp_processor_id() ){
 
          lvtt1_value = SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV) |
              APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;

--->   lvtt1_value = lvtt1_value | APIC_LVT_MASKED;
          printk( "KHZ: Write to AP local APIC (Timer) %x \n", 
lvtt1_value );
 
        } else {
            lvtt1_value = SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV) |
                APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
            printk( "KHZ: Write to BP local APIC (Timer) %x \n", 
lvtt1_value );
} 

---> means my try to mask the timer interrupt for any but the boot cpu.
( since the boot cpu has smp_processor_id() zero ).

but it didn't work since cat /proc/interrupts still reports timer 
interrupts on
both cpus.

even calling clear_local_APIC() at the end of setup_local_APIC()
(both in arch/i386/kernel/apic.c)
which should set all local apic local vector table (LVT) entries to
masked state didn't work.

still cat /proc/interrupts reports timer irqs on both cpus.

what am i doing wrong ??

thanks and greetings,
klaas

Re: timer on just one cpu in linux mp-system

[Klaas Zweck]

me again,

found out myself that it always worked to mask
the local timer out.
cat /proc/interrupts was just the wrong way (tool)
to test if it is really masked out since it only shows the 
external timer irqs.

top and xosview showed an idle time of 100% for cpu with masked
out local timer even if there were processes on it.
this means that the timer didn't update local kstat info anymore
and so mytry to just mask it worked.

a hint would have been helpful, though.
greets,
klaas

Kernel doesn't see both CPU's

[J. Milgram]

Hi,

I'm having trouble getting the kernel to see both CPU's on a
newly-acquired Micron Millenia dual P-Pro machine.

I've compiled in SMP, with enhanced RTC support, and without power
management (and with mtrr, if that matters). On boot, it basically reports
seeing just one processor. I've swapped around the CPUs to make sure
they're both OK, and they are.  There's sort of a phantom jumper switch to
tell the M/B either single or dual CPU, but the pins aren't there, and
from the outline drawn around it on the M/B I'm guessing (hoping) it's
hardwired as "dual".

I've tried
2.2.19 (spontaneously reboots just after loading the kernel)
2.4.5
2.4.18

all with/without "noapic"
and all with the BIOS MP level set at both 1.1 and 1.4 (that's the only
MP-related setting I found in the BIOS). It looks like a 1995 BIOS.

While I could just use it as a single-CPU machine, I had my heart set on
a dual :)

Any suggestions for things to try? Would be most grateful.

Below:

(1) dmesg output
(2) /var/log/syslog excerpt  --- I'm concerned about the symbol table
    version number message
(3) /var/log/messages excerpt

thanks again for any pointers!

Judah Milgram
milgram@cgpp.com

=====   (1)   ========================================================

Linux version 2.4.18 (root@steinway) (gcc version 2.95.3 20010315
(release)) #1
SMP Fri Apr 19 21:52:01 EDT 2002
BIOS-provided physical RAM map:
 BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
 BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
 BIOS-e820: 00000000000f9ec9 - 0000000000100000 (reserved)
 BIOS-e820: 0000000000100000 - 0000000008000000 (usable)
 BIOS-e820: 00000000fec00000 - 00000000fec01000 (reserved)
 BIOS-e820: 00000000fee00000 - 00000000fee01000 (reserved)
 BIOS-e820: 00000000ffff9ec9 - 0000000100000000 (reserved)
found SMP MP-table at 000f9ad0
hm, page 000f9000 reserved twice.
hm, page 000fa000 reserved twice.
hm, page 0009f000 reserved twice.
hm, page 000a0000 reserved twice.
On node 0 totalpages: 32768
zone(0): 4096 pages.
zone(1): 28672 pages.
zone(2): 0 pages.
Intel MultiProcessor Specification v1.1
    Virtual Wire compatibility mode.
OEM ID: INTEL    Product ID: 440FX        APIC at: 0xFEE00000
Processor #0 Pentium(tm) Pro APIC version 17
I/O APIC #1 Version 17 at 0xFEC00000.
Processors: 1
Kernel command line: auto BOOT_IMAGE=linux2418smp ro root=302 noapic
Initializing CPU#0
Detected 199.311 MHz processor.
Console: colour VGA+ 80x25
Calibrating delay loop... 397.31 BogoMIPS
Memory: 126872k/131072k available (893k kernel code, 3812k reserved, 258k
data,
212k init, 0k highmem)
Dentry-cache hash table entries: 16384 (order: 5, 131072 bytes)
Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)
Mount-cache hash table entries: 2048 (order: 2, 16384 bytes)
Buffer-cache hash table entries: 8192 (order: 3, 32768 bytes)
Page-cache hash table entries: 32768 (order: 5, 131072 bytes)
CPU: Before vendor init, caps: 0000fbff 00000000 00000000, vendor = 0
CPU: L1 I cache: 8K, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: After vendor init, caps: 0000fbff 00000000 00000000 00000000
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
CPU:     After generic, caps: 0000fbff 00000000 00000000 00000000
CPU:             Common caps: 0000fbff 00000000 00000000 00000000
Checking 'hlt' instruction... OK.
POSIX conformance testing by UNIFIX
mtrr: v1.40 (20010327) Richard Gooch (rgooch@atnf.csiro.au)
mtrr: detected mtrr type: Intel
CPU: Before vendor init, caps: 0000fbff 00000000 00000000, vendor = 0
CPU: L1 I cache: 8K, L1 D cache: 8K
CPU: L2 cache: 256K
CPU: After vendor init, caps: 0000fbff 00000000 00000000 00000000
Intel machine check reporting enabled on CPU#0.
CPU:     After generic, caps: 0000fbff 00000000 00000000 00000000
CPU:             Common caps: 0000fbff 00000000 00000000 00000000
CPU0: Intel Pentium Pro stepping 09
per-CPU timeslice cutoff: 730.16 usecs.
enabled ExtINT on CPU#0
ESR value before enabling vector: 00000000
ESR value after enabling vector: 00000000
Error: only one processor found.
Using local APIC timer interrupts.
calibrating APIC timer ...
..... CPU clock speed is 199.3156 MHz.
..... host bus clock speed is 66.4382 MHz.
cpu: 0, clocks: 664382, slice: 332191
CPU0<T0:664368,T1:332176,D:1,S:332191,C:664382>
Waiting on wait_init_idle (map = 0x0)
All processors have done init_idle

(etc)

========   (2)   ========================================

Apr 21 09:57:14 steinway kernel: Symbol table has incorrect version number.
Apr 21 09:57:15 steinway kernel: Error: only one processor found.

=======    (3)   ======================================


Apr 21 09:57:12 steinway syslogd 1.4.1: restart.
Apr 21 09:57:13 steinway kernel: klogd 1.4.1, log source = /proc/kmsg
started.
Apr 21 09:57:13 steinway kernel: Inspecting /boot/System.map
Apr 21 09:57:14 steinway kernel: No module symbols loaded.
Apr 21 09:57:14 steinway kernel: BIOS-provided physical RAM map:
Apr 21 09:57:14 steinway kernel: Initializing CPU#0
Apr 21 09:57:14 steinway kernel: CPU: L1 I cache: 8K, L1 D cache: 8K
Apr 21 09:57:14 steinway kernel: CPU: L2 cache: 256K
Apr 21 09:57:14 steinway kernel: Intel machine check architecture
supported.
Apr 21 09:57:14 steinway kernel: Intel machine check reporting enabled on
CPU#0.
Apr 21 09:57:14 steinway kernel: Checking 'hlt' instruction... OK.
Apr 21 09:57:15 steinway kernel: CPU: L1 I cache: 8K, L1 D cache: 8K
Apr 21 09:57:15 steinway kernel: CPU: L2 cache: 256K
Apr 21 09:57:15 steinway kernel: Intel machine check reporting enabled on
CPU#0.