[PATCH 0/6] Enable DMIC for Genio 700/510 EVK

[PATCH 0/6] Enable DMIC for Genio 700/510 EVK

[Nícolas F. R. A. Prado]

This series enables the dual digital microphones present on the Genio
700 and 510 EVK boards.

Patches 1 and 2 add some required clocks, patch 3 adds the DMIC DAI
driver for MT8188, patch 4 adds the DMIC routes for the MT8188 platform,
patch 5 adds the DMIC backend and widget to the mt8188-6359 machine
sound driver and patch 6 adds the audio routes for the DMIC to the
Devicetree.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
Nícolas F. R. A. Prado (4):
      ASoC: mediatek: mt8188: Add audsys hires clocks
      ASoC: mediatek: mt8188: Add reference for dmic clocks
      ASoC: mediatek: mt8188-mt6359: Add DMIC
      arm64: dts: mediatek: mt8390-genio-common: Add routes for DMIC

parkeryang (2):
      ASoC: mediatek: mt8188: Add DMIC DAI driver
      ASoC: mediatek: mt8188: Support DMIC in AFE

 .../boot/dts/mediatek/mt8390-genio-common.dtsi     |   6 +-
 sound/soc/mediatek/mt8188/Makefile                 |   1 +
 sound/soc/mediatek/mt8188/mt8188-afe-clk.c         |   8 +
 sound/soc/mediatek/mt8188/mt8188-afe-clk.h         |   8 +
 sound/soc/mediatek/mt8188/mt8188-afe-common.h      |   1 +
 sound/soc/mediatek/mt8188/mt8188-afe-pcm.c         |  28 +-
 sound/soc/mediatek/mt8188/mt8188-audsys-clk.c      |   4 +
 sound/soc/mediatek/mt8188/mt8188-audsys-clkid.h    |   4 +
 sound/soc/mediatek/mt8188/mt8188-dai-dmic.c        | 754 +++++++++++++++++++++
 sound/soc/mediatek/mt8188/mt8188-mt6359.c          |  14 +
 sound/soc/mediatek/mt8188/mt8188-reg.h             |  18 +-
 11 files changed, 839 insertions(+), 7 deletions(-)
---
base-commit: 253c82b3a2cec22bf9db65645f934fbe095899a3
change-id: 20250218-genio700-dmic-dc6ee9dc0638

Best regards,
-- 
Nícolas F. R. A. Prado <nfraprado@collabora.com>

[PATCH 1/6] ASoC: mediatek: mt8188: Add audsys hires clocks

[Nícolas F. R. A. Prado]

Describe and register the aud_dmic_hires audsys clocks, which are needed
when recording the DMIC at a sample rate of 96k.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
 sound/soc/mediatek/mt8188/mt8188-audsys-clk.c   | 4 ++++
 sound/soc/mediatek/mt8188/mt8188-audsys-clkid.h | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/sound/soc/mediatek/mt8188/mt8188-audsys-clk.c b/sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
index c796ad8b62eeaa929f24c09755f428116b105404..e7b2c9da61f6b5dbe9002a294ebbb7f4415fe54c 100644
--- a/sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
+++ b/sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
@@ -81,6 +81,10 @@ static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
 	GATE_AUD1(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "top_a1sys_hp", 11),
 	GATE_AUD1(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "top_a1sys_hp", 12),
 	GATE_AUD1(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "top_a1sys_hp", 13),
+	GATE_AUD1(CLK_AUD_DMIC_HIRES1, "aud_dmic_hires1", "top_audio_h", 20),
+	GATE_AUD1(CLK_AUD_DMIC_HIRES2, "aud_dmic_hires2", "top_audio_h", 21),
+	GATE_AUD1(CLK_AUD_DMIC_HIRES3, "aud_dmic_hires3", "top_audio_h", 22),
+	GATE_AUD1(CLK_AUD_DMIC_HIRES4, "aud_dmic_hires4", "top_audio_h", 23),
 	GATE_AUD1(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm", "top_a1sys_hp", 14),
 	GATE_AUD1(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires", "top_audio_h", 16),
 	GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "top_audio_h", 17),
diff --git a/sound/soc/mediatek/mt8188/mt8188-audsys-clkid.h b/sound/soc/mediatek/mt8188/mt8188-audsys-clkid.h
index 6f34ffc760e03beddc3001046e554edd7ea2c478..820f2aef17ea40be1a80aece604b4a319934312f 100644
--- a/sound/soc/mediatek/mt8188/mt8188-audsys-clkid.h
+++ b/sound/soc/mediatek/mt8188/mt8188-audsys-clkid.h
@@ -30,6 +30,10 @@ enum{
 	CLK_AUD_AFE_DMIC2,
 	CLK_AUD_AFE_DMIC3,
 	CLK_AUD_AFE_DMIC4,
+	CLK_AUD_DMIC_HIRES1,
+	CLK_AUD_DMIC_HIRES2,
+	CLK_AUD_DMIC_HIRES3,
+	CLK_AUD_DMIC_HIRES4,
 	CLK_AUD_AFE_26M_DMIC_TM,
 	CLK_AUD_UL_TML_HIRES,
 	CLK_AUD_ADC_HIRES,

-- 
2.48.1

[PATCH 2/6] ASoC: mediatek: mt8188: Add reference for dmic clocks

[Nícolas F. R. A. Prado]

Add the names for the dmic clocks, aud_afe_dmic* and aud_dmic_hires*, so
they can be acquired and enabled by the platform driver.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
 sound/soc/mediatek/mt8188/mt8188-afe-clk.c | 8 ++++++++
 sound/soc/mediatek/mt8188/mt8188-afe-clk.h | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
index e69c1bb2cb239596dee50b166c20192d5408be10..44c25b6e3d873448163b22e70f5b94cb5070654d 100644
--- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
@@ -58,6 +58,14 @@ static const char *aud_clks[MT8188_CLK_NUM] = {
 	[MT8188_CLK_AUD_ADC] = "aud_adc",
 	[MT8188_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
 	[MT8188_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
+	[MT8188_CLK_AUD_AFE_DMIC1] = "aud_afe_dmic1",
+	[MT8188_CLK_AUD_AFE_DMIC2] = "aud_afe_dmic2",
+	[MT8188_CLK_AUD_AFE_DMIC3] = "aud_afe_dmic3",
+	[MT8188_CLK_AUD_AFE_DMIC4] = "aud_afe_dmic4",
+	[MT8188_CLK_AUD_DMIC_HIRES1] = "aud_dmic_hires1",
+	[MT8188_CLK_AUD_DMIC_HIRES2] = "aud_dmic_hires2",
+	[MT8188_CLK_AUD_DMIC_HIRES3] = "aud_dmic_hires3",
+	[MT8188_CLK_AUD_DMIC_HIRES4] = "aud_dmic_hires4",
 	[MT8188_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
 	[MT8188_CLK_AUD_I2SIN] = "aud_i2sin",
 	[MT8188_CLK_AUD_TDM_IN] = "aud_tdm_in",
diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.h b/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
index ec53c171c170a8b4b47900e63ef79d53641e9b12..68c46feb72271b950d4e538f63cedf524354147e 100644
--- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
@@ -54,6 +54,14 @@ enum {
 	MT8188_CLK_AUD_ADC,
 	MT8188_CLK_AUD_DAC_HIRES,
 	MT8188_CLK_AUD_A1SYS_HP,
+	MT8188_CLK_AUD_AFE_DMIC1,
+	MT8188_CLK_AUD_AFE_DMIC2,
+	MT8188_CLK_AUD_AFE_DMIC3,
+	MT8188_CLK_AUD_AFE_DMIC4,
+	MT8188_CLK_AUD_DMIC_HIRES1,
+	MT8188_CLK_AUD_DMIC_HIRES2,
+	MT8188_CLK_AUD_DMIC_HIRES3,
+	MT8188_CLK_AUD_DMIC_HIRES4,
 	MT8188_CLK_AUD_ADC_HIRES,
 	MT8188_CLK_AUD_I2SIN,
 	MT8188_CLK_AUD_TDM_IN,

-- 
2.48.1

[PATCH 3/6] ASoC: mediatek: mt8188: Add DMIC DAI driver

[Nícolas F. R. A. Prado]

From: parkeryang <Parker.Yang@mediatek.com>

Add support for the DMIC DAIs present on the MT8188 SoC.

Signed-off-by: parkeryang <Parker.Yang@mediatek.com>
Co-developed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
 sound/soc/mediatek/mt8188/mt8188-afe-pcm.c  |   4 -
 sound/soc/mediatek/mt8188/mt8188-dai-dmic.c | 754 ++++++++++++++++++++++++++++
 sound/soc/mediatek/mt8188/mt8188-reg.h      |  18 +-
 3 files changed, 770 insertions(+), 6 deletions(-)

diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c b/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
index 73e5c63aeec8783905d656af225c42cd95069049..d36520c6272dd8c8302bc3f59da33f82f273f366 100644
--- a/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
@@ -2855,10 +2855,6 @@ static bool mt8188_is_volatile_reg(struct device *dev, unsigned int reg)
 	case AFE_DMIC3_SRC_DEBUG_MON0:
 	case AFE_DMIC3_UL_SRC_MON0:
 	case AFE_DMIC3_UL_SRC_MON1:
-	case DMIC_GAIN1_CUR:
-	case DMIC_GAIN2_CUR:
-	case DMIC_GAIN3_CUR:
-	case DMIC_GAIN4_CUR:
 	case ETDM_IN1_MONITOR:
 	case ETDM_IN2_MONITOR:
 	case ETDM_OUT1_MONITOR:
diff --git a/sound/soc/mediatek/mt8188/mt8188-dai-dmic.c b/sound/soc/mediatek/mt8188/mt8188-dai-dmic.c
new file mode 100644
index 0000000000000000000000000000000000000000..9df08783ff80173095809c20538d0fb073ed7fae
--- /dev/null
+++ b/sound/soc/mediatek/mt8188/mt8188-dai-dmic.c
@@ -0,0 +1,754 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek ALSA SoC Audio DAI DMIC I/F Control
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
+ *         Trevor Wu <trevor.wu@mediatek.com>
+ *         Parker Yang <parker.yang@mediatek.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/regmap.h>
+#include <sound/pcm_params.h>
+#include "mt8188-afe-clk.h"
+#include "mt8188-afe-common.h"
+#include "mt8188-reg.h"
+
+#define DMIC_MAX_CH (8)
+
+/* DMIC HW Gain configuration maximum value. */
+#define DMIC_GAIN_MAX_STEP	GENMASK(19, 0)
+#define DMIC_GAIN_MAX_PER_STEP	GENMASK(7, 0)
+#define DMIC_GAIN_MAX_TARGET	GENMASK(27, 0)
+#define DMIC_GAIN_MAX_CURRENT	GENMASK(27, 0)
+
+#define CLK_PHASE_SEL_CH1 0
+#define CLK_PHASE_SEL_CH2 ((CLK_PHASE_SEL_CH1) + 4)
+
+#define DMIC1_SRC_SEL 0
+#define DMIC2_SRC_SEL 0
+#define DMIC3_SRC_SEL 2
+#define DMIC4_SRC_SEL 0
+#define DMIC5_SRC_SEL 4
+#define DMIC6_SRC_SEL 0
+#define DMIC7_SRC_SEL 6
+#define DMIC8_SRC_SEL 0
+
+enum {
+	SUPPLY_SEQ_DMIC_GAIN,
+	SUPPLY_SEQ_DMIC_CK,
+};
+
+enum {
+	DMIC0,
+	DMIC1,
+	DMIC2,
+	DMIC3,
+	DMIC_NUM,
+};
+
+struct mtk_dai_dmic_ctrl_reg {
+	unsigned int con0;
+};
+
+struct mtk_dai_dmic_hw_gain_ctrl_reg {
+	unsigned int bypass;
+	unsigned int con0;
+};
+
+struct mtk_dai_dmic_priv {
+	unsigned int gain_on[DMIC_NUM];
+	unsigned int channels;
+	bool hires_required;
+};
+
+static const struct mtk_dai_dmic_ctrl_reg dmic_ctrl_regs[DMIC_NUM] = {
+	[DMIC0] = {
+		.con0 = AFE_DMIC0_UL_SRC_CON0,
+	},
+	[DMIC1] = {
+		.con0 = AFE_DMIC1_UL_SRC_CON0,
+	},
+	[DMIC2] = {
+		.con0 = AFE_DMIC2_UL_SRC_CON0,
+	},
+	[DMIC3] = {
+		.con0 = AFE_DMIC3_UL_SRC_CON0,
+	},
+};
+
+static const struct mtk_dai_dmic_ctrl_reg *get_dmic_ctrl_reg(int id)
+{
+	if (id < 0 || id >= DMIC_NUM)
+		return NULL;
+
+	return &dmic_ctrl_regs[id];
+}
+
+static const struct mtk_dai_dmic_hw_gain_ctrl_reg
+	dmic_hw_gain_ctrl_regs[DMIC_NUM] = {
+	[DMIC0] = {
+		.bypass = DMIC_BYPASS_HW_GAIN,
+		.con0 = DMIC_GAIN1_CON0,
+	},
+	[DMIC1] = {
+		.bypass = DMIC_BYPASS_HW_GAIN,
+		.con0 = DMIC_GAIN2_CON0,
+	},
+	[DMIC2] = {
+		.bypass = DMIC_BYPASS_HW_GAIN,
+		.con0 = DMIC_GAIN3_CON0,
+	},
+	[DMIC3] = {
+		.bypass = DMIC_BYPASS_HW_GAIN,
+		.con0 = DMIC_GAIN4_CON0,
+	},
+};
+
+static const struct mtk_dai_dmic_hw_gain_ctrl_reg
+	*get_dmic_hw_gain_ctrl_reg(struct mtk_base_afe *afe, int id)
+{
+	if ((id < 0) || (id >= DMIC_NUM)) {
+		dev_dbg(afe->dev, "%s invalid id\n", __func__);
+		return NULL;
+	}
+
+	return &dmic_hw_gain_ctrl_regs[id];
+}
+
+static void mtk_dai_dmic_hw_gain_byass(struct mtk_base_afe *afe,
+				       unsigned int id, bool bypass)
+{
+	const struct mtk_dai_dmic_hw_gain_ctrl_reg *reg;
+	unsigned int msk;
+
+	reg = get_dmic_hw_gain_ctrl_reg(afe, id);
+	if (!reg)
+		return;
+
+	switch (id) {
+	case DMIC0:
+		msk = DMIC_BYPASS_HW_GAIN_DMIC1_BYPASS;
+		break;
+	case DMIC1:
+		msk = DMIC_BYPASS_HW_GAIN_DMIC2_BYPASS;
+		break;
+	case DMIC2:
+		msk = DMIC_BYPASS_HW_GAIN_DMIC3_BYPASS;
+		break;
+	case DMIC3:
+		msk = DMIC_BYPASS_HW_GAIN_DMIC4_BYPASS;
+		break;
+	default:
+		return;
+	}
+
+	if (bypass)
+		regmap_set_bits(afe->regmap, reg->bypass, msk);
+	else
+		regmap_clear_bits(afe->regmap, reg->bypass, msk);
+}
+
+static void mtk_dai_dmic_hw_gain_on(struct mtk_base_afe *afe,
+				    unsigned int id, bool on)
+{
+	const struct mtk_dai_dmic_hw_gain_ctrl_reg *reg;
+	unsigned int msk = DMIC_GAIN_CON0_GAIN_ON;
+
+	reg = get_dmic_hw_gain_ctrl_reg(afe, id);
+	if (!reg)
+		return;
+
+	if (on)
+		regmap_set_bits(afe->regmap, reg->con0, msk);
+	else
+		regmap_clear_bits(afe->regmap, reg->con0, msk);
+}
+
+static const struct reg_sequence mtk_dai_dmic_iir_coeff_reg_defaults[] = {
+	{ AFE_DMIC0_IIR_COEF_02_01, 0x00000000 },
+	{ AFE_DMIC0_IIR_COEF_04_03, 0x00003FB8 },
+	{ AFE_DMIC0_IIR_COEF_06_05, 0x3FB80000 },
+	{ AFE_DMIC0_IIR_COEF_08_07, 0x3FB80000 },
+	{ AFE_DMIC0_IIR_COEF_10_09, 0x0000C048 },
+	{ AFE_DMIC1_IIR_COEF_02_01, 0x00000000 },
+	{ AFE_DMIC1_IIR_COEF_04_03, 0x00003FB8 },
+	{ AFE_DMIC1_IIR_COEF_06_05, 0x3FB80000 },
+	{ AFE_DMIC1_IIR_COEF_08_07, 0x3FB80000 },
+	{ AFE_DMIC1_IIR_COEF_10_09, 0x0000C048 },
+	{ AFE_DMIC2_IIR_COEF_02_01, 0x00000000 },
+	{ AFE_DMIC2_IIR_COEF_04_03, 0x00003FB8 },
+	{ AFE_DMIC2_IIR_COEF_06_05, 0x3FB80000 },
+	{ AFE_DMIC2_IIR_COEF_08_07, 0x3FB80000 },
+	{ AFE_DMIC2_IIR_COEF_10_09, 0x0000C048 },
+	{ AFE_DMIC3_IIR_COEF_02_01, 0x00000000 },
+	{ AFE_DMIC3_IIR_COEF_04_03, 0x00003FB8 },
+	{ AFE_DMIC3_IIR_COEF_06_05, 0x3FB80000 },
+	{ AFE_DMIC3_IIR_COEF_08_07, 0x3FB80000 },
+	{ AFE_DMIC3_IIR_COEF_10_09, 0x0000C048 },
+};
+
+static int mtk_dai_dmic_load_iir_coeff_table(struct mtk_base_afe *afe)
+{
+	return regmap_multi_reg_write(afe->regmap,
+				      mtk_dai_dmic_iir_coeff_reg_defaults,
+				      ARRAY_SIZE(mtk_dai_dmic_iir_coeff_reg_defaults));
+}
+
+static int mtk_dai_dmic_configure_array(struct snd_soc_dai *dai)
+{
+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+	struct mt8188_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_dai_dmic_priv *dmic_priv = NULL;
+	unsigned int mask =
+			PWR2_TOP_CON_DMIC8_SRC_SEL_MASK |
+			PWR2_TOP_CON_DMIC7_SRC_SEL_MASK |
+			PWR2_TOP_CON_DMIC6_SRC_SEL_MASK |
+			PWR2_TOP_CON_DMIC5_SRC_SEL_MASK |
+			PWR2_TOP_CON_DMIC4_SRC_SEL_MASK |
+			PWR2_TOP_CON_DMIC3_SRC_SEL_MASK |
+			PWR2_TOP_CON_DMIC2_SRC_SEL_MASK |
+			PWR2_TOP_CON_DMIC1_SRC_SEL_MASK;
+	unsigned int val = 0;
+
+	if (dai->id < 0)
+		return -EINVAL;
+
+	dmic_priv = afe_priv->dai_priv[dai->id];
+	val = PWR2_TOP_CON_DMIC8_SRC_SEL_VAL(DMIC8_SRC_SEL) |
+	      PWR2_TOP_CON_DMIC7_SRC_SEL_VAL(DMIC7_SRC_SEL) |
+	      PWR2_TOP_CON_DMIC6_SRC_SEL_VAL(DMIC6_SRC_SEL) |
+	      PWR2_TOP_CON_DMIC5_SRC_SEL_VAL(DMIC5_SRC_SEL) |
+	      PWR2_TOP_CON_DMIC4_SRC_SEL_VAL(DMIC4_SRC_SEL) |
+	      PWR2_TOP_CON_DMIC3_SRC_SEL_VAL(DMIC3_SRC_SEL) |
+	      PWR2_TOP_CON_DMIC2_SRC_SEL_VAL(DMIC2_SRC_SEL) |
+	      PWR2_TOP_CON_DMIC1_SRC_SEL_VAL(DMIC1_SRC_SEL);
+
+	regmap_update_bits(afe->regmap, PWR2_TOP_CON0, mask, val);
+
+	return 0;
+}
+
+static void mtk_dai_dmic_hw_gain_enable(struct mtk_base_afe *afe,
+					unsigned int channels, bool enable)
+{
+	struct mt8188_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_dai_dmic_priv *dmic_priv;
+	unsigned int end;
+	unsigned int id;
+
+	if (!channels)
+		return;
+
+	dmic_priv = afe_priv->dai_priv[MT8188_AFE_IO_DMIC_IN];
+	if (channels > 3)
+		end = 3;
+	else if (channels > 2)
+		end = 2;
+	else if (channels > 1)
+		end = 1;
+	else if (channels > 0)
+		end = 0;
+
+	for (id = DMIC0; id <= end; id++) {
+		if (enable && dmic_priv->gain_on[id]) {
+			mtk_dai_dmic_hw_gain_byass(afe, id, false);
+			mtk_dai_dmic_hw_gain_on(afe, id, true);
+		} else {
+			mtk_dai_dmic_hw_gain_on(afe, id, false);
+			mtk_dai_dmic_hw_gain_byass(afe, id, true);
+		}
+	}
+}
+
+static int mtk_dmic_gain_event(struct snd_soc_dapm_widget *w,
+			       struct snd_kcontrol *kcontrol,
+			       int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mt8188_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_dai_dmic_priv *dmic_priv = NULL;
+	unsigned int channels;
+
+	dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
+		__func__, w->name, event);
+
+	dmic_priv = afe_priv->dai_priv[MT8188_AFE_IO_DMIC_IN];
+	channels = dmic_priv->channels;
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		mtk_dai_dmic_hw_gain_enable(afe, channels, true);
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		mtk_dai_dmic_hw_gain_enable(afe, channels, false);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int mtk_dmic_event(struct snd_soc_dapm_widget *w,
+			  struct snd_kcontrol *kcontrol,
+			  int event)
+{
+	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
+	struct mt8188_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_dai_dmic_priv *dmic_priv = NULL;
+	const struct mtk_dai_dmic_ctrl_reg *reg = NULL;
+	unsigned int channels;
+	unsigned int msk;
+
+	dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
+		__func__, w->name, event);
+
+	dmic_priv = afe_priv->dai_priv[MT8188_AFE_IO_DMIC_IN];
+	channels = dmic_priv->channels;
+
+	switch (event) {
+	case SND_SOC_DAPM_PRE_PMU:
+		/* request fifo soft rst */
+		msk = 0;
+		if (channels > 3)
+			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC3);
+		if (channels > 2)
+			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC2);
+		if (channels > 1)
+			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC1);
+		if (channels > 0)
+			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC0);
+
+		regmap_set_bits(afe->regmap, PWR2_TOP_CON1, msk);
+
+		msk = 0;
+		msk |= AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH1_CTL;
+		msk |= AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH2_CTL;
+		msk |= AFE_DMIC_UL_SRC_CON0_UL_SDM_3_LEVEL_CTL;
+		msk |= AFE_DMIC_UL_SRC_CON0_UL_IIR_ON_TMP_CTL;
+
+		if (channels > 3) {
+			reg = get_dmic_ctrl_reg(DMIC3);
+			if (reg)
+				regmap_set_bits(afe->regmap, reg->con0, msk);
+		}
+		if (channels > 2) {
+			reg = get_dmic_ctrl_reg(DMIC2);
+			if (reg)
+				regmap_set_bits(afe->regmap, reg->con0, msk);
+		}
+		if (channels > 1) {
+			reg = get_dmic_ctrl_reg(DMIC1);
+			if (reg)
+				regmap_set_bits(afe->regmap, reg->con0, msk);
+		}
+		if (channels > 0) {
+			reg = get_dmic_ctrl_reg(DMIC0);
+			if (reg)
+				regmap_set_bits(afe->regmap, reg->con0, msk);
+		}
+		break;
+	case SND_SOC_DAPM_POST_PMU:
+		msk = AFE_DMIC_UL_SRC_CON0_UL_SRC_ON_TMP_CTL;
+		if (channels > 3) {
+			reg = get_dmic_ctrl_reg(DMIC3);
+			if (reg)
+				regmap_set_bits(afe->regmap, reg->con0, msk);
+		}
+		if (channels > 2) {
+			reg = get_dmic_ctrl_reg(DMIC2);
+			if (reg)
+				regmap_set_bits(afe->regmap, reg->con0, msk);
+		}
+		if (channels > 1) {
+			reg = get_dmic_ctrl_reg(DMIC1);
+			if (reg)
+				regmap_set_bits(afe->regmap, reg->con0, msk);
+		}
+		if (channels > 0) {
+			reg = get_dmic_ctrl_reg(DMIC0);
+			if (reg)
+				regmap_set_bits(afe->regmap, reg->con0, msk);
+		}
+
+		if (dmic_priv->hires_required) {
+			mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES1]);
+			mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES2]);
+			mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES3]);
+			mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES4]);
+		}
+
+		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC1]);
+		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC2]);
+		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC3]);
+		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC4]);
+
+		/* release fifo soft rst */
+		msk = 0;
+		if (channels > 3)
+			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC3);
+		if (channels > 2)
+			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC2);
+		if (channels > 1)
+			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC1);
+		if (channels > 0)
+			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC0);
+
+		regmap_clear_bits(afe->regmap, PWR2_TOP_CON1, msk);
+		break;
+	case SND_SOC_DAPM_PRE_PMD:
+		msk =  AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH1_CTL |
+			AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH2_CTL |
+			AFE_DMIC_UL_SRC_CON0_UL_SRC_ON_TMP_CTL |
+			AFE_DMIC_UL_SRC_CON0_UL_IIR_ON_TMP_CTL |
+			AFE_DMIC_UL_SRC_CON0_UL_SDM_3_LEVEL_CTL;
+
+		if (channels > 3) {
+			reg = get_dmic_ctrl_reg(DMIC3);
+			if (reg)
+				regmap_clear_bits(afe->regmap, reg->con0, msk);
+		}
+		if (channels > 2) {
+			reg = get_dmic_ctrl_reg(DMIC2);
+			if (reg)
+				regmap_clear_bits(afe->regmap, reg->con0, msk);
+		}
+		if (channels > 1) {
+			reg = get_dmic_ctrl_reg(DMIC1);
+			if (reg)
+				regmap_clear_bits(afe->regmap, reg->con0, msk);
+		}
+		if (channels > 0) {
+			reg = get_dmic_ctrl_reg(DMIC0);
+			if (reg)
+				regmap_clear_bits(afe->regmap, reg->con0, msk);
+		}
+		break;
+	case SND_SOC_DAPM_POST_PMD:
+		/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
+		usleep_range(125, 126);
+
+		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC1]);
+		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC2]);
+		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC3]);
+		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC4]);
+
+		if (dmic_priv->hires_required) {
+			mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES1]);
+			mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES2]);
+			mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES3]);
+			mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES4]);
+		}
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int mtk_dai_dmic_hw_params(struct snd_pcm_substream *substream,
+				  struct snd_pcm_hw_params *params,
+				  struct snd_soc_dai *dai)
+{
+	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
+	struct mt8188_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_dai_dmic_priv *dmic_priv = NULL;
+	unsigned int rate = params_rate(params);
+	unsigned int channels = params_channels(params);
+	const struct mtk_dai_dmic_ctrl_reg *reg = NULL;
+	unsigned int val = 0;
+	unsigned int msk = 0;
+
+	if (dai->id < 0)
+		return -EINVAL;
+
+	dmic_priv = afe_priv->dai_priv[dai->id];
+
+	val = AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_CH1(CLK_PHASE_SEL_CH1) |
+	      AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_CH2(CLK_PHASE_SEL_CH2) |
+	      AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL(0);
+	msk = AFE_DMIC_UL_SRC_CON0_UL_TWO_WIRE_MODE_CTL_MASK |
+	      AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_MASK |
+	      AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL_MASK |
+	      AFE_DMIC_UL_VOICE_MODE_MASK;
+
+	mtk_dai_dmic_configure_array(dai);
+	dmic_priv->hires_required = 0;
+
+	switch (rate) {
+	case 96000:
+		val |= AFE_DMIC_UL_CON0_VOCIE_MODE_96K;
+		dmic_priv->hires_required = 1;
+		break;
+	case 48000:
+		val |= AFE_DMIC_UL_CON0_VOCIE_MODE_48K;
+		break;
+	case 32000:
+		val |= AFE_DMIC_UL_CON0_VOCIE_MODE_32K;
+		break;
+	case 16000:
+		val |= AFE_DMIC_UL_CON0_VOCIE_MODE_16K;
+		break;
+	case 8000:
+		val |= AFE_DMIC_UL_CON0_VOCIE_MODE_8K;
+		break;
+	default:
+		dev_dbg(afe->dev, "%s invalid rate %u, use 48000Hz\n", __func__, rate);
+		val |= AFE_DMIC_UL_CON0_VOCIE_MODE_48K;
+		break;
+	}
+
+	mtk_dai_dmic_load_iir_coeff_table(afe);
+
+	if (channels > 3) {
+		reg = get_dmic_ctrl_reg(DMIC3);
+		if (reg)
+			regmap_update_bits(afe->regmap, reg->con0, msk, val);
+	}
+	if (channels > 2) {
+		reg = get_dmic_ctrl_reg(DMIC2);
+		if (reg)
+			regmap_update_bits(afe->regmap, reg->con0, msk, val);
+	}
+	if (channels > 1) {
+		reg = get_dmic_ctrl_reg(DMIC1);
+		if (reg)
+			regmap_update_bits(afe->regmap, reg->con0, msk, val);
+	}
+	if (channels > 0) {
+		reg = get_dmic_ctrl_reg(DMIC0);
+		if (reg)
+			regmap_update_bits(afe->regmap, reg->con0, msk, val);
+	}
+
+	dmic_priv->channels = channels;
+
+	return 0;
+}
+
+static const struct snd_soc_dai_ops mtk_dai_dmic_ops = {
+	.hw_params	= mtk_dai_dmic_hw_params,
+};
+
+#define MTK_DMIC_RATES (SNDRV_PCM_RATE_8000 |\
+		       SNDRV_PCM_RATE_16000 |\
+		       SNDRV_PCM_RATE_32000 |\
+		       SNDRV_PCM_RATE_48000 |\
+		       SNDRV_PCM_RATE_96000)
+
+#define MTK_DMIC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
+			 SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_driver mtk_dai_dmic_driver[] = {
+	{
+		.name = "DMIC",
+		.id = MT8188_AFE_IO_DMIC_IN,
+		.capture = {
+			.stream_name = "DMIC Capture",
+			.channels_min = 1,
+			.channels_max = 8,
+			.rates = MTK_DMIC_RATES,
+			.formats = MTK_DMIC_FORMATS,
+		},
+		.ops = &mtk_dai_dmic_ops,
+	},
+};
+
+static const struct snd_soc_dapm_widget mtk_dai_dmic_widgets[] = {
+	SND_SOC_DAPM_MIXER("I004", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_MIXER("I005", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_MIXER("I006", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_MIXER("I007", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_MIXER("I008", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_MIXER("I009", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_MIXER("I010", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_MIXER("I011", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+	SND_SOC_DAPM_SUPPLY_S("DMIC_GAIN_ON", SUPPLY_SEQ_DMIC_GAIN,
+			      SND_SOC_NOPM, 0, 0,
+			      mtk_dmic_gain_event,
+			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+	SND_SOC_DAPM_SUPPLY_S("DMIC_CK_ON", SUPPLY_SEQ_DMIC_CK,
+			      PWR2_TOP_CON1,
+			      PWR2_TOP_CON1_DMIC_CKDIV_ON_SHIFT, 0,
+			      mtk_dmic_event,
+			      SND_SOC_DAPM_PRE_POST_PMU |
+			      SND_SOC_DAPM_PRE_POST_PMD),
+	SND_SOC_DAPM_INPUT("DMIC_INPUT"),
+};
+
+static const struct snd_soc_dapm_route mtk_dai_dmic_routes[] = {
+	{"I004", NULL, "DMIC Capture"},
+	{"I005", NULL, "DMIC Capture"},
+	{"I006", NULL, "DMIC Capture"},
+	{"I007", NULL, "DMIC Capture"},
+	{"I008", NULL, "DMIC Capture"},
+	{"I009", NULL, "DMIC Capture"},
+	{"I010", NULL, "DMIC Capture"},
+	{"I011", NULL, "DMIC Capture"},
+	{"DMIC Capture", NULL, "DMIC_CK_ON"},
+	{"DMIC Capture", NULL, "DMIC_GAIN_ON"},
+	{"DMIC Capture", NULL, "DMIC_INPUT"},
+};
+
+static const char * const mt8188_dmic_gain_enable_text[] = {
+	"Bypass", "Connect",
+};
+
+static SOC_ENUM_SINGLE_EXT_DECL(dmic_gain_on_enum,
+				mt8188_dmic_gain_enable_text);
+
+static int mtk_dai_dmic_hw_gain_ctrl_put(struct snd_kcontrol *kcontrol,
+					 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
+	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
+	struct mt8188_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_dai_dmic_priv *dmic_priv;
+	unsigned int source = ucontrol->value.enumerated.item[0];
+	unsigned int *cached = 0;
+
+	if (source >= e->items)
+		return -EINVAL;
+
+	dmic_priv = afe_priv->dai_priv[MT8188_AFE_IO_DMIC_IN];
+
+	if (!strcmp(kcontrol->id.name, "DMIC1_HW_GAIN_EN"))
+		cached = &dmic_priv->gain_on[0];
+	else if (!strcmp(kcontrol->id.name, "DMIC2_HW_GAIN_EN"))
+		cached = &dmic_priv->gain_on[1];
+	else if (!strcmp(kcontrol->id.name, "DMIC3_HW_GAIN_EN"))
+		cached = &dmic_priv->gain_on[2];
+	else if (!strcmp(kcontrol->id.name, "DMIC4_HW_GAIN_EN"))
+		cached = &dmic_priv->gain_on[3];
+	else
+		return -EINVAL;
+
+	if (source == *cached)
+		return 0;
+
+	*cached = source;
+	return 1;
+}
+
+static int mtk_dai_dmic_hw_gain_ctrl_get(struct snd_kcontrol *kcontrol,
+					 struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *component =
+		snd_soc_kcontrol_component(kcontrol);
+	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
+	struct mt8188_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_dai_dmic_priv *dmic_priv;
+	unsigned int val = 0;
+
+	dmic_priv = afe_priv->dai_priv[MT8188_AFE_IO_DMIC_IN];
+
+	if (!strcmp(kcontrol->id.name, "DMIC1_HW_GAIN_EN"))
+		val = dmic_priv->gain_on[0];
+	else if (!strcmp(kcontrol->id.name, "DMIC2_HW_GAIN_EN"))
+		val = dmic_priv->gain_on[1];
+	else if (!strcmp(kcontrol->id.name, "DMIC3_HW_GAIN_EN"))
+		val = dmic_priv->gain_on[2];
+	else if (!strcmp(kcontrol->id.name, "DMIC4_HW_GAIN_EN"))
+		val = dmic_priv->gain_on[3];
+
+	ucontrol->value.enumerated.item[0] = val;
+	return 0;
+}
+
+static const struct snd_kcontrol_new mtk_dai_dmic_controls[] = {
+	SOC_ENUM_EXT("DMIC1_HW_GAIN_EN", dmic_gain_on_enum,
+		     mtk_dai_dmic_hw_gain_ctrl_get,
+		     mtk_dai_dmic_hw_gain_ctrl_put),
+	SOC_ENUM_EXT("DMIC2_HW_GAIN_EN", dmic_gain_on_enum,
+		     mtk_dai_dmic_hw_gain_ctrl_get,
+		     mtk_dai_dmic_hw_gain_ctrl_put),
+	SOC_ENUM_EXT("DMIC3_HW_GAIN_EN", dmic_gain_on_enum,
+		     mtk_dai_dmic_hw_gain_ctrl_get,
+		     mtk_dai_dmic_hw_gain_ctrl_put),
+	SOC_ENUM_EXT("DMIC4_HW_GAIN_EN", dmic_gain_on_enum,
+		     mtk_dai_dmic_hw_gain_ctrl_get,
+		     mtk_dai_dmic_hw_gain_ctrl_put),
+	SOC_SINGLE("DMIC1_HW_GAIN_TARGET", DMIC_GAIN1_CON1,
+		   0, DMIC_GAIN_MAX_TARGET, 0),
+	SOC_SINGLE("DMIC2_HW_GAIN_TARGET", DMIC_GAIN2_CON1,
+		   0, DMIC_GAIN_MAX_TARGET, 0),
+	SOC_SINGLE("DMIC3_HW_GAIN_TARGET", DMIC_GAIN3_CON1,
+		   0, DMIC_GAIN_MAX_TARGET, 0),
+	SOC_SINGLE("DMIC4_HW_GAIN_TARGET", DMIC_GAIN4_CON1,
+		   0, DMIC_GAIN_MAX_TARGET, 0),
+	SOC_SINGLE("DMIC1_HW_GAIN_CURRENT", DMIC_GAIN1_CUR,
+		   0, DMIC_GAIN_MAX_CURRENT, 0),
+	SOC_SINGLE("DMIC2_HW_GAIN_CURRENT", DMIC_GAIN2_CUR,
+		   0, DMIC_GAIN_MAX_CURRENT, 0),
+	SOC_SINGLE("DMIC3_HW_GAIN_CURRENT", DMIC_GAIN3_CUR,
+		   0, DMIC_GAIN_MAX_CURRENT, 0),
+	SOC_SINGLE("DMIC4_HW_GAIN_CURRENT", DMIC_GAIN4_CUR,
+		   0, DMIC_GAIN_MAX_CURRENT, 0),
+	SOC_SINGLE("DMIC1_HW_GAIN_UP_STEP", DMIC_GAIN1_CON3,
+		   0, DMIC_GAIN_MAX_STEP, 0),
+	SOC_SINGLE("DMIC2_HW_GAIN_UP_STEP", DMIC_GAIN2_CON3,
+		   0, DMIC_GAIN_MAX_STEP, 0),
+	SOC_SINGLE("DMIC3_HW_GAIN_UP_STEP", DMIC_GAIN3_CON3,
+		   0, DMIC_GAIN_MAX_STEP, 0),
+	SOC_SINGLE("DMIC4_HW_GAIN_UP_STEP", DMIC_GAIN4_CON3,
+		   0, DMIC_GAIN_MAX_STEP, 0),
+	SOC_SINGLE("DMIC1_HW_GAIN_DOWN_STEP", DMIC_GAIN1_CON2,
+		   0, DMIC_GAIN_MAX_STEP, 0),
+	SOC_SINGLE("DMIC2_HW_GAIN_DOWN_STEP", DMIC_GAIN2_CON2,
+		   0, DMIC_GAIN_MAX_STEP, 0),
+	SOC_SINGLE("DMIC3_HW_GAIN_DOWN_STEP", DMIC_GAIN3_CON2,
+		   0, DMIC_GAIN_MAX_STEP, 0),
+	SOC_SINGLE("DMIC4_HW_GAIN_DOWN_STEP", DMIC_GAIN4_CON2,
+		   0, DMIC_GAIN_MAX_STEP, 0),
+	SOC_SINGLE("DMIC1_HW_GAIN_SAMPLE_PER_STEP", DMIC_GAIN1_CON0,
+		   DMIC_GAIN_CON0_SAMPLE_PER_STEP_SHIFT, DMIC_GAIN_MAX_PER_STEP, 0),
+	SOC_SINGLE("DMIC2_HW_GAIN_SAMPLE_PER_STEP", DMIC_GAIN2_CON0,
+		   DMIC_GAIN_CON0_SAMPLE_PER_STEP_SHIFT, DMIC_GAIN_MAX_PER_STEP, 0),
+	SOC_SINGLE("DMIC3_HW_GAIN_SAMPLE_PER_STEP", DMIC_GAIN3_CON0,
+		   DMIC_GAIN_CON0_SAMPLE_PER_STEP_SHIFT, DMIC_GAIN_MAX_PER_STEP, 0),
+	SOC_SINGLE("DMIC4_HW_GAIN_SAMPLE_PER_STEP", DMIC_GAIN4_CON0,
+		   DMIC_GAIN_CON0_SAMPLE_PER_STEP_SHIFT, DMIC_GAIN_MAX_PER_STEP, 0),
+};
+
+static int init_dmic_priv_data(struct mtk_base_afe *afe)
+{
+	struct mt8188_afe_private *afe_priv = afe->platform_priv;
+	struct mtk_dai_dmic_priv *dmic_priv;
+
+	dmic_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_dmic_priv),
+				 GFP_KERNEL);
+	if (!dmic_priv)
+		return -ENOMEM;
+
+	afe_priv->dai_priv[MT8188_AFE_IO_DMIC_IN] = dmic_priv;
+	return 0;
+}
+
+int mt8188_dai_dmic_register(struct mtk_base_afe *afe)
+{
+	struct mtk_base_afe_dai *dai;
+
+	dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
+	if (!dai)
+		return -ENOMEM;
+
+	list_add(&dai->list, &afe->sub_dais);
+
+	dai->dai_drivers = mtk_dai_dmic_driver;
+	dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_dmic_driver);
+	dai->dapm_widgets = mtk_dai_dmic_widgets;
+	dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_dmic_widgets);
+	dai->dapm_routes = mtk_dai_dmic_routes;
+	dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_dmic_routes);
+	dai->controls = mtk_dai_dmic_controls;
+	dai->num_controls = ARRAY_SIZE(mtk_dai_dmic_controls);
+
+	return init_dmic_priv_data(afe);
+}
diff --git a/sound/soc/mediatek/mt8188/mt8188-reg.h b/sound/soc/mediatek/mt8188/mt8188-reg.h
index bdd885419ff3874bab80549ea3ff4617172b8245..4154548aca36108667036f9889476c30f9b6171a 100644
--- a/sound/soc/mediatek/mt8188/mt8188-reg.h
+++ b/sound/soc/mediatek/mt8188/mt8188-reg.h
@@ -2837,9 +2837,20 @@
 #define PWR2_TOP_CON_DMIC3_SRC_SEL_MASK     GENMASK(16, 14)
 #define PWR2_TOP_CON_DMIC2_SRC_SEL_MASK     GENMASK(13, 11)
 #define PWR2_TOP_CON_DMIC1_SRC_SEL_MASK     GENMASK(10, 8)
+#define PWR2_TOP_CON_DMIC8_SRC_SEL_VAL(x)   ((x) << 29)
+#define PWR2_TOP_CON_DMIC7_SRC_SEL_VAL(x)   ((x) << 26)
+#define PWR2_TOP_CON_DMIC6_SRC_SEL_VAL(x)   ((x) << 23)
+#define PWR2_TOP_CON_DMIC5_SRC_SEL_VAL(x)   ((x) << 20)
+#define PWR2_TOP_CON_DMIC4_SRC_SEL_VAL(x)   ((x) << 17)
+#define PWR2_TOP_CON_DMIC3_SRC_SEL_VAL(x)   ((x) << 14)
+#define PWR2_TOP_CON_DMIC2_SRC_SEL_VAL(x)   ((x) << 11)
+#define PWR2_TOP_CON_DMIC1_SRC_SEL_VAL(x)   ((x) << 8)
 
 /* PWR2_TOP_CON1 */
-#define PWR2_TOP_CON1_DMIC_CKDIV_ON        BIT(1)
+#define PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(x)	BIT((5 + 6 * x))
+#define PWR2_TOP_CON1_DMIC_CKDIV_ON             BIT(1)
+#define PWR2_TOP_CON1_DMIC_CKDIV_ON_SHIFT       1
+
 
 /* PCM_INTF_CON1 */
 #define PCM_INTF_CON1_SYNC_OUT_INV     BIT(23)
@@ -2919,15 +2930,17 @@
 #define AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_CH2(x)	(((x) & 0x7) << 24)
 #define AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_MASK		GENMASK(29, 24)
 #define AFE_DMIC_UL_SRC_CON0_UL_TWO_WIRE_MODE_CTL	BIT(23)
+#define AFE_DMIC_UL_SRC_CON0_UL_TWO_WIRE_MODE_CTL_MASK  BIT(23)
 #define AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH2_CTL	BIT(22)
 #define AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH1_CTL	BIT(21)
-
+#define AFE_DMIC_UL_VOICE_MODE(x)			(((x) & 0x7) << 17)
 #define AFE_DMIC_UL_VOICE_MODE_MASK			GENMASK(19, 17)
 #define AFE_DMIC_UL_CON0_VOCIE_MODE_8K			AFE_DMIC_UL_VOICE_MODE(0)
 #define AFE_DMIC_UL_CON0_VOCIE_MODE_16K			AFE_DMIC_UL_VOICE_MODE(1)
 #define AFE_DMIC_UL_CON0_VOCIE_MODE_32K			AFE_DMIC_UL_VOICE_MODE(2)
 #define AFE_DMIC_UL_CON0_VOCIE_MODE_48K			AFE_DMIC_UL_VOICE_MODE(3)
 #define AFE_DMIC_UL_CON0_VOCIE_MODE_96K			AFE_DMIC_UL_VOICE_MODE(4)
+#define AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL(x)		(((x) & 0x7) << 7)
 #define AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL_MASK	GENMASK(9, 7)
 #define AFE_DMIC_UL_SRC_CON0_UL_IIR_ON_TMP_CTL		BIT(10)
 #define AFE_DMIC_UL_SRC_CON0_UL_SDM_3_LEVEL_CTL		BIT(1)
@@ -2944,6 +2957,7 @@
 
 /* DMIC_GAINx_CON0 */
 #define DMIC_GAIN_CON0_GAIN_ON			BIT(0)
+#define DMIC_GAIN_CON0_SAMPLE_PER_STEP_SHIFT	8
 #define DMIC_GAIN_CON0_SAMPLE_PER_STEP_MASK	GENMASK(15, 8)
 
 /* DMIC_GAINx_CON1 */

-- 
2.48.1

[PATCH 4/6] ASoC: mediatek: mt8188: Support DMIC in AFE

[Nícolas F. R. A. Prado]

From: parkeryang <Parker.Yang@mediatek.com>

Add the AFE routes that connect the DMIC (I004-I011) to the UL9 frontend
(O002-O009) and register the mt8188-dmic DAI driver during probe.

Signed-off-by: parkeryang <Parker.Yang@mediatek.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
 sound/soc/mediatek/mt8188/Makefile            |  1 +
 sound/soc/mediatek/mt8188/mt8188-afe-common.h |  1 +
 sound/soc/mediatek/mt8188/mt8188-afe-pcm.c    | 24 ++++++++++++++++++++++++
 3 files changed, 26 insertions(+)

diff --git a/sound/soc/mediatek/mt8188/Makefile b/sound/soc/mediatek/mt8188/Makefile
index 1178bce45c50ba252672a32b3877732a5a76c610..b9f3e4ad7b07ba9e21c846706371c53269f894db 100644
--- a/sound/soc/mediatek/mt8188/Makefile
+++ b/sound/soc/mediatek/mt8188/Makefile
@@ -6,6 +6,7 @@ snd-soc-mt8188-afe-y := \
 	mt8188-afe-pcm.o \
 	mt8188-audsys-clk.o \
 	mt8188-dai-adda.o \
+	mt8188-dai-dmic.o \
 	mt8188-dai-etdm.o \
 	mt8188-dai-pcm.o
 
diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-common.h b/sound/soc/mediatek/mt8188/mt8188-afe-common.h
index 1304d685a306bcb43b5131eff165b80051810b04..01aa11242e29c51539903fd1decc4c575d5e97bd 100644
--- a/sound/soc/mediatek/mt8188/mt8188-afe-common.h
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-common.h
@@ -137,6 +137,7 @@ struct mt8188_afe_private {
 int mt8188_afe_fs_timing(unsigned int rate);
 /* dai register */
 int mt8188_dai_adda_register(struct mtk_base_afe *afe);
+int mt8188_dai_dmic_register(struct mtk_base_afe *afe);
 int mt8188_dai_etdm_register(struct mtk_base_afe *afe);
 int mt8188_dai_pcm_register(struct mtk_base_afe *afe);
 
diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c b/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
index d36520c6272dd8c8302bc3f59da33f82f273f366..a2b57e00ff4e502bfd8bc57835b792825f348c1b 100644
--- a/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
+++ b/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
@@ -652,6 +652,7 @@ static struct snd_soc_dai_driver mt8188_memif_dai_driver[] = {
 
 static const struct snd_kcontrol_new o002_mix[] = {
 	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN2, 0, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I004 Switch", AFE_CONN2, 4, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I012 Switch", AFE_CONN2, 12, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN2, 20, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN2, 22, 1, 0),
@@ -662,6 +663,8 @@ static const struct snd_kcontrol_new o002_mix[] = {
 
 static const struct snd_kcontrol_new o003_mix[] = {
 	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN3, 1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I005 Switch", AFE_CONN3, 5, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I006 Switch", AFE_CONN3, 6, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I013 Switch", AFE_CONN3, 13, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN3, 21, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN3, 23, 1, 0),
@@ -672,6 +675,8 @@ static const struct snd_kcontrol_new o003_mix[] = {
 
 static const struct snd_kcontrol_new o004_mix[] = {
 	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN4, 0, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I006 Switch", AFE_CONN4, 6, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I008 Switch", AFE_CONN4, 8, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I014 Switch", AFE_CONN4, 14, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN4, 24, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I074 Switch", AFE_CONN4_2, 10, 1, 0),
@@ -679,6 +684,8 @@ static const struct snd_kcontrol_new o004_mix[] = {
 
 static const struct snd_kcontrol_new o005_mix[] = {
 	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN5, 1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I007 Switch", AFE_CONN5, 7, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I010 Switch", AFE_CONN5, 10, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I015 Switch", AFE_CONN5, 15, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN5, 25, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I075 Switch", AFE_CONN5_2, 11, 1, 0),
@@ -686,6 +693,7 @@ static const struct snd_kcontrol_new o005_mix[] = {
 
 static const struct snd_kcontrol_new o006_mix[] = {
 	SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN6, 0, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I008 Switch", AFE_CONN6, 8, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I016 Switch", AFE_CONN6, 16, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN6, 26, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I076 Switch", AFE_CONN6_2, 12, 1, 0),
@@ -693,18 +701,21 @@ static const struct snd_kcontrol_new o006_mix[] = {
 
 static const struct snd_kcontrol_new o007_mix[] = {
 	SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN7, 1, 1, 0),
+	SOC_DAPM_SINGLE_AUTODISABLE("I009 Switch", AFE_CONN7, 9, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I017 Switch", AFE_CONN7, 17, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN7, 27, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I077 Switch", AFE_CONN7_2, 13, 1, 0),
 };
 
 static const struct snd_kcontrol_new o008_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("I010 Switch", AFE_CONN8, 10, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I018 Switch", AFE_CONN8, 18, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN8, 28, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I078 Switch", AFE_CONN8_2, 14, 1, 0),
 };
 
 static const struct snd_kcontrol_new o009_mix[] = {
+	SOC_DAPM_SINGLE_AUTODISABLE("I011 Switch", AFE_CONN9, 11, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I019 Switch", AFE_CONN9, 19, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN9, 29, 1, 0),
 	SOC_DAPM_SINGLE_AUTODISABLE("I079 Switch", AFE_CONN9_2, 15, 1, 0),
@@ -1275,6 +1286,18 @@ static const struct snd_soc_dapm_route mt8188_memif_routes[] = {
 	{"O002", "I070 Switch", "I070"},
 	{"O003", "I071 Switch", "I071"},
 
+	{"O002", "I004 Switch", "I004"},
+	{"O003", "I005 Switch", "I005"},
+	{"O003", "I006 Switch", "I006"},
+	{"O004", "I006 Switch", "I006"},
+	{"O004", "I008 Switch", "I008"},
+	{"O005", "I007 Switch", "I007"},
+	{"O005", "I010 Switch", "I010"},
+	{"O006", "I008 Switch", "I008"},
+	{"O007", "I009 Switch", "I009"},
+	{"O008", "I010 Switch", "I010"},
+	{"O009", "I011 Switch", "I011"},
+
 	{"O034", "I000 Switch", "I000"},
 	{"O035", "I001 Switch", "I001"},
 	{"O034", "I002 Switch", "I002"},
@@ -3072,6 +3095,7 @@ static int mt8188_dai_memif_register(struct mtk_base_afe *afe)
 typedef int (*dai_register_cb)(struct mtk_base_afe *);
 static const dai_register_cb dai_register_cbs[] = {
 	mt8188_dai_adda_register,
+	mt8188_dai_dmic_register,
 	mt8188_dai_etdm_register,
 	mt8188_dai_pcm_register,
 	mt8188_dai_memif_register,

-- 
2.48.1

[PATCH 5/6] ASoC: mediatek: mt8188-mt6359: Add DMIC

[Nícolas F. R. A. Prado]

Add the DMIC backend, which connects to the DMIC DAI in the platform
driver, as well as a "AP DMIC" mic widget. On the Genio 700 EVK board
the dual DMIC on-board are wired through that DMIC DAI.

Co-developed-by: parkeryang <Parker.Yang@mediatek.com>
Signed-off-by: parkeryang <Parker.Yang@mediatek.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
 sound/soc/mediatek/mt8188/mt8188-mt6359.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/sound/soc/mediatek/mt8188/mt8188-mt6359.c b/sound/soc/mediatek/mt8188/mt8188-mt6359.c
index 2d0d04e0232da07ba43a030b14853322427d55e7..420b1427b71dc1424a52f7ab6140c14659036733 100644
--- a/sound/soc/mediatek/mt8188/mt8188-mt6359.c
+++ b/sound/soc/mediatek/mt8188/mt8188-mt6359.c
@@ -150,6 +150,11 @@ SND_SOC_DAILINK_DEFS(dl_src,
 						   "mt6359-snd-codec-aif1")),
 		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
 
+SND_SOC_DAILINK_DEFS(DMIC_BE,
+		     DAILINK_COMP_ARRAY(COMP_CPU("DMIC")),
+		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
+		     DAILINK_COMP_ARRAY(COMP_EMPTY()));
+
 SND_SOC_DAILINK_DEFS(dptx,
 		     DAILINK_COMP_ARRAY(COMP_CPU("DPTX")),
 		     DAILINK_COMP_ARRAY(COMP_DUMMY()),
@@ -297,6 +302,7 @@ static const struct snd_soc_dapm_widget mt8188_rear_spk_widgets[] = {
 static const struct snd_soc_dapm_widget mt8188_mt6359_widgets[] = {
 	SND_SOC_DAPM_HP("Headphone", NULL),
 	SND_SOC_DAPM_MIC("Headset Mic", NULL),
+	SND_SOC_DAPM_MIC("AP DMIC", NULL),
 	SND_SOC_DAPM_SINK("HDMI"),
 	SND_SOC_DAPM_SINK("DP"),
 	SND_SOC_DAPM_MIXER(SOF_DMA_DL2, SND_SOC_NOPM, 0, 0, NULL, 0),
@@ -533,6 +539,7 @@ enum {
 	DAI_LINK_UL9_FE,
 	DAI_LINK_UL10_FE,
 	DAI_LINK_DL_SRC_BE,
+	DAI_LINK_DMIC_BE,
 	DAI_LINK_DPTX_BE,
 	DAI_LINK_ETDM1_IN_BE,
 	DAI_LINK_ETDM2_IN_BE,
@@ -1120,6 +1127,13 @@ static struct snd_soc_dai_link mt8188_mt6359_dai_links[] = {
 		.playback_only = 1,
 		SND_SOC_DAILINK_REG(dl_src),
 	},
+	[DAI_LINK_DMIC_BE] = {
+		.name = "DMIC_BE",
+		.no_pcm = 1,
+		.capture_only = 1,
+		.ignore_suspend = 1,
+		SND_SOC_DAILINK_REG(DMIC_BE),
+	},
 	[DAI_LINK_DPTX_BE] = {
 		.name = "DPTX_BE",
 		.ops = &mt8188_dptx_ops,

-- 
2.48.1

[PATCH 6/6] arm64: dts: mediatek: mt8390-genio-common: Add routes for DMIC

[Nícolas F. R. A. Prado]

Add necessary routes for the onboard dual DMIC present on the Genio
700/510 EVK. The dmic is supplied by micbias0 and micbias2, and inputs
into the MT8188 DMIC DAI.

Co-developed-by: parkeryang <Parker.Yang@mediatek.com>
Signed-off-by: parkeryang <Parker.Yang@mediatek.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
---
 arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
index a37cf102a6e928440cc88e7e8fe0225fc28ec962..efdeca88b8c4e58f0c17825156276babf19af145 100644
--- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
@@ -959,7 +959,11 @@ &sound {
 	pinctrl-0 = <&audio_default_pins>;
 	audio-routing =
 		"Headphone", "Headphone L",
-		"Headphone", "Headphone R";
+		"Headphone", "Headphone R",
+		"DMIC_INPUT", "AP DMIC",
+		"AP DMIC", "AUDGLB",
+		"AP DMIC", "MIC_BIAS_0",
+		"AP DMIC", "MIC_BIAS_2";
 	mediatek,adsp = <&adsp>;
 	status = "okay";
 

-- 
2.48.1

Re: [PATCH 6/6] arm64: dts: mediatek: mt8390-genio-common: Add routes for DMIC

[Chen-Yu Tsai]

On Wed, Feb 19, 2025 at 5:27 AM Nícolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
> Add necessary routes for the onboard dual DMIC present on the Genio
> 700/510 EVK. The dmic is supplied by micbias0 and micbias2, and inputs
> into the MT8188 DMIC DAI.
>
> Co-developed-by: parkeryang <Parker.Yang@mediatek.com>
> Signed-off-by: parkeryang <Parker.Yang@mediatek.com>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
> index a37cf102a6e928440cc88e7e8fe0225fc28ec962..efdeca88b8c4e58f0c17825156276babf19af145 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
> @@ -959,7 +959,11 @@ &sound {
>         pinctrl-0 = <&audio_default_pins>;
>         audio-routing =
>                 "Headphone", "Headphone L",
> -               "Headphone", "Headphone R";
> +               "Headphone", "Headphone R",
> +               "DMIC_INPUT", "AP DMIC",
> +               "AP DMIC", "AUDGLB",
> +               "AP DMIC", "MIC_BIAS_0",
> +               "AP DMIC", "MIC_BIAS_2";
>         mediatek,adsp = <&adsp>;
>         status = "okay";

Shouldn't there also be one or two new dmic-codecs, and a dai-link here?

ChenYu

>
> --
> 2.48.1
>
>

Re: [PATCH 6/6] arm64: dts: mediatek: mt8390-genio-common: Add routes for DMIC

[AngeloGioacchino Del Regno]

Il 18/02/25 21:52, Nícolas F. R. A. Prado ha scritto:
> Add necessary routes for the onboard dual DMIC present on the Genio
> 700/510 EVK. The dmic is supplied by micbias0 and micbias2, and inputs
> into the MT8188 DMIC DAI.
> 
> Co-developed-by: parkeryang <Parker.Yang@mediatek.com>
> Signed-off-by: parkeryang <Parker.Yang@mediatek.com>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH 4/6] ASoC: mediatek: mt8188: Support DMIC in AFE

[AngeloGioacchino Del Regno]

Il 18/02/25 21:52, Nícolas F. R. A. Prado ha scritto:
> From: parkeryang <Parker.Yang@mediatek.com>
> 
> Add the AFE routes that connect the DMIC (I004-I011) to the UL9 frontend
> (O002-O009) and register the mt8188-dmic DAI driver during probe.
> 
> Signed-off-by: parkeryang <Parker.Yang@mediatek.com>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---
>   sound/soc/mediatek/mt8188/Makefile            |  1 +
>   sound/soc/mediatek/mt8188/mt8188-afe-common.h |  1 +
>   sound/soc/mediatek/mt8188/mt8188-afe-pcm.c    | 24 ++++++++++++++++++++++++
>   3 files changed, 26 insertions(+)
> 
> diff --git a/sound/soc/mediatek/mt8188/Makefile b/sound/soc/mediatek/mt8188/Makefile
> index 1178bce45c50ba252672a32b3877732a5a76c610..b9f3e4ad7b07ba9e21c846706371c53269f894db 100644
> --- a/sound/soc/mediatek/mt8188/Makefile
> +++ b/sound/soc/mediatek/mt8188/Makefile
> @@ -6,6 +6,7 @@ snd-soc-mt8188-afe-y := \
>   	mt8188-afe-pcm.o \
>   	mt8188-audsys-clk.o \
>   	mt8188-dai-adda.o \
> +	mt8188-dai-dmic.o \
>   	mt8188-dai-etdm.o \
>   	mt8188-dai-pcm.o

The Makefile addition doesn't belong to this commit. Please fix.

The rest looks good.

Cheers,
Angelo

Re: [PATCH 3/6] ASoC: mediatek: mt8188: Add DMIC DAI driver

[AngeloGioacchino Del Regno]

Il 18/02/25 21:52, Nícolas F. R. A. Prado ha scritto:
> From: parkeryang <Parker.Yang@mediatek.com>
> 
> Add support for the DMIC DAIs present on the MT8188 SoC.
> 
> Signed-off-by: parkeryang <Parker.Yang@mediatek.com>
> Co-developed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---
>   sound/soc/mediatek/mt8188/mt8188-afe-pcm.c  |   4 -
>   sound/soc/mediatek/mt8188/mt8188-dai-dmic.c | 754 ++++++++++++++++++++++++++++
>   sound/soc/mediatek/mt8188/mt8188-reg.h      |  18 +-
>   3 files changed, 770 insertions(+), 6 deletions(-)
> 
> diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c b/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
> index 73e5c63aeec8783905d656af225c42cd95069049..d36520c6272dd8c8302bc3f59da33f82f273f366 100644
> --- a/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
> +++ b/sound/soc/mediatek/mt8188/mt8188-afe-pcm.c
> @@ -2855,10 +2855,6 @@ static bool mt8188_is_volatile_reg(struct device *dev, unsigned int reg)
>   	case AFE_DMIC3_SRC_DEBUG_MON0:
>   	case AFE_DMIC3_UL_SRC_MON0:
>   	case AFE_DMIC3_UL_SRC_MON1:
> -	case DMIC_GAIN1_CUR:
> -	case DMIC_GAIN2_CUR:
> -	case DMIC_GAIN3_CUR:
> -	case DMIC_GAIN4_CUR:

Why are you removing those?!

If you really have to, that goes into a different commit.

>   	case ETDM_IN1_MONITOR:
>   	case ETDM_IN2_MONITOR:
>   	case ETDM_OUT1_MONITOR:
> diff --git a/sound/soc/mediatek/mt8188/mt8188-dai-dmic.c b/sound/soc/mediatek/mt8188/mt8188-dai-dmic.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..9df08783ff80173095809c20538d0fb073ed7fae
> --- /dev/null
> +++ b/sound/soc/mediatek/mt8188/mt8188-dai-dmic.c
> @@ -0,0 +1,754 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * MediaTek ALSA SoC Audio DAI DMIC I/F Control
> + *
> + * Copyright (c) 2020 MediaTek Inc.
> + * Author: Bicycle Tsai <bicycle.tsai@mediatek.com>
> + *         Trevor Wu <trevor.wu@mediatek.com>
> + *         Parker Yang <parker.yang@mediatek.com>
> + */
> +

..snip..

> +
> +static void mtk_dai_dmic_hw_gain_on(struct mtk_base_afe *afe,
> +				    unsigned int id, bool on)
> +{
> +	const struct mtk_dai_dmic_hw_gain_ctrl_reg *reg;
> +	unsigned int msk = DMIC_GAIN_CON0_GAIN_ON;

msk never changes here, just use that definition directly in the regmap calls
below.... and also, reg can be NULL, but you're not checking that, which may
result in a kernel panic.

So this function should look like....

static void mtk_dai_dmic_hw_gain_on(struct mtk_base_afe *afe,
				    unsigned int id, bool on)
{
	const struct mtk_dai_dmic_hw_gain_ctrl_reg *reg = get_dmic_hw_gain_ctrl_reg(afe, id);

	if (!reg)
		return;

	if (on)
		regmap_set_bits(afe->regmap, reg->con0, DMIC_GAIN_CON0_GAIN_ON);
	else
		regmap_clear_bits( ....)
};


> +
> +	reg = get_dmic_hw_gain_ctrl_reg(afe, id);
> +	if (!reg)
> +		return;
> +
> +	if (on)
> +		regmap_set_bits(afe->regmap, reg->con0, msk);
> +	else
> +		regmap_clear_bits(afe->regmap, reg->con0, msk);
> +}
> +

..snip..

> +
> +static int mtk_dai_dmic_configure_array(struct snd_soc_dai *dai)
> +{
> +	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
> +	struct mt8188_afe_private *afe_priv = afe->platform_priv;
> +	struct mtk_dai_dmic_priv *dmic_priv = NULL;
> +	unsigned int mask =
> +			PWR2_TOP_CON_DMIC8_SRC_SEL_MASK |
> +			PWR2_TOP_CON_DMIC7_SRC_SEL_MASK |
> +			PWR2_TOP_CON_DMIC6_SRC_SEL_MASK |
> +			PWR2_TOP_CON_DMIC5_SRC_SEL_MASK |
> +			PWR2_TOP_CON_DMIC4_SRC_SEL_MASK |
> +			PWR2_TOP_CON_DMIC3_SRC_SEL_MASK |
> +			PWR2_TOP_CON_DMIC2_SRC_SEL_MASK |
> +			PWR2_TOP_CON_DMIC1_SRC_SEL_MASK;

const u32 mask = ....

> +	unsigned int val = 0;

const u32 val = PWR2_TOP_CON ......

> +
> +	if (dai->id < 0)
> +		return -EINVAL;
> +
> +	dmic_priv = afe_priv->dai_priv[dai->id];
> +	val = PWR2_TOP_CON_DMIC8_SRC_SEL_VAL(DMIC8_SRC_SEL) |
> +	      PWR2_TOP_CON_DMIC7_SRC_SEL_VAL(DMIC7_SRC_SEL) |
> +	      PWR2_TOP_CON_DMIC6_SRC_SEL_VAL(DMIC6_SRC_SEL) |
> +	      PWR2_TOP_CON_DMIC5_SRC_SEL_VAL(DMIC5_SRC_SEL) |
> +	      PWR2_TOP_CON_DMIC4_SRC_SEL_VAL(DMIC4_SRC_SEL) |
> +	      PWR2_TOP_CON_DMIC3_SRC_SEL_VAL(DMIC3_SRC_SEL) |
> +	      PWR2_TOP_CON_DMIC2_SRC_SEL_VAL(DMIC2_SRC_SEL) |
> +	      PWR2_TOP_CON_DMIC1_SRC_SEL_VAL(DMIC1_SRC_SEL);
> +
> +	regmap_update_bits(afe->regmap, PWR2_TOP_CON0, mask, val);
> +
> +	return 0;
> +}
> +
> +static void mtk_dai_dmic_hw_gain_enable(struct mtk_base_afe *afe,
> +					unsigned int channels, bool enable)
> +{
> +	struct mt8188_afe_private *afe_priv = afe->platform_priv;
> +	struct mtk_dai_dmic_priv *dmic_priv;
> +	unsigned int end;
> +	unsigned int id;
> +
> +	if (!channels)
> +		return;
> +
> +	dmic_priv = afe_priv->dai_priv[MT8188_AFE_IO_DMIC_IN];
> +	if (channels > 3)
> +		end = 3;

	else
		end = channels - 1;

way shorter :-)

> +	else if (channels > 2)
> +		end = 2;
> +	else if (channels > 1)
> +		end = 1;
> +	else if (channels > 0)
> +		end = 0;
> +
> +	for (id = DMIC0; id <= end; id++) {
> +		if (enable && dmic_priv->gain_on[id]) {
> +			mtk_dai_dmic_hw_gain_byass(afe, id, false);

by...what? LOL! :-)

That typo is hilarious, but still fix it.

> +			mtk_dai_dmic_hw_gain_on(afe, id, true);
> +		} else {
> +			mtk_dai_dmic_hw_gain_on(afe, id, false);
> +			mtk_dai_dmic_hw_gain_byass(afe, id, true);
> +		}
> +	}
> +}
> +
> +static int mtk_dmic_gain_event(struct snd_soc_dapm_widget *w,
> +			       struct snd_kcontrol *kcontrol,
> +			       int event)
> +{
> +	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
> +	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
> +	struct mt8188_afe_private *afe_priv = afe->platform_priv;
> +	struct mtk_dai_dmic_priv *dmic_priv = NULL;
> +	unsigned int channels;
> +
> +	dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
> +		__func__, w->name, event);
> +
> +	dmic_priv = afe_priv->dai_priv[MT8188_AFE_IO_DMIC_IN];
> +	channels = dmic_priv->channels;

Either you check if afe_priv is NULL before assigning, or just stack-assign these.

> +
> +	switch (event) {
> +	case SND_SOC_DAPM_PRE_PMU:
> +		mtk_dai_dmic_hw_gain_enable(afe, channels, true);
> +		break;
> +	case SND_SOC_DAPM_POST_PMD:
> +		mtk_dai_dmic_hw_gain_enable(afe, channels, false);
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	return 0;
> +}
> +
> +static int mtk_dmic_event(struct snd_soc_dapm_widget *w,
> +			  struct snd_kcontrol *kcontrol,
> +			  int event)
> +{
> +	struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
> +	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
> +	struct mt8188_afe_private *afe_priv = afe->platform_priv;
> +	struct mtk_dai_dmic_priv *dmic_priv = NULL;
> +	const struct mtk_dai_dmic_ctrl_reg *reg = NULL;
> +	unsigned int channels;
> +	unsigned int msk;

	u8 dmic_num;

> +
> +	dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
> +		__func__, w->name, event);
> +
> +	dmic_priv = afe_priv->dai_priv[MT8188_AFE_IO_DMIC_IN];
> +	channels = dmic_priv->channels;
> +

if (channels == 0) {
	dev_dbg(something);
	return -EINVAL;
}



/* This function assumes that the caller checked that channels is valid */
static u8 mtk_dmic_channels_to_dmic_number_or_another_name_you_choose(unsigned int 
channels)
{
	switch (channels) {
	case 1:
		return DMIC0;
	case 2:
		return DMIC1;
	case 3:
		return DMIC2;
	case 4:
	default:
		return DMIC3;
	}
}


dmic_num = mtk_dmic_channels_to_dmic_number_or_another_name_you_choose(channels);

> +	switch (event) {
> +	case SND_SOC_DAPM_PRE_PMU:
> +		/* request fifo soft rst */
> +		msk = 0;

for (i = dmic_num; i > 0; i--)
	msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(i);

> +		if (channels > 3)
> +			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC3);
> +		if (channels > 2)
> +			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC2);
> +		if (channels > 1)
> +			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC1);
> +		if (channels > 0)
> +			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC0);
> +
> +		regmap_set_bits(afe->regmap, PWR2_TOP_CON1, msk);
> +
> +		msk = 0;

msk = AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH1_CTL |
       AFE_DMIC_UL ....

> +		msk |= AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH1_CTL;
> +		msk |= AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH2_CTL;
> +		msk |= AFE_DMIC_UL_SRC_CON0_UL_SDM_3_LEVEL_CTL;
> +		msk |= AFE_DMIC_UL_SRC_CON0_UL_IIR_ON_TMP_CTL;
> +

reg = get_dmic_ctrl_reg(dmic_num);
if (reg)
	regmap_set_bits .....

> +		if (channels > 3) {
> +			reg = get_dmic_ctrl_reg(DMIC3);
> +			if (reg)
> +				regmap_set_bits(afe->regmap, reg->con0, msk);
> +		}
> +		if (channels > 2) {
> +			reg = get_dmic_ctrl_reg(DMIC2);
> +			if (reg)
> +				regmap_set_bits(afe->regmap, reg->con0, msk);
> +		}
> +		if (channels > 1) {
> +			reg = get_dmic_ctrl_reg(DMIC1);
> +			if (reg)
> +				regmap_set_bits(afe->regmap, reg->con0, msk);
> +		}
> +		if (channels > 0) {
> +			reg = get_dmic_ctrl_reg(DMIC0);
> +			if (reg)
> +				regmap_set_bits(afe->regmap, reg->con0, msk);
> +		}
> +		break;
> +	case SND_SOC_DAPM_POST_PMU:
> +		msk = AFE_DMIC_UL_SRC_CON0_UL_SRC_ON_TMP_CTL;

same comments apply here.

> +		if (channels > 3) {
> +			reg = get_dmic_ctrl_reg(DMIC3);
> +			if (reg)
> +				regmap_set_bits(afe->regmap, reg->con0, msk);
> +		}
> +		if (channels > 2) {
> +			reg = get_dmic_ctrl_reg(DMIC2);
> +			if (reg)
> +				regmap_set_bits(afe->regmap, reg->con0, msk);
> +		}
> +		if (channels > 1) {
> +			reg = get_dmic_ctrl_reg(DMIC1);
> +			if (reg)
> +				regmap_set_bits(afe->regmap, reg->con0, msk);
> +		}
> +		if (channels > 0) {
> +			reg = get_dmic_ctrl_reg(DMIC0);
> +			if (reg)
> +				regmap_set_bits(afe->regmap, reg->con0, msk);
> +		}
> +
> +		if (dmic_priv->hires_required) {
> +			mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES1]);
> +			mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES2]);
> +			mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES3]);
> +			mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES4]);
> +		}
> +
> +		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC1]);
> +		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC2]);
> +		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC3]);
> +		mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC4]);
> +
> +		/* release fifo soft rst */
> +		msk = 0;

for (i = dmic_num; i .... same as before
msk |= MACRO(i)

> +		if (channels > 3)
> +			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC3);
> +		if (channels > 2)
> +			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC2);
> +		if (channels > 1)
> +			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC1);
> +		if (channels > 0)
> +			msk |= PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(DMIC0);
> +
> +		regmap_clear_bits(afe->regmap, PWR2_TOP_CON1, msk);
> +		break;
> +	case SND_SOC_DAPM_PRE_PMD:
> +		msk =  AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH1_CTL |
> +			AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH2_CTL |
> +			AFE_DMIC_UL_SRC_CON0_UL_SRC_ON_TMP_CTL |
> +			AFE_DMIC_UL_SRC_CON0_UL_IIR_ON_TMP_CTL |
> +			AFE_DMIC_UL_SRC_CON0_UL_SDM_3_LEVEL_CTL;
> +

same fixes apply here.

> +		if (channels > 3) {
> +			reg = get_dmic_ctrl_reg(DMIC3);
> +			if (reg)
> +				regmap_clear_bits(afe->regmap, reg->con0, msk);
> +		}
> +		if (channels > 2) {
> +			reg = get_dmic_ctrl_reg(DMIC2);
> +			if (reg)
> +				regmap_clear_bits(afe->regmap, reg->con0, msk);
> +		}
> +		if (channels > 1) {
> +			reg = get_dmic_ctrl_reg(DMIC1);
> +			if (reg)
> +				regmap_clear_bits(afe->regmap, reg->con0, msk);
> +		}
> +		if (channels > 0) {
> +			reg = get_dmic_ctrl_reg(DMIC0);
> +			if (reg)
> +				regmap_clear_bits(afe->regmap, reg->con0, msk);
> +		}
> +		break;
> +	case SND_SOC_DAPM_POST_PMD:
> +		/* should delayed 1/fs(smallest is 8k) = 125us before afe off */
> +		usleep_range(125, 126);
> +
> +		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC1]);
> +		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC2]);
> +		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC3]);
> +		mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE_DMIC4]);
> +
> +		if (dmic_priv->hires_required) {
> +			mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES1]);
> +			mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES2]);
> +			mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES3]);
> +			mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_DMIC_HIRES4]);
> +		}
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	return 0;
> +}
> +
> +static int mtk_dai_dmic_hw_params(struct snd_pcm_substream *substream,
> +				  struct snd_pcm_hw_params *params,
> +				  struct snd_soc_dai *dai)
> +{
> +	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
> +	struct mt8188_afe_private *afe_priv = afe->platform_priv;
> +	struct mtk_dai_dmic_priv *dmic_priv = NULL;
> +	unsigned int rate = params_rate(params);
> +	unsigned int channels = params_channels(params);
> +	const struct mtk_dai_dmic_ctrl_reg *reg = NULL;
> +	unsigned int val = 0;
> +	unsigned int msk = 0;
> +
> +	if (dai->id < 0)
> +		return -EINVAL;
> +
> +	dmic_priv = afe_priv->dai_priv[dai->id];
> +
> +	val = AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_CH1(CLK_PHASE_SEL_CH1) |
> +	      AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_CH2(CLK_PHASE_SEL_CH2) |
> +	      AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL(0);
> +	msk = AFE_DMIC_UL_SRC_CON0_UL_TWO_WIRE_MODE_CTL_MASK |
> +	      AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_MASK |
> +	      AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL_MASK |
> +	      AFE_DMIC_UL_VOICE_MODE_MASK;

double assignment of both val and msk. fix it.

> +
> +	mtk_dai_dmic_configure_array(dai);
> +	dmic_priv->hires_required = 0;

repeat that assignment in all rate cases, don't do double assignments.

> +
> +	switch (rate) {
> +	case 96000:
> +		val |= AFE_DMIC_UL_CON0_VOCIE_MODE_96K;
> +		dmic_priv->hires_required = 1;
> +		break;
> +	case 48000:
> +		val |= AFE_DMIC_UL_CON0_VOCIE_MODE_48K;
> +		break;
> +	case 32000:
> +		val |= AFE_DMIC_UL_CON0_VOCIE_MODE_32K;
> +		break;
> +	case 16000:
> +		val |= AFE_DMIC_UL_CON0_VOCIE_MODE_16K;
> +		break;
> +	case 8000:
> +		val |= AFE_DMIC_UL_CON0_VOCIE_MODE_8K;
> +		break;
> +	default:
> +		dev_dbg(afe->dev, "%s invalid rate %u, use 48000Hz\n", __func__, rate);
> +		val |= AFE_DMIC_UL_CON0_VOCIE_MODE_48K;
> +		break;
> +	}
> +
> +	mtk_dai_dmic_load_iir_coeff_table(afe);
> +
> +	if (channels > 3) {

simplify that with the same comments as before... or actually you could even
commonize that pattern, as it seems to be duplicated over and over again.

> +		reg = get_dmic_ctrl_reg(DMIC3);
> +		if (reg)
> +			regmap_update_bits(afe->regmap, reg->con0, msk, val);
> +	}
> +	if (channels > 2) {
> +		reg = get_dmic_ctrl_reg(DMIC2);
> +		if (reg)
> +			regmap_update_bits(afe->regmap, reg->con0, msk, val);
> +	}
> +	if (channels > 1) {
> +		reg = get_dmic_ctrl_reg(DMIC1);
> +		if (reg)
> +			regmap_update_bits(afe->regmap, reg->con0, msk, val);
> +	}
> +	if (channels > 0) {
> +		reg = get_dmic_ctrl_reg(DMIC0);
> +		if (reg)
> +			regmap_update_bits(afe->regmap, reg->con0, msk, val);
> +	}
> +
> +	dmic_priv->channels = channels;
> +
> +	return 0;
> +}
> +
> +static const struct snd_soc_dai_ops mtk_dai_dmic_ops = {
> +	.hw_params	= mtk_dai_dmic_hw_params,
> +};
> +
> +#define MTK_DMIC_RATES (SNDRV_PCM_RATE_8000 |\
> +		       SNDRV_PCM_RATE_16000 |\
> +		       SNDRV_PCM_RATE_32000 |\
> +		       SNDRV_PCM_RATE_48000 |\
> +		       SNDRV_PCM_RATE_96000)
> +
> +#define MTK_DMIC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
> +			 SNDRV_PCM_FMTBIT_S32_LE)
> +
> +static struct snd_soc_dai_driver mtk_dai_dmic_driver[] = {
> +	{
> +		.name = "DMIC",
> +		.id = MT8188_AFE_IO_DMIC_IN,
> +		.capture = {
> +			.stream_name = "DMIC Capture",
> +			.channels_min = 1,
> +			.channels_max = 8,
> +			.rates = MTK_DMIC_RATES,
> +			.formats = MTK_DMIC_FORMATS,
> +		},
> +		.ops = &mtk_dai_dmic_ops,
> +	},
> +};
> +

..snip..

> +
> +static int mtk_dai_dmic_hw_gain_ctrl_put(struct snd_kcontrol *kcontrol,
> +					 struct snd_ctl_elem_value *ucontrol)
> +{
> +	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
> +	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
> +	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
> +	struct mt8188_afe_private *afe_priv = afe->platform_priv;
> +	struct mtk_dai_dmic_priv *dmic_priv;
> +	unsigned int source = ucontrol->value.enumerated.item[0];
> +	unsigned int *cached = 0;

Why are you initializing *cached?

There's no way it can be used uninitialized in this function, as if anything is
wrong you're either returning -EINVAL or assigning `source` to it later.

> +
> +	if (source >= e->items)
> +		return -EINVAL;
> +
> +	dmic_priv = afe_priv->dai_priv[MT8188_AFE_IO_DMIC_IN];
> +
> +	if (!strcmp(kcontrol->id.name, "DMIC1_HW_GAIN_EN"))
> +		cached = &dmic_priv->gain_on[0];
> +	else if (!strcmp(kcontrol->id.name, "DMIC2_HW_GAIN_EN"))
> +		cached = &dmic_priv->gain_on[1];
> +	else if (!strcmp(kcontrol->id.name, "DMIC3_HW_GAIN_EN"))
> +		cached = &dmic_priv->gain_on[2];
> +	else if (!strcmp(kcontrol->id.name, "DMIC4_HW_GAIN_EN"))
> +		cached = &dmic_priv->gain_on[3];
> +	else
> +		return -EINVAL;
> +
> +	if (source == *cached)
> +		return 0;
> +
> +	*cached = source;
> +	return 1;
> +}
> +
> +static int mtk_dai_dmic_hw_gain_ctrl_get(struct snd_kcontrol *kcontrol,
> +					 struct snd_ctl_elem_value *ucontrol)
> +{
> +	struct snd_soc_component *component =
> +		snd_soc_kcontrol_component(kcontrol);
> +	struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
> +	struct mt8188_afe_private *afe_priv = afe->platform_priv;
> +	struct mtk_dai_dmic_priv *dmic_priv;
> +	unsigned int val = 0;

double assignment again

> +
> +	dmic_priv = afe_priv->dai_priv[MT8188_AFE_IO_DMIC_IN];

stack initialize dmic_priv instead.

> +
> +	if (!strcmp(kcontrol->id.name, "DMIC1_HW_GAIN_EN"))
> +		val = dmic_priv->gain_on[0];
> +	else if (!strcmp(kcontrol->id.name, "DMIC2_HW_GAIN_EN"))
> +		val = dmic_priv->gain_on[1];
> +	else if (!strcmp(kcontrol->id.name, "DMIC3_HW_GAIN_EN"))
> +		val = dmic_priv->gain_on[2];
> +	else if (!strcmp(kcontrol->id.name, "DMIC4_HW_GAIN_EN"))
> +		val = dmic_priv->gain_on[3];

else
	val = 0;

> +
> +	ucontrol->value.enumerated.item[0] = val;
> +	return 0;
> +}
> +


..snip..

> diff --git a/sound/soc/mediatek/mt8188/mt8188-reg.h b/sound/soc/mediatek/mt8188/mt8188-reg.h
> index bdd885419ff3874bab80549ea3ff4617172b8245..4154548aca36108667036f9889476c30f9b6171a 100644
> --- a/sound/soc/mediatek/mt8188/mt8188-reg.h
> +++ b/sound/soc/mediatek/mt8188/mt8188-reg.h
> @@ -2837,9 +2837,20 @@
>   #define PWR2_TOP_CON_DMIC3_SRC_SEL_MASK     GENMASK(16, 14)
>   #define PWR2_TOP_CON_DMIC2_SRC_SEL_MASK     GENMASK(13, 11)
>   #define PWR2_TOP_CON_DMIC1_SRC_SEL_MASK     GENMASK(10, 8)
> +#define PWR2_TOP_CON_DMIC8_SRC_SEL_VAL(x)   ((x) << 29)
> +#define PWR2_TOP_CON_DMIC7_SRC_SEL_VAL(x)   ((x) << 26)
> +#define PWR2_TOP_CON_DMIC6_SRC_SEL_VAL(x)   ((x) << 23)
> +#define PWR2_TOP_CON_DMIC5_SRC_SEL_VAL(x)   ((x) << 20)
> +#define PWR2_TOP_CON_DMIC4_SRC_SEL_VAL(x)   ((x) << 17)
> +#define PWR2_TOP_CON_DMIC3_SRC_SEL_VAL(x)   ((x) << 14)
> +#define PWR2_TOP_CON_DMIC2_SRC_SEL_VAL(x)   ((x) << 11)
> +#define PWR2_TOP_CON_DMIC1_SRC_SEL_VAL(x)   ((x) << 8)
>   
>   /* PWR2_TOP_CON1 */
> -#define PWR2_TOP_CON1_DMIC_CKDIV_ON        BIT(1)
> +#define PWR2_TOP_CON1_DMIC_FIFO_SOFT_RST_EN(x)	BIT((5 + 6 * x))
> +#define PWR2_TOP_CON1_DMIC_CKDIV_ON             BIT(1)
> +#define PWR2_TOP_CON1_DMIC_CKDIV_ON_SHIFT       1
> +
>   
>   /* PCM_INTF_CON1 */
>   #define PCM_INTF_CON1_SYNC_OUT_INV     BIT(23)
> @@ -2919,15 +2930,17 @@
>   #define AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_CH2(x)	(((x) & 0x7) << 24)
>   #define AFE_DMIC_UL_SRC_CON0_UL_PHASE_SEL_MASK		GENMASK(29, 24)
>   #define AFE_DMIC_UL_SRC_CON0_UL_TWO_WIRE_MODE_CTL	BIT(23)
> +#define AFE_DMIC_UL_SRC_CON0_UL_TWO_WIRE_MODE_CTL_MASK  BIT(23)

That's the same as AFE_DMIC_UL_SRC_CON0_UL_TWO_WIRE_MODE_CTL, drop it.

>   #define AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH2_CTL	BIT(22)
>   #define AFE_DMIC_UL_SRC_CON0_UL_MODE_3P25M_CH1_CTL	BIT(21)
> -
> +#define AFE_DMIC_UL_VOICE_MODE(x)			(((x) & 0x7) << 17)

(((x) & GENMASK(2, 0) << 17)

>   #define AFE_DMIC_UL_VOICE_MODE_MASK			GENMASK(19, 17)
>   #define AFE_DMIC_UL_CON0_VOCIE_MODE_8K			AFE_DMIC_UL_VOICE_MODE(0)
>   #define AFE_DMIC_UL_CON0_VOCIE_MODE_16K			AFE_DMIC_UL_VOICE_MODE(1)
>   #define AFE_DMIC_UL_CON0_VOCIE_MODE_32K			AFE_DMIC_UL_VOICE_MODE(2)
>   #define AFE_DMIC_UL_CON0_VOCIE_MODE_48K			AFE_DMIC_UL_VOICE_MODE(3)
>   #define AFE_DMIC_UL_CON0_VOCIE_MODE_96K			AFE_DMIC_UL_VOICE_MODE(4)
> +#define AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL(x)		(((x) & 0x7) << 7)

same here

>   #define AFE_DMIC_UL_SRC_CON0_UL_IIR_MODE_CTL_MASK	GENMASK(9, 7)
>   #define AFE_DMIC_UL_SRC_CON0_UL_IIR_ON_TMP_CTL		BIT(10)
>   #define AFE_DMIC_UL_SRC_CON0_UL_SDM_3_LEVEL_CTL		BIT(1)
> @@ -2944,6 +2957,7 @@
>   
>   /* DMIC_GAINx_CON0 */
>   #define DMIC_GAIN_CON0_GAIN_ON			BIT(0)
> +#define DMIC_GAIN_CON0_SAMPLE_PER_STEP_SHIFT	8
>   #define DMIC_GAIN_CON0_SAMPLE_PER_STEP_MASK	GENMASK(15, 8)
>   
>   /* DMIC_GAINx_CON1 */
> 


Cheers,
Angelo

Re: [PATCH 2/6] ASoC: mediatek: mt8188: Add reference for dmic clocks

[AngeloGioacchino Del Regno]

Il 18/02/25 21:52, Nícolas F. R. A. Prado ha scritto:
> Add the names for the dmic clocks, aud_afe_dmic* and aud_dmic_hires*, so
> they can be acquired and enabled by the platform driver.
> 
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---
>   sound/soc/mediatek/mt8188/mt8188-afe-clk.c | 8 ++++++++
>   sound/soc/mediatek/mt8188/mt8188-afe-clk.h | 8 ++++++++
>   2 files changed, 16 insertions(+)
> 
> diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
> index e69c1bb2cb239596dee50b166c20192d5408be10..44c25b6e3d873448163b22e70f5b94cb5070654d 100644
> --- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
> +++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.c
> @@ -58,6 +58,14 @@ static const char *aud_clks[MT8188_CLK_NUM] = {
>   	[MT8188_CLK_AUD_ADC] = "aud_adc",
>   	[MT8188_CLK_AUD_DAC_HIRES] = "aud_dac_hires",
>   	[MT8188_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp",
> +	[MT8188_CLK_AUD_AFE_DMIC1] = "aud_afe_dmic1",
> +	[MT8188_CLK_AUD_AFE_DMIC2] = "aud_afe_dmic2",
> +	[MT8188_CLK_AUD_AFE_DMIC3] = "aud_afe_dmic3",
> +	[MT8188_CLK_AUD_AFE_DMIC4] = "aud_afe_dmic4",
> +	[MT8188_CLK_AUD_DMIC_HIRES1] = "aud_dmic_hires1",
> +	[MT8188_CLK_AUD_DMIC_HIRES2] = "aud_dmic_hires2",
> +	[MT8188_CLK_AUD_DMIC_HIRES3] = "aud_dmic_hires3",
> +	[MT8188_CLK_AUD_DMIC_HIRES4] = "aud_dmic_hires4",
>   	[MT8188_CLK_AUD_ADC_HIRES] = "aud_adc_hires",
>   	[MT8188_CLK_AUD_I2SIN] = "aud_i2sin",
>   	[MT8188_CLK_AUD_TDM_IN] = "aud_tdm_in",
> diff --git a/sound/soc/mediatek/mt8188/mt8188-afe-clk.h b/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
> index ec53c171c170a8b4b47900e63ef79d53641e9b12..68c46feb72271b950d4e538f63cedf524354147e 100644
> --- a/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
> +++ b/sound/soc/mediatek/mt8188/mt8188-afe-clk.h
> @@ -54,6 +54,14 @@ enum {
>   	MT8188_CLK_AUD_ADC,
>   	MT8188_CLK_AUD_DAC_HIRES,
>   	MT8188_CLK_AUD_A1SYS_HP,
> +	MT8188_CLK_AUD_AFE_DMIC1,
> +	MT8188_CLK_AUD_AFE_DMIC2,
> +	MT8188_CLK_AUD_AFE_DMIC3,
> +	MT8188_CLK_AUD_AFE_DMIC4,
> +	MT8188_CLK_AUD_DMIC_HIRES1,
> +	MT8188_CLK_AUD_DMIC_HIRES2,
> +	MT8188_CLK_AUD_DMIC_HIRES3,
> +	MT8188_CLK_AUD_DMIC_HIRES4,
>   	MT8188_CLK_AUD_ADC_HIRES,

Following the comments from audsys, put those after CLK_AUD_ADC_HIRES.

Cheers,
Angelo

>   	MT8188_CLK_AUD_I2SIN,
>   	MT8188_CLK_AUD_TDM_IN,
> 

Re: [PATCH 1/6] ASoC: mediatek: mt8188: Add audsys hires clocks

[AngeloGioacchino Del Regno]

Il 18/02/25 21:52, Nícolas F. R. A. Prado ha scritto:
> Describe and register the aud_dmic_hires audsys clocks, which are needed
> when recording the DMIC at a sample rate of 96k.
> 
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---
>   sound/soc/mediatek/mt8188/mt8188-audsys-clk.c   | 4 ++++
>   sound/soc/mediatek/mt8188/mt8188-audsys-clkid.h | 4 ++++
>   2 files changed, 8 insertions(+)
> 
> diff --git a/sound/soc/mediatek/mt8188/mt8188-audsys-clk.c b/sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
> index c796ad8b62eeaa929f24c09755f428116b105404..e7b2c9da61f6b5dbe9002a294ebbb7f4415fe54c 100644
> --- a/sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
> +++ b/sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
> @@ -81,6 +81,10 @@ static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = {
>   	GATE_AUD1(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "top_a1sys_hp", 11),
>   	GATE_AUD1(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "top_a1sys_hp", 12),
>   	GATE_AUD1(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "top_a1sys_hp", 13),
> +	GATE_AUD1(CLK_AUD_DMIC_HIRES1, "aud_dmic_hires1", "top_audio_h", 20),
> +	GATE_AUD1(CLK_AUD_DMIC_HIRES2, "aud_dmic_hires2", "top_audio_h", 21),
> +	GATE_AUD1(CLK_AUD_DMIC_HIRES3, "aud_dmic_hires3", "top_audio_h", 22),
> +	GATE_AUD1(CLK_AUD_DMIC_HIRES4, "aud_dmic_hires4", "top_audio_h", 23),
>   	GATE_AUD1(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm", "top_a1sys_hp", 14),
>   	GATE_AUD1(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires", "top_audio_h", 16),
>   	GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "top_audio_h", 17),
> diff --git a/sound/soc/mediatek/mt8188/mt8188-audsys-clkid.h b/sound/soc/mediatek/mt8188/mt8188-audsys-clkid.h
> index 6f34ffc760e03beddc3001046e554edd7ea2c478..820f2aef17ea40be1a80aece604b4a319934312f 100644
> --- a/sound/soc/mediatek/mt8188/mt8188-audsys-clkid.h
> +++ b/sound/soc/mediatek/mt8188/mt8188-audsys-clkid.h
> @@ -30,6 +30,10 @@ enum{
>   	CLK_AUD_AFE_DMIC2,
>   	CLK_AUD_AFE_DMIC3,
>   	CLK_AUD_AFE_DMIC4,
> +	CLK_AUD_DMIC_HIRES1,
> +	CLK_AUD_DMIC_HIRES2,
> +	CLK_AUD_DMIC_HIRES3,
> +	CLK_AUD_DMIC_HIRES4,
>   	CLK_AUD_AFE_26M_DMIC_TM,
>   	CLK_AUD_UL_TML_HIRES,
>   	CLK_AUD_ADC_HIRES,

Please either put it after CLK_AUD_ADC_HIRES, which corresponds to the end of AUD1
and also orders that alphabetically.

Same for the addition in audsys-clk.c, that would order the clocks also per bit.

Thanks,
Angelo

Re: [PATCH 5/6] ASoC: mediatek: mt8188-mt6359: Add DMIC

[AngeloGioacchino Del Regno]

Il 18/02/25 21:52, Nícolas F. R. A. Prado ha scritto:
> Add the DMIC backend, which connects to the DMIC DAI in the platform
> driver, as well as a "AP DMIC" mic widget. On the Genio 700 EVK board
> the dual DMIC on-board are wired through that DMIC DAI.
> 
> Co-developed-by: parkeryang <Parker.Yang@mediatek.com>
> Signed-off-by: parkeryang <Parker.Yang@mediatek.com>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>

Since you have to send a v2, perhaps you can also change the title to read

ASoC: mediatek: mt8188-mt6359: Add DMIC support

After which

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH 6/6] arm64: dts: mediatek: mt8390-genio-common: Add routes for DMIC

[Nícolas F. R. A. Prado]

On Wed, Feb 19, 2025 at 12:29:15PM +0800, Chen-Yu Tsai wrote:
> On Wed, Feb 19, 2025 at 5:27 AM Nícolas F. R. A. Prado
> <nfraprado@collabora.com> wrote:
> >
> > Add necessary routes for the onboard dual DMIC present on the Genio
> > 700/510 EVK. The dmic is supplied by micbias0 and micbias2, and inputs
> > into the MT8188 DMIC DAI.
> >
> > Co-developed-by: parkeryang <Parker.Yang@mediatek.com>
> > Signed-off-by: parkeryang <Parker.Yang@mediatek.com>
> > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > ---
> >  arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi | 6 +++++-
> >  1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
> > index a37cf102a6e928440cc88e7e8fe0225fc28ec962..efdeca88b8c4e58f0c17825156276babf19af145 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-common.dtsi
> > @@ -959,7 +959,11 @@ &sound {
> >         pinctrl-0 = <&audio_default_pins>;
> >         audio-routing =
> >                 "Headphone", "Headphone L",
> > -               "Headphone", "Headphone R";
> > +               "Headphone", "Headphone R",
> > +               "DMIC_INPUT", "AP DMIC",
> > +               "AP DMIC", "AUDGLB",
> > +               "AP DMIC", "MIC_BIAS_0",
> > +               "AP DMIC", "MIC_BIAS_2";
> >         mediatek,adsp = <&adsp>;
> >         status = "okay";
> 
> Shouldn't there also be one or two new dmic-codecs, and a dai-link here?

The DMIC codec is only needed to get a wakeup delay and avoid an initial "pop"
noise. Same as for the analog mic, for which I've recently sent a patch [1].

Depending on the order that things get picked up, I can either add the patch for
it to this series, or the series in [1]. (Well, looks like I'll be sending a v2
for this series anyway, so I can add that patch here).

Thanks,
Nícolas

[1] https://lore.kernel.org/all/20250214-genio700-amic-wakeup-delay-200ms-v1-1-0094837c62b7@collabora.com

Re: [PATCH 4/6] ASoC: mediatek: mt8188: Support DMIC in AFE

[Nícolas F. R. A. Prado]

On Wed, Feb 19, 2025 at 12:29:13PM +0100, AngeloGioacchino Del Regno wrote:
> Il 18/02/25 21:52, Nícolas F. R. A. Prado ha scritto:
> > From: parkeryang <Parker.Yang@mediatek.com>
> > 
> > Add the AFE routes that connect the DMIC (I004-I011) to the UL9 frontend
> > (O002-O009) and register the mt8188-dmic DAI driver during probe.
> > 
> > Signed-off-by: parkeryang <Parker.Yang@mediatek.com>
> > Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > ---
> >   sound/soc/mediatek/mt8188/Makefile            |  1 +
> >   sound/soc/mediatek/mt8188/mt8188-afe-common.h |  1 +
> >   sound/soc/mediatek/mt8188/mt8188-afe-pcm.c    | 24 ++++++++++++++++++++++++
> >   3 files changed, 26 insertions(+)
> > 
> > diff --git a/sound/soc/mediatek/mt8188/Makefile b/sound/soc/mediatek/mt8188/Makefile
> > index 1178bce45c50ba252672a32b3877732a5a76c610..b9f3e4ad7b07ba9e21c846706371c53269f894db 100644
> > --- a/sound/soc/mediatek/mt8188/Makefile
> > +++ b/sound/soc/mediatek/mt8188/Makefile
> > @@ -6,6 +6,7 @@ snd-soc-mt8188-afe-y := \
> >   	mt8188-afe-pcm.o \
> >   	mt8188-audsys-clk.o \
> >   	mt8188-dai-adda.o \
> > +	mt8188-dai-dmic.o \
> >   	mt8188-dai-etdm.o \
> >   	mt8188-dai-pcm.o
> 
> The Makefile addition doesn't belong to this commit. Please fix.

I was divided between adding it here or in the previous commit that adds the
dmic driver. Only in this commit is the mt8188_dai_dmic_register() added, so
this is the first commit in which any of the code from the dmic driver is
actually used, hence why I added it here. But adding the makefile entry together
with the driver code, even if it's not used, makes sense too, so I'll move it
there.

Thanks,
Nícolas

Re: [PATCH 4/6] ASoC: mediatek: mt8188: Support DMIC in AFE

[AngeloGioacchino Del Regno]

Il 19/02/25 14:40, Nícolas F. R. A. Prado ha scritto:
> On Wed, Feb 19, 2025 at 12:29:13PM +0100, AngeloGioacchino Del Regno wrote:
>> Il 18/02/25 21:52, Nícolas F. R. A. Prado ha scritto:
>>> From: parkeryang <Parker.Yang@mediatek.com>
>>>
>>> Add the AFE routes that connect the DMIC (I004-I011) to the UL9 frontend
>>> (O002-O009) and register the mt8188-dmic DAI driver during probe.
>>>
>>> Signed-off-by: parkeryang <Parker.Yang@mediatek.com>
>>> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
>>> ---
>>>    sound/soc/mediatek/mt8188/Makefile            |  1 +
>>>    sound/soc/mediatek/mt8188/mt8188-afe-common.h |  1 +
>>>    sound/soc/mediatek/mt8188/mt8188-afe-pcm.c    | 24 ++++++++++++++++++++++++
>>>    3 files changed, 26 insertions(+)
>>>
>>> diff --git a/sound/soc/mediatek/mt8188/Makefile b/sound/soc/mediatek/mt8188/Makefile
>>> index 1178bce45c50ba252672a32b3877732a5a76c610..b9f3e4ad7b07ba9e21c846706371c53269f894db 100644
>>> --- a/sound/soc/mediatek/mt8188/Makefile
>>> +++ b/sound/soc/mediatek/mt8188/Makefile
>>> @@ -6,6 +6,7 @@ snd-soc-mt8188-afe-y := \
>>>    	mt8188-afe-pcm.o \
>>>    	mt8188-audsys-clk.o \
>>>    	mt8188-dai-adda.o \
>>> +	mt8188-dai-dmic.o \
>>>    	mt8188-dai-etdm.o \
>>>    	mt8188-dai-pcm.o
>>
>> The Makefile addition doesn't belong to this commit. Please fix.
> 
> I was divided between adding it here or in the previous commit that adds the
> dmic driver. Only in this commit is the mt8188_dai_dmic_register() added, so
> this is the first commit in which any of the code from the dmic driver is
> actually used, hence why I added it here. But adding the makefile entry together
> with the driver code, even if it's not used, makes sense too, so I'll move it
> there.
> 

You can even squash the two commits... after all, adding a piece that doesn't
get used until a later time is practically useless... right?! :-)