Linux SPI subsystem development
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From: Jaime Liao <jaimeliao.tw@gmail.com>
To: linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org,
	tudor.ambarus@linaro.org, pratyush@kernel.org, mwalle@kernel.org,
	miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
	broonie@kernel.org
Cc: leoyu@mxic.com.tw, jaimeliao@mxic.com.tw
Subject: [PATCH v8 3/9] mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode
Date: Thu,  1 Feb 2024 17:43:47 +0800	[thread overview]
Message-ID: <20240201094353.33281-4-jaimeliao.tw@gmail.com> (raw)
In-Reply-To: <20240201094353.33281-1-jaimeliao.tw@gmail.com>

From: JaimeLiao <jaimeliao@mxic.com.tw>

Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR.
The byte order of 16-bit words is swapped when read or written in 8D-8D-8D
mode compared to STR modes. Allow operations to specify the byte order in
DTR mode, so that controllers can swap the bytes back at run-time to
address the flash's endianness requirements, if they are capable. If the
controllers are not capable of swapping the bytes, the protocol is
downgrade via spi_nor_spimem_adjust_hwcaps(). When available, the swapping
of the bytes is always done regardless if it's a data or register access,
so that we comply with the JESD216 requirements: "Byte order of 16-bit
words is swapped when read in 8D-8D-8D mode compared to 1-1-1".

Merge Tudor's patch and add modifications for suiting newer version
of Linux kernel.

Suggested-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
---
 drivers/mtd/spi-nor/core.c | 5 +++++
 drivers/mtd/spi-nor/core.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 4129764fad8c..0076007e1cde 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -113,6 +113,11 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor,
 		op->cmd.opcode = (op->cmd.opcode << 8) | ext;
 		op->cmd.nbytes = 2;
 	}
+
+	/* SWAP16 is only applicable when Octal DTR mode */
+	if (nor->read_proto == SNOR_PROTO_8_8_8_DTR)
+		if (nor->flags & SNOR_F_SWAP16)
+			op->data.swap16 = true;
 }
 
 /**
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index d36c0e072954..3c5190ac0a79 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -140,6 +140,7 @@ enum spi_nor_option_flags {
 	SNOR_F_RWW		= BIT(14),
 	SNOR_F_ECC		= BIT(15),
 	SNOR_F_NO_WP		= BIT(16),
+	SNOR_F_SWAP16		= BIT(17),
 };
 
 struct spi_nor_read_command {
-- 
2.25.1


  parent reply	other threads:[~2024-02-01  9:44 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-01  9:43 [PATCH v8 0/9] Add octal DTR support for Macronix flash Jaime Liao
2024-02-01  9:43 ` [PATCH v8 1/9] mtd: spi-nor: add Octal " Jaime Liao
2024-02-01  9:43 ` [PATCH v8 2/9] spi: spi-mem: Allow specifying the byte order in Octal DTR mode Jaime Liao
2024-02-01 12:04   ` Mark Brown
2024-02-01 15:18   ` Michael Walle
2024-02-01  9:43 ` Jaime Liao [this message]
2024-02-01 15:28   ` [PATCH v8 3/9] mtd: spi-nor: core: " Michael Walle
2024-02-01  9:43 ` [PATCH v8 4/9] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT Jaime Liao
2024-02-01  9:43 ` [PATCH v8 5/9] spi: mxic: Add support for swapping byte Jaime Liao
2024-02-01 12:05   ` Mark Brown
2024-02-01 15:39   ` Michael Walle
2024-02-01  9:43 ` [PATCH v8 6/9] mtd: spi-nor: add support for Macronix Octal flash MX25 series with RWW feature Jaime Liao
2024-02-01 15:48   ` Michael Walle
2024-02-01  9:43 ` [PATCH v8 7/9] mtd: spi-nor: add support for Macronix Octal flash MX66 " Jaime Liao
2024-02-01  9:43 ` [PATCH v8 8/9] mtd: spi-nor: add support for Macronix Octal flash MX25 series Jaime Liao
2024-02-01  9:43 ` [PATCH v8 9/9] mtd: spi-nor: add support for Macronix Octal flash MX66 series Jaime Liao
2024-02-01 15:52   ` Michael Walle
2024-02-22  9:32 ` [PATCH v8 0/9] Add octal DTR support for Macronix flash Tudor Ambarus
2024-02-22  9:55   ` liao jaime
2024-02-26  2:02     ` Alvin Zhou

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