[PATCH v3] spi: cadence-xspi: Support 32bit and 64bit slave dma interface

[PATCH v3] spi: cadence-xspi: Support 32bit and 64bit slave dma interface

[Jisheng Zhang]

The cdns xspi controller slave dma interface may support wider data
width. Wider I/O width can benefit performance. We can know the width
by checking the CTRL_FEATURES_REG's DMA_DATA_WIDTH bit, 0 means 32bit
1 means 64bit.

A simple test with QSPI nor flash on one arm64 platform:

Use 8bit slave dma data width (now):
 # dd if=/dev/mtdblock0 of=/dev/null bs=8192 count=1000
 1000+0 records in
 1000+0 records out
 8192000 bytes (7.8MB) copied, 1.368735 seconds, 5.7MB/s

Use 32bit slave dma data width:
 # dd if=/dev/mtdblock0 of=/dev/null bs=8192 count=1000
 1000+0 records in
 1000+0 records out
 8192000 bytes (7.8MB) copied, 1.088787 seconds, 7.2MB/s

Improved by 26.3%!

Use 64bit slave dma data width:
 # dd if=/dev/mtdblock0 of=/dev/null bs=8192 count=1000
 1000+0 records in
 1000+0 records out
 8192000 bytes (7.8MB) copied, 0.831104 seconds, 9.4MB/s

Improved by 64.9%!

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---

Since v2:
 - use readsq/writesq instead of ioread64_rep/iowrite64_rep to fix build
   error for x86. Similar solution as cadence-nand-controller.c

Since v1:
 - the hw capability(slave dma data width) can be found by checking the
   CTRL_FEATURES_REG's DMA_DATA_WIDTH, so no need dt property any more.

 drivers/spi/spi-cadence-xspi.c | 53 +++++++++++++++++++++++++++++++---
 1 file changed, 49 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-cadence-xspi.c b/drivers/spi/spi-cadence-xspi.c
index 895b4b3276a5..ab6f1c68a2eb 100644
--- a/drivers/spi/spi-cadence-xspi.c
+++ b/drivers/spi/spi-cadence-xspi.c
@@ -369,6 +369,8 @@ struct cdns_xspi_dev {
 
 	void *in_buffer;
 	const void *out_buffer;
+	/* Slave DMA data width in bytes (4 or 8). */
+	u8 dma_data_width;
 
 	u8 hw_num_banks;
 
@@ -573,11 +575,56 @@ static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi)
 
 	ctrl_features = readl(cdns_xspi->iobase + CDNS_XSPI_CTRL_FEATURES_REG);
 	cdns_xspi->hw_num_banks = FIELD_GET(CDNS_XSPI_NUM_BANKS, ctrl_features);
+	cdns_xspi->dma_data_width = (ctrl_features & CDNS_XSPI_DMA_DATA_WIDTH) ? 8 : 4;
 	cdns_xspi->set_interrupts_handler(cdns_xspi, false);
 
 	return 0;
 }
 
+static inline void cdns_xspi_sdma_read(struct cdns_xspi_dev *cdns_xspi, size_t len)
+{
+	void __iomem *src = cdns_xspi->sdmabase;
+	void *buf = cdns_xspi->in_buffer;
+	size_t offset = 0;
+
+	if (cdns_xspi->dma_data_width == 4) {
+		if (IS_ALIGNED((uintptr_t)src, 4) && IS_ALIGNED((uintptr_t)buf, 4)) {
+			ioread32_rep(src, buf, len >> 2);
+			offset = len & ~0x3;
+			len -= offset;
+		}
+	} else {
+		if (IS_ALIGNED((uintptr_t)src, 8) && IS_ALIGNED((uintptr_t)buf, 8)) {
+			readsq(src, buf, len >> 3);
+			offset = len & ~0x7;
+			len -= offset;
+		}
+	}
+	ioread8_rep(src, (u8 *)buf + offset, len);
+}
+
+static inline void cdns_xspi_sdma_write(struct cdns_xspi_dev *cdns_xspi, size_t len)
+{
+	void __iomem *dst = cdns_xspi->sdmabase;
+	const void *buf = cdns_xspi->out_buffer;
+	size_t offset = 0;
+
+	if (cdns_xspi->dma_data_width == 4) {
+		if (IS_ALIGNED((uintptr_t)dst, 4) && IS_ALIGNED((uintptr_t)buf, 4)) {
+			iowrite32_rep(dst, buf, len >> 2);
+			offset = len & ~0x3;
+			len -= offset;
+		}
+	} else {
+		if (IS_ALIGNED((uintptr_t)dst, 8) && IS_ALIGNED((uintptr_t)buf, 8)) {
+			writesq(dst, buf, len >> 3);
+			offset = len & ~0x7;
+			len -= offset;
+		}
+	}
+	iowrite8_rep(dst, (const u8 *)buf + offset, len);
+}
+
 static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
 {
 	u32 sdma_size, sdma_trd_info;
@@ -589,13 +636,11 @@ static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
 
 	switch (sdma_dir) {
 	case CDNS_XSPI_SDMA_DIR_READ:
-		ioread8_rep(cdns_xspi->sdmabase,
-			    cdns_xspi->in_buffer, sdma_size);
+		cdns_xspi_sdma_read(cdns_xspi, sdma_size);
 		break;
 
 	case CDNS_XSPI_SDMA_DIR_WRITE:
-		iowrite8_rep(cdns_xspi->sdmabase,
-			     cdns_xspi->out_buffer, sdma_size);
+		cdns_xspi_sdma_write(cdns_xspi, sdma_size);
 		break;
 	}
 }
-- 
2.53.0

Re: [PATCH v3] spi: cadence-xspi: Support 32bit and 64bit slave dma interface

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 354 bytes --]

On Wed, Jun 03, 2026 at 07:58:25AM +0800, Jisheng Zhang wrote:

> +	} else {
> +		if (IS_ALIGNED((uintptr_t)src, 8) && IS_ALIGNED((uintptr_t)buf, 8)) {
> +			readsq(src, buf, len >> 3);

readsq() and writesq() are only defined under CONFIG_64BIT AFAICT, but
the driver will build on 32 bit.  We need to configure out this option
on 32 bit architectures.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [PATCH v3] spi: cadence-xspi: Support 32bit and 64bit slave dma interface

[Jisheng Zhang]

On Wed, Jun 03, 2026 at 09:20:29AM +0100, Mark Brown wrote:
> On Wed, Jun 03, 2026 at 07:58:25AM +0800, Jisheng Zhang wrote:
> 
> > +	} else {
> > +		if (IS_ALIGNED((uintptr_t)src, 8) && IS_ALIGNED((uintptr_t)buf, 8)) {
> > +			readsq(src, buf, len >> 3);
> 
> readsq() and writesq() are only defined under CONFIG_64BIT AFAICT, but
> the driver will build on 32 bit.  We need to configure out this option
> on 32 bit architectures.

Currently, the cadence-xspi has depended on 64BIT, the dependency was
introduced by commit d58ecc54bb09 ("spi: cadence: Add 64BIT Kconfig
dependency") for marvell sdma handling. So we have two choices:

A. guard the marvell sdma handling with CONFIG_64BIT, and remove the
above hardcoded dependency, then introduce proper readsq/writesq
handling.

B. keep the 64BIT dependency, and review the merge this patch as is.

Which do you prefer? I'll cook newer version if you prefer option A.

Thanks

Re: [PATCH v3] spi: cadence-xspi: Support 32bit and 64bit slave dma interface

[Mark Brown]

On Wed, 03 Jun 2026 07:58:25 +0800, Jisheng Zhang wrote:
> spi: cadence-xspi: Support 32bit and 64bit slave dma interface

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-7.2

Thanks!

[1/1] spi: cadence-xspi: Support 32bit and 64bit slave dma interface
      https://git.kernel.org/broonie/sound/c/4954d4eca469

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

Re: [PATCH v3] spi: cadence-xspi: Support 32bit and 64bit slave dma interface

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 675 bytes --]

On Thu, Jun 04, 2026 at 07:51:12AM +0800, Jisheng Zhang wrote:
> On Wed, Jun 03, 2026 at 09:20:29AM +0100, Mark Brown wrote:

> > readsq() and writesq() are only defined under CONFIG_64BIT AFAICT, but
> > the driver will build on 32 bit.  We need to configure out this option
> > on 32 bit architectures.

> Currently, the cadence-xspi has depended on 64BIT, the dependency was
> introduced by commit d58ecc54bb09 ("spi: cadence: Add 64BIT Kconfig
> dependency") for marvell sdma handling. So we have two choices:

Ah, the patch is fine then - I must have been looking at a fixes tree
without the dependency when I reviewed it, I'd forgotten that Marvell
update had gone in.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]