From: Andre Przywara <andre.przywara@arm.com>
To: Jagan Teki <jagan@amarulasolutions.com>
Cc: Samuel Holland <samuel@sholland.org>,
linux-sunxi@lists.linux.dev, u-boot@lists.denx.de
Subject: [PATCH 18/19] sunxi: SPL pinmux: split out UART pinmux per port
Date: Wed, 3 Jan 2024 00:12:38 +0000 [thread overview]
Message-ID: <20240103001239.17482-19-andre.przywara@arm.com> (raw)
In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com>
The UART SPL pinmux function is particularly hard to read, as it
combines per-SoC definitions with per-configuration choices (which UART
to use).
Split the existing single function into one per UART port, to reduce
the #ifdef hell and improve readability. The four cases which deal with
UARTs other than 0 or 1 are left in the main function, to reduce
clutter.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/mach-sunxi/uart_pinmux.c | 66 ++++++++++++++++++++-----------
1 file changed, 42 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-sunxi/uart_pinmux.c b/arch/arm/mach-sunxi/uart_pinmux.c
index af5ecc4fb3c..cb4b16f0e37 100644
--- a/arch/arm/mach-sunxi/uart_pinmux.c
+++ b/arch/arm/mach-sunxi/uart_pinmux.c
@@ -15,9 +15,8 @@
#include <config.h>
#include <sunxi_gpio.h>
-void uart_pinmux_setup(void)
+void uart0_portf_pinmux_setup(void)
{
-#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \
defined(CONFIG_MACH_SUN8I_R40)
@@ -35,68 +34,92 @@ void uart_pinmux_setup(void)
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#endif
sunxi_gpio_set_pull(SUNXI_GPF(4), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNIV)
+}
+
+void uart0_pinmux_setup(void)
+{
+#if defined(CONFIG_MACH_SUNIV)
sunxi_gpio_set_cfgpin(SUNXI_GPE(0), SUNIV_GPE_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPE(1), SUNIV_GPE_UART0);
sunxi_gpio_set_pull(SUNXI_GPE(1), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
- defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40))
+#elif (defined(CONFIG_MACH_SUN4I) || \
+ defined(CONFIG_MACH_SUN7I) || \
+ defined(CONFIG_MACH_SUN8I_R40))
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
+#elif defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
+#elif defined(CONFIG_MACH_SUN6I)
sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
+#elif defined(CONFIG_MACH_SUN8I_A33)
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
+#elif defined(CONFIG_MACH_SUNXI_H3_H5)
sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
+#elif defined(CONFIG_MACH_SUN50I)
sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
+#elif defined(CONFIG_MACH_SUN50I_H6)
sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616)
+#elif defined(CONFIG_MACH_SUN50I_H616)
sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0);
sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
+#elif defined(CONFIG_MACH_SUN8I_A83T)
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
+#elif defined(CONFIG_MACH_SUN8I_V3S)
sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
+#elif defined(CONFIG_MACH_SUN9I)
sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_R528)
+#elif defined(CONFIG_MACH_SUN8I_R528)
sunxi_gpio_set_cfgpin(SUNXI_GPE(2), 6);
sunxi_gpio_set_cfgpin(SUNXI_GPE(3), 6);
sunxi_gpio_set_pull(SUNXI_GPE(3), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUNIV)
+#endif
+}
+
+void uart1_pinmux_setup(void)
+{
+#if defined(CONFIG_MACH_SUNIV)
sunxi_gpio_set_cfgpin(SUNXI_GPA(2), SUNIV_GPE_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPA(3), SUNIV_GPE_UART0);
sunxi_gpio_set_pull(SUNXI_GPA(3), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
+#elif defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1);
+ sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
+#endif
+}
+
+void uart_pinmux_setup(void)
+{
+#if CONFIG_CONS_INDEX == 1
+ uart0_pinmux_setup();
+ return;
+#elif CONFIG_CONS_INDEX == 2
+ uart1_pinmux_setup();
+ return;
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I_H3)
sunxi_gpio_set_cfgpin(SUNXI_GPA(0), SUN8I_H3_GPA_UART2);
sunxi_gpio_set_cfgpin(SUNXI_GPA(1), SUN8I_H3_GPA_UART2);
@@ -113,11 +136,6 @@ void uart_pinmux_setup(void)
sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \
- !defined(CONFIG_MACH_SUN8I_R40)
- sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1);
- sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN8I_GPG_UART1);
- sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
--
2.35.8
next prev parent reply other threads:[~2024-01-03 0:13 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-03 0:12 [PATCH 00/19] sunxi: SPL cleanup part 1 Andre Przywara
2024-01-03 0:12 ` [PATCH 01/19] sunxi: cleanup sunxi-common.h Andre Przywara
2024-01-03 0:12 ` [PATCH 02/19] sunxi: sun50i-h6: remove unneeded base addresses from header Andre Przywara
2024-01-03 0:12 ` [PATCH 03/19] sunxi: sun4i: " Andre Przywara
2024-01-03 0:12 ` [PATCH 04/19] sunxi: sun9i: " Andre Przywara
2024-01-03 0:12 ` [PATCH 05/19] sunxi: move #ifdef guards around tzpc_init() to header file Andre Przywara
2024-01-03 0:12 ` [PATCH 06/19] sunxi: remove common.h inclusion Andre Przywara
2024-01-03 0:12 ` [PATCH 07/19] sunxi: simplify U-Boot proper only builds Andre Przywara
2024-01-03 0:12 ` [PATCH 08/19] sunxi: remove unneeded i2c_init_board() call for U-Boot proper Andre Przywara
2024-01-03 0:12 ` [PATCH 09/19] sunxi: compile clock.c for SPL only Andre Przywara
2024-01-03 0:12 ` [PATCH 10/19] sunxi: sun4i: make more clock functions " Andre Przywara
2024-01-03 0:12 ` [PATCH 11/19] sunxi: sun6i: " Andre Przywara
2024-01-03 0:12 ` [PATCH 12/19] sunxi: sun50i_h6: " Andre Przywara
2024-01-03 0:12 ` [PATCH 13/19] sunxi: sun8i_a83t: " Andre Przywara
2024-01-03 0:12 ` [PATCH 14/19] sunxi: sun9i: " Andre Przywara
2024-01-03 0:12 ` [PATCH 15/19] sunxi: move pinmux setup into separate SPL only file Andre Przywara
2024-01-03 0:12 ` [PATCH 16/19] sunxi: SPL pinmux: rewrite without #ifdefs Andre Przywara
2024-01-03 0:12 ` [PATCH 17/19] sunxi: move UART pinmux setup into separate file Andre Przywara
2024-01-03 0:12 ` Andre Przywara [this message]
2024-01-03 0:12 ` [PATCH 19/19] sunxi: SPL pinmux: rewrite UART setup without #ifdefs Andre Przywara
2024-01-17 13:52 ` [PATCH 00/19] sunxi: SPL cleanup part 1 Andre Przywara
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