From: Andre Przywara <andre.przywara@arm.com>
To: Jagan Teki <jagan@amarulasolutions.com>
Cc: Samuel Holland <samuel@sholland.org>,
linux-sunxi@lists.linux.dev, u-boot@lists.denx.de
Subject: [PATCH 04/19] sunxi: sun9i: remove unneeded base addresses from header
Date: Wed, 3 Jan 2024 00:12:24 +0000 [thread overview]
Message-ID: <20240103001239.17482-5-andre.przywara@arm.com> (raw)
In-Reply-To: <20240103001239.17482-1-andre.przywara@arm.com>
The cpu_sun9i.h header file defined the base addresses for quite some
peripherals of the Allwinner A80 CPU, even though we now only use a
fraction of that.
Most of the addresses are now either read from the DT, or were never
used in U-Boot in the first place.
Removed the ones that are not used in the whole of the U-Boot source.
to make it clear that this file only contains addresses that are needed
for the SPL operation.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 41 ---------------------
1 file changed, 41 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index 2bf2675d5c1..73de4707c16 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -20,7 +20,6 @@
/* AHB0 Module */
#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
-#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
#define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
/* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */
@@ -32,14 +31,7 @@
#define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000)
#define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000)
-#define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000)
-#define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000)
-#define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000)
-#define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000)
-
#define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000)
-#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000)
-#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000)
#define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000)
#define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000)
@@ -47,59 +39,26 @@
#define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000)
#define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000)
-/* AHB1 Module */
-#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000)
-#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000)
-#define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000)
-#define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000)
-#define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000)
-
-/* AHB2 Module */
-#define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
-#define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000)
#define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
-#define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
-#define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
-
#define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
-#define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
-#define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000)
-
-#define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000)
-#define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000)
-#define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000)
-#define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000)
-
#define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
#define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
#define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
-#define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000)
-/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */
-#define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100)
#define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000)
/* APB0 Module */
#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000)
-#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400)
#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00)
#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400)
-#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800)
/* APB1 Module */
#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800)
#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00)
-#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000)
-#define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400)
-#define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800)
/* RCPUS Module */
#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400)
#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400)
-/* Misc. */
-#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */
-#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
-
#ifndef __ASSEMBLY__
void sunxi_board_init(void);
void sunxi_reset(void);
--
2.35.8
next prev parent reply other threads:[~2024-01-03 0:13 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-03 0:12 [PATCH 00/19] sunxi: SPL cleanup part 1 Andre Przywara
2024-01-03 0:12 ` [PATCH 01/19] sunxi: cleanup sunxi-common.h Andre Przywara
2024-01-03 0:12 ` [PATCH 02/19] sunxi: sun50i-h6: remove unneeded base addresses from header Andre Przywara
2024-01-03 0:12 ` [PATCH 03/19] sunxi: sun4i: " Andre Przywara
2024-01-03 0:12 ` Andre Przywara [this message]
2024-01-03 0:12 ` [PATCH 05/19] sunxi: move #ifdef guards around tzpc_init() to header file Andre Przywara
2024-01-03 0:12 ` [PATCH 06/19] sunxi: remove common.h inclusion Andre Przywara
2024-01-03 0:12 ` [PATCH 07/19] sunxi: simplify U-Boot proper only builds Andre Przywara
2024-01-03 0:12 ` [PATCH 08/19] sunxi: remove unneeded i2c_init_board() call for U-Boot proper Andre Przywara
2024-01-03 0:12 ` [PATCH 09/19] sunxi: compile clock.c for SPL only Andre Przywara
2024-01-03 0:12 ` [PATCH 10/19] sunxi: sun4i: make more clock functions " Andre Przywara
2024-01-03 0:12 ` [PATCH 11/19] sunxi: sun6i: " Andre Przywara
2024-01-03 0:12 ` [PATCH 12/19] sunxi: sun50i_h6: " Andre Przywara
2024-01-03 0:12 ` [PATCH 13/19] sunxi: sun8i_a83t: " Andre Przywara
2024-01-03 0:12 ` [PATCH 14/19] sunxi: sun9i: " Andre Przywara
2024-01-03 0:12 ` [PATCH 15/19] sunxi: move pinmux setup into separate SPL only file Andre Przywara
2024-01-03 0:12 ` [PATCH 16/19] sunxi: SPL pinmux: rewrite without #ifdefs Andre Przywara
2024-01-03 0:12 ` [PATCH 17/19] sunxi: move UART pinmux setup into separate file Andre Przywara
2024-01-03 0:12 ` [PATCH 18/19] sunxi: SPL pinmux: split out UART pinmux per port Andre Przywara
2024-01-03 0:12 ` [PATCH 19/19] sunxi: SPL pinmux: rewrite UART setup without #ifdefs Andre Przywara
2024-01-17 13:52 ` [PATCH 00/19] sunxi: SPL cleanup part 1 Andre Przywara
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