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From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: Vidya Sagar <vidyas@nvidia.com>,
	thierry.reding@gmail.com, bhelgaas@google.com,
	jonathanh@nvidia.com
Cc: linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org,
	kthota@nvidia.com
Subject: Re: [PATCH 06/12] PCI: tegra: Enable opportunistic update FC and ACK
Date: Mon, 30 Oct 2017 09:25:18 +0530	[thread overview]
Message-ID: <14de423a-5bf3-7a00-e956-c291379dd412@nvidia.com> (raw)
In-Reply-To: <c59099be-16e9-ddd4-97e7-127363c4db65@nvidia.com>



On 29-Oct-17 3:11 PM, Vidya Sagar wrote:
> 
> 
> On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
>> This patch ensures that DL sends pending ACKs and update FC packets when
>> link is idle instead of waiting for timers to expire which improves PCIe
>> bandwidth.
>>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>>   drivers/pci/host/pci-tegra.c | 15 ++++++++++++++-
>>   1 file changed, 14 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
>> index af34daf3c6a2..27a8211c48b2 100644
>> --- a/drivers/pci/host/pci-tegra.c
>> +++ b/drivers/pci/host/pci-tegra.c
>> @@ -209,7 +209,9 @@
>>   #define  RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK    0xffffffff
>>     #define RP_VEND_XP    0x00000f00
>> -#define  RP_VEND_XP_DL_UP    (1 << 30)
>> +#define  RP_VEND_XP_DL_UP            (1 << 30)
>> +#define  RP_VEND_XP_OPPORTUNISTIC_ACK        (1 << 27)
>> +#define  RP_VEND_XP_OPPORTUNISTIC_UPDATEFC    (1 << 28)
>>   
> BIT macro is preferred here.
Left shift is used everywhere, so to be inline with that I used same format
>>   #define RP_VEND_CTL1    0xf48
>>   #define  RP_VEND_CTL1_ERPT    (1 << 13)
>> @@ -2147,6 +2149,16 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
>>       writel(value, port->base + RP_VEND_CTL1);
>>   }
>>   +static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
>> +{
>> +    unsigned long value;
>> +
>> +    /* Optimal settings to enhance bandwidth */
>> +    value = readl(port->base + RP_VEND_XP);
>> +    value |= RP_VEND_XP_OPPORTUNISTIC_ACK;
>> +    value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC;
>> +    writel(value, port->base + RP_VEND_XP);
>> +}
>>   /*
>>    * FIXME: If there are no PCIe cards attached, then calling this function
>>    * can result in the increase of the bootup time as there are big timeout
>> @@ -2215,6 +2227,7 @@ static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
>>           if (soc->program_ectl_settings)
>>               tegra_pcie_program_ectl_settings(port);
>>           tegra_pcie_enable_rp_features(port);
>> +        tegra_pcie_apply_sw_fixup(port);
>>       }
>>         /* take the PCIe interface module out of reset */
> 

  reply	other threads:[~2017-10-30  3:55 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-27 19:29 [PATCH 00/12] Enable Tegra root port features and apply SW fixups Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 01/12] PCI: tegra: Start LTSSM after programming root port Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 03/12] PCI: tegra: Retrain link for Gen2 speed Manikanta Maddireddy
     [not found]   ` <1509132569-9398-4-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-29  9:34     ` Vidya Sagar
2017-10-29  9:38       ` Vidya Sagar
2017-10-30  3:51       ` Manikanta Maddireddy
     [not found] ` <1509132569-9398-1-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-27 19:29   ` [PATCH 02/12] PCI: tegra: Move REFCLK pad settings out of phy_power_on() Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 04/12] PCI: tegra: Advertise AER capability Manikanta Maddireddy
     [not found]     ` <1509132569-9398-5-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-29  9:39       ` Vidya Sagar
     [not found]         ` <64d00808-9c79-86b5-130d-835e3e5d5c1c-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-30  3:54           ` Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 05/12] PCI: tegra: Program UPHY electrical settings in Tegra210 Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2 Manikanta Maddireddy
2017-10-29  9:42     ` Vidya Sagar
     [not found]       ` <76a66fde-077b-7ced-7a4b-70d68451295d-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-30  3:56         ` Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 11/12] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 12/12] PCI: tegra: Update flow control threshold in Tegra210 Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 06/12] PCI: tegra: Enable opportunistic update FC and ACK Manikanta Maddireddy
     [not found]   ` <1509132569-9398-7-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-29  9:41     ` Vidya Sagar
2017-10-30  3:55       ` Manikanta Maddireddy [this message]
2017-10-27 19:29 ` [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2017-10-29  9:42   ` Vidya Sagar
2017-10-30  3:55     ` Manikanta Maddireddy
     [not found]   ` <1509132569-9398-8-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-30 15:58     ` David Laight
     [not found]       ` <063D6719AE5E284EB5DD2968C1650D6DD00A90B0-VkEWCZq2GCInGFn1LkZF6NBPR1lH4CV8@public.gmane.org>
2017-10-30 16:18         ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 09/12] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2017-10-29  9:43   ` Vidya Sagar
     [not found]     ` <f5173fb7-1c4a-f3bb-92a6-25034dfb3573-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-30  3:56       ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 10/12] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy

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