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From: Vidya Sagar <vidyas@nvidia.com>
To: Manikanta Maddireddy <mmaddireddy@nvidia.com>,
	thierry.reding@gmail.com, bhelgaas@google.com,
	jonathanh@nvidia.com
Cc: linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org,
	kthota@nvidia.com
Subject: Re: [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating
Date: Sun, 29 Oct 2017 15:12:32 +0530	[thread overview]
Message-ID: <171c265a-c1f9-913c-54e5-02b325a7487c@nvidia.com> (raw)
In-Reply-To: <1509132569-9398-8-git-send-email-mmaddireddy@nvidia.com>



On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
> When there are 32 outstanding writes from AFI to memory, the outstanding
> write counter overflows and indicates that there are "0" outstanding write
> transactions. This outstanding write counter is used to generate IDLE
> signal to dynamically gate the AFI clock.
>
> When memory controller is under heavy load, its possible that write
> completions will come back to AFI after long delay and AFI write counter
> overflows. AFI clock gets gated even when there are outstanding
> transactions towards memory controller resutling in system hang.
>
> Disable dynamic clock gating of AFI clock to avoid system hang.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>   drivers/pci/host/pci-tegra.c | 10 ++++++----
>   1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index 27a8211c48b2..b8cac871712b 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -103,8 +103,9 @@
>   #define AFI_MSI_EN_VEC6		0xa4
>   #define AFI_MSI_EN_VEC7		0xa8
>   
> -#define AFI_CONFIGURATION		0xac
> -#define  AFI_CONFIGURATION_EN_FPCI	(1 << 0)
> +#define AFI_CONFIGURATION			0xac
> +#define  AFI_CONFIGURATION_EN_FPCI		(1 << 0)
> +#define  AFI_CONFIGURATION_CLKEN_OVERRIDE	(1 << 31)
BIT macro is preferred here.
>   
>   #define AFI_FPCI_ERROR_MASKS	0xb0
>   
> @@ -1057,9 +1058,10 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
>   		}
>   	}
>   
> -	/* finally enable PCIe */
> +	/* Disable AFI dynamic clock gating and enable PCIe */
>   	value = afi_readl(pcie, AFI_CONFIGURATION);
> -	value |= AFI_CONFIGURATION_EN_FPCI;
> +	value |= (AFI_CONFIGURATION_EN_FPCI |
> +			AFI_CONFIGURATION_CLKEN_OVERRIDE);
>   	afi_writel(pcie, value, AFI_CONFIGURATION);
>   
>   	value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |

  reply	other threads:[~2017-10-29  9:42 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-27 19:29 [PATCH 00/12] Enable Tegra root port features and apply SW fixups Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 01/12] PCI: tegra: Start LTSSM after programming root port Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 03/12] PCI: tegra: Retrain link for Gen2 speed Manikanta Maddireddy
     [not found]   ` <1509132569-9398-4-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-29  9:34     ` Vidya Sagar
2017-10-29  9:38       ` Vidya Sagar
2017-10-30  3:51       ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 06/12] PCI: tegra: Enable opportunistic update FC and ACK Manikanta Maddireddy
     [not found]   ` <1509132569-9398-7-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-29  9:41     ` Vidya Sagar
2017-10-30  3:55       ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2017-10-29  9:42   ` Vidya Sagar [this message]
2017-10-30  3:55     ` Manikanta Maddireddy
     [not found]   ` <1509132569-9398-8-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-30 15:58     ` David Laight
     [not found]       ` <063D6719AE5E284EB5DD2968C1650D6DD00A90B0-VkEWCZq2GCInGFn1LkZF6NBPR1lH4CV8@public.gmane.org>
2017-10-30 16:18         ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 09/12] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2017-10-29  9:43   ` Vidya Sagar
     [not found]     ` <f5173fb7-1c4a-f3bb-92a6-25034dfb3573-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-30  3:56       ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 10/12] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy
     [not found] ` <1509132569-9398-1-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-27 19:29   ` [PATCH 02/12] PCI: tegra: Move REFCLK pad settings out of phy_power_on() Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 04/12] PCI: tegra: Advertise AER capability Manikanta Maddireddy
     [not found]     ` <1509132569-9398-5-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-29  9:39       ` Vidya Sagar
     [not found]         ` <64d00808-9c79-86b5-130d-835e3e5d5c1c-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-30  3:54           ` Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 05/12] PCI: tegra: Program UPHY electrical settings in Tegra210 Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2 Manikanta Maddireddy
2017-10-29  9:42     ` Vidya Sagar
     [not found]       ` <76a66fde-077b-7ced-7a4b-70d68451295d-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-30  3:56         ` Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 11/12] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 12/12] PCI: tegra: Update flow control threshold in Tegra210 Manikanta Maddireddy

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