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From: Vidya Sagar <vidyas@nvidia.com>
To: Manikanta Maddireddy <mmaddireddy@nvidia.com>,
	thierry.reding@gmail.com, bhelgaas@google.com,
	jonathanh@nvidia.com
Cc: linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org,
	kthota@nvidia.com
Subject: Re: [PATCH 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2
Date: Sun, 29 Oct 2017 15:12:48 +0530	[thread overview]
Message-ID: <76a66fde-077b-7ced-7a4b-70d68451295d@nvidia.com> (raw)
In-Reply-To: <1509132569-9398-9-git-send-email-mmaddireddy@nvidia.com>



On Saturday 28 October 2017 12:59 AM, Manikanta Maddireddy wrote:
> Set required bit to have LTSSM wait for DLLP to finish before entering L1
> or L2. This avoids truncation of PM messages which results in receiver
> errors.
>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>   drivers/pci/host/pci-tegra.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
>
> diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
> index b8cac871712b..6028d5f3d5bb 100644
> --- a/drivers/pci/host/pci-tegra.c
> +++ b/drivers/pci/host/pci-tegra.c
> @@ -217,6 +217,9 @@
>   #define RP_VEND_CTL1	0xf48
>   #define  RP_VEND_CTL1_ERPT	(1 << 13)
>   
> +#define RP_VEND_XP_BIST	0xf4c
> +#define  RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE	(1 << 28)
> +
BIT macro is preferred here.
>   #define RP_VEND_CTL2 0x00000fa8
>   #define  RP_VEND_CTL2_PCA_ENABLE (1 << 7)
>   
> @@ -2160,6 +2163,13 @@ static void tegra_pcie_apply_sw_fixup(struct tegra_pcie_port *port)
>   	value |= RP_VEND_XP_OPPORTUNISTIC_ACK;
>   	value |= RP_VEND_XP_OPPORTUNISTIC_UPDATEFC;
>   	writel(value, port->base + RP_VEND_XP);
> +
> +	/* LTSSM will wait for DLLP to finish before entering L1 or L2,
> +	 * to avoid truncation of PM messages which results in receiver errors
> +	 */
> +	value = readl(port->base + RP_VEND_XP_BIST);
> +	value |= RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE;
> +	writel(value, port->base + RP_VEND_XP_BIST);
>   }
>   /*
>    * FIXME: If there are no PCIe cards attached, then calling this function

  reply	other threads:[~2017-10-29  9:42 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-27 19:29 [PATCH 00/12] Enable Tegra root port features and apply SW fixups Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 01/12] PCI: tegra: Start LTSSM after programming root port Manikanta Maddireddy
     [not found] ` <1509132569-9398-1-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-27 19:29   ` [PATCH 02/12] PCI: tegra: Move REFCLK pad settings out of phy_power_on() Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 04/12] PCI: tegra: Advertise AER capability Manikanta Maddireddy
     [not found]     ` <1509132569-9398-5-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-29  9:39       ` Vidya Sagar
     [not found]         ` <64d00808-9c79-86b5-130d-835e3e5d5c1c-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-30  3:54           ` Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 05/12] PCI: tegra: Program UPHY electrical settings in Tegra210 Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 08/12] PCI: tegra: Wait for DLLP to finish before entering L1 or L2 Manikanta Maddireddy
2017-10-29  9:42     ` Vidya Sagar [this message]
     [not found]       ` <76a66fde-077b-7ced-7a4b-70d68451295d-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-30  3:56         ` Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 11/12] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2017-10-27 19:29   ` [PATCH 12/12] PCI: tegra: Update flow control threshold in Tegra210 Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 03/12] PCI: tegra: Retrain link for Gen2 speed Manikanta Maddireddy
     [not found]   ` <1509132569-9398-4-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-29  9:34     ` Vidya Sagar
2017-10-29  9:38       ` Vidya Sagar
2017-10-30  3:51       ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 06/12] PCI: tegra: Enable opportunistic update FC and ACK Manikanta Maddireddy
     [not found]   ` <1509132569-9398-7-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-29  9:41     ` Vidya Sagar
2017-10-30  3:55       ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2017-10-29  9:42   ` Vidya Sagar
2017-10-30  3:55     ` Manikanta Maddireddy
     [not found]   ` <1509132569-9398-8-git-send-email-mmaddireddy-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-30 15:58     ` David Laight
     [not found]       ` <063D6719AE5E284EB5DD2968C1650D6DD00A90B0-VkEWCZq2GCInGFn1LkZF6NBPR1lH4CV8@public.gmane.org>
2017-10-30 16:18         ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 09/12] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2017-10-29  9:43   ` Vidya Sagar
     [not found]     ` <f5173fb7-1c4a-f3bb-92a6-25034dfb3573-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-10-30  3:56       ` Manikanta Maddireddy
2017-10-27 19:29 ` [PATCH 10/12] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy

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