[PATCH v2 0/6] Keep the fuse clock enabled while the Tegra GPU is powered

[PATCH v2 0/6] Keep the fuse clock enabled while the Tegra GPU is powered

[Sasha Levin]

Since the GPU on the Jetson TX1 was enabled in its device tree, nouveau
often fails to bring up the GM20B: BOOT_0 reads back garbage, PRI reads
time out, or the first register reads stall until an SError. The GPU needs
the fuse clock running while it is powered, but nothing keeps that clock
enabled: the Tegra fuse driver only turns it on around its own fuse reads.

This series describes the fuse clock in the GPU device tree nodes and has
nouveau keep it enabled from before the GPU rail is turned on until after
it is turned off. Patch 1 makes the fuse clock required by the binding and
lists the exact clocks for each GPU. Patches 2-5 add it to the Tegra124,
Tegra132, Tegra186 and Tegra210 device trees; Tegra194 already has it.
Patch 6 makes nouveau use it.

nouveau keeps treating the fuse clock as optional, so device trees that
lack it continue to work as before.

On eight Jetson TX1 devkits, the GPU failed to come up in 27 of 109 boots
without the fix and in 11 of 291 with it; patch 6 has the details. Aaron
Kling reported that a Jetson Nano that almost never loaded nouveau did so
on 3 of 3 boots with v1. The Tegra124, Tegra132 and Tegra186 device tree
changes have only been checked with dtbs_check.

Changes in v2:
- 1/6: List the exact clocks for each GPU, so that "fuse" cannot appear
  twice, and make the fuse clock required (Thierry).
- 2/6, 3/6, 4/6: New. Add the fuse clock to the Tegra124, Tegra132 and
  Tegra186 GPUs as well (Thierry).
- 5/6: Add a Fixes: tag, as the nouveau fix depends on it.
- 6/6: Disable the fuse clock on power down even if disabling the
  regulator fails (sashiko).

v1: https://lore.kernel.org/r/20261013145210.103565-1-sashal@kernel.org

Sasha Levin (6):
  dt-bindings: gpu: nvidia,gk20a: Require the fuse clock
  ARM: tegra: Add the fuse clock to the Tegra124 GPU
  arm64: tegra: Add the fuse clock to the Tegra132 GPU
  arm64: tegra: Add the fuse clock to the Tegra186 GPU
  arm64: tegra: Add the fuse clock to the Tegra210 GPU
  drm/nouveau/tegra: Keep the fuse clock enabled while the GPU is
    powered

 .../devicetree/bindings/gpu/nvidia,gk20a.yaml | 52 ++++++++++++++-----
 arch/arm/boot/dts/nvidia/tegra124.dtsi        |  5 +-
 arch/arm64/boot/dts/nvidia/tegra132.dtsi      |  5 +-
 arch/arm64/boot/dts/nvidia/tegra186.dtsi      |  5 +-
 arch/arm64/boot/dts/nvidia/tegra210.dtsi      |  5 +-
 .../gpu/drm/nouveau/include/nvkm/core/tegra.h |  1 +
 .../drm/nouveau/nvkm/engine/device/tegra.c    | 22 +++++---
 7 files changed, 69 insertions(+), 26 deletions(-)


base-commit: 70dd4ee72eb2d5793c62e71c14e3aba78e5a4e56
-- 
2.53.0

[PATCH v2 1/6] dt-bindings: gpu: nvidia,gk20a: Require the fuse clock

[Sasha Levin]

The GM20B on Tegra210 often fails to initialize unless the fuse clock
is running while the GPU is powered, and the GPUs on the other Tegra
generations are expected to have the same requirement. Tegra194 already
describes the fuse clock for its GV11B.

Make the fuse clock required for all of them, and list the exact clocks
for each GPU instead of allowing either the reference or the fuse clock
as the third one: GM20B takes the fuse clock after its reference clock,
the others take it after the GPU and power clocks.

The nouveau driver keeps treating the fuse clock as optional, so device
trees that lack it continue to work as before.

Assisted-by: LLM
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 .../devicetree/bindings/gpu/nvidia,gk20a.yaml | 52 ++++++++++++++-----
 1 file changed, 40 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
index 4d856a8b674c5..af0ada6e02557 100644
--- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
+++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml
@@ -39,18 +39,12 @@ properties:
       Regulator for GPU supply voltage
 
   clocks:
-    minItems: 2
-    items:
-      - description: GPU clock
-      - description: Power clock
-      - description: Reference or fuse clock
+    minItems: 3
+    maxItems: 4
 
   clock-names:
-    minItems: 2
-    items:
-      - const: gpu
-      - const: pwr
-      - enum: [ ref, fuse ]
+    minItems: 3
+    maxItems: 4
 
   resets:
     maxItems: 1
@@ -86,6 +80,39 @@ required:
   - reset-names
 
 allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,gm20b
+    then:
+      properties:
+        clocks:
+          items:
+            - description: GPU clock
+            - description: Power clock
+            - description: Reference clock
+            - description: Fuse clock
+
+        clock-names:
+          items:
+            - const: gpu
+            - const: pwr
+            - const: ref
+            - const: fuse
+    else:
+      properties:
+        clocks:
+          items:
+            - description: GPU clock
+            - description: Power clock
+            - description: Fuse clock
+
+        clock-names:
+          items:
+            - const: gpu
+            - const: pwr
+            - const: fuse
   - if:
       properties:
         compatible:
@@ -163,8 +190,9 @@ examples:
         interrupt-names = "stall", "nonstall";
         vdd-supply = <&vdd_gpu>;
         clocks = <&tegra_car TEGRA124_CLK_GPU>,
-                 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
-        clock-names = "gpu", "pwr";
+                 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>,
+                 <&tegra_car TEGRA124_CLK_FUSE>;
+        clock-names = "gpu", "pwr", "fuse";
         resets = <&tegra_car 184>;
         reset-names = "gpu";
         iommus = <&mc TEGRA_SWGROUP_GPU>;
-- 
2.53.0

[PATCH v2 2/6] ARM: tegra: Add the fuse clock to the Tegra124 GPU

[Sasha Levin]

The GPU needs the fuse clock running while it is powered: the GM20B
on Tegra210 often fails to initialize without it, and the GK20A on
Tegra124 is expected to have the same requirement. Describe the fuse
clock so that the GPU driver can keep it enabled.

Assisted-by: LLM
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/arm/boot/dts/nvidia/tegra124.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi
index ce4efa1de509b..002acc7357238 100644
--- a/arch/arm/boot/dts/nvidia/tegra124.dtsi
+++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi
@@ -327,8 +327,9 @@ gpu@57000000 {
 			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "stall", "nonstall";
 		clocks = <&tegra_car TEGRA124_CLK_GPU>,
-			 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
-		clock-names = "gpu", "pwr";
+			 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>,
+			 <&tegra_car TEGRA124_CLK_FUSE>;
+		clock-names = "gpu", "pwr", "fuse";
 		resets = <&tegra_car 184>;
 		reset-names = "gpu";
 
-- 
2.53.0

[PATCH v2 3/6] arm64: tegra: Add the fuse clock to the Tegra132 GPU

[Sasha Levin]

The GPU needs the fuse clock running while it is powered: the GM20B
on Tegra210 often fails to initialize without it, and the GK20A on
Tegra132 is expected to have the same requirement. Describe the fuse
clock so that the GPU driver can keep it enabled.

Assisted-by: LLM
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/arm64/boot/dts/nvidia/tegra132.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
index 26cd11a8a4a12..30f0d87aa70c2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi
@@ -195,8 +195,9 @@ gpu@57000000 {
 			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "stall", "nonstall";
 		clocks = <&tegra_car TEGRA124_CLK_GPU>,
-			 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
-		clock-names = "gpu", "pwr";
+			 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>,
+			 <&tegra_car TEGRA124_CLK_FUSE>;
+		clock-names = "gpu", "pwr", "fuse";
 		resets = <&tegra_car 184>;
 		reset-names = "gpu";
 		status = "disabled";
-- 
2.53.0

[PATCH v2 4/6] arm64: tegra: Add the fuse clock to the Tegra186 GPU

[Sasha Levin]

The GPU needs the fuse clock running while it is powered: Tegra194
already describes it for its GV11B, and the GM20B on Tegra210 often
fails to initialize without it, so the GP10B on Tegra186 is expected
to need it as well. Describe the fuse clock so that the GPU driver
can keep it enabled.

Assisted-by: LLM
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 705af0373a090..7d2dd0713de5c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1883,8 +1883,9 @@ gpu@17000000 {
 		interrupt-names = "stall", "nonstall";
 
 		clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
-			 <&bpmp TEGRA186_CLK_GPU>;
-		clock-names = "gpu", "pwr";
+			 <&bpmp TEGRA186_CLK_GPU>,
+			 <&bpmp TEGRA186_CLK_FUSE>;
+		clock-names = "gpu", "pwr", "fuse";
 		resets = <&bpmp TEGRA186_RESET_GPU>;
 		reset-names = "gpu";
 		status = "disabled";
-- 
2.53.0

[PATCH v2 5/6] arm64: tegra: Add the fuse clock to the Tegra210 GPU

[Sasha Levin]

The GM20B GPU on Tegra210 needs the fuse clock running while it is
powered. Describe it so that the GPU driver can keep it enabled.

Fixes: d1b725476104 ("arm64: tegra: p2180: Explicitly enable GPU")
Assisted-by: LLM
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 5f5e5370d7096..2e84b2bda3142 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -446,8 +446,9 @@ gpu@57000000 {
 		interrupt-names = "stall", "nonstall";
 		clocks = <&tegra_car TEGRA210_CLK_GPU>,
 			 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
-			 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
-		clock-names = "gpu", "pwr", "ref";
+			 <&tegra_car TEGRA210_CLK_PLL_G_REF>,
+			 <&tegra_car TEGRA210_CLK_FUSE>;
+		clock-names = "gpu", "pwr", "ref", "fuse";
 		resets = <&tegra_car 184>;
 		reset-names = "gpu";
 
-- 
2.53.0

[PATCH v2 6/6] drm/nouveau/tegra: Keep the fuse clock enabled while the GPU is powered

[Sasha Levin]

Since the GPU on the Jetson TX1 was enabled in commit d1b725476104
("arm64: tegra: p2180: Explicitly enable GPU"), nouveau often fails to
bring up the GM20B. Either BOOT_0 reads back garbage ("unknown chipset
(5ffefa47)"), or PRI reads of the GPC PLL time out ("MMIO read of
00000000 FAULT at 137000 [ TIMEOUT ]"), or the first register reads in
nvkm_device_ctor() stall until an asynchronous SError. How often depends
on the board; one board fails on every boot.

nouveau powers the GPU up with the fuse clock gated: since commit
24a15252ff04 ("soc/tegra: fuse: Add runtime PM support"), the Tegra fuse
driver only enables that clock around its own fuse reads. NVIDIA's
downstream nvgpu driver enables the fuse clock along with the other GPU
clocks whenever the GPU is powered. Do the same: take an optional "fuse"
clock and keep it enabled from before the GPU rail is turned on until
after it is turned off. The clock is optional so that device trees that
lack it keep working as before.

Tested on eight Jetson TX1 devkits, on mainline and on v6.18. Without
this patch, the GPU failed to come up in 27 of 109 boots; with it, in 11
of 291, none of them with a garbage BOOT_0. On the board that failed on
every boot, 38 of 40 boots now succeed. The remaining failures are
mostly a register read that stalls until an SError; wherever the console
shows when, nouveau had already finished probing. Such stalls also occur
without this patch and are a separate problem. The Jetson Nano, which
shares the Tegra210 GPU node, still works (24 of 24 boots).

Fixes: d1b725476104 ("arm64: tegra: p2180: Explicitly enable GPU")
Assisted-by: LLM
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 .../gpu/drm/nouveau/include/nvkm/core/tegra.h |  1 +
 .../drm/nouveau/nvkm/engine/device/tegra.c    | 22 ++++++++++++++-----
 2 files changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
index 6aaa30ef167f6..0189043382d02 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
@@ -15,6 +15,7 @@ struct nvkm_device_tegra {
 	struct clk *clk;
 	struct clk *clk_ref;
 	struct clk *clk_pwr;
+	struct clk *clk_fuse;
 
 	struct regulator *vdd;
 
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
index 3c8d0878891ad..74b292659ee9a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
@@ -32,6 +32,10 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
 {
 	int ret;
 
+	ret = clk_prepare_enable(tdev->clk_fuse);
+	if (ret)
+		return ret;
+
 	if (tdev->vdd) {
 		ret = regulator_enable(tdev->vdd);
 		if (ret)
@@ -76,26 +80,26 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
 	if (tdev->vdd)
 		regulator_disable(tdev->vdd);
 err_power:
+	clk_disable_unprepare(tdev->clk_fuse);
 	return ret;
 }
 
 static int
 nvkm_device_tegra_power_down(struct nvkm_device_tegra *tdev)
 {
-	int ret;
+	int ret = 0;
 
 	clk_disable_unprepare(tdev->clk_pwr);
 	clk_disable_unprepare(tdev->clk_ref);
 	clk_disable_unprepare(tdev->clk);
 	udelay(10);
 
-	if (tdev->vdd) {
+	if (tdev->vdd)
 		ret = regulator_disable(tdev->vdd);
-		if (ret)
-			return ret;
-	}
 
-	return 0;
+	clk_disable_unprepare(tdev->clk_fuse);
+
+	return ret;
 }
 
 static void
@@ -308,6 +312,12 @@ nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func,
 		goto free;
 	}
 
+	tdev->clk_fuse = devm_clk_get_optional(&pdev->dev, "fuse");
+	if (IS_ERR(tdev->clk_fuse)) {
+		ret = PTR_ERR(tdev->clk_fuse);
+		goto free;
+	}
+
 	tdev->pmc = devm_tegra_pmc_get(&pdev->dev);
 	if (IS_ERR(tdev->pmc)) {
 		ret = PTR_ERR(tdev->pmc);
-- 
2.53.0