From: Jon Hunter <jonathanh@nvidia.com>
To: webgeek1234@gmail.com, Thierry Reding <thierry.reding@gmail.com>,
Joseph Lo <josephl@nvidia.com>, Stephen Boyd <sboyd@kernel.org>
Cc: Thierry Reding <treding@nvidia.com>,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3] soc: tegra: fuse: speedo-tegra210: Update speedo ids
Date: Thu, 18 Sep 2025 10:45:37 +0100 [thread overview]
Message-ID: <2334a545-9a06-42d9-8282-674b94fdcb2f@nvidia.com> (raw)
In-Reply-To: <20250903-tegra210-speedo-v3-1-73e09e0fbb36@gmail.com>
On 04/09/2025 02:58, Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@gmail.com>
>
> Existing code only sets cpu and gpu speedo ids 0 and 1. The cpu dvfs
> code supports 11 ids and nouveau supports 5. This aligns with what the
> downstream vendor kernel supports. Align skus with the downstream list.
Do you have a reference for the downstream kernel change you are
referring to? I have found this change [0]. However, this does not quite
align with what you have in this patch.
Jon
[0]
https://nv-tegra.nvidia.com/r/plugins/gitiles/linux-5.10/+/2a8660e3d1e4f75ba4390b72991744174237b025%5E%21/#F0
--
nvpublic
next prev parent reply other threads:[~2025-09-18 9:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-04 1:58 [PATCH v3] soc: tegra: fuse: speedo-tegra210: Update speedo ids Aaron Kling via B4 Relay
2025-09-18 3:18 ` Mikko Perttunen
2025-09-18 9:45 ` Jon Hunter [this message]
2025-09-18 17:19 ` Aaron Kling
2025-09-19 9:55 ` Jon Hunter
2025-09-22 17:16 ` Aaron Kling
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