Re: [PATCH v3] soc: tegra: fuse: speedo-tegra210: Update speedo ids

[Mikko Perttunen <mperttunen@nvidia.com>]

On Thursday, September 4, 2025 10:58 AM Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@gmail.com>
> 
> Existing code only sets cpu and gpu speedo ids 0 and 1. The cpu dvfs
> code supports 11 ids and nouveau supports 5. This aligns with what the
> downstream vendor kernel supports. Align skus with the downstream list.
> 
> The Tegra210 CVB tables were added in the first referenced fixes commit.
> Since then, all Tegra210 socs have tried to scale to 1.9 GHz, when the
> supported devkits are only supposed to scale to 1.5 or 1.7 GHZ.
> Overclocking should not be the default state.
> 
> Fixes: 2b2dbc2f94e5 ("clk: tegra: dfll: add CVB tables for Tegra210")
> Fixes: 579db6e5d9b8 ("arm64: tegra: Enable DFLL support on Jetson Nano")
> Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
> ---
> The Tegra210 CVB tables were added in commit 2b2dbc2f94e5. Since then,
> all Tegra210 socs have tried to scale the cpu to 1.9 GHz, when the
> supported devkits are only supposed to scale to 1.5 or 1.7 GHZ.
> Overclocking should not be the default state.
> ---
> Changes in v3:
> - Drop all patches related to limiting cpu frequency from a dt property
> - Link to v2: https://lore.kernel.org/r/20250903-tegra210-speedo-v2-0-89e6f86b8942@gmail.com
> 
> Changes in v2:
> - Define units in patch 1
> - Update patch 1 commit message to better explain the need
> - Pull all downstream sku's into patch 2, which eliminates patch 3
> - Update patch 4 commit message to indicate the limit is due to thermal
>   constraints.
> - Link to v1: https://lore.kernel.org/r/20250816-tegra210-speedo-v1-0-a981360adc27@gmail.com
> ---
>  drivers/soc/tegra/fuse/speedo-tegra210.c | 62 ++++++++++++++++++++++----------
>  1 file changed, 43 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/soc/tegra/fuse/speedo-tegra210.c b/drivers/soc/tegra/fuse/speedo-tegra210.c
> index 695d0b7f9a8abe53c497155603147420cda40b63..60356159e00d2059e55eaacba27b5ca63bf96c90 100644
> --- a/drivers/soc/tegra/fuse/speedo-tegra210.c
> +++ b/drivers/soc/tegra/fuse/speedo-tegra210.c
> @@ -65,27 +65,51 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info,
>  	sku_info->gpu_speedo_id = 0;
>  	*threshold = THRESHOLD_INDEX_0;
>  
> -	switch (sku) {
> -	case 0x00: /* Engineering SKU */
> -	case 0x01: /* Engineering SKU */
> -	case 0x07:
> -	case 0x17:
> -	case 0x27:
> -		if (speedo_rev >= 2)
> +	if (speedo_rev >= 2) {
> +		switch (sku) {
> +		case 0x00: /* Engineering SKU */
> +		case 0x01: /* Engineering SKU */
> +		case 0x13:
> +			sku_info->cpu_speedo_id = 5;
> +			sku_info->gpu_speedo_id = 2;
> +			break;
> +
> +		case 0x07:
> +		case 0x17:
> +		case 0x1F:
> +			sku_info->cpu_speedo_id = 7;
> +			sku_info->gpu_speedo_id = 2;
> +			break;
> +
> +		case 0x27:
> +			sku_info->cpu_speedo_id = 1;
> +			sku_info->gpu_speedo_id = 2;
> +			break;
> +
> +		case 0x83:
> +			sku_info->cpu_speedo_id = 3;
> +			sku_info->gpu_speedo_id = 3;
> +			break;
> +
> +		case 0x87:
> +			sku_info->cpu_speedo_id = 2;
>  			sku_info->gpu_speedo_id = 1;
> -		break;
> -
> -	case 0x13:
> -		if (speedo_rev >= 2)
> -			sku_info->gpu_speedo_id = 1;
> -
> -		sku_info->cpu_speedo_id = 1;
> -		break;
> -
> -	default:
> +			break;
> +
> +		case 0x8F:
> +			sku_info->cpu_speedo_id = 9;
> +			sku_info->gpu_speedo_id = 2;
> +			break;
> +
> +		default:
> +			pr_err("Tegra210: unknown revision 2 or newer SKU %#04x\n", sku);
> +			/* Using the default for the error case */
> +			break;
> +		}
> +	} else if (sku == 0x00 || sku == 0x01 || sku == 0x07 || sku == 0x13 || sku == 0x17) {
> +		sku_info->gpu_speedo_id = 1;
> +	} else {
>  		pr_err("Tegra210: unknown SKU %#04x\n", sku);
> -		/* Using the default for the error case */
> -		break;
>  	}
>  }
>  
> 
> ---
> base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585
> change-id: 20250812-tegra210-speedo-470691e8b8cc
> 
> Best regards,
> 

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>