Re: [PATCH v3] soc: tegra: fuse: speedo-tegra210: Update speedo ids

[Jon Hunter <jonathanh@nvidia.com>]

On 18/09/2025 18:19, Aaron Kling wrote:
> On Thu, Sep 18, 2025 at 4:45 AM Jon Hunter <jonathanh@nvidia.com> wrote:
>>
>>
>> On 04/09/2025 02:58, Aaron Kling via B4 Relay wrote:
>>> From: Aaron Kling <webgeek1234@gmail.com>
>>>
>>> Existing code only sets cpu and gpu speedo ids 0 and 1. The cpu dvfs
>>> code supports 11 ids and nouveau supports 5. This aligns with what the
>>> downstream vendor kernel supports. Align skus with the downstream list.
>>
>> Do you have a reference for the downstream kernel change you are
>> referring to? I have found this change [0]. However, this does not quite
>> align with what you have in this patch.
> 
> This is based on L4T r32.7.6 [0], which builds up the list over
> several commits, so I can't link to just one. The first revision only
> added sku's that I had specifically verified. Mikko suggested to just
> import everything from downstream and to simplify the conditionals.
> And that's this revision.

...

> [0] https://nv-tegra.nvidia.com/r/plugins/gitiles/linux-4.9/+/refs/tags/tegra-l4t-r32.7.6_good/drivers/soc/tegra/fuse/speedo-tegra210.c#72


Thanks! I saw Mikko's comments on V2 and that makes sense. The problem I 
have is that comparing this with the above, it is not clear that these 
are equivalent. The above is using the 'a02' chip version for setting 
the speedo IDs but this is using the speedo revision. Now it might turn 
out this is equivalent, but it is not obvious to me. Ideally we would 
end up with something similar to the above.

Jon

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