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* [PATCH V2] PCI: tegra194: Set EP alignment restriction for inbound ATU
@ 2024-05-08  9:22 Jon Hunter
  2024-05-08  9:27 ` Niklas Cassel
  2024-05-17 11:31 ` Krzysztof Wilczyński
  0 siblings, 2 replies; 4+ messages in thread
From: Jon Hunter @ 2024-05-08  9:22 UTC (permalink / raw)
  To: Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
	Thierry Reding, Niklas Cassel
  Cc: Vidya Sagar, linux-pci, linux-tegra, Jon Hunter,
	Manikanta Maddireddy

Tegra194 and Tegra234 PCIe EP controllers have 64K alignment
restriction for the inbound ATU. Set the endpoint inbound ATU alignment to
64kB in the Tegra194 PCIe driver.

Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Suggested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
Changes since V1: Updated commit message.

 drivers/pci/controller/dwc/pcie-tegra194.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 93f5433c5c55..4537313ef37a 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2015,6 +2015,7 @@ static const struct pci_epc_features tegra_pcie_epc_features = {
 	.bar[BAR_3] = { .type = BAR_RESERVED, },
 	.bar[BAR_4] = { .type = BAR_RESERVED, },
 	.bar[BAR_5] = { .type = BAR_RESERVED, },
+	.align = SZ_64K,
 };
 
 static const struct pci_epc_features*
-- 
2.34.1


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Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2024-05-08  9:22 [PATCH V2] PCI: tegra194: Set EP alignment restriction for inbound ATU Jon Hunter
2024-05-08  9:27 ` Niklas Cassel
2024-05-15 21:21   ` Bjorn Helgaas
2024-05-17 11:31 ` Krzysztof Wilczyński

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