[PATCH 0/2] rt5677: add mclk to DT binding and define it for Smaug

[PATCH 0/2] rt5677: add mclk to DT binding and define it for Smaug

[Diogo Ivo]

The RT5677 codec has an mclk input that can be fed by an externally
provided clock signal. This small series adds this to the existing
device tree binding and defines the clock that is connected to it
in the specific case of Smaug.

Signed-off-by: Diogo Ivo <diogo.ivo@bootlin.com>
---
Diogo Ivo (2):
      ASoC: dt-bindings: realtek,rt5677: Add clock property
      arm64: tegra: smaug: Add rt5677 mclk input

 Documentation/devicetree/bindings/sound/realtek,rt5677.yaml | 10 ++++++++++
 arch/arm64/boot/dts/nvidia/tegra210-smaug.dts               |  2 ++
 2 files changed, 12 insertions(+)
---
base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
change-id: 20260903-rt5677-mclk-f3ad74db43e1

Best regards,
--  
Diogo Ivo <diogo.ivo@bootlin.com>

[PATCH 1/2] ASoC: dt-bindings: realtek,rt5677: Add clock property

[Diogo Ivo]

Add a clock property as the RT5677 codec can be fed an
external clock signal.

Signed-off-by: Diogo Ivo <diogo.ivo@bootlin.com>
---
 Documentation/devicetree/bindings/sound/realtek,rt5677.yaml | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/sound/realtek,rt5677.yaml b/Documentation/devicetree/bindings/sound/realtek,rt5677.yaml
index ae27ae78b1b2..e9fb97a48445 100644
--- a/Documentation/devicetree/bindings/sound/realtek,rt5677.yaml
+++ b/Documentation/devicetree/bindings/sound/realtek,rt5677.yaml
@@ -44,6 +44,14 @@ properties:
   '#gpio-cells':
     const: 2
 
+  clocks:
+    items:
+      - description: phandle and clock specifier for codec MCLK.
+
+  clock-names:
+    items:
+      - const: mclk
+
   realtek,pow-ldo2-gpio:
     maxItems: 1
     description: CODEC's POW_LDO2 pin.
@@ -127,6 +135,8 @@ examples:
             interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
             gpio-controller;
             #gpio-cells = <2>;
+            clocks = <&osc>;
+            clock-names = "mclk";
             realtek,pow-ldo2-gpio = <&gpio 3 GPIO_ACTIVE_HIGH>;
             realtek,reset-gpio = <&gpio 3 GPIO_ACTIVE_LOW>;
             realtek,in1-differential;

-- 
2.55.0

[PATCH 2/2] arm64: tegra: smaug: Add rt5677 mclk input

[Diogo Ivo]

The mclk input of the RT5677 codec is connected to an SoC-provided
clock signal on Smaug. Add the clock definition to its node.

Signed-off-by: Diogo Ivo <diogo.ivo@bootlin.com>
---
 arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
index e0fde65a552b..5513319d3198 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
@@ -1754,6 +1754,8 @@ audio-codec@2d {
 			realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>;
 			gpio-controller;
 			#gpio-cells = <2>;
+			clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
+			clock-names = "mclk";
 			status = "okay";
 		};
 

-- 
2.55.0

Re: [PATCH 1/2] ASoC: dt-bindings: realtek,rt5677: Add clock property

[Mark Brown]

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On Thu, Sep 03, 2026 at 12:11:00AM +0200, Diogo Ivo wrote:
> Add a clock property as the RT5677 codec can be fed an
> external clock signal.

> +  clocks:
> +    items:
> +      - description: phandle and clock specifier for codec MCLK.
> +
> +  clock-names:
> +    items:
> +      - const: mclk

The driver code has a reference to MCLK1 which implies multiple MCLKs,
unfortunately no pinout seems to be available and other references in
the driver are just to MCLK so it could be cut'n'paste.

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Re: [PATCH 1/2] ASoC: dt-bindings: realtek,rt5677: Add clock property

[Diogo Ivo]

Hi Mark,

On 9/3/26 11:57 AM, Mark Brown wrote:
> On Thu, Sep 03, 2026 at 12:11:00AM +0200, Diogo Ivo wrote:
>> Add a clock property as the RT5677 codec can be fed an
>> external clock signal.
> 
>> +  clocks:
>> +    items:
>> +      - description: phandle and clock specifier for codec MCLK.
>> +
>> +  clock-names:
>> +    items:
>> +      - const: mclk
> 
> The driver code has a reference to MCLK1 which implies multiple MCLKs,
> unfortunately no pinout seems to be available and other references in
> the driver are just to MCLK so it could be cut'n'paste.

Thanks for raising this point, I had missed it completely. In fact,
looking at rt5677.h there are two places where MCLK2 is mentioned:

#define RT5677_MCLK_SRC_SFT                     10
#define RT5677_MCLK1_SRC                        (0x0 << 10)
#define RT5677_MCLK2_SRC                        (0x1 << 10)

and

#define RT5677_PLL2_PR_SRC_SFT                  15
#define RT5677_PLL2_PR_SRC_MCLK1                (0x0 << 15)
#define RT5677_PLL2_PR_SRC_MCLK2                (0x1 << 15)

so to me it _looks_ like there are indeed two MCLK inputs, both of which
can drive the MCLK clock and can also be the input of PLL2. However, as
you mentioned I also wasn't able to find the pinout/datasheet and I have
no way of testing this. I think the safest bet here is that I send a v2
where I rename "mclk" to "mclk1" that we know for a fact exists, and
then later on if someone with access to the actual datasheet comes along
and confirms the existence of "mclk2" we can add it to the binding.

Let me know what you think!

Best regards,
Diogo

Re: [PATCH 1/2] ASoC: dt-bindings: realtek,rt5677: Add clock property

[Mark Brown]

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On Thu, Sep 03, 2026 at 03:26:46PM +0200, Diogo Ivo wrote:
> On 9/3/26 11:57 AM, Mark Brown wrote:
> > On Thu, Sep 03, 2026 at 12:11:00AM +0200, Diogo Ivo wrote:

> > > +  clock-names:
> > > +    items:
> > > +      - const: mclk

> > The driver code has a reference to MCLK1 which implies multiple MCLKs,
> > unfortunately no pinout seems to be available and other references in
> > the driver are just to MCLK so it could be cut'n'paste.

> Thanks for raising this point, I had missed it completely. In fact,
> looking at rt5677.h there are two places where MCLK2 is mentioned:

> #define RT5677_MCLK_SRC_SFT                     10
> #define RT5677_MCLK1_SRC                        (0x0 << 10)
> #define RT5677_MCLK2_SRC                        (0x1 << 10)

> and

> #define RT5677_PLL2_PR_SRC_SFT                  15
> #define RT5677_PLL2_PR_SRC_MCLK1                (0x0 << 15)
> #define RT5677_PLL2_PR_SRC_MCLK2                (0x1 << 15)

> so to me it _looks_ like there are indeed two MCLK inputs, both of which
> can drive the MCLK clock and can also be the input of PLL2. However, as
> you mentioned I also wasn't able to find the pinout/datasheet and I have
> no way of testing this. I think the safest bet here is that I send a v2
> where I rename "mclk" to "mclk1" that we know for a fact exists, and
> then later on if someone with access to the actual datasheet comes along
> and confirms the existence of "mclk2" we can add it to the binding.

> Let me know what you think!

That would be safe, but let's add the Realtek maintainer (who I'm
surprised you didn't CC...).  I've also added Ben Zhang who did a bunch
of work on the device for Chrome and might be able to check too.

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Re: [PATCH 1/2] ASoC: dt-bindings: realtek,rt5677: Add clock property

[Diogo Ivo]

On 9/3/26 11:01 PM, Mark Brown wrote:
> On Thu, Sep 03, 2026 at 03:26:46PM +0200, Diogo Ivo wrote:
>> On 9/3/26 11:57 AM, Mark Brown wrote:
>>> On Thu, Sep 03, 2026 at 12:11:00AM +0200, Diogo Ivo wrote:
> 
>>>> +  clock-names:
>>>> +    items:
>>>> +      - const: mclk
> 
>>> The driver code has a reference to MCLK1 which implies multiple MCLKs,
>>> unfortunately no pinout seems to be available and other references in
>>> the driver are just to MCLK so it could be cut'n'paste.
> 
>> Thanks for raising this point, I had missed it completely. In fact,
>> looking at rt5677.h there are two places where MCLK2 is mentioned:
> 
>> #define RT5677_MCLK_SRC_SFT                     10
>> #define RT5677_MCLK1_SRC                        (0x0 << 10)
>> #define RT5677_MCLK2_SRC                        (0x1 << 10)
> 
>> and
> 
>> #define RT5677_PLL2_PR_SRC_SFT                  15
>> #define RT5677_PLL2_PR_SRC_MCLK1                (0x0 << 15)
>> #define RT5677_PLL2_PR_SRC_MCLK2                (0x1 << 15)
> 
>> so to me it _looks_ like there are indeed two MCLK inputs, both of which
>> can drive the MCLK clock and can also be the input of PLL2. However, as
>> you mentioned I also wasn't able to find the pinout/datasheet and I have
>> no way of testing this. I think the safest bet here is that I send a v2
>> where I rename "mclk" to "mclk1" that we know for a fact exists, and
>> then later on if someone with access to the actual datasheet comes along
>> and confirms the existence of "mclk2" we can add it to the binding.
> 
>> Let me know what you think!
> 
> That would be safe, but let's add the Realtek maintainer (who I'm
> surprised you didn't CC...).  I've also added Ben Zhang who did a bunch
> of work on the device for Chrome and might be able to check too.

Thanks for including them. I simply continued the conversation with the
initial recipients coming from b4 prep --auto-to-cc.

Diogo