* [RFC 6/7] ath9k_hw: Program correct PLL value for AR9565
@ 2012-09-08 7:28 Sujith Manoharan
2012-09-08 8:08 ` Felix Fietkau
0 siblings, 1 reply; 3+ messages in thread
From: Sujith Manoharan @ 2012-09-08 7:28 UTC (permalink / raw)
To: linville; +Cc: linux-wireless
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
---
drivers/net/wireless/ath/ath9k/hw.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 063d724..07dd330 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -837,6 +837,9 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
udelay(1000);
+
+ if (AR_SREV_9565(ah))
+ REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x4142c);
} else if (AR_SREV_9330(ah)) {
u32 ddr_dpll2, pll_control2, kd;
@@ -917,9 +920,10 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
udelay(1000);
}
- pll = ath9k_hw_compute_pll_control(ah, chan);
-
- REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
+ if (!AR_SREV_9565(ah)) {
+ pll = ath9k_hw_compute_pll_control(ah, chan);
+ REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
+ }
if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
AR_SREV_9550(ah))
--
1.7.12
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [RFC 6/7] ath9k_hw: Program correct PLL value for AR9565
2012-09-08 7:28 [RFC 6/7] ath9k_hw: Program correct PLL value for AR9565 Sujith Manoharan
@ 2012-09-08 8:08 ` Felix Fietkau
2012-09-08 8:17 ` Sujith Manoharan
0 siblings, 1 reply; 3+ messages in thread
From: Felix Fietkau @ 2012-09-08 8:08 UTC (permalink / raw)
To: Sujith Manoharan; +Cc: linville, linux-wireless
On 2012-09-08 9:28 AM, Sujith Manoharan wrote:
> Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
> ---
> drivers/net/wireless/ath/ath9k/hw.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
> index 063d724..07dd330 100644
> --- a/drivers/net/wireless/ath/ath9k/hw.c
> +++ b/drivers/net/wireless/ath/ath9k/hw.c
> @@ -837,6 +837,9 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
> REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
> AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
> udelay(1000);
> +
> + if (AR_SREV_9565(ah))
> + REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x4142c);
> } else if (AR_SREV_9330(ah)) {
> u32 ddr_dpll2, pll_control2, kd;
>
> @@ -917,9 +920,10 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
> udelay(1000);
> }
>
> - pll = ath9k_hw_compute_pll_control(ah, chan);
> -
> - REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
> + if (!AR_SREV_9565(ah)) {
> + pll = ath9k_hw_compute_pll_control(ah, chan);
> + REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
> + }
That looks messed up, how about just:
pll = ath9k_hw_compute_pll_control(ah, chan);
if (AR_SREV_9565(ah))
pll |= 0x40000;
REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
Or alternatively move that OR mask into ath9k_hw_compute_pll_control
- Felix
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [RFC 6/7] ath9k_hw: Program correct PLL value for AR9565
2012-09-08 8:08 ` Felix Fietkau
@ 2012-09-08 8:17 ` Sujith Manoharan
0 siblings, 0 replies; 3+ messages in thread
From: Sujith Manoharan @ 2012-09-08 8:17 UTC (permalink / raw)
To: Felix Fietkau; +Cc: Sujith Manoharan, linville, linux-wireless
Felix Fietkau wrote:
> That looks messed up, how about just:
>
> pll = ath9k_hw_compute_pll_control(ah, chan);
> if (AR_SREV_9565(ah))
> pll |= 0x40000;
> REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
>
> Or alternatively move that OR mask into ath9k_hw_compute_pll_control
[RFC v2] ath9k_hw: Program correct PLL value for AR9565
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
---
drivers/net/wireless/ath/ath9k/hw.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 063d724..47de1a9 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -918,7 +918,8 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
}
pll = ath9k_hw_compute_pll_control(ah, chan);
-
+ if (AR_SREV_9565(ah))
+ pll |= 0x40000;
REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
--
1.7.12
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2012-09-08 8:21 UTC | newest]
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2012-09-08 7:28 [RFC 6/7] ath9k_hw: Program correct PLL value for AR9565 Sujith Manoharan
2012-09-08 8:08 ` Felix Fietkau
2012-09-08 8:17 ` Sujith Manoharan
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