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From: "kannappan" <kannappan@tesbv.com>
To: <linuxppc-embedded@ozlabs.org>
Subject: PPC440SPe: generating PCIe INTx
Date: Wed, 16 Jan 2008 14:16:44 +0530	[thread overview]
Message-ID: <003601c8581c$55f27220$2900140a@Kanslaptop> (raw)

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Hello All,
 
I would like to know how to generate PCIe INTx interrupt from Legacy
PCIe EP in PPC440SPe.
 
Also, please clarify,
Page 741 of the user manual (PPC440SPe_UM2014_V1_26.pdf) write
Assert_INTx message to INT_ADDR[61:63].
Page 739, table 27-9, mentions, Assert_INTA by writing to Outbound GBIF
write channel 9, A[52:59]=0x20.
 
Whether the INT_ADDR is any addresses BAR3 / POM3 address?
What is the Assert_INTx value to be written to INT_ADDR[61:63]?  How do
I correlate with the message code values given in PCI express system
architecture?
 
The message codes given in PCI express system architecture is as follows
 

INTx Messages
Message Code

Assert_INTA
0010 0000

Assert_INTB
0010 0001

Assert_INTC
0010 0010

Assert_INTD
0010 0011

Deassert_INTA
0010 0100

Deassert_INTB
0010 0101

Deassert_INTC
0010 0110

Deassert_INTD
0010 0111
 
 
Regards,
Kans.

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                 reply	other threads:[~2008-01-16  9:13 UTC|newest]

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