Re: [PATCH 5/6] Clock and power management define fixes for 440SP

[Wade Farnsworth <wfarnsworth@mvista.com>]

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This fixes the clock and power management defines on the 440SP.

--Wade

Signed off by: Wade Farnsworth <wfarnsworth@mvista.com>

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diff --git a/arch/ppc/platforms/4xx/ibm440sp.h b/arch/ppc/platforms/4xx/ibm440sp.h
--- a/arch/ppc/platforms/4xx/ibm440sp.h
+++ b/arch/ppc/platforms/4xx/ibm440sp.h
@@ -32,33 +32,28 @@
 /* Clock and Power Management */
 #define IBM_CPM_IIC0		0x80000000	/* IIC interface */
 #define IBM_CPM_IIC1		0x40000000	/* IIC interface */
-#define IBM_CPM_PCI		0x20000000	/* PCI bridge */
-#define IBM_CPM_CPU		    0x02000000	/* processor core */
-#define IBM_CPM_DMA		    0x01000000	/* DMA controller */
-#define IBM_CPM_BGO		    0x00800000	/* PLB to OPB bus arbiter */
-#define IBM_CPM_BGI		    0x00400000	/* OPB to PLB bridge */
-#define IBM_CPM_EBC		    0x00200000	/* External Bux Controller */
-#define IBM_CPM_EBM		    0x00100000	/* Ext Bus Master Interface */
-#define IBM_CPM_DMC		    0x00080000	/* SDRAM peripheral controller */
-#define IBM_CPM_PLB		    0x00040000	/* PLB bus arbiter */
+#define IBM_CPM_PCIX0		0x20000000	/* PCIX bridge 0 */
+#define IBM_CPM_PCIX1		0x10000000	/* PCIX bridge 1 */
+#define IBM_CPM_PCIX2		0x08000000	/* PCIX bridge 2 */
+#define IBM_CPM_CPU		0x02000000	/* processor core */
+#define IBM_CPM_BGO		0x00800000	/* PLB to OPB bus arbiter */
+#define IBM_CPM_EBC		0x00200000	/* External Bux Controller */
+#define IBM_CPM_PLB		0x00040000	/* PLB bus arbiter */
 #define IBM_CPM_SRAM		0x00020000	/* SRAM memory controller */
-#define IBM_CPM_PPM		    0x00002000	/* PLB Performance Monitor */
 #define IBM_CPM_UIC1		0x00001000	/* Universal Interrupt Controller */
 #define IBM_CPM_GPIO0		0x00000800	/* General Purpose IO (??) */
-#define IBM_CPM_GPT		    0x00000400	/* General Purpose Timers  */
+#define IBM_CPM_GPT		0x00000400	/* General Purpose Timers  */
 #define IBM_CPM_UART0		0x00000200	/* serial port 0 */
 #define IBM_CPM_UART1		0x00000100	/* serial port 1 */
-#define IBM_CPM_UART2		0x00000100	/* serial port 1 */
 #define IBM_CPM_UIC0		0x00000080	/* Universal Interrupt Controller */
 #define IBM_CPM_TMRCLK		0x00000040	/* CPU timers */
 #define IBM_CPM_EMAC0  		0x00000020	/* EMAC 0     */
+#define IBM_CPM_UART2		0x00000010	/* serial port 2 */
 
-#define DFLT_IBM4xx_PM		~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
+#define DFLT_IBM4xx_PM		~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
 				| IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
-				| IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
-				| IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
-				| IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
-				| IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
-			  	| IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
+				| IBM_CPM_PLB | IBM_CPM_TMRCLK | IBM_CPM_PCIX0 \
+				| IBM_CPM_PCIX1 | IBM_CPM_PCIX2\
+				| IBM_CPM_EMAC0 )
 #endif /* __PPC_PLATFORMS_IBM440SP_H */
 #endif /* __KERNEL__ */