* PCIe interrupts in the device tree @ 2009-03-24 20:24 Johns Daniel 2009-03-24 20:54 ` Kumar Gala 0 siblings, 1 reply; 5+ messages in thread From: Johns Daniel @ 2009-03-24 20:24 UTC (permalink / raw) To: linuxppc-dev Could somebody please explain the declaration of the PCIe interrupts in the device tree? I was under the impression that PCIe interrupts in the PowerPC Linux kernel default to using INTx signaling (vs. external IRQ pin assertion and MSI signaling). Am I right? If so, then do the interrupt-map lines in the DTS refer to the internal IRQ used by Freescale processors to implement INTx virtual wire interrupts? For example, in the mpc8536ds.dts file, under "pci1: pcie@ffe09000" we have: interrupt-map = < /* IDSEL 0x0 */ 0000 0 0 1 &mpic 4 1 0000 0 0 2 &mpic 5 1 0000 0 0 3 &mpic 6 1 0000 0 0 4 &mpic 7 1 >; Are the 4, 5, 6, and 7 internal or external IRQs? And the "msi@41600" section in the same mpc8536ds.dts file does NOT affect PCIe interrupts unless a driver calls pci_enable_msi()? TIA! -- Johns ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: PCIe interrupts in the device tree 2009-03-24 20:24 PCIe interrupts in the device tree Johns Daniel @ 2009-03-24 20:54 ` Kumar Gala 2009-03-24 21:13 ` Johns Daniel 0 siblings, 1 reply; 5+ messages in thread From: Kumar Gala @ 2009-03-24 20:54 UTC (permalink / raw) To: Johns Daniel; +Cc: linuxppc-dev On Mar 24, 2009, at 3:24 PM, Johns Daniel wrote: > Could somebody please explain the declaration of the PCIe interrupts > in the device tree? > > I was under the impression that PCIe interrupts in the PowerPC Linux > kernel default to using INTx signaling (vs. external IRQ pin assertion > and MSI signaling). Am I right? > > If so, then do the interrupt-map lines in the DTS refer to the > internal IRQ used by Freescale processors to implement INTx virtual > wire interrupts? > > For example, in the mpc8536ds.dts file, under "pci1: pcie@ffe09000" > we have: > interrupt-map = < > /* IDSEL 0x0 */ > 0000 0 0 1 &mpic 4 1 > 0000 0 0 2 &mpic 5 1 > 0000 0 0 3 &mpic 6 1 > 0000 0 0 4 &mpic 7 1 > >; > Are the 4, 5, 6, and 7 internal or external IRQs? The .dts and linux make no distinction between internal & external IRQs. This is a silly artifact of Freescale UMs. IRQ 0 starts at offset 0x50000 and each 0x20 offset is another IRQ. So typically External 0 == IRQ0, Internal 0 == IRQ16. So this says that Ext 4, 5, 6, 7 and wired to INTA, INTB, INTC, INTD for this particular PCIe controller. > And the "msi@41600" section in the same mpc8536ds.dts file does NOT > affect PCIe interrupts unless a driver calls pci_enable_msi()? correct. - k ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: PCIe interrupts in the device tree 2009-03-24 20:54 ` Kumar Gala @ 2009-03-24 21:13 ` Johns Daniel 2009-03-25 1:12 ` Kumar Gala 0 siblings, 1 reply; 5+ messages in thread From: Johns Daniel @ 2009-03-24 21:13 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev [-- Attachment #1: Type: text/plain, Size: 1653 bytes --] On Tue, Mar 24, 2009 at 3:54 PM, Kumar Gala <galak@kernel.crashing.org>wrote: > > On Mar 24, 2009, at 3:24 PM, Johns Daniel wrote: > > Could somebody please explain the declaration of the PCIe interrupts >> in the device tree? >> >> I was under the impression that PCIe interrupts in the PowerPC Linux >> kernel default to using INTx signaling (vs. external IRQ pin assertion >> and MSI signaling). Am I right? >> >> If so, then do the interrupt-map lines in the DTS refer to the >> internal IRQ used by Freescale processors to implement INTx virtual >> wire interrupts? >> >> For example, in the mpc8536ds.dts file, under "pci1: pcie@ffe09000" we >> have: >> interrupt-map = < >> /* IDSEL 0x0 */ >> 0000 0 0 1 &mpic 4 1 >> 0000 0 0 2 &mpic 5 1 >> 0000 0 0 3 &mpic 6 1 >> 0000 0 0 4 &mpic 7 1 >> >; >> Are the 4, 5, 6, and 7 internal or external IRQs? >> > > The .dts and linux make no distinction between internal & external IRQs. > This is a silly artifact of Freescale UMs. IRQ 0 starts at offset 0x50000 > and each 0x20 offset is another IRQ. So typically External 0 == IRQ0, > Internal 0 == IRQ16. > > So this says that Ext 4, 5, 6, 7 and wired to INTA, INTB, INTC, INTD for > this particular PCIe controller. > When you say "wired", do you mean hard-wired? If so, how would you specify and use INTx message interrupts? > > > And the "msi@41600" section in the same mpc8536ds.dts file does NOT >> affect PCIe interrupts unless a driver calls pci_enable_msi()? >> > > correct. > > - k > [-- Attachment #2: Type: text/html, Size: 2603 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: PCIe interrupts in the device tree 2009-03-24 21:13 ` Johns Daniel @ 2009-03-25 1:12 ` Kumar Gala 2009-03-25 13:45 ` Johns Daniel 0 siblings, 1 reply; 5+ messages in thread From: Kumar Gala @ 2009-03-25 1:12 UTC (permalink / raw) To: Johns Daniel; +Cc: linuxppc-dev On Mar 24, 2009, at 4:13 PM, Johns Daniel wrote: > > On Tue, Mar 24, 2009 at 3:54 PM, Kumar Gala > <galak@kernel.crashing.org> wrote: > > On Mar 24, 2009, at 3:24 PM, Johns Daniel wrote: > > Could somebody please explain the declaration of the PCIe interrupts > in the device tree? > > I was under the impression that PCIe interrupts in the PowerPC Linux > kernel default to using INTx signaling (vs. external IRQ pin assertion > and MSI signaling). Am I right? > > If so, then do the interrupt-map lines in the DTS refer to the > internal IRQ used by Freescale processors to implement INTx virtual > wire interrupts? > > For example, in the mpc8536ds.dts file, under "pci1: pcie@ffe09000" > we have: > interrupt-map = < > /* IDSEL 0x0 */ > 0000 0 0 1 &mpic 4 1 > 0000 0 0 2 &mpic 5 1 > 0000 0 0 3 &mpic 6 1 > 0000 0 0 4 &mpic 7 1 > >; > Are the 4, 5, 6, and 7 internal or external IRQs? > > The .dts and linux make no distinction between internal & external > IRQs. This is a silly artifact of Freescale UMs. IRQ 0 starts at > offset 0x50000 and each 0x20 offset is another IRQ. So typically > External 0 == IRQ0, Internal 0 == IRQ16. > > So this says that Ext 4, 5, 6, 7 and wired to INTA, INTB, INTC, INTD > for this particular PCIe controller. > > When you say "wired", do you mean hard-wired? Yes. The INTx emulation interrupts are hard-wired by the SoC on top of the external IRQs. > If so, how would you specify and use INTx message interrupts? Do you mean MSI or INTx emulation? - k ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: PCIe interrupts in the device tree 2009-03-25 1:12 ` Kumar Gala @ 2009-03-25 13:45 ` Johns Daniel 0 siblings, 0 replies; 5+ messages in thread From: Johns Daniel @ 2009-03-25 13:45 UTC (permalink / raw) To: Kumar Gala; +Cc: linuxppc-dev On Tue, Mar 24, 2009 at 8:12 PM, Kumar Gala <galak@kernel.crashing.org> wro= te: > > On Mar 24, 2009, at 4:13 PM, Johns Daniel wrote: > >> >> On Tue, Mar 24, 2009 at 3:54 PM, Kumar Gala <galak@kernel.crashing.org> = wrote: >> >> On Mar 24, 2009, at 3:24 PM, Johns Daniel wrote: >> >> Could somebody please explain the declaration of the PCIe interrupts >> in the device tree? >> >> I was under the impression that PCIe interrupts in the PowerPC Linux >> kernel default to using INTx signaling (vs. external IRQ pin assertion >> and MSI signaling). Am I right? >> >> If so, then do the interrupt-map lines in the DTS refer to the >> internal IRQ used by Freescale processors to implement INTx virtual >> wire interrupts? >> >> For example, in the mpc8536ds.dts file, under "pci1: pcie@ffe09000" we h= ave: >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 interrupt-map =3D < >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* IDSEL 0x0 */ >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0000 0 0 1 &mpic 4 1 >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0000 0 0 2 &mpic 5 1 >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0000 0 0 3 &mpic 6 1 >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 0000 0 0 4 &mpic 7 1 >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 >; >> Are the 4, 5, 6, and 7 internal or external IRQs? >> >> The .dts and linux make no distinction between internal & external IRQs.= =A0This is a silly artifact of Freescale UMs. =A0IRQ 0 starts at offset 0x= 50000 and each 0x20 offset is another IRQ. =A0So typically External 0 =3D= =3D IRQ0, Internal 0 =3D=3D IRQ16. >> >> So this says that Ext 4, 5, 6, 7 and wired to INTA, INTB, INTC, INTD for= this particular PCIe controller. >> >> When you say "wired", do you mean hard-wired? > > Yes. =A0The INTx emulation interrupts are hard-wired by the SoC on top of= the external IRQs. > >> If so, how would you specify and use INTx message interrupts? > > Do you mean MSI or INTx emulation? INTx emulation. I think I finally understand! From what you are saying, IRQ pin assertion and INTx emulation are indistinct from the point of view of the processor core, Linux, and the device tree. (The PCIe controller translates the INTx message to an IRQ assertion.) We can switch to MSI by having the driver call pci_enable_msi(). Thank you very much, Kumar! ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2009-03-25 13:45 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2009-03-24 20:24 PCIe interrupts in the device tree Johns Daniel 2009-03-24 20:54 ` Kumar Gala 2009-03-24 21:13 ` Johns Daniel 2009-03-25 1:12 ` Kumar Gala 2009-03-25 13:45 ` Johns Daniel
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