* [PATCH] Extended keyboard+mouse emulation
From: Joakim Karlsson @ 2005-01-26 0:12 UTC (permalink / raw)
To: linuxppc-dev
Hi everyone!
This is my first patch ever, so I hope I'm doing this right. In short,
this patch allows standard usage of the mouse button emulation in the
mac_hid. It extends the functionality to a combination of a key and mouse
button, retaining full compatibility. Project site:
http://aio.nocrew.org/projects/pbmousehack/
I have successfully tested it on 2.6.9 and 2.6.10.
Regards, Joakim Karlsson <aio@nocrew.org>
diff -urN linux-2.6.9.old/drivers/input/mousedev.c linux-2.6.9.new/drivers/input/mousedev.c
--- linux-2.6.9.old/drivers/input/mousedev.c 2004-10-18 23:55:07.000000000 +0200
+++ linux-2.6.9.new/drivers/input/mousedev.c 2004-12-14 01:11:48.644153752 +0100
@@ -168,6 +168,11 @@
}
}
+#ifdef CONFIG_MAC_EMUMOUSEBTN
+extern int mac_hid_mouse_emulate_buttons(int, int, int);
+extern int mac_hid_get_mouse_combination(int);
+#endif /* CONFIG_MAC_EMUMOUSEBTN */
+
static void mousedev_key_event(struct mousedev *mousedev, unsigned int code, int value)
{
int index;
@@ -192,9 +197,17 @@
}
if (value) {
+#ifdef CONFIG_MAC_EMUMOUSEBTN
+ if (index == 0)
+ index += mac_hid_get_mouse_combination(1);
+#endif /* CONFIG_MAC_EMUMOUSEBTN */
set_bit(index, &mousedev->packet.buttons);
set_bit(index, &mousedev_mix.packet.buttons);
} else {
+#ifdef CONFIG_MAC_EMUMOUSEBTN
+ if (index == 0)
+ index += mac_hid_get_mouse_combination(0);
+#endif /* CONFIG_MAC_EMUMOUSEBTN */
clear_bit(index, &mousedev->packet.buttons);
clear_bit(index, &mousedev_mix.packet.buttons);
}
diff -urN linux-2.6.9.old/drivers/macintosh/mac_hid.c linux-2.6.9.new/drivers/macintosh/mac_hid.c
--- linux-2.6.9.old/drivers/macintosh/mac_hid.c 2004-10-18 23:54:55.000000000 +0200
+++ linux-2.6.9.new/drivers/macintosh/mac_hid.c 2004-12-14 01:12:11.998603336 +0100
@@ -15,10 +15,10 @@
#include <linux/input.h>
#include <linux/module.h>
-
static struct input_dev emumousebtn;
static void emumousebtn_input_register(void);
static int mouse_emulate_buttons = 0;
+static int mouse_combine_buttons = 0;
static int mouse_button2_keycode = KEY_RIGHTCTRL; /* right control key */
static int mouse_button3_keycode = KEY_RIGHTALT; /* right option key */
static int mouse_last_keycode = 0;
@@ -35,6 +35,14 @@
.proc_handler = &proc_dointvec,
},
{
+ .ctl_name = DEV_MAC_HID_MOUSE_BUTTON_COMBINATION,
+ .procname = "mouse_combine_emulation",
+ .data = &mouse_combine_buttons,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec,
+ },
+ {
.ctl_name = DEV_MAC_HID_MOUSE_BUTTON2_KEYCODE,
.procname = "mouse_button2_keycode",
.data = &mouse_button2_keycode,
@@ -81,12 +89,37 @@
#endif /* endif CONFIG_SYSCTL */
+int mac_hid_get_mouse_combination(int set)
+{
+ static int button = 0;
+ int retval = 0;
+
+ if (set == 1) {
+ button = mouse_last_keycode;
+ if (button == mouse_button2_keycode)
+ retval = 1;
+ else if (button == mouse_button3_keycode)
+ retval = 2;
+ else
+ retval = 0;
+ } else {
+ if (button == mouse_button2_keycode)
+ retval = 1;
+ else if (button == mouse_button3_keycode)
+ retval = 2;
+ else
+ retval = 0;
+ button = 0;
+ }
+ return retval;
+}
+
int mac_hid_mouse_emulate_buttons(int caller, unsigned int keycode, int down)
{
switch (caller) {
case 1:
/* Called from keyboard.c */
- if (mouse_emulate_buttons
+ if (mouse_emulate_buttons && !mouse_combine_buttons
&& (keycode == mouse_button2_keycode
|| keycode == mouse_button3_keycode)) {
if (mouse_emulate_buttons == 1) {
@@ -98,6 +131,12 @@
}
mouse_last_keycode = down ? keycode : 0;
}
+ if (mouse_combine_buttons
+ && (keycode == mouse_button2_keycode
+ || keycode == mouse_button3_keycode)) {
+ mouse_last_keycode = down ? keycode : 0;
+ return 0;
+ }
break;
}
return 0;
diff -urN linux-2.6.9.old/include/linux/sysctl.h linux-2.6.9.new/include/linux/sysctl.h
--- linux-2.6.9.old/include/linux/sysctl.h 2004-10-18 23:54:31.000000000 +0200
+++ linux-2.6.9.new/include/linux/sysctl.h 2004-12-14 01:13:44.179589696 +0100
@@ -747,7 +747,8 @@
DEV_MAC_HID_MOUSE_BUTTON_EMULATION=3,
DEV_MAC_HID_MOUSE_BUTTON2_KEYCODE=4,
DEV_MAC_HID_MOUSE_BUTTON3_KEYCODE=5,
- DEV_MAC_HID_ADB_MOUSE_SENDS_KEYCODES=6
+ DEV_MAC_HID_ADB_MOUSE_SENDS_KEYCODES=6,
+ DEV_MAC_HID_MOUSE_BUTTON_COMBINATION=8
};
/* /proc/sys/dev/scsi */
^ permalink raw reply
* [PATCH] netdrv gianfar: Fix usage of gfar_read in debug code
From: Kumar Gala @ 2005-01-26 0:17 UTC (permalink / raw)
To: akpm; +Cc: linux-kernel, linuxppc-embedded
Fixes instances where gfar_read() was invoked in debug codewith a value,
rather than a pointer.
Signed-of-by: Andy Fleming <afleming@freescale.com>
Signed-of-by: Kumar Gala <afleming@freescale.com>
---
diff -Nru a/drivers/net/gianfar.c b/drivers/net/gianfar.c
--- a/drivers/net/gianfar.c 2005-01-25 18:14:13 -06:00
+++ b/drivers/net/gianfar.c 2005-01-25 18:14:13 -06:00
@@ -1190,8 +1190,8 @@
} else {
#ifdef VERBOSE_GFAR_ERRORS
printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
- dev->name, gfar_read(priv->regs->ievent),
- gfar_read(priv->regs->imask));
+ dev->name, gfar_read(&priv->regs->ievent),
+ gfar_read(&priv->regs->imask));
#endif
}
#else
@@ -1415,7 +1415,7 @@
#ifdef VERBOSE_GFAR_ERRORS
printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n", dev->name,
- gfar_read(priv->regs->rstat));
+ gfar_read(&priv->regs->rstat));
#endif
}
if (events & IEVENT_BABR) {
@@ -1793,7 +1793,7 @@
#ifdef VERBOSE_GFAR_ERRORS
printk(KERN_DEBUG "%s: busy error (rhalt: %x)\n", dev->name,
- gfar_read(priv->regs->rstat));
+ gfar_read(&priv->regs->rstat));
#endif
}
if (events & IEVENT_BABR) {
^ permalink raw reply
* [PATCH][PPC32] mv64x60 updates
From: Mark A. Greer @ 2005-01-26 0:14 UTC (permalink / raw)
To: akpm; +Cc: Embedded PPC Linux list
[-- Attachment #1: Type: text/plain, Size: 325 bytes --]
Hi Andrew.
This patch briges the mv64x60 related code up to the latest that I have.
It:
- adds MPSC support to some ppc bootwrapper files
- adds an erratum workaround for the mv64460
- changes some platform_data related structure names
- cleans up a bunch of whitespace
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
--
[-- Attachment #2: mv64x60.patch --]
[-- Type: text/plain, Size: 21427 bytes --]
diff -Nru a/arch/ppc/boot/common/misc-common.c b/arch/ppc/boot/common/misc-common.c
--- a/arch/ppc/boot/common/misc-common.c 2005-01-25 17:05:15 -07:00
+++ b/arch/ppc/boot/common/misc-common.c 2005-01-25 17:05:15 -07:00
@@ -60,7 +60,8 @@
unsigned char *ISA_io = NULL;
#if defined(CONFIG_SERIAL_CPM_CONSOLE) || defined(CONFIG_SERIAL_8250_CONSOLE) \
- || defined(CONFIG_SERIAL_MPC52xx_CONSOLE)
+ || defined(CONFIG_SERIAL_MPC52xx_CONSOLE) \
+ || defined(CONFIG_SERIAL_MPSC_CONSOLE)
extern unsigned long com_port;
extern int serial_tstc(unsigned long com_port);
@@ -82,7 +83,8 @@
int tstc(void)
{
#if defined(CONFIG_SERIAL_CPM_CONSOLE) || defined(CONFIG_SERIAL_8250_CONSOLE) \
- || defined(CONFIG_SERIAL_MPC52xx_CONSOLE)
+ || defined(CONFIG_SERIAL_MPC52xx_CONSOLE) \
+ || defined(CONFIG_SERIAL_MPSC_CONSOLE)
if(keyb_present)
return (CRT_tstc() || serial_tstc(com_port));
else
@@ -96,7 +98,8 @@
{
while (1) {
#if defined(CONFIG_SERIAL_CPM_CONSOLE) || defined(CONFIG_SERIAL_8250_CONSOLE) \
- || defined(CONFIG_SERIAL_MPC52xx_CONSOLE)
+ || defined(CONFIG_SERIAL_MPC52xx_CONSOLE) \
+ || defined(CONFIG_SERIAL_MPSC_CONSOLE)
if (serial_tstc(com_port))
return (serial_getc(com_port));
#endif /* serial console */
@@ -112,7 +115,8 @@
int x,y;
#if defined(CONFIG_SERIAL_CPM_CONSOLE) || defined(CONFIG_SERIAL_8250_CONSOLE) \
- || defined(CONFIG_SERIAL_MPC52xx_CONSOLE)
+ || defined(CONFIG_SERIAL_MPC52xx_CONSOLE) \
+ || defined(CONFIG_SERIAL_MPSC_CONSOLE)
serial_putc(com_port, c);
if ( c == '\n' )
serial_putc(com_port, '\r');
@@ -160,7 +164,8 @@
while ( ( c = *s++ ) != '\0' ) {
#if defined(CONFIG_SERIAL_CPM_CONSOLE) || defined(CONFIG_SERIAL_8250_CONSOLE) \
- || defined(CONFIG_SERIAL_MPC52xx_CONSOLE)
+ || defined(CONFIG_SERIAL_MPC52xx_CONSOLE) \
+ || defined(CONFIG_SERIAL_MPSC_CONSOLE)
serial_putc(com_port, c);
if ( c == '\n' ) serial_putc(com_port, '\r');
#endif /* serial console */
diff -Nru a/arch/ppc/boot/simple/misc.c b/arch/ppc/boot/simple/misc.c
--- a/arch/ppc/boot/simple/misc.c 2005-01-25 17:05:15 -07:00
+++ b/arch/ppc/boot/simple/misc.c 2005-01-25 17:05:15 -07:00
@@ -50,7 +50,8 @@
*/
#if (defined(CONFIG_SERIAL_8250_CONSOLE) \
|| defined(CONFIG_VGA_CONSOLE) \
- || defined(CONFIG_SERIAL_MPC52xx_CONSOLE)) \
+ || defined(CONFIG_SERIAL_MPC52xx_CONSOLE) \
+ || defined(CONFIG_SERIAL_MPSC_CONSOLE)) \
&& !defined(CONFIG_GEMINI)
#define INTERACTIVE_CONSOLE 1
#endif
@@ -98,7 +99,7 @@
struct bi_record *rec;
unsigned long initrd_loc = 0, TotalMemory = 0;
-#ifdef CONFIG_SERIAL_8250_CONSOLE
+#if defined(CONFIG_SERIAL_8250_CONSOLE) || defined(CONFIG_SERIAL_MPSC_CONSOLE)
com_port = serial_init(0, NULL);
#endif
diff -Nru a/arch/ppc/boot/simple/mv64x60_tty.c b/arch/ppc/boot/simple/mv64x60_tty.c
--- a/arch/ppc/boot/simple/mv64x60_tty.c 2005-01-25 17:05:15 -07:00
+++ b/arch/ppc/boot/simple/mv64x60_tty.c 2005-01-25 17:05:15 -07:00
@@ -6,12 +6,10 @@
*
* Author: Mark A. Greer <mgreer@mvista.com>
*
- * Copyright 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
+ * 2001 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
*/
/* This code assumes that the data cache has been disabled (L1, L2, L3). */
diff -Nru a/arch/ppc/syslib/mv64360_pic.c b/arch/ppc/syslib/mv64360_pic.c
--- a/arch/ppc/syslib/mv64360_pic.c 2005-01-25 17:05:15 -07:00
+++ b/arch/ppc/syslib/mv64360_pic.c 2005-01-25 17:05:15 -07:00
@@ -369,7 +369,8 @@
u32 mask;
int rc;
- /* Register CPU interface error interrupt handler */
+ /* Clear old errors and register CPU interface error intr handler */
+ mv64x60_write(&bh, MV64x60_CPU_ERR_CAUSE, 0);
if ((rc = request_irq(MV64x60_IRQ_CPU_ERR,
mv64360_cpu_error_int_handler, SA_INTERRUPT, CPU_INTR_STR, 0)))
printk(KERN_WARNING "Can't register cpu error handler: %d", rc);
@@ -377,7 +378,8 @@
mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0);
mv64x60_write(&bh, MV64x60_CPU_ERR_MASK, 0x000000ff);
- /* Register internal SRAM error interrupt handler */
+ /* Clear old errors and register internal SRAM error intr handler */
+ mv64x60_write(&bh, MV64360_SRAM_ERR_CAUSE, 0);
if ((rc = request_irq(MV64360_IRQ_SRAM_PAR_ERR,
mv64360_sram_error_int_handler,SA_INTERRUPT,SRAM_INTR_STR, 0)))
printk(KERN_WARNING "Can't register SRAM error handler: %d",rc);
@@ -393,18 +395,20 @@
(mv64x60_get_bridge_rev() > 1))
mask |= 0x1; /* enable DPErr on 64460 */
- /* Register PCI 0 error interrupt handler */
+ /* Clear old errors and register PCI 0 error intr handler */
+ mv64x60_write(&bh, MV64x60_PCI0_ERR_CAUSE, 0);
if ((rc = request_irq(MV64360_IRQ_PCI0, mv64360_pci_error_int_handler,
- SA_INTERRUPT, PCI0_INTR_STR, (void *)0)))
+ SA_INTERRUPT, PCI0_INTR_STR, (void *)0)))
printk(KERN_WARNING "Can't register pci 0 error handler: %d",
rc);
mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, 0);
mv64x60_write(&bh, MV64x60_PCI0_ERR_MASK, mask);
- /* Register PCI 1 error interrupt handler */
+ /* Clear old errors and register PCI 1 error intr handler */
+ mv64x60_write(&bh, MV64x60_PCI1_ERR_CAUSE, 0);
if ((rc = request_irq(MV64360_IRQ_PCI1, mv64360_pci_error_int_handler,
- SA_INTERRUPT, PCI1_INTR_STR, (void *)1)))
+ SA_INTERRUPT, PCI1_INTR_STR, (void *)1)))
printk(KERN_WARNING "Can't register pci 1 error handler: %d",
rc);
diff -Nru a/arch/ppc/syslib/mv64x60.c b/arch/ppc/syslib/mv64x60.c
--- a/arch/ppc/syslib/mv64x60.c 2005-01-25 17:05:15 -07:00
+++ b/arch/ppc/syslib/mv64x60.c 2005-01-25 17:05:15 -07:00
@@ -34,10 +34,10 @@
u8 mv64x60_pci_exclude_bridge = 1;
spinlock_t mv64x60_lock; /* Only really used by PIC code once init done */
-static u32 mv64x60_bridge_pbase = 0;
-static u32 mv64x60_bridge_vbase = 0;
-static u32 mv64x60_bridge_type = MV64x60_TYPE_INVALID;
-static u32 mv64x60_bridge_rev = 0;
+static phys_addr_t mv64x60_bridge_pbase = 0;
+static void *mv64x60_bridge_vbase = 0;
+static u32 mv64x60_bridge_type = MV64x60_TYPE_INVALID;
+static u32 mv64x60_bridge_rev = 0;
static u32 gt64260_translate_size(u32 base, u32 size, u32 num_bits);
static u32 gt64260_untranslate_size(u32 base, u32 size, u32 num_bits);
@@ -88,7 +88,7 @@
.translate_size = gt64260_translate_size,
.untranslate_size = gt64260_untranslate_size,
.set_pci2mem_window = gt64260_set_pci2mem_window,
- .set_pci2regs_window = gt64260_set_pci2regs_window,
+ .set_pci2regs_window = gt64260_set_pci2regs_window,
.is_enabled_32bit = gt64260_is_enabled_32bit,
.enable_window_32bit = gt64260_enable_window_32bit,
.disable_window_32bit = gt64260_disable_window_32bit,
@@ -104,7 +104,7 @@
.translate_size = gt64260_translate_size,
.untranslate_size = gt64260_untranslate_size,
.set_pci2mem_window = gt64260_set_pci2mem_window,
- .set_pci2regs_window = gt64260_set_pci2regs_window,
+ .set_pci2regs_window = gt64260_set_pci2regs_window,
.is_enabled_32bit = gt64260_is_enabled_32bit,
.enable_window_32bit = gt64260_enable_window_32bit,
.disable_window_32bit = gt64260_disable_window_32bit,
@@ -120,7 +120,7 @@
.translate_size = mv64360_translate_size,
.untranslate_size = mv64360_untranslate_size,
.set_pci2mem_window = mv64360_set_pci2mem_window,
- .set_pci2regs_window = mv64360_set_pci2regs_window,
+ .set_pci2regs_window = mv64360_set_pci2regs_window,
.is_enabled_32bit = mv64360_is_enabled_32bit,
.enable_window_32bit = mv64360_enable_window_32bit,
.disable_window_32bit = mv64360_disable_window_32bit,
@@ -138,7 +138,7 @@
.translate_size = mv64360_translate_size,
.untranslate_size = mv64360_untranslate_size,
.set_pci2mem_window = mv64360_set_pci2mem_window,
- .set_pci2regs_window = mv64360_set_pci2regs_window,
+ .set_pci2regs_window = mv64360_set_pci2regs_window,
.is_enabled_32bit = mv64360_is_enabled_32bit,
.enable_window_32bit = mv64360_enable_window_32bit,
.disable_window_32bit = mv64360_disable_window_32bit,
@@ -160,7 +160,7 @@
*****************************************************************************
*/
#ifdef CONFIG_SERIAL_MPSC
-static struct mpsc_shared_pd_dd mv64x60_mpsc_shared_pd_dd = {
+static struct mpsc_shared_pdata mv64x60_mpsc_shared_pdata = {
.mrr_val = 0x3ffffe38,
.rcrr_val = 0,
.tcrr_val = 0,
@@ -192,11 +192,11 @@
.num_resources = ARRAY_SIZE(mv64x60_mpsc_shared_resources),
.resource = mv64x60_mpsc_shared_resources,
.dev = {
- .driver_data = &mv64x60_mpsc_shared_pd_dd,
+ .platform_data = &mv64x60_mpsc_shared_pdata,
},
};
-static struct mpsc_pd_dd mv64x60_mpsc0_pd_dd = {
+static struct mpsc_pdata mv64x60_mpsc0_pdata = {
.mirror_regs = 0,
.cache_mgmt = 0,
.max_idle = 0,
@@ -248,11 +248,11 @@
.num_resources = ARRAY_SIZE(mv64x60_mpsc0_resources),
.resource = mv64x60_mpsc0_resources,
.dev = {
- .driver_data = &mv64x60_mpsc0_pd_dd,
+ .platform_data = &mv64x60_mpsc0_pdata,
},
};
-static struct mpsc_pd_dd mv64x60_mpsc1_pd_dd = {
+static struct mpsc_pdata mv64x60_mpsc1_pdata = {
.mirror_regs = 0,
.cache_mgmt = 0,
.max_idle = 0,
@@ -305,7 +305,130 @@
.num_resources = ARRAY_SIZE(mv64x60_mpsc1_resources),
.resource = mv64x60_mpsc1_resources,
.dev = {
- .driver_data = &mv64x60_mpsc1_pd_dd,
+ .platform_data = &mv64x60_mpsc1_pdata,
+ },
+};
+#endif
+
+#ifdef CONFIG_MV643XX_ETH
+static struct resource mv64x60_eth_shared_resources[] = {
+ [0] = {
+ .name = "ethernet shared base",
+ .start = MV64340_ETH_SHARED_REGS,
+ .end = MV64340_ETH_SHARED_REGS +
+ MV64340_ETH_SHARED_REGS_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device mv64x60_eth_shared_device = {
+ .name = MV64XXX_ETH_SHARED_NAME,
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mv64x60_eth_shared_resources),
+ .resource = mv64x60_eth_shared_resources,
+};
+
+#ifdef CONFIG_MV643XX_ETH_0
+static struct resource mv64x60_eth0_resources[] = {
+ [0] = {
+ .name = "eth0 irq",
+ .start = MV64x60_IRQ_ETH_0,
+ .end = MV64x60_IRQ_ETH_0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mv64xxx_eth_platform_data eth0_pd;
+
+static struct platform_device eth0_device = {
+ .name = MV64XXX_ETH_NAME,
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
+ .resource = mv64x60_eth0_resources,
+ .dev = {
+ .platform_data = ð0_pd,
+ },
+};
+#endif
+
+#ifdef CONFIG_MV643XX_ETH_1
+static struct resource mv64x60_eth1_resources[] = {
+ [0] = {
+ .name = "eth1 irq",
+ .start = MV64x60_IRQ_ETH_1,
+ .end = MV64x60_IRQ_ETH_1,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mv64xxx_eth_platform_data eth1_pd;
+
+static struct platform_device eth1_device = {
+ .name = MV64XXX_ETH_NAME,
+ .id = 1,
+ .num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
+ .resource = mv64x60_eth1_resources,
+ .dev = {
+ .platform_data = ð1_pd,
+ },
+};
+#endif
+
+#ifdef CONFIG_MV643XX_ETH_2
+static struct resource mv64x60_eth2_resources[] = {
+ [0] = {
+ .name = "eth2 irq",
+ .start = MV64x60_IRQ_ETH_2,
+ .end = MV64x60_IRQ_ETH_2,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mv64xxx_eth_platform_data eth2_pd;
+
+static struct platform_device eth2_device = {
+ .name = MV64XXX_ETH_NAME,
+ .id = 2,
+ .num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
+ .resource = mv64x60_eth2_resources,
+ .dev = {
+ .platform_data = ð2_pd,
+ },
+};
+#endif
+#endif
+
+#ifdef CONFIG_I2C_MV64XXX
+static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata = {
+ .freq_m = 8,
+ .freq_n = 3,
+ .timeout = 1000, /* Default timeout of 1 second */
+ .retries = 1,
+};
+
+static struct resource mv64xxx_i2c_resources[] = {
+ /* Do not change the order of the IORESOURCE_MEM resources */
+ [0] = {
+ .name = "mv64xxx i2c base",
+ .start = MV64XXX_I2C_OFFSET,
+ .end = MV64XXX_I2C_OFFSET + MV64XXX_I2C_REG_BLOCK_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .name = "mv64xxx i2c irq",
+ .start = MV64x60_IRQ_I2C,
+ .end = MV64x60_IRQ_I2C,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device i2c_device = {
+ .name = MV64XXX_I2C_CTLR_NAME,
+ .id = 0,
+ .num_resources = ARRAY_SIZE(mv64xxx_i2c_resources),
+ .resource = mv64xxx_i2c_resources,
+ .dev = {
+ .platform_data = &mv64xxx_i2c_pdata,
},
};
#endif
@@ -316,6 +439,21 @@
&mpsc0_device,
&mpsc1_device,
#endif
+#ifdef CONFIG_MV643XX_ETH
+ &mv64x60_eth_shared_device,
+#endif
+#ifdef CONFIG_MV643XX_ETH_0
+ ð0_device,
+#endif
+#ifdef CONFIG_MV643XX_ETH_1
+ ð1_device,
+#endif
+#ifdef CONFIG_MV643XX_ETH_2
+ ð2_device,
+#endif
+#ifdef CONFIG_I2C_MV64XXX
+ &i2c_device,
+#endif
};
/*
@@ -344,7 +482,7 @@
mv64x60_early_init(bh, si);
if (mv64x60_get_type(bh) || mv64x60_setup_for_chip(bh)) {
- iounmap((void *)bh->v_base);
+ iounmap(bh->v_base);
bh->v_base = 0;
if (ppc_md.progress)
ppc_md.progress("mv64x60_init: Can't determine chip",0);
@@ -416,7 +554,7 @@
memset(bh, 0, sizeof(*bh));
bh->p_base = si->phys_reg_base;
- bh->v_base = (u32)ioremap(bh->p_base, MV64x60_INTERNAL_SPACE_SIZE);
+ bh->v_base = ioremap(bh->p_base, MV64x60_INTERNAL_SPACE_SIZE);
mv64x60_bridge_pbase = bh->p_base;
mv64x60_bridge_vbase = bh->v_base;
@@ -598,7 +736,7 @@
*/
void __init
mv64x60_set_64bit_window(struct mv64x60_handle *bh, u32 window,
- u32 base_hi, u32 base_lo, u32 size, u32 other_bits)
+ u32 base_hi, u32 base_lo, u32 size, u32 other_bits)
{
u32 val, base_lo_reg, size_reg, base_lo_bits, size_bits;
u32 (*map_to_field)(u32 val, u32 num_bits);
@@ -645,7 +783,7 @@
}
/*
- * mv64x60_mask_shift_left()
+ * mv64x60_shift_left()
*
* Take the low-order 'num_bits' of 'val', shift left to align at bit 31 (MSB).
*/
@@ -702,7 +840,7 @@
/* Get the revision of the chip */
early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_CLASS_REVISION,
&val);
- bh->rev = (u32) (val & 0xff);
+ bh->rev = (u32)(val & 0xff);
/* Figure out the type of Marvell bridge it is */
early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &val);
@@ -790,7 +928,7 @@
*
* Return the virtual address of the bridge's registers.
*/
-u32
+void *
mv64x60_get_bridge_vbase(void)
{
return mv64x60_bridge_vbase;
@@ -836,13 +974,13 @@
mv64x60_get_mem_size(u32 bridge_base, u32 chip_type)
{
struct mv64x60_handle bh;
- u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
- u32 rc = 0;
+ u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2];
+ u32 rc = 0;
memset(&bh, 0, sizeof(bh));
bh.type = chip_type;
- bh.v_base = bridge_base;
+ bh.v_base = (void *)bridge_base;
if (!mv64x60_setup_for_chip(&bh)) {
mv64x60_get_mem_windows(&bh, mem_windows);
@@ -1117,7 +1255,7 @@
IORESOURCE_IO, s[hose->index][0]);
hose->io_space.start = pi->pci_io.pci_base_lo;
hose->io_space.end = pi->pci_io.pci_base_lo + pi->pci_io.size-1;
- hose->io_base_phys = (ulong)pi->pci_io.cpu_base;
+ hose->io_base_phys = pi->pci_io.cpu_base;
hose->io_base_virt = (void *)isa_io_base;
}
@@ -1592,8 +1730,8 @@
struct resource *r;
#endif
#if !defined(CONFIG_NOT_COHERENT_CACHE)
- u32 val;
- u8 save_exclude;
+ u32 val;
+ u8 save_exclude;
#endif
if (si->pci_0.enable_bus)
@@ -1638,10 +1776,10 @@
mv64x60_clr_bits(bh, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
#ifdef CONFIG_SERIAL_MPSC
- mv64x60_mpsc0_pd_dd.mirror_regs = 1;
- mv64x60_mpsc0_pd_dd.cache_mgmt = 1;
- mv64x60_mpsc1_pd_dd.mirror_regs = 1;
- mv64x60_mpsc1_pd_dd.cache_mgmt = 1;
+ mv64x60_mpsc0_pdata.mirror_regs = 1;
+ mv64x60_mpsc0_pdata.cache_mgmt = 1;
+ mv64x60_mpsc1_pdata.mirror_regs = 1;
+ mv64x60_mpsc1_pdata.cache_mgmt = 1;
if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
!= NULL) {
@@ -1667,8 +1805,8 @@
struct resource *r;
#endif
#if !defined(CONFIG_NOT_COHERENT_CACHE)
- u32 val;
- u8 save_exclude;
+ u32 val;
+ u8 save_exclude;
#endif
if (si->pci_0.enable_bus)
@@ -1720,8 +1858,8 @@
* can't access cache coherent regions. However, testing has shown
* that the MPSC, at least, still has this bug.
*/
- mv64x60_mpsc0_pd_dd.cache_mgmt = 1;
- mv64x60_mpsc1_pd_dd.cache_mgmt = 1;
+ mv64x60_mpsc0_pdata.cache_mgmt = 1;
+ mv64x60_mpsc1_pdata.cache_mgmt = 1;
if ((r = platform_get_resource(&mpsc1_device, IORESOURCE_IRQ, 0))
!= NULL) {
@@ -2228,10 +2366,10 @@
struct mv64x60_setup_info *si)
{
#ifdef CONFIG_SERIAL_MPSC
- mv64x60_mpsc0_pd_dd.brg_can_tune = 1;
- mv64x60_mpsc0_pd_dd.cache_mgmt = 1;
- mv64x60_mpsc1_pd_dd.brg_can_tune = 1;
- mv64x60_mpsc1_pd_dd.cache_mgmt = 1;
+ mv64x60_mpsc0_pdata.brg_can_tune = 1;
+ mv64x60_mpsc0_pdata.cache_mgmt = 1;
+ mv64x60_mpsc1_pdata.brg_can_tune = 1;
+ mv64x60_mpsc1_pdata.cache_mgmt = 1;
#endif
return;
@@ -2247,8 +2385,8 @@
struct mv64x60_setup_info *si)
{
#ifdef CONFIG_SERIAL_MPSC
- mv64x60_mpsc0_pd_dd.brg_can_tune = 1;
- mv64x60_mpsc1_pd_dd.brg_can_tune = 1;
+ mv64x60_mpsc0_pdata.brg_can_tune = 1;
+ mv64x60_mpsc1_pdata.brg_can_tune = 1;
#endif
return;
}
diff -Nru a/include/asm-ppc/mv64x60.h b/include/asm-ppc/mv64x60.h
--- a/include/asm-ppc/mv64x60.h 2005-01-25 17:05:15 -07:00
+++ b/include/asm-ppc/mv64x60.h 2005-01-25 17:05:15 -07:00
@@ -27,7 +27,7 @@
#include <asm/pci-bridge.h>
#include <asm/mv64x60_defs.h>
-extern u8 mv64x60_pci_exclude_bridge;
+extern u8 mv64x60_pci_exclude_bridge;
extern spinlock_t mv64x60_lock;
@@ -210,7 +210,7 @@
void (*enable_window_64bit)(mv64x60_handle_t *bh, u32 window);
void (*disable_window_64bit)(mv64x60_handle_t *bh, u32 window);
void (*disable_all_windows)(mv64x60_handle_t *bh,
- struct mv64x60_setup_info *si);
+ struct mv64x60_setup_info *si);
void (*config_io2mem_windows)(mv64x60_handle_t *bh,
struct mv64x60_setup_info *si,
u32 mem_windows[MV64x60_CPU2MEM_WINDOWS][2]);
@@ -223,16 +223,16 @@
};
struct mv64x60_handle {
- u32 type; /* type of bridge */
- u32 rev; /* revision of bridge */
- u32 v_base; /* virtual base addr of bridge regs */
- u32 p_base; /* physical base addr of bridge regs */
+ u32 type; /* type of bridge */
+ u32 rev; /* revision of bridge */
+ void *v_base; /* virtual base addr of bridge regs */
+ phys_addr_t p_base; /* physical base addr of bridge regs */
- u32 pci_mode_a; /* pci bus 0 mode: conventional pci, pci-x */
- u32 pci_mode_b; /* pci bus 1 mode: conventional pci, pci-x */
+ u32 pci_mode_a; /* pci 0 mode: conventional pci, pci-x*/
+ u32 pci_mode_b; /* pci 1 mode: conventional pci, pci-x*/
- u32 io_base_a; /* vaddr of pci 0's I/O space */
- u32 io_base_b; /* vaddr of pci 1's I/O space */
+ u32 io_base_a; /* vaddr of pci 0's I/O space */
+ u32 io_base_b; /* vaddr of pci 1's I/O space */
struct pci_controller *hose_a;
struct pci_controller *hose_b;
@@ -247,7 +247,7 @@
ulong flags;
spin_lock_irqsave(&mv64x60_lock, flags);
- out_le32((volatile u32 *)(bh->v_base + offset), val);
+ out_le32(bh->v_base + offset, val);
spin_unlock_irqrestore(&mv64x60_lock, flags);
}
@@ -256,7 +256,7 @@
ulong flags;
spin_lock_irqsave(&mv64x60_lock, flags);
- return in_le32((volatile u32 *)(bh->v_base + offset));
+ return in_le32(bh->v_base + offset);
spin_unlock_irqrestore(&mv64x60_lock, flags);
}
@@ -282,11 +282,11 @@
u32 mv64x60_get_mem_size(u32 bridge_base, u32 chip_type);
void mv64x60_early_init(struct mv64x60_handle *bh,
struct mv64x60_setup_info *si);
-void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr, u32 cfg_data,
- struct pci_controller **hose);
+void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr,
+ u32 cfg_data, struct pci_controller **hose);
int mv64x60_get_type(struct mv64x60_handle *bh);
int mv64x60_setup_for_chip(struct mv64x60_handle *bh);
-u32 mv64x60_get_bridge_vbase(void);
+void *mv64x60_get_bridge_vbase(void);
u32 mv64x60_get_bridge_type(void);
u32 mv64x60_get_bridge_rev(void);
void mv64x60_get_mem_windows(struct mv64x60_handle *bh,
diff -Nru a/include/asm-ppc/mv64x60_defs.h b/include/asm-ppc/mv64x60_defs.h
--- a/include/asm-ppc/mv64x60_defs.h 2005-01-25 17:05:15 -07:00
+++ b/include/asm-ppc/mv64x60_defs.h 2005-01-25 17:05:15 -07:00
@@ -216,9 +216,9 @@
#define MV64360_CPU1_SYNC_BARRIER_VIRT 0x00d8
/* CPU Deadlock and Ordering registers (Rev B part only) */
-#define GT64260_CPU_DEADLOCK_ORDERING 0x02d0
-#define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH 0x02d8
-#define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE 0x02e0
+#define GT64260_CPU_DEADLOCK_ORDERING 0x02d0
+#define GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH 0x02d8
+#define GT64260_CPU_COUNTERS_SYNC_BARRIER_ATTRIBUTE 0x02e0
/* CPU Access Protection Registers (gt64260 realy has 8 but don't need) */
#define MV64x260_CPU_PROT_WINDOWS 4
diff -Nru a/include/linux/mv643xx.h b/include/linux/mv643xx.h
--- a/include/linux/mv643xx.h 2005-01-25 17:05:15 -07:00
+++ b/include/linux/mv643xx.h 2005-01-25 17:05:15 -07:00
@@ -1048,7 +1048,7 @@
#define MPSC_ROUTING_REG_BLOCK_SIZE 0x000c
#define MPSC_SDMA_INTR_REG_BLOCK_SIZE 0x0084
-struct mpsc_shared_pd_dd {
+struct mpsc_shared_pdata {
u32 mrr_val;
u32 rcrr_val;
u32 tcrr_val;
@@ -1067,7 +1067,7 @@
#define MPSC_SDMA_REG_BLOCK_SIZE 0x0c18
#define MPSC_BRG_REG_BLOCK_SIZE 0x0008
-struct mpsc_pd_dd {
+struct mpsc_pdata {
u8 mirror_regs;
u8 cache_mgmt;
u8 max_idle;
^ permalink raw reply
* Re: BUG: 2.6.11-rc2 and -rc1 hang during boot on PowerMacs
From: Benjamin Herrenschmidt @ 2005-01-25 23:47 UTC (permalink / raw)
To: Mikael Pettersson; +Cc: linuxppc-dev list, Paul Mackerras, Linux Kernel list
In-Reply-To: <16886.2489.823835.17801@alkaid.it.uu.se>
On Tue, 2005-01-25 at 09:56 +0100, Mikael Pettersson wrote:
> On the eMac:
> /proc/sys/kernel/powersave-nap exists and contains "0".
> /proc/device-tree/cpus/PowerPC,G4/flush-on-lock exists as an empty file.
Ok, that is weird... so for some reason, Apple decided not to allow the
eMac to do NAP mode, and thus to power manage the CPU when idle...
Ben.
^ permalink raw reply
* [PATCH] ppc32: (Updated) Pegasos support
From: Benjamin Herrenschmidt @ 2005-01-25 23:43 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-dev list, Sven Luther
Hi Andrew !
Here's an updated version of the pegasos support patch for ppc32, fixing
a typo in the previous one. Driver patches to come soon.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Index: linux-work/arch/ppc/syslib/prom_init.c
===================================================================
--- linux-work.orig/arch/ppc/syslib/prom_init.c 2005-01-24 11:42:36.000000000 +1100
+++ linux-work/arch/ppc/syslib/prom_init.c 2005-01-24 15:45:43.000000000 +1100
@@ -810,6 +810,9 @@
char *p, *d;
unsigned long phys;
void *result[3];
+ char model[32];
+ phandle node;
+ int rc;
/* Default */
phys = (unsigned long) &_stext;
@@ -866,11 +869,20 @@
klimit = (char *) (mem - offset);
- /* If we are already running at 0xc0000000, we assume we were
- * loaded by an OF bootloader which did set a BAT for us.
- * This breaks OF translate so we force phys to be 0.
- */
- if (offset == 0) {
+ node = call_prom("finddevice", 1, 1, "/");
+ rc = call_prom("getprop", 4, 1, node, "model", model, sizeof(model));
+ if (rc > 0 && !strncmp (model, "Pegasos", 7)
+ && strncmp (model, "Pegasos2", 8)) {
+ /* Pegasos 1 has a broken translate method in the OF,
+ * and furthermore the BATs are mapped 1:1 so the phys
+ * address calculated above is correct, so let's use
+ * it directly.
+ */
+ } else if (offset == 0) {
+ /* If we are already running at 0xc0000000, we assume we were
+ * loaded by an OF bootloader which did set a BAT for us.
+ * This breaks OF translate so we force phys to be 0.
+ */
prom_print("(already at 0xc0000000) phys=0\n");
phys = 0;
} else if ((int) call_prom("getprop", 4, 1, prom_chosen, "mmu",
Index: linux-work/arch/ppc/platforms/chrp_pci.c
===================================================================
--- linux-work.orig/arch/ppc/platforms/chrp_pci.c 2005-01-24 11:42:35.000000000 +1100
+++ linux-work/arch/ppc/platforms/chrp_pci.c 2005-01-26 10:41:05.000000000 +1100
@@ -97,8 +97,10 @@
rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val)
{
+ struct pci_controller *hose = bus->sysdata;
unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
- | ((bus->number & 0xff) << 16);
+ | (((bus->number - hose->first_busno) & 0xff) << 16)
+ | (hose->index << 24);
unsigned long ret = ~0UL;
int rval;
@@ -111,8 +113,10 @@
rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 val)
{
+ struct pci_controller *hose = bus->sysdata;
unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
- | ((bus->number & 0xff) << 16);
+ | (((bus->number - hose->first_busno) & 0xff) << 16)
+ | (hose->index << 24);
int rval;
rval = call_rtas("write-pci-config", 3, 1, NULL, addr, len, val);
@@ -186,6 +190,22 @@
iounmap(reg);
}
+/* Marvell Discovery II based Pegasos 2 */
+static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
+{
+ struct device_node *root = find_path_device("/");
+ struct device_node *rtas;
+
+ rtas = of_find_node_by_name (root, "rtas");
+ if (rtas) {
+ hose->ops = &rtas_pci_ops;
+ } else {
+ printk ("RTAS supporting Pegasos OF not found, please upgrade"
+ " your firmware\n");
+ }
+ pci_assign_all_busses = 1;
+}
+
void __init
chrp_find_bridges(void)
{
@@ -195,7 +215,7 @@
struct pci_controller *hose;
unsigned int *dma;
char *model, *machine;
- int is_longtrail = 0, is_mot = 0;
+ int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
struct device_node *root = find_path_device("/");
/*
@@ -207,6 +227,10 @@
if (machine != NULL) {
is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
is_mot = strncmp(machine, "MOT", 3) == 0;
+ if (strncmp(machine, "Pegasos2", 8) == 0)
+ is_pegasos = 2;
+ else if (strncmp(machine, "Pegasos", 7) == 0)
+ is_pegasos = 1;
}
for (dev = root->child; dev != NULL; dev = dev->sibling) {
if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
@@ -257,6 +281,10 @@
hose->ops = &gg2_pci_ops;
hose->cfg_data = p;
gg2_pci_config_base = p;
+ } else if (is_pegasos == 1) {
+ setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
+ } else if (is_pegasos == 2) {
+ setup_peg2(hose, dev);
} else {
printk("No methods for %s (model %s), using RTAS\n",
dev->full_name, model);
@@ -275,5 +303,7 @@
}
}
- ppc_md.pcibios_fixup = chrp_pcibios_fixup;
+ /* Do not fixup interrupts from OF tree on pegasos */
+ if (is_pegasos == 0)
+ ppc_md.pcibios_fixup = chrp_pcibios_fixup;
}
Index: linux-work/arch/ppc/platforms/chrp_time.c
===================================================================
--- linux-work.orig/arch/ppc/platforms/chrp_time.c 2005-01-24 11:42:35.000000000 +1100
+++ linux-work/arch/ppc/platforms/chrp_time.c 2005-01-24 15:43:37.000000000 +1100
@@ -41,6 +41,8 @@
int base;
rtcs = find_compatible_devices("rtc", "pnpPNP,b00");
+ if (rtcs == NULL)
+ rtcs = find_compatible_devices("rtc", "ds1385-rtc");
if (rtcs == NULL || rtcs->addrs == NULL)
return 0;
base = rtcs->addrs[0].address;
Index: linux-work/arch/ppc/platforms/chrp_setup.c
===================================================================
--- linux-work.orig/arch/ppc/platforms/chrp_setup.c 2005-01-24 11:42:35.000000000 +1100
+++ linux-work/arch/ppc/platforms/chrp_setup.c 2005-01-24 16:01:01.000000000 +1100
@@ -37,6 +37,7 @@
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <linux/initrd.h>
+#include <linux/module.h>
#include <asm/io.h>
#include <asm/pgtable.h>
@@ -68,6 +69,9 @@
extern unsigned long pmac_find_end_of_memory(void);
extern int of_show_percpuinfo(struct seq_file *, int);
+int _chrp_type;
+EXPORT_SYMBOL(_chrp_type);
+
/*
* XXX this should be in xmon.h, but putting it there means xmon.h
* has to include <linux/interrupt.h> (to get irqreturn_t), which
@@ -214,8 +218,33 @@
}
-void __init
-chrp_setup_arch(void)
+static void __init pegasos_set_l2cr(void)
+{
+ struct device_node *np;
+
+ /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
+ if (_chrp_type != _CHRP_Pegasos)
+ return;
+
+ /* Enable L2 cache if needed */
+ np = find_type_devices("cpu");
+ if (np != NULL) {
+ unsigned int *l2cr = (unsigned int *)
+ get_property (np, "l2cr", NULL);
+ if (l2cr == NULL) {
+ printk ("Pegasos l2cr : no cpu l2cr property found\n");
+ return;
+ }
+ if (!((*l2cr) & 0x80000000)) {
+ printk ("Pegasos l2cr : L2 cache was not active, "
+ "activating\n");
+ _set_L2CR(0);
+ _set_L2CR((*l2cr) | 0x80000000);
+ }
+ }
+}
+
+void __init chrp_setup_arch(void)
{
struct device_node *device;
@@ -232,6 +261,9 @@
#endif
ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
+ /* On pegasos, enable the L2 cache if not already done by OF */
+ pegasos_set_l2cr();
+
/* Lookup PCI host bridges */
chrp_find_bridges();
@@ -402,15 +434,17 @@
chrp_find_openpic();
- prom_get_irq_senses(init_senses, NUM_8259_INTERRUPTS, NR_IRQS);
- OpenPIC_InitSenses = init_senses;
- OpenPIC_NumInitSenses = NR_IRQS - NUM_8259_INTERRUPTS;
-
- openpic_init(NUM_8259_INTERRUPTS);
- /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
- openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
- i8259_irq);
+ if (OpenPIC_Addr) {
+ prom_get_irq_senses(init_senses, NUM_8259_INTERRUPTS, NR_IRQS);
+ OpenPIC_InitSenses = init_senses;
+ OpenPIC_NumInitSenses = NR_IRQS - NUM_8259_INTERRUPTS;
+
+ openpic_init(NUM_8259_INTERRUPTS);
+ /* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
+ openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
+ i8259_irq);
+ }
for (i = 0; i < NUM_8259_INTERRUPTS; i++)
irq_desc[i].handler = &i8259_pic;
i8259_init(chrp_int_ack);
@@ -450,6 +484,9 @@
chrp_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
+ struct device_node *root = find_path_device ("/");
+ char *machine = NULL;
+
#ifdef CONFIG_BLK_DEV_INITRD
/* take care of initrd if we have one */
if ( r6 )
@@ -464,12 +501,29 @@
DMA_MODE_WRITE = 0x48;
isa_io_base = CHRP_ISA_IO_BASE; /* default value */
+ if (root)
+ machine = get_property(root, "model", NULL);
+ if (machine && strncmp(machine, "Pegasos", 7) == 0) {
+ _chrp_type = _CHRP_Pegasos;
+ } else if (machine && strncmp(machine, "IBM", 3) == 0) {
+ _chrp_type = _CHRP_IBM;
+ } else if (machine && strncmp(machine, "MOT", 3) == 0) {
+ _chrp_type = _CHRP_Motorola;
+ } else {
+ /* Let's assume it is an IBM chrp if all else fails */
+ _chrp_type = _CHRP_IBM;
+ }
+
ppc_md.setup_arch = chrp_setup_arch;
ppc_md.show_percpuinfo = of_show_percpuinfo;
ppc_md.show_cpuinfo = chrp_show_cpuinfo;
+
ppc_md.irq_canonicalize = chrp_irq_canonicalize;
ppc_md.init_IRQ = chrp_init_IRQ;
- ppc_md.get_irq = openpic_get_irq;
+ if (_chrp_type == _CHRP_Pegasos)
+ ppc_md.get_irq = i8259_irq;
+ else
+ ppc_md.get_irq = openpic_get_irq;
ppc_md.init = chrp_init2;
Index: linux-work/include/asm-ppc/processor.h
===================================================================
--- linux-work.orig/include/asm-ppc/processor.h 2005-01-24 11:43:03.000000000 +1100
+++ linux-work/include/asm-ppc/processor.h 2005-01-24 15:39:17.000000000 +1100
@@ -34,6 +34,7 @@
/* these are arbitrary */
#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
+#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
#define _GLOBAL(n)\
.stabs __stringify(n:F-1),N_FUN,0,0,n;\
@@ -54,6 +55,7 @@
/* what kind of prep workstation we are */
extern int _prep_type;
+extern int _chrp_type;
/*
* This is used to identify the board type from a given PReP board
^ permalink raw reply
* Is there a DER for the MPC82xx?
From: annamaya @ 2005-01-25 22:54 UTC (permalink / raw)
To: linuxppc-embedded
Is there something similar to a DER (debug enable
register on a MPC8xx) on the MPC82xx processor? I was
unable to find anything similar to that on this
processor. According to the MPC8280 Reference Manual,
Appendix A.3, it says something about Chapter 36 being
the "System Development and Debugging" chapter. Well,
chapter 36 happens to be FCC ethernet stuff. Can
someone point me in the right direction here?
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^ permalink raw reply
* Re: Additional data/instruction BATs not initialized for MPC8280?
From: annamaya @ 2005-01-25 19:40 UTC (permalink / raw)
To: Eugene Surovegin; +Cc: linuxppc-embedded
In-Reply-To: <20050125191047.GA3818@gate.ebshome.net>
Doh! So that's how we get away with it.
--- Eugene Surovegin <ebs@ebshome.net> wrote:
> On Tue, Jan 25, 2005 at 09:49:13AM -0800, annamaya
> wrote:
> > I have read in the specs for the MPC8280 that it
> has a
> > G2_LE core which has 4 additional data and
> instruction
> > BATs. However, I dont see these BATS being cleared
> > early in the kernel. I only see that the first 4
> pairs
> > are cleared using the mtspr instructions. But my
> > kernel comes up just fine and everything seems to
> work
> > OK. Dont we need to clear the other set of
> I/DBATS?
> > What happens when we dont do this? Thanks in
> advance.
>
> Additional BATs in G2_LE core must be explicitly
> enabled in HID2 (HBE
> bit), until then they "don't exist" :).
>
> --
> Eugene
>
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^ permalink raw reply
* Re: Additional data/instruction BATs not initialized for MPC8280?
From: Eugene Surovegin @ 2005-01-25 19:10 UTC (permalink / raw)
To: annamaya; +Cc: linuxppc-embedded
In-Reply-To: <20050125174913.42739.qmail@web53805.mail.yahoo.com>
On Tue, Jan 25, 2005 at 09:49:13AM -0800, annamaya wrote:
> I have read in the specs for the MPC8280 that it has a
> G2_LE core which has 4 additional data and instruction
> BATs. However, I dont see these BATS being cleared
> early in the kernel. I only see that the first 4 pairs
> are cleared using the mtspr instructions. But my
> kernel comes up just fine and everything seems to work
> OK. Dont we need to clear the other set of I/DBATS?
> What happens when we dont do this? Thanks in advance.
Additional BATs in G2_LE core must be explicitly enabled in HID2 (HBE
bit), until then they "don't exist" :).
--
Eugene
^ permalink raw reply
* Additional data/instruction BATs not initialized for MPC8280?
From: annamaya @ 2005-01-25 17:49 UTC (permalink / raw)
To: linuxppc-embedded
I have read in the specs for the MPC8280 that it has a
G2_LE core which has 4 additional data and instruction
BATs. However, I dont see these BATS being cleared
early in the kernel. I only see that the first 4 pairs
are cleared using the mtspr instructions. But my
kernel comes up just fine and everything seems to work
OK. Dont we need to clear the other set of I/DBATS?
What happens when we dont do this? Thanks in advance.
__________________________________
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^ permalink raw reply
* Re: About I-cache and D-cache of MPC8245
From: Jerry Van Baren @ 2005-01-25 14:37 UTC (permalink / raw)
To: chao yu; +Cc: linuxppc-embedded
In-Reply-To: <20050125012333.17213.qmail@web90003.mail.scd.yahoo.com>
chao yu wrote:
> Hi, All
> I am a newbie in embeded system from China, recently i enable
> the I-cache and D-cache of MPC8245. But it will crash. What the cause
> might be? I have set the ICE and DCE filed of HID0 reg. and WIMG field
> of BAT reg. Who can give me a hand? Thanks.
>
> Regard,
> Yu.Chao
Your SDRAM initialization is probably not correct. When you turn on
caches, the processor starts doing burst reads of the SDRAM and that is
when SDRAM initialization problems show up.
<http://www.denx.de/twiki/bin/view/DULG/UBootCrashAfterRelocation>
gvb
^ permalink raw reply
* Re: BUG: 2.6.11-rc2 and -rc1 hang during boot on PowerMacs
From: Mikael Pettersson @ 2005-01-25 8:56 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev list, Paul Mackerras, Linux Kernel list,
Mikael Pettersson
In-Reply-To: <1106623515.6244.11.camel@gaston>
Benjamin Herrenschmidt writes:
> On Mon, 2005-01-24 at 18:42 +0100, Mikael Pettersson wrote:
> > Benjamin Herrenschmidt writes:
> > > On Sun, 2005-01-23 at 11:43 +1100, Benjamin Herrenschmidt wrote:
> > >
> > > > I know about this problem, I'm working on a proper fix. Thanks for your
> > > > report.
> > >
> > > Can you send me the PVR value for both of these CPUs
> > > (cat /proc/cpuinfo) ? I can't find right now why they would lock up
> > > unless the default idle loop is _not_ run properly, that is for some
> > > reason, NAP or DOZE mode end up not beeing enabled. Can you send me
> > > your .config as well ?
> >
> > === cpuinfo.emac ===
> > processor : 0
> > cpu : 7447/7457, altivec supported
> > clock : 1249MHz
> > revision : 1.1 (pvr 8002 0101)
> > bogomips : 830.66
> > machine : PowerMac6,4
> > motherboard : PowerMac6,4 MacRISC3 Power Macintosh
> > detected as : 287 (Unknown Intrepid-based)
> > pmac flags : 00000000
> > L2 cache : 512K unified
> > memory : 256MB
> > pmac-generation : NewWorld
>
> Ok, it's normal that the Beige G3 doesn't do NAP, and the 7455 cannot do
> DOZE, so I suspect it's all normal and my patch fixes it.
>
> However, the eMac should have been doing NAP. Can you check what's up in
> arch/ppc/plaform/pmac_feature.c with powersave_nap ? is it set at all ?
> It should be visible from userland at /proc/sys/kernel/powersave-nap
> and should be set to 1 by default on your machine... unless your cpu
> node in the device-tree has the "flush-on-lock" property...
On the eMac:
/proc/sys/kernel/powersave-nap exists and contains "0".
/proc/device-tree/cpus/PowerPC,G4/flush-on-lock exists as an empty file.
/Mikael
^ permalink raw reply
* Re: Serial console problem on MPC8272ADS board
From: Vitaly Bordug @ 2005-01-25 8:27 UTC (permalink / raw)
To: ningmin, linuxppc-embedded
Ning,
Well, AFAIK the serial console on the second UART (and second UART on
SCC4 as well) haven't been included yet to the community tree. To be
sure you can take a look in the 8260_io/uart.c where in rs_table
structure second entry should be {0, 0, PROFF_SCC4 ... Implementation is
not that hard, you need only make proper mentioned entry, enable
transceiver (BCSR+4), and program parallel port pins (take a look at
chapter 37 of MPC8272 reference manual, grep for SCC4).
--
Regards, Vitaly
^ permalink raw reply
* Re: BUG: 2.6.11-rc2 and -rc1 hang during boot on PowerMacs
From: Benjamin Herrenschmidt @ 2005-01-25 3:25 UTC (permalink / raw)
To: Mikael Pettersson; +Cc: linuxppc-dev list, Paul Mackerras, Linux Kernel list
In-Reply-To: <16885.13185.849070.479328@alkaid.it.uu.se>
On Mon, 2005-01-24 at 18:42 +0100, Mikael Pettersson wrote:
> Benjamin Herrenschmidt writes:
> > On Sun, 2005-01-23 at 11:43 +1100, Benjamin Herrenschmidt wrote:
> >
> > > I know about this problem, I'm working on a proper fix. Thanks for your
> > > report.
> >
> > Can you send me the PVR value for both of these CPUs
> > (cat /proc/cpuinfo) ? I can't find right now why they would lock up
> > unless the default idle loop is _not_ run properly, that is for some
> > reason, NAP or DOZE mode end up not beeing enabled. Can you send me
> > your .config as well ?
>
> === cpuinfo.emac ===
> processor : 0
> cpu : 7447/7457, altivec supported
> clock : 1249MHz
> revision : 1.1 (pvr 8002 0101)
> bogomips : 830.66
> machine : PowerMac6,4
> motherboard : PowerMac6,4 MacRISC3 Power Macintosh
> detected as : 287 (Unknown Intrepid-based)
> pmac flags : 00000000
> L2 cache : 512K unified
> memory : 256MB
> pmac-generation : NewWorld
Ok, it's normal that the Beige G3 doesn't do NAP, and the 7455 cannot do
DOZE, so I suspect it's all normal and my patch fixes it.
However, the eMac should have been doing NAP. Can you check what's up in
arch/ppc/plaform/pmac_feature.c with powersave_nap ? is it set at all ?
It should be visible from userland at /proc/sys/kernel/powersave-nap
and should be set to 1 by default on your machine... unless your cpu
node in the device-tree has the "flush-on-lock" property...
Ben.
^ permalink raw reply
* [PATCH] ppc64: Missing call to ioremap in pci_iomap()
From: Benjamin Herrenschmidt @ 2005-01-25 2:35 UTC (permalink / raw)
To: Kumar Gala
Cc: Andrew Morton, linuxppc-dev list, rvinson, Linux Kernel list,
linuxppc-embedded
In-Reply-To: <Pine.LNX.4.61.0501241543530.23252@blarg.somerset.sps.mot.com>
On Mon, 2005-01-24 at 15:46 -0600, Kumar Gala wrote:
> The PPC version of pci_iomap seems to be missing a call to ioremap. This
> patch corrects that oversight and has been tested on a IBM PPC750FX Eval
> board.
Looks like the ppc64 version as well !
This patch adds the missing ioremap call to pci_iomap on ppc64.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Index: linux-work/arch/ppc64/kernel/iomap.c
===================================================================
--- linux-work.orig/arch/ppc64/kernel/iomap.c 2005-01-24 11:42:36.000000000 +1100
+++ linux-work/arch/ppc64/kernel/iomap.c 2005-01-25 13:33:13.000000000 +1100
@@ -113,7 +113,7 @@
if (flags & IORESOURCE_IO)
return ioport_map(start, len);
if (flags & IORESOURCE_MEM)
- return (void __iomem *) start;
+ return ioremap(start, len);
/* What? */
return NULL;
}
^ permalink raw reply
* Re: [PATCH] ppc32: fix powersave with interrupts disabled
From: Benjamin Herrenschmidt @ 2005-01-25 2:31 UTC (permalink / raw)
To: Kumar Gala; +Cc: Andrew Morton, waite, Linux Kernel list, linuxppc-dev list
In-Reply-To: <Pine.LNX.4.61.0501241548380.23263@blarg.somerset.sps.mot.com>
On Mon, 2005-01-24 at 15:51 -0600, Kumar Gala wrote:
> It looks like the problem has to do with entering the powersave routine
> with irqs disabled. Here is a patch that will only enter powersave if irqs
> are enabled.
>
> Entering powersave on PPC while irqs are disabled causes a hang. Only
> enter powersave if irqs are disabled.
I have a different fix which is to re-enable them (basically to move the
local_irq_disable we do in #ifdef CONFIG_SMP above the whole block,
removing the #else case).
I'm waiting for Ingo's ack about what exact race he's trying to fix
though...
Ben.
^ permalink raw reply
* About I-cache and D-cache of MPC8245
From: chao yu @ 2005-01-25 1:23 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 383 bytes --]
Hi, All
I am a newbie in embeded system from China, recently i enable the I-cache and D-cache of MPC8245. But it will crash. What the cause might be? I have set the ICE and DCE filed of HID0 reg. and WIMG field of BAT reg. Who can give me a hand? Thanks.
Regard,
Yu.Chao
---------------------------------
Do you Yahoo!?
Yahoo! Search presents - Jib Jab's 'Second Term'
[-- Attachment #2: Type: text/html, Size: 578 bytes --]
^ permalink raw reply
* [PATCH] ppc32: fix powersave with interrupts disabled
From: Kumar Gala @ 2005-01-24 21:51 UTC (permalink / raw)
To: akpm; +Cc: waite, linuxppc-dev, linux-kernel
It looks like the problem has to do with entering the powersave routine
with irqs disabled. Here is a patch that will only enter powersave if irqs
are enabled.
Entering powersave on PPC while irqs are disabled causes a hang. Only
enter powersave if irqs are disabled.
Signed-off-by: Brian Waite <waite@skycomputers.com>
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
diff -Nru a/arch/ppc/kernel/idle.c b/arch/ppc/kernel/idle.c
--- a/arch/ppc/kernel/idle.c 2005-01-24 15:48:24 -06:00
+++ b/arch/ppc/kernel/idle.c 2005-01-24 15:48:24 -06:00
@@ -39,7 +39,7 @@
powersave = ppc_md.power_save;
if (!need_resched()) {
- if (powersave != NULL)
+ if (powersave != NULL && !irqs_disabled())
powersave();
else {
#ifdef CONFIG_SMP
^ permalink raw reply
* [PATCH] ppc32: Missing call to ioremap in pci_iomap()
From: Kumar Gala @ 2005-01-24 21:46 UTC (permalink / raw)
To: akpm; +Cc: linuxppc-dev, rvinson, linux-kernel, linuxppc-embedded
The PPC version of pci_iomap seems to be missing a call to ioremap. This
patch corrects that oversight and has been tested on a IBM PPC750FX Eval
board.
Signed-off-by Randy Vinson <rvinson@mvista.com>
Signed-off-by Kumar Gala <kumar.gala@freescale.com>
---
diff -Nru a/arch/ppc/kernel/pci.c b/arch/ppc/kernel/pci.c
--- a/arch/ppc/kernel/pci.c 2005-01-24 15:43:19 -06:00
+++ b/arch/ppc/kernel/pci.c 2005-01-24 15:43:19 -06:00
@@ -1712,7 +1712,11 @@
if (flags & IORESOURCE_IO)
return ioport_map(start, len);
if (flags & IORESOURCE_MEM)
- return (void __iomem *) start;
+ /* Not checking IORESOURCE_CACHEABLE because PPC does
+ * not currently distinguish between ioremap and
+ * ioremap_nocache.
+ */
+ return ioremap(start, len);
/* What? */
return NULL;
}
^ permalink raw reply
* Re: Kernel booting issues on a MPC8270 board
From: annamaya @ 2005-01-24 22:42 UTC (permalink / raw)
To: annamaya, Mark Chambers, linuxppc-embedded
In-Reply-To: <20050124151131.769.qmail@web53802.mail.yahoo.com>
I finally figured out my problem had to do with the
fact that my MPC8270 processor was not supported in
the cpu table. I was able to find the definition for
82xx, HiP7 603e entry for CPU table in the 2.4.24 from
denx and copied that table into the cpu table of the
MVista kernel. Otherwise, the cpu_spec[] structure was
defaulting to some entry that set the
CPU_FTR_HPTE_TABLE option in the cpu_spec which
resulted in execution of some code in
cacheable_memzero() routine that resulted in resetting
my CPU and my board.
Sorry for all the noise but I thought I should share
my debug experience here since someone else might go
through this trying to run MVista kernel on a HiP7
82xx processor.
And for the record, the kernel from denx works great.
I was just trying to figure out why the MVista one
wasn't working.
Thanks for everyone's input on this.
--- annamaya <annamaya@yahoo.com> wrote:
> As someone who has worked on the 8xx processors
> before, I went looking for the DER for the 8270 but
> was unable to find such a register. If someone can
> point me to such a register on the 8270, I would
> really appreciate it.
>
> It looks like single-stepping doesn't work till
> later
> in the Kernel. Anyways, I found out after much
> debugging that it wasn't the first instruction that
> the break was occuring but the code made it all the
> way to the "cacheable_memzero" routine and fails in
> the "dcbz" instruction. The cpu gets reset as soon
> as
> I try to single-step this instruction. Any ideas as
> to
> why this is happening?
>
> --- Mark Chambers <mchambers@microfirst.com> wrote:
>
> > I'm not familiar with the 8270 per se, but on the
> > 8xx you've got this Debug
> > Enable Register (DER) where you set different bits
> > for things you want the
> > processor to jump into debug mode when they
> happen.
> > You might need to play
> > with that to get the BDI to catch whatever is
> > happening. It's probably set
> > in the BDI config file somewhere.
> >
> > ----- Original Message -----
> > From: "annamaya" <annamaya@yahoo.com>
> > To: "annamaya" <annamaya@yahoo.com>;
> > <linuxppc-embedded@ozlabs.org>
> > Sent: Friday, January 21, 2005 4:20 PM
> > Subject: Re: Kernel booting issues on a MPC8270
> > board
> >
> >
> > > I am sorry but I dont believe the "mfpvr"
> > instruction
> > > has anything to do with it. I thought removing
> it
> > was
> > > getting rid of the problem but I was wrong. The
> > board
> > > still gets reset when the very first instruction
> > is
> > > executed. I am stumped.
> > >
> > > --- annamaya <annamaya@yahoo.com> wrote:
> > >
> > > > I debugged this problem a little more and
> > realized
> > > > that the reset was happenning right after the
> > > > execution of the first kernel instruction at
> > > > 0x0000000c. The instruction at this location
> was
> > > > "mfpvr r28". I traced this back to a snippet
> of
> > code
> > > > that was dealing with pipeline depth issues on
> > the
> > > > MPC8260. Once I commented this code out, more
> > > > instructions were issued but the reboot
> happens
> > > > elsewhere. I am not able to pin-point the
> > location
> > > > of
> > > > the debug since my BDI fails to catch the
> reset
> > when
> > > > it happens. Can someone point me to the cause
> of
> > > > this
> > > > situation? Thanks in advance.
> > > >
> > > > --- annamaya <annamaya@yahoo.com> wrote:
> > > >
> > > > > I am trying to boot a mvista Linux Kernel
> ver.
> > > > > 2.4.20
> > > > > on a MPC8270 board. I am using the
> > embed_config()
> > > > > in
> > > > > zImage to pass the board info since the
> > bootloader
> > > > > is
> > > > > not ppcboot. After the message, "Now booting
> > the
> > > > > kernel", the board just reboots, as if
> someone
> > > > > yanked
> > > > > the reset line. I have BDI hooked up but it
> > > > doesn't
> > > > > seem to catch the reset point in the code.
> And
> > I
> > > > am
> > > > > unable to trace this to anything in the
> code.
> > Any
> > > > > suggestions? Thanks in advance.
> > > > >
> > > > >
> > > > >
> > > > > __________________________________
> > > > > Do you Yahoo!?
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> > > > > more.
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> > > > >
> > _______________________________________________
> > > > > Linuxppc-embedded mailing list
> > > > > Linuxppc-embedded@ozlabs.org
> > > > >
> > > >
> > >
> >
>
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> > > > >
> > > >
> > > >
> > > >
> > > >
> > > > __________________________________
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> > > Linuxppc-embedded@ozlabs.org
> > >
> >
>
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> >
>
>
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^ permalink raw reply
* Re: Serial console problem on MPC8272ADS board
From: annamaya @ 2005-01-24 18:28 UTC (permalink / raw)
To: ning, linuxppc-embedded
In-Reply-To: <20050123085652.42295.qmail@web605.mail.yahoo.co.jp>
I do not know much about the MPC82702ADS but are you
sure that the SCC4 is actually hooked up to an
external serial port on this board? It may be that the
SCC4 may not even be used on this board. Take a look
at the datasheet for the board and see if SCC4 is used
at all.
--- ning <ningmin@yahoo.co.jp> wrote:
> Hello to all
>
> I am trying to use ttyS1(SCC4) as Linux serial
> console
> port on on MPC8272ADS board.
> but it doesn't work.
> My linux kernel is 2.4.22,and using u-boot-1.1.1 as
> a
> bootload.
> Linux kernel doesn't output any log information
> after
> u-boot's message:
> Uncompressing kernel Image ... OK
>
> If I use ttyS0(SCC1) as a serial console port,Linux
> will
> startup successfully.
>
> CPM UART driver version 0.01
> ttyS0 at 0x8000 is a SCC
> ttyS1 at 0x8300 is a SCC
> ...
>
> I found serial console port seems be defined in
> /arch/ppc/8260_io/uart.c,
> but it doesn't work enen if I change
> CONFIG_SERIAL_CONSOLE_PORT to 1 (default:0)
>
> I wonder serial console port only can be set to
> ttyS0(SCC1) on MPC8272ADS?
>
> Thanks.
>
> __________________________________
> Do You Yahoo!?
> Upgrade Your Life
> http://bb.yahoo.co.jp/
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
>
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>
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^ permalink raw reply
* Re: BUG: 2.6.11-rc2 and -rc1 hang during boot on PowerMacs
From: Mikael Pettersson @ 2005-01-24 17:42 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev list, Paul Mackerras, Linux Kernel list,
Mikael Pettersson
In-Reply-To: <1106529935.5587.9.camel@gaston>
Benjamin Herrenschmidt writes:
> On Sun, 2005-01-23 at 11:43 +1100, Benjamin Herrenschmidt wrote:
>
> > I know about this problem, I'm working on a proper fix. Thanks for your
> > report.
>
> Can you send me the PVR value for both of these CPUs
> (cat /proc/cpuinfo) ? I can't find right now why they would lock up
> unless the default idle loop is _not_ run properly, that is for some
> reason, NAP or DOZE mode end up not beeing enabled. Can you send me
> your .config as well ?
=== cpuinfo.emac ===
processor : 0
cpu : 7447/7457, altivec supported
clock : 1249MHz
revision : 1.1 (pvr 8002 0101)
bogomips : 830.66
machine : PowerMac6,4
motherboard : PowerMac6,4 MacRISC3 Power Macintosh
detected as : 287 (Unknown Intrepid-based)
pmac flags : 00000000
L2 cache : 512K unified
memory : 256MB
pmac-generation : NewWorld
=== cpuinfo.beige-g3 ===
processor : 0
cpu : 7455, altivec supported (a Sonnet G4 upgrade processor)
clock : 66MHz <-- bogus, is 1.0GHz in reality
revision : 2.1 (pvr 8001 0201)
bogomips : 999.42
machine : Power Macintosh
motherboard : AAPL,Gossamer MacRISC
detected as : 48 (PowerMac G3 (Gossamer))
pmac flags : 00000000
memory : 768MB
pmac-generation : OldWorld
The .config files are a bit big, I'm sending them off-list.
> Finally, try that patch and tell me if it makes a difference. It makes
> sure we re-enable interrupts in cpu_idle, and thus should only be a
> workaround. I found _one_ actual code path where we fail to re-enable
> them, and this is when neither DOZE nor NAP mode is enabled, which
> should not happen on any G3 (they should all support DOZE mode), and
> might happe non some G4s if the chipset doesn't support NAP or
> powersave_nap is set to 0 in proc, but that shouldn't be the case of an
> eMac neither...
>
> --- linux-work.orig/arch/ppc/kernel/idle.c 2005-01-24 11:42:35.000000000 +1100
> +++ linux-work/arch/ppc/kernel/idle.c 2005-01-24 12:19:41.114353760 +1100
> @@ -39,17 +39,15 @@
> powersave = ppc_md.power_save;
>
> if (!need_resched()) {
> + local_irq_enable();
> if (powersave != NULL)
> powersave();
> else {
> #ifdef CONFIG_SMP
> set_thread_flag(TIF_POLLING_NRFLAG);
> - local_irq_enable();
> while (!need_resched())
> barrier();
> clear_thread_flag(TIF_POLLING_NRFLAG);
> -#else
> - local_irq_enable();
> #endif
> }
> }
Yes, this patch made the eMac boot Ok -- I can't test the Beige G3 until Friday.
/Mikael
^ permalink raw reply
* MPC8XX with an ISP1362 USB host controller in burst mode
From: Jordan, Kyle @ 2005-01-24 16:00 UTC (permalink / raw)
To: linuxppc-embedded
We are currently planning to use an ISP1362 USB host controller with a
Freescale (Motorola) MPC8xx. Our plan is to use the hcd-1161.c driver
for the 2.4 kernel for this device. I was wondering if anyone out there
has used this combination operating in either bust mode or with burst
mode turned off. We are running into some hardware design issues and we
did not know if we would suffer a large performance hit by not running
in burst mode with this particular driver. If anyone has any experience
with this, I would greatly appreciate your advice.
Thanks,
Kyle Jordan
^ permalink raw reply
* Re: Java/eclipse in PPC
From: David Woodhouse @ 2005-01-24 15:43 UTC (permalink / raw)
To: David Medina; +Cc: linuxppc-dev
In-Reply-To: <6ecd913805012402451b425320@mail.gmail.com>
On Mon, 2005-01-24 at 11:45 +0100, David Medina wrote:
> I have a Ibook G4 (the last - 23.01.05) where are installed
> Debian Ubuntu 4.01 to PPC (logical)
> I want to install Java and Eclipse to development. The SDK of
> Java is "easy" because can be downloaded to www.ibm.com the version
> "1.4.2 SR1"
There are packages in Fedora rawhide which use gcj. They seem to work
for me on a FC3 installation. You may be able to use those in Debian;
I'm not sure.
--
dwmw2
^ permalink raw reply
* Re: Kernel booting issues on a MPC8270 board
From: annamaya @ 2005-01-24 15:11 UTC (permalink / raw)
To: Mark Chambers, linuxppc-embedded
In-Reply-To: <000b01c50013$d7070fb0$0301a8c0@chuck2>
As someone who has worked on the 8xx processors
before, I went looking for the DER for the 8270 but
was unable to find such a register. If someone can
point me to such a register on the 8270, I would
really appreciate it.
It looks like single-stepping doesn't work till later
in the Kernel. Anyways, I found out after much
debugging that it wasn't the first instruction that
the break was occuring but the code made it all the
way to the "cacheable_memzero" routine and fails in
the "dcbz" instruction. The cpu gets reset as soon as
I try to single-step this instruction. Any ideas as to
why this is happening?
--- Mark Chambers <mchambers@microfirst.com> wrote:
> I'm not familiar with the 8270 per se, but on the
> 8xx you've got this Debug
> Enable Register (DER) where you set different bits
> for things you want the
> processor to jump into debug mode when they happen.
> You might need to play
> with that to get the BDI to catch whatever is
> happening. It's probably set
> in the BDI config file somewhere.
>
> ----- Original Message -----
> From: "annamaya" <annamaya@yahoo.com>
> To: "annamaya" <annamaya@yahoo.com>;
> <linuxppc-embedded@ozlabs.org>
> Sent: Friday, January 21, 2005 4:20 PM
> Subject: Re: Kernel booting issues on a MPC8270
> board
>
>
> > I am sorry but I dont believe the "mfpvr"
> instruction
> > has anything to do with it. I thought removing it
> was
> > getting rid of the problem but I was wrong. The
> board
> > still gets reset when the very first instruction
> is
> > executed. I am stumped.
> >
> > --- annamaya <annamaya@yahoo.com> wrote:
> >
> > > I debugged this problem a little more and
> realized
> > > that the reset was happenning right after the
> > > execution of the first kernel instruction at
> > > 0x0000000c. The instruction at this location was
> > > "mfpvr r28". I traced this back to a snippet of
> code
> > > that was dealing with pipeline depth issues on
> the
> > > MPC8260. Once I commented this code out, more
> > > instructions were issued but the reboot happens
> > > elsewhere. I am not able to pin-point the
> location
> > > of
> > > the debug since my BDI fails to catch the reset
> when
> > > it happens. Can someone point me to the cause of
> > > this
> > > situation? Thanks in advance.
> > >
> > > --- annamaya <annamaya@yahoo.com> wrote:
> > >
> > > > I am trying to boot a mvista Linux Kernel ver.
> > > > 2.4.20
> > > > on a MPC8270 board. I am using the
> embed_config()
> > > > in
> > > > zImage to pass the board info since the
> bootloader
> > > > is
> > > > not ppcboot. After the message, "Now booting
> the
> > > > kernel", the board just reboots, as if someone
> > > > yanked
> > > > the reset line. I have BDI hooked up but it
> > > doesn't
> > > > seem to catch the reset point in the code. And
> I
> > > am
> > > > unable to trace this to anything in the code.
> Any
> > > > suggestions? Thanks in advance.
> > > >
> > > >
> > > >
> > > > __________________________________
> > > > Do you Yahoo!?
> > > > Yahoo! Mail - now with 250MB free storage.
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> > > > more.
> > > > http://info.mail.yahoo.com/mail_250
> > > >
> _______________________________________________
> > > > Linuxppc-embedded mailing list
> > > > Linuxppc-embedded@ozlabs.org
> > > >
> > >
> >
>
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> > > >
> > >
> > >
> > >
> > >
> > > __________________________________
> > > Do you Yahoo!?
> > > Read only the mail you want - Yahoo! Mail
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> > >
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> > >
> >
> >
> > __________________________________________________
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> > _______________________________________________
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> > Linuxppc-embedded@ozlabs.org
> >
>
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>
>
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^ permalink raw reply
* lk2.4.25 compile fails with ELDK3.1
From: Sanjay Bajaj @ 2005-01-24 14:30 UTC (permalink / raw)
To: linuxppc-embedded
Hi! All,
I am new to this list, therefore, please correct my mistakes, if I do =
any.
I downloaded/installed ELDK 3.1 and also unzip lk2.4.25 which came with =
it. I used the default Xilinx ml300 config to compile the lk2.4.25. The =
following error is seen at the end of the compile:
ppc_4xx-objcopy -O elf32-powerpc \
--add-section=3D.image=3D../images/vmlinux.gz \
--set-section-flags=3D.image=3Dcontents,alloc,load,readonly,data =
\
../common/dummy.o image.o
ppc_4xx-ld -T ../ld.script -Ttext 0x00400000 -Bstatic -o zvmlinux head.o =
../common/relocate.o misc-embedded.o .
./common/misc-common.o ../common/string.o ../common/util.o =
../common/serial_stub.o embed_config.o xiic_l.o ../co
mmon/ns16550.o image.o ../lib/zlib.a
ppc_4xx-objcopy -O elf32-powerpc zvmlinux zvmlinux -R .comment -R .stab =
-R .stabstr \
-R .ramdisk -R .sysmap
mv zvmlinux ../images/zImage.
mv zvmlinux ../images/zImage.elf
mv: can't stat source zvmlinux
make[2]: *** [zImage] Error 1
make[2]: Leaving directory `/usr/src/linux-2.4.25/arch/ppc/boot/simple'
make[1]: *** [zImage] Error 2
make[1]: Leaving directory `/usr/src/linux-2.4.25/arch/ppc/boot'
make: *** [zImage] Error 2
I tried the same effort with ELDK 3.0 for lk2.4.24, that works fine. I =
have used different lk versions with ELDK 3.1 with the same result. Any =
ideas/pointers/explanations? They would greatly help.
Thanks,
Sanjay
^ permalink raw reply
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