* [PATCH] Extended keyboard+mouse emulation
From: Joakim Karlsson @ 2005-01-26 0:12 UTC (permalink / raw)
To: linuxppc-dev
Hi everyone!
This is my first patch ever, so I hope I'm doing this right. In short,
this patch allows standard usage of the mouse button emulation in the
mac_hid. It extends the functionality to a combination of a key and mouse
button, retaining full compatibility. Project site:
http://aio.nocrew.org/projects/pbmousehack/
I have successfully tested it on 2.6.9 and 2.6.10.
Regards, Joakim Karlsson <aio@nocrew.org>
diff -urN linux-2.6.9.old/drivers/input/mousedev.c linux-2.6.9.new/drivers/input/mousedev.c
--- linux-2.6.9.old/drivers/input/mousedev.c 2004-10-18 23:55:07.000000000 +0200
+++ linux-2.6.9.new/drivers/input/mousedev.c 2004-12-14 01:11:48.644153752 +0100
@@ -168,6 +168,11 @@
}
}
+#ifdef CONFIG_MAC_EMUMOUSEBTN
+extern int mac_hid_mouse_emulate_buttons(int, int, int);
+extern int mac_hid_get_mouse_combination(int);
+#endif /* CONFIG_MAC_EMUMOUSEBTN */
+
static void mousedev_key_event(struct mousedev *mousedev, unsigned int code, int value)
{
int index;
@@ -192,9 +197,17 @@
}
if (value) {
+#ifdef CONFIG_MAC_EMUMOUSEBTN
+ if (index == 0)
+ index += mac_hid_get_mouse_combination(1);
+#endif /* CONFIG_MAC_EMUMOUSEBTN */
set_bit(index, &mousedev->packet.buttons);
set_bit(index, &mousedev_mix.packet.buttons);
} else {
+#ifdef CONFIG_MAC_EMUMOUSEBTN
+ if (index == 0)
+ index += mac_hid_get_mouse_combination(0);
+#endif /* CONFIG_MAC_EMUMOUSEBTN */
clear_bit(index, &mousedev->packet.buttons);
clear_bit(index, &mousedev_mix.packet.buttons);
}
diff -urN linux-2.6.9.old/drivers/macintosh/mac_hid.c linux-2.6.9.new/drivers/macintosh/mac_hid.c
--- linux-2.6.9.old/drivers/macintosh/mac_hid.c 2004-10-18 23:54:55.000000000 +0200
+++ linux-2.6.9.new/drivers/macintosh/mac_hid.c 2004-12-14 01:12:11.998603336 +0100
@@ -15,10 +15,10 @@
#include <linux/input.h>
#include <linux/module.h>
-
static struct input_dev emumousebtn;
static void emumousebtn_input_register(void);
static int mouse_emulate_buttons = 0;
+static int mouse_combine_buttons = 0;
static int mouse_button2_keycode = KEY_RIGHTCTRL; /* right control key */
static int mouse_button3_keycode = KEY_RIGHTALT; /* right option key */
static int mouse_last_keycode = 0;
@@ -35,6 +35,14 @@
.proc_handler = &proc_dointvec,
},
{
+ .ctl_name = DEV_MAC_HID_MOUSE_BUTTON_COMBINATION,
+ .procname = "mouse_combine_emulation",
+ .data = &mouse_combine_buttons,
+ .maxlen = sizeof(int),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec,
+ },
+ {
.ctl_name = DEV_MAC_HID_MOUSE_BUTTON2_KEYCODE,
.procname = "mouse_button2_keycode",
.data = &mouse_button2_keycode,
@@ -81,12 +89,37 @@
#endif /* endif CONFIG_SYSCTL */
+int mac_hid_get_mouse_combination(int set)
+{
+ static int button = 0;
+ int retval = 0;
+
+ if (set == 1) {
+ button = mouse_last_keycode;
+ if (button == mouse_button2_keycode)
+ retval = 1;
+ else if (button == mouse_button3_keycode)
+ retval = 2;
+ else
+ retval = 0;
+ } else {
+ if (button == mouse_button2_keycode)
+ retval = 1;
+ else if (button == mouse_button3_keycode)
+ retval = 2;
+ else
+ retval = 0;
+ button = 0;
+ }
+ return retval;
+}
+
int mac_hid_mouse_emulate_buttons(int caller, unsigned int keycode, int down)
{
switch (caller) {
case 1:
/* Called from keyboard.c */
- if (mouse_emulate_buttons
+ if (mouse_emulate_buttons && !mouse_combine_buttons
&& (keycode == mouse_button2_keycode
|| keycode == mouse_button3_keycode)) {
if (mouse_emulate_buttons == 1) {
@@ -98,6 +131,12 @@
}
mouse_last_keycode = down ? keycode : 0;
}
+ if (mouse_combine_buttons
+ && (keycode == mouse_button2_keycode
+ || keycode == mouse_button3_keycode)) {
+ mouse_last_keycode = down ? keycode : 0;
+ return 0;
+ }
break;
}
return 0;
diff -urN linux-2.6.9.old/include/linux/sysctl.h linux-2.6.9.new/include/linux/sysctl.h
--- linux-2.6.9.old/include/linux/sysctl.h 2004-10-18 23:54:31.000000000 +0200
+++ linux-2.6.9.new/include/linux/sysctl.h 2004-12-14 01:13:44.179589696 +0100
@@ -747,7 +747,8 @@
DEV_MAC_HID_MOUSE_BUTTON_EMULATION=3,
DEV_MAC_HID_MOUSE_BUTTON2_KEYCODE=4,
DEV_MAC_HID_MOUSE_BUTTON3_KEYCODE=5,
- DEV_MAC_HID_ADB_MOUSE_SENDS_KEYCODES=6
+ DEV_MAC_HID_ADB_MOUSE_SENDS_KEYCODES=6,
+ DEV_MAC_HID_MOUSE_BUTTON_COMBINATION=8
};
/* /proc/sys/dev/scsi */
^ permalink raw reply
* [PATCH][SERIAL] mpsc updates
From: Mark A. Greer @ 2005-01-26 0:36 UTC (permalink / raw)
To: akpm; +Cc: lkml, Russell King, Embedded PPC Linux list
[-- Attachment #1: Type: text/plain, Size: 360 bytes --]
Hi again, Andrew.
This patch:
- replaces several macros with the actual code
- change the type of pointer variables from u32 to void *
- removes unecessary casts
- puts the contents of mpsc_defs.h into mpsc.h and removes the mpsc_defs.h
- reflects the new names of some structs
- cleans up some whitespace
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
--
[-- Attachment #2: mpsc.patch --]
[-- Type: text/plain, Size: 39078 bytes --]
diff -Nru a/drivers/serial/mpsc.c b/drivers/serial/mpsc.c
--- a/drivers/serial/mpsc.c 2005-01-25 17:28:43 -07:00
+++ b/drivers/serial/mpsc.c 2005-01-25 17:28:43 -07:00
@@ -36,16 +36,14 @@
*
* 1) Some chips have an erratum where several regs cannot be
* read. To work around that, we keep a local copy of those regs in
- * 'mpsc_port_info' and use the *_M or *_S macros when accessing those regs.
+ * 'mpsc_port_info'.
*
* 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
- * accesses system mem in a cache coherent region. This *should* be a
- * show-stopper when coherency is turned on but it seems to work okay as
- * long as there are no snoop hits. Therefore, the ring buffer entries and
- * the buffers themselves are allocated via 'dma_alloc_noncoherent()' and
- * 'dma_cache_sync()' is used. Also, since most PPC platforms are coherent
- * which makes 'dma_cache_sync()' a no-op, explicit cache management macros
- * have been added ensuring there are no snoop hits when coherency is on.
+ * accesses system mem with coherency enabled. For that reason, the driver
+ * assumes that coherency for that ctlr has been disabled. This means
+ * that when in a cache coherent system, the driver has to manually manage
+ * the data cache on the areas that it touches because the dma_* macro are
+ * basically no-ops.
*
* 3) There is an erratum (on PPC) where you can't use the instruction to do
* a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
@@ -54,7 +52,6 @@
* 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
*/
-#include <linux/mv643xx.h>
#include "mpsc.h"
/*
@@ -81,25 +78,48 @@
static void
mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
{
+ u32 v;
+
+ v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
+ v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18);
+
if (pi->brg_can_tune)
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 1, 25, 0);
+ v &= ~(1 << 25);
+
+ if (pi->mirror_regs)
+ pi->BRG_BCR_m = v;
+ writel(v, pi->brg_base + BRG_BCR);
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 4, 18, clk_src);
- MPSC_MOD_FIELD(pi, brg, BRG_BTR, 16, 0, 0);
+ writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
+ pi->brg_base + BRG_BTR);
return;
}
static void
mpsc_brg_enable(struct mpsc_port_info *pi)
{
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 1, 16, 1);
+ u32 v;
+
+ v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
+ v |= (1 << 16);
+
+ if (pi->mirror_regs)
+ pi->BRG_BCR_m = v;
+ writel(v, pi->brg_base + BRG_BCR);
return;
}
static void
mpsc_brg_disable(struct mpsc_port_info *pi)
{
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 1, 16, 0);
+ u32 v;
+
+ v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
+ v &= ~(1 << 16);
+
+ if (pi->mirror_regs)
+ pi->BRG_BCR_m = v;
+ writel(v, pi->brg_base + BRG_BCR);
return;
}
@@ -115,10 +135,16 @@
* that accounts for the way the mpsc is set up is:
* CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
*/
- u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
+ u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
+ u32 v;
mpsc_brg_disable(pi);
- MPSC_MOD_FIELD_M(pi, brg, BRG_BCR, 16, 0, cdv);
+ v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
+ v = (v & 0xffff0000) | (cdv & 0xffff);
+
+ if (pi->mirror_regs)
+ pi->BRG_BCR_m = v;
+ writel(v, pi->brg_base + BRG_BCR);
mpsc_brg_enable(pi);
return;
@@ -135,7 +161,7 @@
static void
mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
{
- u32 v;
+ u32 v;
pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
pi->port.line, burst_size);
@@ -151,7 +177,8 @@
else
v = 0x3; /* 8 64-bit words */
- MPSC_MOD_FIELD(pi, sdma, SDMA_SDC, 2, 12, v);
+ writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
+ pi->sdma_base + SDMA_SDC);
return;
}
@@ -161,7 +188,8 @@
pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
burst_size);
- MPSC_MOD_FIELD(pi, sdma, SDMA_SDC, 10, 0, 0x03f);
+ writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
+ pi->sdma_base + SDMA_SDC);
mpsc_sdma_burstsize(pi, burst_size);
return;
}
@@ -169,16 +197,21 @@
static inline u32
mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
{
- u32 old, v;
+ u32 old, v;
pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask);
- old = v = MPSC_READ_S(pi, sdma_intr, SDMA_INTR_MASK);
+ old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
+ readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
+
mask &= 0xf;
if (pi->port.line)
mask <<= 8;
v &= ~mask;
- MPSC_WRITE_S(pi, sdma_intr, SDMA_INTR_MASK, v);
+
+ if (pi->mirror_regs)
+ pi->shared_regs->SDMA_INTR_MASK_m = v;
+ writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
if (pi->port.line)
old >>= 8;
@@ -188,16 +221,21 @@
static inline void
mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
{
- u32 v;
+ u32 v;
pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
- v = MPSC_READ_S(pi, sdma_intr, SDMA_INTR_MASK);
+ v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
+ readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
+
mask &= 0xf;
if (pi->port.line)
mask <<= 8;
v |= mask;
- MPSC_WRITE_S(pi, sdma_intr, SDMA_INTR_MASK, v);
+
+ if (pi->mirror_regs)
+ pi->shared_regs->SDMA_INTR_MASK_m = v;
+ writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
return;
}
@@ -205,7 +243,10 @@
mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
{
pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
- MPSC_WRITE_S(pi, sdma_intr, SDMA_INTR_CAUSE, 0);
+
+ if (pi->mirror_regs)
+ pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
+ writel(0, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE);
return;
}
@@ -215,30 +256,30 @@
pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
pi->port.line, (u32) rxre_p);
- MPSC_WRITE(pi, sdma, SDMA_SCRDP, (u32) rxre_p);
+ writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
return;
}
static inline void
mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, struct mpsc_tx_desc *txre_p)
{
- MPSC_WRITE(pi, sdma, SDMA_SFTDP, (u32) txre_p);
- MPSC_WRITE(pi, sdma, SDMA_SCTDP, (u32) txre_p);
+ writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
+ writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
return;
}
static inline void
mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
{
- u32 v;
+ u32 v;
- v = MPSC_READ(pi, sdma, SDMA_SDCM);
+ v = readl(pi->sdma_base + SDMA_SDCM);
if (val)
v |= val;
else
v = 0;
wmb();
- MPSC_WRITE(pi, sdma, SDMA_SDCM, v);
+ writel(v, pi->sdma_base + SDMA_SDCM);
wmb();
return;
}
@@ -246,7 +287,7 @@
static inline uint
mpsc_sdma_tx_active(struct mpsc_port_info *pi)
{
- return MPSC_READ(pi, sdma, SDMA_SDCM) & SDMA_SDCM_TXD;
+ return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
}
static inline void
@@ -259,7 +300,11 @@
txre = (struct mpsc_tx_desc *)(pi->txr +
(pi->txr_tail * MPSC_TXRE_SIZE));
dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
- MPSC_CACHE_INVALIDATE(pi, (u32)txre, (u32)txre+MPSC_TXRE_SIZE);
+#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
+ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
+ invalidate_dcache_range((ulong)txre,
+ (ulong)txre + MPSC_TXRE_SIZE);
+#endif
if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
txre_p = (struct mpsc_tx_desc *)(pi->txr_p +
@@ -305,32 +350,61 @@
static void
mpsc_hw_init(struct mpsc_port_info *pi)
{
+ u32 v;
+
pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line);
/* Set up clock routing */
- MPSC_MOD_FIELD_S(pi, mpsc_routing, MPSC_MRR, 3, 0, 0);
- MPSC_MOD_FIELD_S(pi, mpsc_routing, MPSC_MRR, 3, 6, 0);
- MPSC_MOD_FIELD_S(pi, mpsc_routing, MPSC_RCRR, 4, 0, 0);
- MPSC_MOD_FIELD_S(pi, mpsc_routing, MPSC_RCRR, 4, 8, 1);
- MPSC_MOD_FIELD_S(pi, mpsc_routing, MPSC_TCRR, 4, 0, 0);
- MPSC_MOD_FIELD_S(pi, mpsc_routing, MPSC_TCRR, 4, 8, 1);
+ if (pi->mirror_regs) {
+ v = pi->shared_regs->MPSC_MRR_m;
+ v &= ~0x1c7;
+ pi->shared_regs->MPSC_MRR_m = v;
+ writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
+
+ v = pi->shared_regs->MPSC_RCRR_m;
+ v = (v & ~0xf0f) | 0x100;
+ pi->shared_regs->MPSC_RCRR_m = v;
+ writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
+
+ v = pi->shared_regs->MPSC_TCRR_m;
+ v = (v & ~0xf0f) | 0x100;
+ pi->shared_regs->MPSC_TCRR_m = v;
+ writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
+ }
+ else {
+ v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
+ v &= ~0x1c7;
+ writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
+
+ v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
+ v = (v & ~0xf0f) | 0x100;
+ writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
+
+ v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
+ v = (v & ~0xf0f) | 0x100;
+ writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
+ }
/* Put MPSC in UART mode & enabel Tx/Rx egines */
- MPSC_WRITE(pi, mpsc, MPSC_MMCRL, 0x000004c4);
+ writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
/* No preamble, 16x divider, low-latency, */
- MPSC_WRITE(pi, mpsc, MPSC_MMCRH, 0x04400400);
+ writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
- MPSC_WRITE_M(pi, mpsc, MPSC_CHR_1, 0);
- MPSC_WRITE_M(pi, mpsc, MPSC_CHR_2, 0);
- MPSC_WRITE(pi, mpsc, MPSC_CHR_3, pi->mpsc_max_idle);
- MPSC_WRITE(pi, mpsc, MPSC_CHR_4, 0);
- MPSC_WRITE(pi, mpsc, MPSC_CHR_5, 0);
- MPSC_WRITE(pi, mpsc, MPSC_CHR_6, 0);
- MPSC_WRITE(pi, mpsc, MPSC_CHR_7, 0);
- MPSC_WRITE(pi, mpsc, MPSC_CHR_8, 0);
- MPSC_WRITE(pi, mpsc, MPSC_CHR_9, 0);
- MPSC_WRITE(pi, mpsc, MPSC_CHR_10, 0);
+ if (pi->mirror_regs) {
+ pi->MPSC_CHR_1_m = 0;
+ pi->MPSC_CHR_2_m = 0;
+ }
+ writel(0, pi->mpsc_base + MPSC_CHR_1);
+ writel(0, pi->mpsc_base + MPSC_CHR_2);
+ writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3);
+ writel(0, pi->mpsc_base + MPSC_CHR_4);
+ writel(0, pi->mpsc_base + MPSC_CHR_5);
+ writel(0, pi->mpsc_base + MPSC_CHR_6);
+ writel(0, pi->mpsc_base + MPSC_CHR_7);
+ writel(0, pi->mpsc_base + MPSC_CHR_8);
+ writel(0, pi->mpsc_base + MPSC_CHR_9);
+ writel(0, pi->mpsc_base + MPSC_CHR_10);
return;
}
@@ -338,19 +412,21 @@
static inline void
mpsc_enter_hunt(struct mpsc_port_info *pi)
{
- u32 v;
-
pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
- MPSC_MOD_FIELD_M(pi, mpsc, MPSC_CHR_2, 1, 31, 1);
-
- /* If erratum prevents reading CHR_2, just delay for a while */
- if (pi->mirror_regs)
+ if (pi->mirror_regs) {
+ writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH,
+ pi->mpsc_base + MPSC_CHR_2);
+ /* Erratum prevents reading CHR_2 so just delay for a while */
udelay(100);
- else
- do {
- v = MPSC_READ_M(pi, mpsc, MPSC_CHR_2);
- } while (v & MPSC_CHR_2_EH);
+ }
+ else {
+ writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
+ pi->mpsc_base + MPSC_CHR_2);
+
+ while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
+ udelay(10);
+ }
return;
}
@@ -358,16 +434,32 @@
static inline void
mpsc_freeze(struct mpsc_port_info *pi)
{
+ u32 v;
+
pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line);
- MPSC_MOD_FIELD_M(pi, mpsc, MPSC_MPCR, 1, 9, 1);
+ v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
+ readl(pi->mpsc_base + MPSC_MPCR);
+ v |= MPSC_MPCR_FRZ;
+
+ if (pi->mirror_regs)
+ pi->MPSC_MPCR_m = v;
+ writel(v, pi->mpsc_base + MPSC_MPCR);
return;
}
static inline void
mpsc_unfreeze(struct mpsc_port_info *pi)
{
- MPSC_MOD_FIELD_M(pi, mpsc, MPSC_MPCR, 1, 9, 0);
+ u32 v;
+
+ v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
+ readl(pi->mpsc_base + MPSC_MPCR);
+ v &= ~MPSC_MPCR_FRZ;
+
+ if (pi->mirror_regs)
+ pi->MPSC_MPCR_m = v;
+ writel(v, pi->mpsc_base + MPSC_MPCR);
pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
return;
@@ -376,29 +468,55 @@
static inline void
mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
{
+ u32 v;
+
pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len);
- MPSC_MOD_FIELD_M(pi, mpsc, MPSC_MPCR, 2, 12, len);
+ v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
+ readl(pi->mpsc_base + MPSC_MPCR);
+ v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12);
+
+ if (pi->mirror_regs)
+ pi->MPSC_MPCR_m = v;
+ writel(v, pi->mpsc_base + MPSC_MPCR);
return;
}
static inline void
mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
{
+ u32 v;
+
pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",
pi->port.line, len);
- MPSC_MOD_FIELD_M(pi, mpsc, MPSC_MPCR, 1, 14, len);
+ v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
+ readl(pi->mpsc_base + MPSC_MPCR);
+
+ v = (v & ~(1 << 14)) | ((len & 0x1) << 14);
+
+ if (pi->mirror_regs)
+ pi->MPSC_MPCR_m = v;
+ writel(v, pi->mpsc_base + MPSC_MPCR);
return;
}
static inline void
mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
{
+ u32 v;
+
pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p);
- MPSC_MOD_FIELD_M(pi, mpsc, MPSC_CHR_2, 2, 2, p); /* TPM */
- MPSC_MOD_FIELD_M(pi, mpsc, MPSC_CHR_2, 2, 18, p); /* RPM */
+ v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m :
+ readl(pi->mpsc_base + MPSC_CHR_2);
+
+ p &= 0x3;
+ v = (v & ~0xc000c) | (p << 18) | (p << 2);
+
+ if (pi->mirror_regs)
+ pi->MPSC_CHR_2_m = v;
+ writel(v, pi->mpsc_base + MPSC_CHR_2);
return;
}
@@ -560,8 +678,11 @@
dma_cache_sync((void *) pi->dma_region, MPSC_DMA_ALLOC_SIZE,
DMA_BIDIRECTIONAL);
- MPSC_CACHE_FLUSH(pi, pi->dma_region,
- pi->dma_region + MPSC_DMA_ALLOC_SIZE);
+#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
+ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
+ flush_dcache_range((ulong)pi->dma_region,
+ (ulong)pi->dma_region + MPSC_DMA_ALLOC_SIZE);
+#endif
return;
}
@@ -631,7 +752,11 @@
rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
- MPSC_CACHE_INVALIDATE(pi, (u32) rxre, (u32) rxre + MPSC_RXRE_SIZE);
+#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
+ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
+ invalidate_dcache_range((ulong)rxre,
+ (ulong)rxre + MPSC_RXRE_SIZE);
+#endif
/*
* Loop through Rx descriptors handling ones that have been completed.
@@ -651,7 +776,11 @@
bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
dma_cache_sync((void *) bp, MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
- MPSC_CACHE_INVALIDATE(pi, bp, bp + MPSC_RXBE_SIZE);
+#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
+ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
+ invalidate_dcache_range((ulong)bp,
+ (ulong)bp + MPSC_RXBE_SIZE);
+#endif
/*
* Other than for parity error, the manual provides little
@@ -716,20 +845,28 @@
SDMA_DESC_CMDSTAT_L);
wmb();
dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL);
- MPSC_CACHE_FLUSH(pi, (u32) rxre, (u32) rxre + MPSC_RXRE_SIZE);
+#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
+ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
+ flush_dcache_range((ulong)rxre,
+ (ulong)rxre + MPSC_RXRE_SIZE);
+#endif
/* Advance to next descriptor */
pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
rxre = (struct mpsc_rx_desc *)(pi->rxr +
(pi->rxr_posn * MPSC_RXRE_SIZE));
dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
- MPSC_CACHE_INVALIDATE(pi, (u32)rxre, (u32)rxre+MPSC_RXRE_SIZE);
+#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
+ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
+ invalidate_dcache_range((ulong)rxre,
+ (ulong)rxre + MPSC_RXRE_SIZE);
+#endif
rc = 1;
}
/* Restart rx engine, if its stopped */
- if ((MPSC_READ(pi, sdma, SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
+ if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
mpsc_start_rx(pi);
tty_flip_buffer_push(tty);
@@ -753,7 +890,11 @@
: 0));
wmb();
dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_BIDIRECTIONAL);
- MPSC_CACHE_FLUSH(pi, (u32) txre, (u32) txre + MPSC_TXRE_SIZE);
+#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
+ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
+ flush_dcache_range((ulong)txre,
+ (ulong)txre + MPSC_TXRE_SIZE);
+#endif
return;
}
@@ -798,7 +939,11 @@
return;
dma_cache_sync((void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL);
- MPSC_CACHE_FLUSH(pi, bp, bp + MPSC_TXBE_SIZE);
+#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
+ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
+ flush_dcache_range((ulong)bp,
+ (ulong)bp + MPSC_TXBE_SIZE);
+#endif
mpsc_setup_tx_desc(pi, i, 1);
/* Advance to next descriptor */
@@ -819,7 +964,11 @@
(pi->txr_tail * MPSC_TXRE_SIZE));
dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
- MPSC_CACHE_INVALIDATE(pi, (u32) txre, (u32)txre+MPSC_TXRE_SIZE);
+#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
+ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
+ invalidate_dcache_range((ulong)txre,
+ (ulong)txre + MPSC_TXRE_SIZE);
+#endif
while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
rc = 1;
@@ -834,8 +983,11 @@
(pi->txr_tail * MPSC_TXRE_SIZE));
dma_cache_sync((void *) txre, MPSC_TXRE_SIZE,
DMA_FROM_DEVICE);
- MPSC_CACHE_INVALIDATE(pi, (u32) txre,
- (u32) txre + MPSC_TXRE_SIZE);
+#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
+ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
+ invalidate_dcache_range((ulong)txre,
+ (ulong)txre + MPSC_TXRE_SIZE);
+#endif
}
mpsc_copy_tx_data(pi);
@@ -907,7 +1059,8 @@
ulong iflags;
spin_lock_irqsave(&pi->port.lock, iflags);
- status = MPSC_READ_M(pi, mpsc, MPSC_CHR_10);
+ status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m :
+ readl(pi->mpsc_base + MPSC_CHR_10);
spin_unlock_irqrestore(&pi->port.lock, iflags);
mflags = 0;
@@ -976,13 +1129,15 @@
mpsc_break_ctl(struct uart_port *port, int ctl)
{
struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
- ulong flags;
+ ulong flags;
+ u32 v;
+
+ v = ctl ? 0x00ff0000 : 0;
spin_lock_irqsave(&pi->port.lock, flags);
- if (ctl) /* Send as many BRK chars as we can */
- MPSC_WRITE_M(pi, mpsc, MPSC_CHR_1, 0x00ff0000);
- else /* Stop sending BRK chars */
- MPSC_WRITE_M(pi, mpsc, MPSC_CHR_1, 0);
+ if (pi->mirror_regs)
+ pi->MPSC_CHR_1_m = v;
+ writel(v, pi->mpsc_base + MPSC_CHR_1);
spin_unlock_irqrestore(&pi->port.lock, flags);
return;
@@ -1246,7 +1401,11 @@
}
dma_cache_sync((void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL);
- MPSC_CACHE_FLUSH(pi, bp, bp + MPSC_TXBE_SIZE);
+#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
+ if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
+ flush_dcache_range((ulong)bp,
+ (ulong)bp + MPSC_TXBE_SIZE);
+#endif
mpsc_setup_tx_desc(pi, i, 0);
pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
mpsc_sdma_start_tx(pi);
@@ -1339,7 +1498,7 @@
MPSC_ROUTING_BASE_ORDER)) && request_mem_region(r->start,
MPSC_ROUTING_REG_BLOCK_SIZE, "mpsc_routing_regs")) {
- mpsc_shared_regs.mpsc_routing_base = (u32) ioremap(r->start,
+ mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
MPSC_ROUTING_REG_BLOCK_SIZE);
mpsc_shared_regs.mpsc_routing_base_p = r->start;
}
@@ -1352,12 +1511,12 @@
MPSC_SDMA_INTR_BASE_ORDER)) && request_mem_region(r->start,
MPSC_SDMA_INTR_REG_BLOCK_SIZE, "sdma_intr_regs")) {
- mpsc_shared_regs.sdma_intr_base = (u32) ioremap(r->start,
+ mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
MPSC_SDMA_INTR_REG_BLOCK_SIZE);
mpsc_shared_regs.sdma_intr_base_p = r->start;
}
else {
- iounmap((void *)mpsc_shared_regs.mpsc_routing_base);
+ iounmap(mpsc_shared_regs.mpsc_routing_base);
release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
MPSC_ROUTING_REG_BLOCK_SIZE);
mpsc_resource_err("SDMA intr base");
@@ -1371,12 +1530,12 @@
mpsc_shared_unmap_regs(void)
{
if (!mpsc_shared_regs.mpsc_routing_base) {
- iounmap((void *)mpsc_shared_regs.mpsc_routing_base);
+ iounmap(mpsc_shared_regs.mpsc_routing_base);
release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
MPSC_ROUTING_REG_BLOCK_SIZE);
}
if (!mpsc_shared_regs.sdma_intr_base) {
- iounmap((void *)mpsc_shared_regs.sdma_intr_base);
+ iounmap(mpsc_shared_regs.sdma_intr_base);
release_mem_region(mpsc_shared_regs.sdma_intr_base_p,
MPSC_SDMA_INTR_REG_BLOCK_SIZE);
}
@@ -1394,21 +1553,20 @@
mpsc_shared_drv_probe(struct device *dev)
{
struct platform_device *pd = to_platform_device(dev);
- struct mpsc_shared_pd_dd *dd;
+ struct mpsc_shared_pdata *pdata;
int rc = -ENODEV;
if (pd->id == 0) {
if (!(rc = mpsc_shared_map_regs(pd))) {
- dd = (struct mpsc_shared_pd_dd *)
- dev_get_drvdata(dev);
+ pdata = (struct mpsc_shared_pdata *)dev->platform_data;
- mpsc_shared_regs.MPSC_MRR_m = dd->mrr_val;
- mpsc_shared_regs.MPSC_RCRR_m= dd->rcrr_val;
- mpsc_shared_regs.MPSC_TCRR_m= dd->tcrr_val;
+ mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
+ mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
+ mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val;
mpsc_shared_regs.SDMA_INTR_CAUSE_m =
- dd->intr_cause_val;
+ pdata->intr_cause_val;
mpsc_shared_regs.SDMA_INTR_MASK_m =
- dd->intr_mask_val;
+ pdata->intr_mask_val;
rc = 0;
}
@@ -1469,7 +1627,7 @@
if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER)) &&
request_mem_region(r->start, MPSC_REG_BLOCK_SIZE, "mpsc_regs")){
- pi->mpsc_base = (u32) ioremap(r->start, MPSC_REG_BLOCK_SIZE);
+ pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
pi->mpsc_base_p = r->start;
}
else {
@@ -1481,7 +1639,7 @@
MPSC_SDMA_BASE_ORDER)) && request_mem_region(r->start,
MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
- pi->sdma_base = (u32)ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
+ pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
pi->sdma_base_p = r->start;
}
else {
@@ -1493,7 +1651,7 @@
&& request_mem_region(r->start, MPSC_BRG_REG_BLOCK_SIZE,
"brg_regs")) {
- pi->brg_base = (u32) ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
+ pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
pi->brg_base_p = r->start;
}
else {
@@ -1508,15 +1666,15 @@
mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
{
if (!pi->mpsc_base) {
- iounmap((void *)pi->mpsc_base);
+ iounmap(pi->mpsc_base);
release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE);
}
if (!pi->sdma_base) {
- iounmap((void *)pi->sdma_base);
+ iounmap(pi->sdma_base);
release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE);
}
if (!pi->brg_base) {
- iounmap((void *)pi->brg_base);
+ iounmap(pi->brg_base);
release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE);
}
@@ -1535,35 +1693,35 @@
mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
struct platform_device *pd, int num)
{
- struct mpsc_pd_dd *dd;
+ struct mpsc_pdata *pdata;
- dd = (struct mpsc_pd_dd *)dev_get_drvdata(&pd->dev);
+ pdata = (struct mpsc_pdata *)pd->dev.platform_data;
- pi->port.uartclk = dd->brg_clk_freq;
+ pi->port.uartclk = pdata->brg_clk_freq;
pi->port.iotype = UPIO_MEM;
pi->port.line = num;
pi->port.type = PORT_MPSC;
pi->port.fifosize = MPSC_TXBE_SIZE;
- pi->port.membase = (char *)pi->mpsc_base;
- pi->port.mapbase = (ulong) pi->mpsc_base;
+ pi->port.membase = pi->mpsc_base;
+ pi->port.mapbase = (ulong)pi->mpsc_base;
pi->port.ops = &mpsc_pops;
- pi->mirror_regs = dd->mirror_regs;
- pi->cache_mgmt = dd->cache_mgmt;
- pi->brg_can_tune = dd->brg_can_tune;
- pi->brg_clk_src = dd->brg_clk_src;
- pi->mpsc_max_idle = dd->max_idle;
- pi->default_baud = dd->default_baud;
- pi->default_bits = dd->default_bits;
- pi->default_parity = dd->default_parity;
- pi->default_flow = dd->default_flow;
+ pi->mirror_regs = pdata->mirror_regs;
+ pi->cache_mgmt = pdata->cache_mgmt;
+ pi->brg_can_tune = pdata->brg_can_tune;
+ pi->brg_clk_src = pdata->brg_clk_src;
+ pi->mpsc_max_idle = pdata->max_idle;
+ pi->default_baud = pdata->default_baud;
+ pi->default_bits = pdata->default_bits;
+ pi->default_parity = pdata->default_parity;
+ pi->default_flow = pdata->default_flow;
/* Initial values of mirrored regs */
- pi->MPSC_CHR_1_m = dd->chr_1_val;
- pi->MPSC_CHR_2_m = dd->chr_2_val;
- pi->MPSC_CHR_10_m = dd->chr_10_val;
- pi->MPSC_MPCR_m = dd->mpcr_val;
- pi->BRG_BCR_m = dd->bcr_val;
+ pi->MPSC_CHR_1_m = pdata->chr_1_val;
+ pi->MPSC_CHR_2_m = pdata->chr_2_val;
+ pi->MPSC_CHR_10_m = pdata->chr_10_val;
+ pi->MPSC_MPCR_m = pdata->mpcr_val;
+ pi->BRG_BCR_m = pdata->bcr_val;
pi->shared_regs = &mpsc_shared_regs;
diff -Nru a/drivers/serial/mpsc.h b/drivers/serial/mpsc.h
--- a/drivers/serial/mpsc.h 2005-01-25 17:28:43 -07:00
+++ b/drivers/serial/mpsc.h 2005-01-25 17:28:43 -07:00
@@ -22,9 +22,11 @@
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/serial.h>
+#include <linux/serial_core.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
+#include <linux/mv643xx.h>
#include <asm/io.h>
#include <asm/irq.h>
@@ -33,8 +35,7 @@
#define SUPPORT_SYSRQ
#endif
-#include <linux/serial_core.h>
-#include "mpsc_defs.h"
+#define MPSC_NUM_CTLRS 2
/*
* Descriptors and buffers must be cache line aligned.
@@ -79,11 +80,11 @@
* between the two MPSC controllers. This struct contains those shared regs.
*/
struct mpsc_shared_regs {
- u32 mpsc_routing_base_p;
- u32 sdma_intr_base_p;
+ phys_addr_t mpsc_routing_base_p;
+ phys_addr_t sdma_intr_base_p;
- u32 mpsc_routing_base;
- u32 sdma_intr_base;
+ void *mpsc_routing_base;
+ void *sdma_intr_base;
u32 MPSC_MRR_m;
u32 MPSC_RCRR_m;
@@ -114,14 +115,14 @@
int default_flow;
/* Physical addresses of various blocks of registers (from platform) */
- u32 mpsc_base_p;
- u32 sdma_base_p;
- u32 brg_base_p;
+ phys_addr_t mpsc_base_p;
+ phys_addr_t sdma_base_p;
+ phys_addr_t brg_base_p;
/* Virtual addresses of various blocks of registers (from platform) */
- u32 mpsc_base;
- u32 sdma_base;
- u32 brg_base;
+ void *mpsc_base;
+ void *sdma_base;
+ void *brg_base;
/* Descriptor ring and buffer allocations */
void *dma_region;
@@ -149,135 +150,6 @@
struct mpsc_shared_regs *shared_regs;
};
-#if defined(CONFIG_PPC32)
-
-#if defined(CONFIG_NOT_COHERENT_CACHE)
-/* No-ops when coherency is off b/c dma_cache_sync() does that work */
-#define MPSC_CACHE_INVALIDATE(pi, s, e)
-#define MPSC_CACHE_FLUSH(pi, s, e)
-#else /* defined(CONFIG_NOT_COHERENT_CACHE) */
-/* Coherency is on so dma_cache_sync() is no-op so must do manually */
-#define MPSC_CACHE_INVALIDATE(pi, s, e) { \
- if (pi->cache_mgmt) { \
- invalidate_dcache_range((ulong)s, (ulong)e); \
- } \
-}
-
-#define MPSC_CACHE_FLUSH(pi, s, e) { \
- if (pi->cache_mgmt) { \
- flush_dcache_range((ulong)s, (ulong)e); \
- } \
-}
-#endif /* defined(CONFIG_NOT_COHERENT_CACHE) */
-
-#else /* defined(CONFIG_PPC32) */
-/* Other architectures need to fill this in */
-#define MPSC_CACHE_INVALIDATE(pi, s, e) BUG()
-#define MPSC_CACHE_FLUSH(pi, s, e) BUG()
-#endif /* defined(CONFIG_PPC32) */
-
-/*
- * 'MASK_INSERT' takes the low-order 'n' bits of 'i', shifts it 'b' bits to
- * the left, and inserts it into the target 't'. The corresponding bits in
- * 't' will have been cleared before the bits in 'i' are inserted.
- */
-#ifdef CONFIG_PPC32
-#define MASK_INSERT(t, i, n, b) ({ \
- u32 rval = (t); \
- __asm__ __volatile__( \
- "rlwimi %0,%2,%4,32-(%3+%4),31-%4\n" \
- : "=r" (rval) \
- : "0" (rval), "r" (i), "i" (n), "i" (b)); \
- rval; \
-})
-#else
-/* These macros are really just examples. Feel free to change them --MAG */
-#define GEN_MASK(n, b) \
-({ \
- u32 m, sl, sr; \
- sl = 32 - (n); \
- sr = sl - (b); \
- m = (0xffffffff << sl) >> sr; \
-})
-
-#define MASK_INSERT(t, i, n, b) \
-({ \
- u32 m, rval = (t); \
- m = GEN_MASK((n), (b)); \
- rval &= ~m; \
- rval |= (((i) << (b)) & m); \
-})
-#endif
-
-/* I/O macros for regs that you can read */
-#define MPSC_READ(pi, unit, offset) \
- readl((volatile void *)((pi)->unit##_base + (offset)))
-
-#define MPSC_WRITE(pi, unit, offset, v) \
- writel(v, (volatile void *)((pi)->unit##_base + (offset)))
-
-#define MPSC_MOD_FIELD(pi, unit, offset, num_bits, shift, val) \
-{ \
- u32 v; \
- v = readl((volatile void *)((pi)->unit##_base + (offset))); \
- writel(MASK_INSERT(v,val,num_bits,shift), \
- (volatile void *)((pi)->unit##_base+(offset))); \
-}
-
-/* Macros for regs with erratum that are not shared between MPSC ctlrs */
-#define MPSC_READ_M(pi, unit, offset) \
-({ \
- u32 v; \
- if ((pi)->mirror_regs) v = (pi)->offset##_m; \
- else v = readl((volatile void *)((pi)->unit##_base + (offset)));\
- v; \
-})
-
-#define MPSC_WRITE_M(pi, unit, offset, v) \
-({ \
- if ((pi)->mirror_regs) (pi)->offset##_m = v; \
- writel(v, (volatile void *)((pi)->unit##_base + (offset))); \
-})
-
-#define MPSC_MOD_FIELD_M(pi, unit, offset, num_bits, shift, val) \
-({ \
- u32 v; \
- if ((pi)->mirror_regs) v = (pi)->offset##_m; \
- else v = readl((volatile void *)((pi)->unit##_base + (offset)));\
- v = MASK_INSERT(v, val, num_bits, shift); \
- if ((pi)->mirror_regs) (pi)->offset##_m = v; \
- writel(v, (volatile void *)((pi)->unit##_base + (offset))); \
-})
-
-/* Macros for regs with erratum that are shared between MPSC ctlrs */
-#define MPSC_READ_S(pi, unit, offset) \
-({ \
- u32 v; \
- if ((pi)->mirror_regs) v = (pi)->shared_regs->offset##_m; \
- else v = readl((volatile void *)((pi)->shared_regs->unit##_base + \
- (offset))); \
- v; \
-})
-
-#define MPSC_WRITE_S(pi, unit, offset, v) \
-({ \
- if ((pi)->mirror_regs) (pi)->shared_regs->offset##_m = v; \
- writel(v, (volatile void *)((pi)->shared_regs->unit##_base + \
- (offset))); \
-})
-
-#define MPSC_MOD_FIELD_S(pi, unit, offset, num_bits, shift, val) \
-({ \
- u32 v; \
- if ((pi)->mirror_regs) v = (pi)->shared_regs->offset##_m; \
- else v = readl((volatile void *)((pi)->shared_regs->unit##_base + \
- (offset))); \
- v = MASK_INSERT(v, val, num_bits, shift); \
- if ((pi)->mirror_regs) (pi)->shared_regs->offset##_m = v; \
- writel(v, (volatile void *)((pi)->shared_regs->unit##_base + \
- (offset))); \
-})
-
/* Hooks to platform-specific code */
int mpsc_platform_register_driver(void);
void mpsc_platform_unregister_driver(void);
@@ -285,5 +157,133 @@
/* Hooks back in to mpsc common to be called by platform-specific code */
struct mpsc_port_info *mpsc_device_probe(int index);
struct mpsc_port_info *mpsc_device_remove(int index);
+
+/*
+ *****************************************************************************
+ *
+ * Multi-Protocol Serial Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+/* Main Configuratino Register Offsets */
+#define MPSC_MMCRL 0x0000
+#define MPSC_MMCRH 0x0004
+#define MPSC_MPCR 0x0008
+#define MPSC_CHR_1 0x000c
+#define MPSC_CHR_2 0x0010
+#define MPSC_CHR_3 0x0014
+#define MPSC_CHR_4 0x0018
+#define MPSC_CHR_5 0x001c
+#define MPSC_CHR_6 0x0020
+#define MPSC_CHR_7 0x0024
+#define MPSC_CHR_8 0x0028
+#define MPSC_CHR_9 0x002c
+#define MPSC_CHR_10 0x0030
+#define MPSC_CHR_11 0x0034
+
+#define MPSC_MPCR_FRZ (1 << 9)
+#define MPSC_MPCR_CL_5 0
+#define MPSC_MPCR_CL_6 1
+#define MPSC_MPCR_CL_7 2
+#define MPSC_MPCR_CL_8 3
+#define MPSC_MPCR_SBL_1 0
+#define MPSC_MPCR_SBL_2 1
+
+#define MPSC_CHR_2_TEV (1<<1)
+#define MPSC_CHR_2_TA (1<<7)
+#define MPSC_CHR_2_TTCS (1<<9)
+#define MPSC_CHR_2_REV (1<<17)
+#define MPSC_CHR_2_RA (1<<23)
+#define MPSC_CHR_2_CRD (1<<25)
+#define MPSC_CHR_2_EH (1<<31)
+#define MPSC_CHR_2_PAR_ODD 0
+#define MPSC_CHR_2_PAR_SPACE 1
+#define MPSC_CHR_2_PAR_EVEN 2
+#define MPSC_CHR_2_PAR_MARK 3
+
+/* MPSC Signal Routing */
+#define MPSC_MRR 0x0000
+#define MPSC_RCRR 0x0004
+#define MPSC_TCRR 0x0008
+
+/*
+ *****************************************************************************
+ *
+ * Serial DMA Controller Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define SDMA_SDC 0x0000
+#define SDMA_SDCM 0x0008
+#define SDMA_RX_DESC 0x0800
+#define SDMA_RX_BUF_PTR 0x0808
+#define SDMA_SCRDP 0x0810
+#define SDMA_TX_DESC 0x0c00
+#define SDMA_SCTDP 0x0c10
+#define SDMA_SFTDP 0x0c14
+
+#define SDMA_DESC_CMDSTAT_PE (1<<0)
+#define SDMA_DESC_CMDSTAT_CDL (1<<1)
+#define SDMA_DESC_CMDSTAT_FR (1<<3)
+#define SDMA_DESC_CMDSTAT_OR (1<<6)
+#define SDMA_DESC_CMDSTAT_BR (1<<9)
+#define SDMA_DESC_CMDSTAT_MI (1<<10)
+#define SDMA_DESC_CMDSTAT_A (1<<11)
+#define SDMA_DESC_CMDSTAT_AM (1<<12)
+#define SDMA_DESC_CMDSTAT_CT (1<<13)
+#define SDMA_DESC_CMDSTAT_C (1<<14)
+#define SDMA_DESC_CMDSTAT_ES (1<<15)
+#define SDMA_DESC_CMDSTAT_L (1<<16)
+#define SDMA_DESC_CMDSTAT_F (1<<17)
+#define SDMA_DESC_CMDSTAT_P (1<<18)
+#define SDMA_DESC_CMDSTAT_EI (1<<23)
+#define SDMA_DESC_CMDSTAT_O (1<<31)
+
+#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
+ SDMA_DESC_CMDSTAT_EI)
+
+#define SDMA_SDC_RFT (1<<0)
+#define SDMA_SDC_SFM (1<<1)
+#define SDMA_SDC_BLMR (1<<6)
+#define SDMA_SDC_BLMT (1<<7)
+#define SDMA_SDC_POVR (1<<8)
+#define SDMA_SDC_RIFB (1<<9)
+
+#define SDMA_SDCM_ERD (1<<7)
+#define SDMA_SDCM_AR (1<<15)
+#define SDMA_SDCM_STD (1<<16)
+#define SDMA_SDCM_TXD (1<<23)
+#define SDMA_SDCM_AT (1<<31)
+
+#define SDMA_0_CAUSE_RXBUF (1<<0)
+#define SDMA_0_CAUSE_RXERR (1<<1)
+#define SDMA_0_CAUSE_TXBUF (1<<2)
+#define SDMA_0_CAUSE_TXEND (1<<3)
+#define SDMA_1_CAUSE_RXBUF (1<<8)
+#define SDMA_1_CAUSE_RXERR (1<<9)
+#define SDMA_1_CAUSE_TXBUF (1<<10)
+#define SDMA_1_CAUSE_TXEND (1<<11)
+
+#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
+ SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
+#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
+ SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
+
+/* SDMA Interrupt registers */
+#define SDMA_INTR_CAUSE 0x0000
+#define SDMA_INTR_MASK 0x0080
+
+/*
+ *****************************************************************************
+ *
+ * Baud Rate Generator Interface Registers
+ *
+ *****************************************************************************
+ */
+
+#define BRG_BCR 0x0000
+#define BRG_BTR 0x0004
#endif /* __MPSC_H__ */
diff -Nru a/drivers/serial/mpsc_defs.h b/drivers/serial/mpsc_defs.h
--- a/drivers/serial/mpsc_defs.h 2005-01-25 17:28:43 -07:00
+++ /dev/null Wed Dec 31 16:00:00 196900
@@ -1,146 +0,0 @@
-/*
- * drivers/serial/mpsc_defs.h
- *
- * Register definitions for the Marvell Multi-Protocol Serial Controller (MPSC),
- * Serial DMA Controller (SDMA), and Baud Rate Generator (BRG).
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2004 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __MPSC_DEFS_H__
-#define __MPSC_DEFS_H__
-
-#define MPSC_NUM_CTLRS 2
-
-/*
- *****************************************************************************
- *
- * Multi-Protocol Serial Controller Interface Registers
- *
- *****************************************************************************
- */
-
-/* Main Configuratino Register Offsets */
-#define MPSC_MMCRL 0x0000
-#define MPSC_MMCRH 0x0004
-#define MPSC_MPCR 0x0008
-#define MPSC_CHR_1 0x000c
-#define MPSC_CHR_2 0x0010
-#define MPSC_CHR_3 0x0014
-#define MPSC_CHR_4 0x0018
-#define MPSC_CHR_5 0x001c
-#define MPSC_CHR_6 0x0020
-#define MPSC_CHR_7 0x0024
-#define MPSC_CHR_8 0x0028
-#define MPSC_CHR_9 0x002c
-#define MPSC_CHR_10 0x0030
-#define MPSC_CHR_11 0x0034
-
-#define MPSC_MPCR_CL_5 0
-#define MPSC_MPCR_CL_6 1
-#define MPSC_MPCR_CL_7 2
-#define MPSC_MPCR_CL_8 3
-#define MPSC_MPCR_SBL_1 0
-#define MPSC_MPCR_SBL_2 3
-
-#define MPSC_CHR_2_TEV (1<<1)
-#define MPSC_CHR_2_TA (1<<7)
-#define MPSC_CHR_2_TTCS (1<<9)
-#define MPSC_CHR_2_REV (1<<17)
-#define MPSC_CHR_2_RA (1<<23)
-#define MPSC_CHR_2_CRD (1<<25)
-#define MPSC_CHR_2_EH (1<<31)
-#define MPSC_CHR_2_PAR_ODD 0
-#define MPSC_CHR_2_PAR_SPACE 1
-#define MPSC_CHR_2_PAR_EVEN 2
-#define MPSC_CHR_2_PAR_MARK 3
-
-/* MPSC Signal Routing */
-#define MPSC_MRR 0x0000
-#define MPSC_RCRR 0x0004
-#define MPSC_TCRR 0x0008
-
-/*
- *****************************************************************************
- *
- * Serial DMA Controller Interface Registers
- *
- *****************************************************************************
- */
-
-#define SDMA_SDC 0x0000
-#define SDMA_SDCM 0x0008
-#define SDMA_RX_DESC 0x0800
-#define SDMA_RX_BUF_PTR 0x0808
-#define SDMA_SCRDP 0x0810
-#define SDMA_TX_DESC 0x0c00
-#define SDMA_SCTDP 0x0c10
-#define SDMA_SFTDP 0x0c14
-
-#define SDMA_DESC_CMDSTAT_PE (1<<0)
-#define SDMA_DESC_CMDSTAT_CDL (1<<1)
-#define SDMA_DESC_CMDSTAT_FR (1<<3)
-#define SDMA_DESC_CMDSTAT_OR (1<<6)
-#define SDMA_DESC_CMDSTAT_BR (1<<9)
-#define SDMA_DESC_CMDSTAT_MI (1<<10)
-#define SDMA_DESC_CMDSTAT_A (1<<11)
-#define SDMA_DESC_CMDSTAT_AM (1<<12)
-#define SDMA_DESC_CMDSTAT_CT (1<<13)
-#define SDMA_DESC_CMDSTAT_C (1<<14)
-#define SDMA_DESC_CMDSTAT_ES (1<<15)
-#define SDMA_DESC_CMDSTAT_L (1<<16)
-#define SDMA_DESC_CMDSTAT_F (1<<17)
-#define SDMA_DESC_CMDSTAT_P (1<<18)
-#define SDMA_DESC_CMDSTAT_EI (1<<23)
-#define SDMA_DESC_CMDSTAT_O (1<<31)
-
-#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O | \
- SDMA_DESC_CMDSTAT_EI)
-
-#define SDMA_SDC_RFT (1<<0)
-#define SDMA_SDC_SFM (1<<1)
-#define SDMA_SDC_BLMR (1<<6)
-#define SDMA_SDC_BLMT (1<<7)
-#define SDMA_SDC_POVR (1<<8)
-#define SDMA_SDC_RIFB (1<<9)
-
-#define SDMA_SDCM_ERD (1<<7)
-#define SDMA_SDCM_AR (1<<15)
-#define SDMA_SDCM_STD (1<<16)
-#define SDMA_SDCM_TXD (1<<23)
-#define SDMA_SDCM_AT (1<<31)
-
-#define SDMA_0_CAUSE_RXBUF (1<<0)
-#define SDMA_0_CAUSE_RXERR (1<<1)
-#define SDMA_0_CAUSE_TXBUF (1<<2)
-#define SDMA_0_CAUSE_TXEND (1<<3)
-#define SDMA_1_CAUSE_RXBUF (1<<8)
-#define SDMA_1_CAUSE_RXERR (1<<9)
-#define SDMA_1_CAUSE_TXBUF (1<<10)
-#define SDMA_1_CAUSE_TXEND (1<<11)
-
-#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
- SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
-#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
- SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
-
-/* SDMA Interrupt registers */
-#define SDMA_INTR_CAUSE 0x0000
-#define SDMA_INTR_MASK 0x0080
-
-/*
- *****************************************************************************
- *
- * Baud Rate Generator Interface Registers
- *
- *****************************************************************************
- */
-
-#define BRG_BCR 0x0000
-#define BRG_BTR 0x0004
-
-#endif /*__MPSC_DEFS_H__ */
^ permalink raw reply
* [PATCH] katana update
From: Mark A. Greer @ 2005-01-26 0:48 UTC (permalink / raw)
To: akpm; +Cc: Embedded PPC Linux list
[-- Attachment #1: Type: text/plain, Size: 251 bytes --]
Hi Andrew,
This patch updates support for the katana 750i, 752i, and 3750.
It:
- supports more bus frequencies
- uses platform_notify hook to update platform_data entries
- does some misc cleanup
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
--
[-- Attachment #2: katana.patch --]
[-- Type: text/plain, Size: 11507 bytes --]
diff -Nru a/arch/ppc/configs/katana_defconfig b/arch/ppc/configs/katana_defconfig
--- a/arch/ppc/configs/katana_defconfig 2005-01-25 17:44:58 -07:00
+++ b/arch/ppc/configs/katana_defconfig 2005-01-25 17:44:58 -07:00
@@ -1,11 +1,12 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.10-rc2
-# Fri Nov 19 15:17:10 2004
+# Linux kernel version: 2.6.11-rc2
+# Tue Jan 25 16:31:13 2005
#
CONFIG_MMU=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_HAVE_DEC_LOCK=y
CONFIG_PPC=y
CONFIG_PPC32=y
@@ -79,8 +80,10 @@
# CONFIG_APUS is not set
CONFIG_KATANA=y
# CONFIG_WILLOW is not set
+# CONFIG_CPCI690 is not set
# CONFIG_PCORE is not set
# CONFIG_POWERPMC250 is not set
+# CONFIG_CHESTNUT is not set
# CONFIG_SPRUCE is not set
# CONFIG_EV64260 is not set
# CONFIG_LOPEC is not set
@@ -100,6 +103,7 @@
# CONFIG_RPX8260 is not set
# CONFIG_TQM8260 is not set
# CONFIG_ADS8272 is not set
+# CONFIG_PQ2FADS is not set
# CONFIG_LITE5200 is not set
CONFIG_MV64360=y
CONFIG_MV64X60=y
@@ -127,6 +131,15 @@
CONFIG_PCI_NAMES=y
#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PC-card bridges
+#
+
+#
# Advanced setup
#
CONFIG_ADVANCED_OPTIONS=y
@@ -153,6 +166,7 @@
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
#
# Memory Technology Devices (MTD)
@@ -176,11 +190,13 @@
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_SX8 is not set
CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
@@ -194,6 +210,7 @@
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
+# CONFIG_ATA_OVER_ETH is not set
#
# ATA/ATAPI/MFM/RLL support
@@ -449,6 +466,10 @@
#
# Non-8250 serial port support
#
+CONFIG_SERIAL_MPSC=y
+CONFIG_SERIAL_MPSC_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
@@ -510,6 +531,7 @@
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Sound
@@ -524,11 +546,25 @@
CONFIG_USB_ARCH_HAS_OHCI=y
#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
+#
+
+#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
# File systems
#
CONFIG_EXT2_FS=y
@@ -649,3 +685,7 @@
# Cryptographic options
#
# CONFIG_CRYPTO is not set
+
+#
+# Hardware crypto devices
+#
diff -Nru a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c
--- a/arch/ppc/platforms/katana.c 2005-01-25 17:44:58 -07:00
+++ b/arch/ppc/platforms/katana.c 2005-01-25 17:44:58 -07:00
@@ -8,9 +8,9 @@
* Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
* Based on code done by - Mark A. Greer <mgreer@mvista.com>
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/*
@@ -194,6 +194,14 @@
bd_cfg_0 = in_8((volatile char *)(cpld_base + KATANA_CPLD_BD_CFG_0));
switch (bd_cfg_0 & KATANA_CPLD_BD_CFG_0_SYSCLK_MASK) {
+ case KATANA_CPLD_BD_CFG_0_SYSCLK_200:
+ return 200000000;
+ break;
+
+ case KATANA_CPLD_BD_CFG_0_SYSCLK_166:
+ return 166666666;
+ break;
+
case KATANA_CPLD_BD_CFG_0_SYSCLK_133:
return 133333333;
break;
@@ -234,7 +242,7 @@
/* Config GPP intr ctlr to respond to level trigger */
mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
- /* XXXX Erranum FEr PCI-#8 */
+ /* Erranum FEr PCI-#8 */
mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9));
mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9));
@@ -392,7 +400,7 @@
/* Lookup PCI host bridges */
if (mv64x60_init(&bh, &si))
- printk("Bridge initialization failed.\n");
+ printk(KERN_WARNING "Bridge initialization failed.\n");
pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
ppc_md.pci_swizzle = common_swizzle;
@@ -433,7 +441,7 @@
* avoid dirty data in cache
*/
if (PVR_REV(mfspr(PVR)) == 0x0200) {
- printk("DD2.0 detected. Setting L2 cache"
+ printk(KERN_INFO "DD2.0 detected. Setting L2 cache"
"to Writethrough mode\n");
_set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2WT);
}
@@ -447,83 +455,96 @@
katana_setup_peripherals();
katana_enable_ipmi();
- printk("Artesyn Communication Products, LLC - Katana(TM)\n");
+ printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n");
if (ppc_md.progress)
ppc_md.progress("katana_setup_arch: exit", 0);
return;
}
-/* Platform device data fixup routine. */
-static int __init
-katana_fixup_pd(void)
-{
- struct list_head *entry;
- struct platform_device *pd;
- struct device *dev;
+/* Platform device data fixup routines. */
#if defined(CONFIG_SERIAL_MPSC)
- struct mpsc_pd_dd *dd;
+static void __init
+katana_fixup_mpsc_pdata(struct platform_device *pdev)
+{
+ struct mpsc_pdata *pdata;
+
+ pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
+
+ pdata->max_idle = 40;
+ pdata->default_baud = KATANA_DEFAULT_BAUD;
+ pdata->brg_clk_src = KATANA_MPSC_CLK_SRC;
+ pdata->brg_clk_freq = KATANA_MPSC_CLK_FREQ;
+
+ return;
+}
#endif
+
#if defined(CONFIG_MV643XX_ETH)
- struct mv64xxx_eth_pd_dd *eth_dd;
+static void __init
+katana_fixup_eth_pdata(struct platform_device *pdev)
+{
+ struct mv64xxx_eth_platform_data *eth_pd;
static u16 phy_addr[] = {
KATANA_ETH0_PHY_ADDR,
KATANA_ETH1_PHY_ADDR,
KATANA_ETH2_PHY_ADDR,
};
- struct resource *rx_r;
- struct resource *tx_r;
- int rx_size = KATANA_ETH_RX_QUEUE_SIZE * ETH_DESC_SIZE;
- int tx_size = KATANA_ETH_TX_QUEUE_SIZE * ETH_DESC_SIZE;
-#endif
+ int rx_size = KATANA_ETH_RX_QUEUE_SIZE * MV64340_ETH_DESC_SIZE;
+ int tx_size = KATANA_ETH_TX_QUEUE_SIZE * MV64340_ETH_DESC_SIZE;
- list_for_each(entry, &platform_bus_type.devices.list) {
- dev = container_of(entry, struct device, bus_list);
- pd = container_of(dev, struct platform_device, dev);
+ eth_pd = pdev->dev.platform_data;
+ eth_pd->force_phy_addr = 1;
+ eth_pd->phy_addr = phy_addr[pdev->id];
+ eth_pd->tx_queue_size = KATANA_ETH_TX_QUEUE_SIZE;
+ eth_pd->rx_queue_size = KATANA_ETH_RX_QUEUE_SIZE;
+ eth_pd->tx_sram_addr = mv643xx_sram_alloc(tx_size);
-#if defined(CONFIG_SERIAL_MPSC)
- if (!strncmp(pd->name, MPSC_CTLR_NAME, BUS_ID_SIZE)) {
- dd = (struct mpsc_pd_dd *)dev_get_drvdata(&pd->dev);
+ if (eth_pd->tx_sram_addr)
+ eth_pd->tx_sram_size = tx_size;
+ else
+ printk(KERN_ERR "mv643xx_sram_alloc failed\n");
- dd->max_idle = 40; /* XXXX what should be? */
- dd->default_baud = KATANA_DEFAULT_BAUD;
- dd->brg_clk_src = KATANA_MPSC_CLK_SRC;
- dd->brg_clk_freq = KATANA_MPSC_CLK_FREQ;
- }
+ eth_pd->rx_sram_addr = mv643xx_sram_alloc(rx_size);
+ if (eth_pd->rx_sram_addr)
+ eth_pd->rx_sram_size = rx_size;
+ else
+ printk(KERN_ERR "mv643xx_sram_alloc failed\n");
+}
+#endif
+
+static int __init
+katana_platform_notify(struct device *dev)
+{
+ static struct {
+ char *bus_id;
+ void ((*rtn)(struct platform_device *pdev));
+ } dev_map[] = {
+#if defined(CONFIG_SERIAL_MPSC)
+ { MPSC_CTLR_NAME "0", katana_fixup_mpsc_pdata },
+ { MPSC_CTLR_NAME "1", katana_fixup_mpsc_pdata },
#endif
#if defined(CONFIG_MV643XX_ETH)
- if (!strncmp(pd->name, MV64XXX_ETH_NAME, BUS_ID_SIZE)) {
- eth_dd = (struct mv64xxx_eth_pd_dd *)
- dev_get_drvdata(&pd->dev);
- eth_dd->phy_addr = phy_addr[pd->id];
- eth_dd->port_config = KATANA_ETH_PORT_CONFIG_VALUE;
- eth_dd->port_config_extend =
- KATANA_ETH_PORT_CONFIG_EXTEND_VALUE;
- eth_dd->port_sdma_config =
- KATANA_ETH_PORT_SDMA_CONFIG_VALUE;
- eth_dd->port_serial_control =
- KATANA_ETH_PORT_SERIAL_CONTROL_VALUE;
- eth_dd->tx_queue_size = KATANA_ETH_TX_QUEUE_SIZE;
- eth_dd->rx_queue_size = KATANA_ETH_RX_QUEUE_SIZE;
-
- rx_r = &pd->resource[5];
- rx_r->start = KATANA_INTERNAL_SRAM_BASE +
- (rx_size + tx_size) * pd->id;
- rx_r->end = rx_r->start + rx_size - 1;
- rx_r->flags = IORESOURCE_MEM;
-
- tx_r = &pd->resource[6];
- tx_r->start = rx_r->start + rx_size;
- tx_r->end = tx_r->start + tx_size - 1;
- tx_r->flags = IORESOURCE_MEM;
- }
+ { MV64XXX_ETH_NAME "0", katana_fixup_eth_pdata },
+ { MV64XXX_ETH_NAME "1", katana_fixup_eth_pdata },
+ { MV64XXX_ETH_NAME "2", katana_fixup_eth_pdata },
#endif
- }
+ };
+ struct platform_device *pdev;
+ int i;
+
+ if (dev && dev->bus_id)
+ for (i=0; i<ARRAY_SIZE(dev_map); i++)
+ if (!strncmp(dev->bus_id, dev_map[i].bus_id,
+ BUS_ID_SIZE)) {
+
+ pdev = container_of(dev,
+ struct platform_device, dev);
+ dev_map[i].rtn(pdev);
+ }
return 0;
}
-subsys_initcall(katana_fixup_pd);
-
static void
katana_restart(char *cmd)
{
@@ -595,7 +616,7 @@
freq = katana_bus_freq() / 4;
- printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
+ printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
freq / 1000000, freq % 1000000);
tb_ticks_per_jiffy = freq / HZ;
@@ -654,7 +675,10 @@
mv64x60_progress_init(KATANA_BRIDGE_REG_BASE);
#endif
- katana_set_bat(); /* Need for katana_find_end_of_memory and progress */
+#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
+ platform_notify = katana_platform_notify;
+#endif
+ katana_set_bat(); /* Need for katana_find_end_of_memory and progress */
return;
}
diff -Nru a/arch/ppc/platforms/katana.h b/arch/ppc/platforms/katana.h
--- a/arch/ppc/platforms/katana.h 2005-01-25 17:44:58 -07:00
+++ b/arch/ppc/platforms/katana.h 2005-01-25 17:44:58 -07:00
@@ -8,9 +8,9 @@
* Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
* Based on code done by Mark A. Greer <mgreer@mvista.com>
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
@@ -107,6 +107,8 @@
#define KATANA_CPLD_RST_CMD_HR 0x01
#define KATANA_CPLD_BD_CFG_0_SYSCLK_MASK 0xc0
+#define KATANA_CPLD_BD_CFG_0_SYSCLK_200 0x00
+#define KATANA_CPLD_BD_CFG_0_SYSCLK_166 0x80
#define KATANA_CPLD_BD_CFG_0_SYSCLK_133 0xc0
#define KATANA_CPLD_BD_CFG_0_SYSCLK_100 0x40
@@ -170,8 +172,8 @@
#define KATANA_PRODUCT_ID_750i 0x02
#define KATANA_PRODUCT_ID_752i 0x04
-#define KATANA_ETH_TX_QUEUE_SIZE 1050
-#define KATANA_ETH_RX_QUEUE_SIZE 450
+#define KATANA_ETH_TX_QUEUE_SIZE 800
+#define KATANA_ETH_RX_QUEUE_SIZE 400
#define KATANA_ETH_PORT_CONFIG_VALUE \
ETH_UNICAST_NORMAL_MODE | \
^ permalink raw reply
* [PATCH][PPC32] ev64260 update
From: Mark A. Greer @ 2005-01-26 0:54 UTC (permalink / raw)
To: akpm; +Cc: Embedded PPC Linux list
[-- Attachment #1: Type: text/plain, Size: 307 bytes --]
Hello again, Andrew.
This patch updates the support for the ev64260 eval platform from Marvell.
It:
- uses the platform_notify hook to update platform_data
- fixes a bug where a window to a device is disabled instead of enabled
- does some misc fixups
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
--
[-- Attachment #2: ev64260.patch --]
[-- Type: text/plain, Size: 4760 bytes --]
diff -Nru a/arch/ppc/boot/simple/misc-ev64260.S b/arch/ppc/boot/simple/misc-ev64260.S
--- a/arch/ppc/boot/simple/misc-ev64260.S 2005-01-25 17:50:29 -07:00
+++ b/arch/ppc/boot/simple/misc-ev64260.S 2005-01-25 17:50:29 -07:00
@@ -6,12 +6,10 @@
*
* Author: Mark Greer <mgreer@mvista.com>
*
- * Copyright 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
+ * 2001 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
*/
#include <asm/ppc_asm.h>
diff -Nru a/arch/ppc/platforms/ev64260.c b/arch/ppc/platforms/ev64260.c
--- a/arch/ppc/platforms/ev64260.c 2005-01-25 17:50:29 -07:00
+++ b/arch/ppc/platforms/ev64260.c 2005-01-25 17:50:29 -07:00
@@ -294,7 +294,7 @@
/* Lookup PCI host bridges */
if (mv64x60_init(&bh, &si))
- printk("Bridge initialization failed.\n");
+ printk(KERN_ERR "Bridge initialization failed.\n");
pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
ppc_md.pci_swizzle = common_swizzle;
@@ -337,7 +337,8 @@
#endif
if (early_serial_setup(&port) != 0)
- printk("Early serial init of port 0 failed\n");
+ printk(KERN_WARNING "Early serial init of port 0"
+ "failed\n");
first_time = 0;
}
@@ -351,35 +352,6 @@
}
#endif
-static int __init
-ev64260_fixup_pd(void)
-{
-#if defined(CONFIG_SERIAL_MPSC)
- struct list_head *entry;
- struct platform_device *pd;
- struct device *dev;
- struct mpsc_pd_dd *dd;
-
- list_for_each(entry, &platform_bus_type.devices.list) {
- dev = container_of(entry, struct device, bus_list);
- pd = container_of(dev, struct platform_device, dev);
-
- if (!strncmp(pd->name, MPSC_CTLR_NAME, BUS_ID_SIZE)) {
- dd = (struct mpsc_pd_dd *) dev_get_drvdata(&pd->dev);
-
- dd->max_idle = 40;
- dd->default_baud = EV64260_DEFAULT_BAUD;
- dd->brg_clk_src = EV64260_MPSC_CLK_SRC;
- dd->brg_clk_freq = EV64260_MPSC_CLK_FREQ;
- }
- }
-#endif
-
- return 0;
-}
-
-subsys_initcall(ev64260_fixup_pd);
-
static void __init
ev64260_setup_arch(void)
{
@@ -417,8 +389,8 @@
ev64260_early_serial_map();
#endif
- printk(BOARD_VENDOR " " BOARD_MACHINE "\n");
- printk("EV-64260-BP port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
+ printk(KERN_INFO "%s %s port (C) 2001 MontaVista Software, Inc."
+ "(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE);
if (ppc_md.progress)
ppc_md.progress("ev64260_setup_arch: exit", 0);
@@ -426,6 +398,50 @@
return;
}
+/* Platform device data fixup routines. */
+#if defined(CONFIG_SERIAL_MPSC)
+static void __init
+ev64260_fixup_mpsc_pdata(struct platform_device *pdev)
+{
+ struct mpsc_pdata *pdata;
+
+ pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
+
+ pdata->max_idle = 40;
+ pdata->default_baud = EV64260_DEFAULT_BAUD;
+ pdata->brg_clk_src = EV64260_MPSC_CLK_SRC;
+ pdata->brg_clk_freq = EV64260_MPSC_CLK_FREQ;
+
+ return;
+}
+
+static int __init
+ev64260_platform_notify(struct device *dev)
+{
+ static struct {
+ char *bus_id;
+ void ((*rtn)(struct platform_device *pdev));
+ } dev_map[] = {
+ { MPSC_CTLR_NAME "0", ev64260_fixup_mpsc_pdata },
+ { MPSC_CTLR_NAME "1", ev64260_fixup_mpsc_pdata },
+ };
+ struct platform_device *pdev;
+ int i;
+
+ if (dev && dev->bus_id)
+ for (i=0; i<ARRAY_SIZE(dev_map); i++)
+ if (!strncmp(dev->bus_id, dev_map[i].bus_id,
+ BUS_ID_SIZE)) {
+
+ pdev = container_of(dev,
+ struct platform_device, dev);
+ dev_map[i].rtn(pdev);
+ }
+
+ return 0;
+}
+#endif
+
static void
ev64260_reset_board(void *addr)
{
@@ -462,7 +478,7 @@
/* map bootrom back in to gt @ reset defaults */
mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
0xff800000, 8*1024*1024, 0);
- bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
+ bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
/* move reg base back to default, setup default pci0 */
mv64x60_write(&bh, MV64x60_INTERNAL_SPACE_DECODE,
@@ -531,7 +547,7 @@
freq = ev64260_get_bus_speed()/4;
- printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
+ printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
freq/1000000, freq%1000000);
tb_ticks_per_jiffy = freq / HZ;
@@ -625,6 +641,10 @@
ppc_md.early_serial_map = ev64260_early_serial_map;
#endif /* CONFIG_KGDB */
+#endif
+
+#if defined(CONFIG_SERIAL_MPSC)
+ platform_notify = ev64260_platform_notify;
#endif
return;
^ permalink raw reply
* Fix spurious error return in FBIO_RADEON_SET_MIRROR
From: Andreas Schwab @ 2005-01-26 1:05 UTC (permalink / raw)
To: linuxppc-dev
FBIO_RADEON_SET_MIRROR always returns with -EINVAL even if successful due
to an inappropriate fall-through.
Signed-off-by: Andreas Schwab <schwab@suse.de>
--- linux-2.6.10/drivers/video/aty/radeon_base.c.~1~ 2004-12-29 20:17:12.00=
0000000 +0100
+++ linux-2.6.10/drivers/video/aty/radeon_base.c 2005-01-26 01:48:17.000000=
000 +0100
@@ -911,7 +911,7 @@ static int radeonfb_ioctl (struct inode=20
=20
OUTREG(CRTC_EXT_CNTL, tmp);
=20
- break;
+ return 0;
case FBIO_RADEON_GET_MIRROR:
if (!rinfo->is_mobility)
return -EINVAL;
Andreas.
--=20
Andreas Schwab, SuSE Labs, schwab@suse.de
SuSE Linux Products GmbH, Maxfeldstra=C3=9Fe 5, 90409 N=C3=BCrnberg, Germany
Key fingerprint =3D 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
^ permalink raw reply
* [PATCH][I2C] Marvell mv64xxx i2c driver
From: Mark A. Greer @ 2005-01-26 1:29 UTC (permalink / raw)
To: Embedded PPC Linux list
[-- Attachment #1: Type: text/plain, Size: 404 bytes --]
Forgot to cc: this list...
--
Greg, Philip,
Marvell makes a line of host bridge for PPC and MIPS systems. On those
bridges is an i2c controller. This patch adds the driver for that i2c
controller.
Please let me know if you see any problems with this patch.
Also, if you're not the correct person(s), please point me to who is.
Thanks,
Mark
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
--
[-- Attachment #2: i2c.patch --]
[-- Type: text/plain, Size: 22326 bytes --]
diff -Nru a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
--- a/drivers/i2c/busses/Kconfig 2005-01-25 18:15:24 -07:00
+++ b/drivers/i2c/busses/Kconfig 2005-01-25 18:15:24 -07:00
@@ -476,4 +476,14 @@
This driver can also be built as a module. If so, the module
will be called i2c-pca-isa.
+config I2C_MV64XXX
+ tristate "Marvell mv64xxx I2C Controller"
+ depends on I2C && MV64X60
+ help
+ If you say yes to this option, support will be included for the
+ built-in I2C interface on the Marvell 64xxx line of host bridges
+
+ This driver can also be built as a module. If so, the module
+ will be called i2c-mv64xxx.
+
endmenu
diff -Nru a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
--- a/drivers/i2c/busses/Makefile 2005-01-25 18:15:24 -07:00
+++ b/drivers/i2c/busses/Makefile 2005-01-25 18:15:24 -07:00
@@ -20,6 +20,7 @@
obj-$(CONFIG_I2C_IXP4XX) += i2c-ixp4xx.o
obj-$(CONFIG_I2C_KEYWEST) += i2c-keywest.o
obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
+obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o
obj-$(CONFIG_I2C_NFORCE2) += i2c-nforce2.o
obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
obj-$(CONFIG_I2C_PARPORT_LIGHT) += i2c-parport-light.o
diff -Nru a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/drivers/i2c/busses/i2c-mv64xxx.c 2005-01-25 18:15:24 -07:00
@@ -0,0 +1,550 @@
+/*
+ * drivers/i2c/busses/i2c-mv64xxx.c
+ *
+ * Driver for the i2c controller on the Marvell line of host bridges for MIPS
+ * and PPC (e.g, gt642[46]0, mv643[46]0, mv644[46]0).
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2005 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/wait.h>
+#include <linux/spinlock.h>
+#include <asm/io.h>
+#include <asm/ocp.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/mv643xx.h>
+#include "i2c-mv64xxx.h"
+
+/*
+ *****************************************************************************
+ *
+ * Finite State Machine & Interrupt Routines
+ *
+ *****************************************************************************
+ */
+static inline void
+mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
+{
+ pr_debug("mv64xxx_i2c_fsm: ENTER--state: %d, status: 0x%x\n",
+ drv_data->state, status);
+
+ /*
+ * If state is idle, then this is likely the remnants of an old
+ * operation that driver has given up on or the user has killed.
+ * If so, issue the stop condition and go to idle.
+ */
+ if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
+ drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
+ drv_data->state = MV64XXX_I2C_STATE_IDLE;
+ pr_debug("mv64xxx_i2c_fsm: EXIT--Entered when in IDLE state\n");
+ return;
+ }
+
+ if (drv_data->state == MV64XXX_I2C_STATE_ABORTING) {
+ drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
+ drv_data->state = MV64XXX_I2C_STATE_IDLE;
+ pr_debug("mv64xxx_i2c_fsm: EXIT--Aborting\n");
+ return;
+ }
+
+ /* The status from the ctlr [mostly] tells us what to do next */
+ switch (status) {
+ /* Start condition interrupt */
+ case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
+ case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
+ drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
+ drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
+ break;
+
+ /* Performing a write */
+ case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
+ if (drv_data->msg->flags & I2C_M_TEN) {
+ drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
+ drv_data->state =
+ MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
+ break;
+ }
+ /* FALLTHRU */
+ case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
+ case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
+ if (drv_data->bytes_left > 0) {
+ drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
+ drv_data->state =
+ MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
+ drv_data->bytes_left--;
+ }
+ else {
+ drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
+ drv_data->state = MV64XXX_I2C_STATE_IDLE;
+ }
+ break;
+
+ /* Performing a read */
+ case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
+ if (drv_data->msg->flags & I2C_M_TEN) {
+ drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
+ drv_data->state =
+ MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
+ break;
+ }
+ /* FALLTHRU */
+ case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
+ if (drv_data->bytes_left == 0) {
+ drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
+ drv_data->state = MV64XXX_I2C_STATE_IDLE;
+ break;
+ }
+ /* FALLTHRU */
+ case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
+ if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
+ drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
+ else {
+ drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
+ drv_data->bytes_left--;
+ }
+ drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
+
+ if (drv_data->bytes_left == 1)
+ drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
+ break;
+
+ case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
+ drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
+ drv_data->state = MV64XXX_I2C_STATE_IDLE;
+ break;
+
+ case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
+ case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
+ case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
+ /* Doesn't seem to be a device at other end */
+ drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
+ drv_data->state = MV64XXX_I2C_STATE_IDLE;
+ drv_data->rc = -ENODEV;
+ break;
+
+ default:
+ printk(KERN_ERR "mv64xxx_i2c_fsm: Ctlr Error -- "
+ "state: 0x%x, status: 0x%x\n", drv_data->state, status);
+ printk(KERN_INFO "addr: 0x%x, flags: 0x%x\n",
+ drv_data->msg->addr, drv_data->msg->flags);
+ drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
+ drv_data->state = MV64XXX_I2C_STATE_IDLE;
+ drv_data->rc = -EIO;
+ }
+
+ pr_debug("mv64xxx_i2c_fsm: EXIT--action: %d, state: %d, rc: 0x%x\n",
+ drv_data->action, drv_data->state, drv_data->rc);
+ return;
+}
+
+static void
+mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
+{
+ pr_debug("mv64xxx_i2c_do_action: ENTER--action: %d, state: %d, "
+ "cntl: 0x%x\n", drv_data->action, drv_data->state,
+ drv_data->cntl_bits);
+
+ switch(drv_data->action) {
+ case MV64XXX_I2C_ACTION_CONTINUE:
+ writel(drv_data->cntl_bits,
+ drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+ break;
+
+ case MV64XXX_I2C_ACTION_SEND_START:
+ writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
+ drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+ break;
+
+ case MV64XXX_I2C_ACTION_SEND_ADDR_1:
+ writel(drv_data->addr1,
+ drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+ writel(drv_data->cntl_bits,
+ drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+ break;
+
+ case MV64XXX_I2C_ACTION_SEND_ADDR_2:
+ writel(drv_data->addr2,
+ drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+ writel(drv_data->cntl_bits,
+ drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+ break;
+
+ case MV64XXX_I2C_ACTION_SEND_DATA:
+ writel(drv_data->msg->buf[drv_data->byte_posn++],
+ drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+ writel(drv_data->cntl_bits,
+ drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+ break;
+
+ case MV64XXX_I2C_ACTION_RCV_DATA:
+ drv_data->msg->buf[drv_data->byte_posn++] =
+ readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+ writel(drv_data->cntl_bits,
+ drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+ break;
+
+ case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
+ drv_data->msg->buf[drv_data->byte_posn++] =
+ readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+ drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
+ writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
+ drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+ drv_data->block = 0;
+ wake_up_interruptible(&drv_data->waitq);
+ break;
+
+ case MV64XXX_I2C_ACTION_INVALID:
+ default:
+ printk(KERN_ERR "mv64xxx_i2c_do_action: Invalid action: %d\n",
+ drv_data->action);
+ drv_data->rc = -EIO;
+ /* FALLTHRU */
+ case MV64XXX_I2C_ACTION_SEND_STOP:
+ drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
+ writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
+ drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+ drv_data->block = 0;
+ wake_up_interruptible(&drv_data->waitq);
+ break;
+ }
+
+ pr_debug("mv64xxx_i2c_do_action: EXIT\n");
+ return;
+}
+
+static int
+mv64xxx_i2c_intr(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct mv64xxx_i2c_data *drv_data = dev_id;
+ u32 status;
+ long flags;
+ int rc = IRQ_NONE;
+
+ spin_lock_irqsave(&drv_data->lock, flags);
+ while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) &
+ MV64XXX_I2C_REG_CONTROL_IFLG) {
+ status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS);
+ mv64xxx_i2c_fsm(drv_data, status);
+ mv64xxx_i2c_do_action(drv_data);
+ rc = IRQ_HANDLED;
+ }
+ spin_unlock_irqrestore(&drv_data->lock, flags);
+
+ return rc;
+}
+
+/*
+ *****************************************************************************
+ *
+ * I2C Msg Execution Routines
+ *
+ *****************************************************************************
+ */
+static inline void
+mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
+ struct i2c_msg *msg)
+{
+ u32 dir = 0;
+
+ drv_data->msg = msg;
+ drv_data->byte_posn = 0;
+ drv_data->bytes_left = msg->len;
+ drv_data->rc = 0;
+ drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
+ MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
+
+ if (msg->flags & I2C_M_RD)
+ dir = 1;
+
+ if (msg->flags & I2C_M_REV_DIR_ADDR)
+ dir ^= 1;
+
+ if (msg->flags & I2C_M_TEN) {
+ drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
+ drv_data->addr2 = (u32)msg->addr & 0xff;
+ }
+ else {
+ drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
+ drv_data->addr2 = 0;
+ }
+
+ return;
+}
+
+static inline void
+mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
+{
+ long flags, time_left;
+ char abort = 0;
+
+ time_left = wait_event_interruptible_timeout(drv_data->waitq,
+ !drv_data->block, msecs_to_jiffies(drv_data->adapter.timeout));
+
+ spin_lock_irqsave(&drv_data->lock, flags);
+ if (!time_left) { /* Timed out */
+ drv_data->rc = -ETIMEDOUT;
+ abort = 1;
+ }
+ else if (time_left < 0) { /* Interrupted/Error */
+ drv_data->rc = time_left; /* errno value */
+ abort = 1;
+ }
+
+ if (abort && drv_data->block) {
+ drv_data->state = MV64XXX_I2C_STATE_ABORTING;
+ spin_unlock_irqrestore(&drv_data->lock, flags);
+
+ time_left = wait_event_timeout(drv_data->waitq,
+ !drv_data->block,
+ msecs_to_jiffies(drv_data->adapter.timeout));
+
+ if (!time_left <= 0) {
+ drv_data->state = MV64XXX_I2C_STATE_IDLE;
+ printk(KERN_WARNING "mv64xxx: I2C bus locked\n");
+ }
+ }
+ else
+ spin_unlock_irqrestore(&drv_data->lock, flags);
+
+ return;
+}
+
+static inline int
+mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg)
+{
+ long flags;
+
+ spin_lock_irqsave(&drv_data->lock, flags);
+ mv64xxx_i2c_prepare_for_io(drv_data, msg);
+
+ if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */
+ if (drv_data->msg->flags & I2C_M_RD) {
+ /* No action to do, wait for slave to send a byte */
+ drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
+ drv_data->state =
+ MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
+ }
+ else {
+ drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
+ drv_data->state =
+ MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
+ drv_data->bytes_left--;
+ }
+ }
+ else {
+ drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
+ drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
+ }
+
+ drv_data->block = 1;
+ mv64xxx_i2c_do_action(drv_data);
+ spin_unlock_irqrestore(&drv_data->lock, flags);
+
+ mv64xxx_i2c_wait_for_completion(drv_data);
+ return drv_data->rc;
+}
+
+/*
+ *****************************************************************************
+ *
+ * I2C Core Support Routines (Interface to higher level I2C code)
+ *
+ *****************************************************************************
+ */
+static u32
+mv64xxx_i2c_functionality(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_I2C |I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
+}
+
+static int
+mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
+{
+ struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
+ int i, rc = 0;
+
+ for (i=0; i<num; i++)
+ if ((rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i])) != 0)
+ break;
+
+ return rc;
+}
+
+static struct i2c_algorithm mv64xxx_i2c_algo = {
+ .name = MV64XXX_I2C_CTLR_NAME "algorithm",
+ .id = I2C_ALGO_MV64XXX,
+ .master_xfer = mv64xxx_i2c_xfer,
+ .functionality = mv64xxx_i2c_functionality,
+};
+
+/*
+ *****************************************************************************
+ *
+ * Driver Interface & Early Init Routines
+ *
+ *****************************************************************************
+ */
+static void __devinit
+mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
+{
+ writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET);
+ writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)),
+ drv_data->reg_base + MV64XXX_I2C_REG_BAUD);
+ writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR);
+ writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR);
+ writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
+ drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+ drv_data->state = MV64XXX_I2C_STATE_IDLE;
+ return;
+}
+
+static int __devinit
+mv64xxx_i2c_map_regs(struct platform_device *pd,
+ struct mv64xxx_i2c_data *drv_data)
+{
+ struct resource *r;
+
+ if ((r = platform_get_resource(pd, IORESOURCE_MEM, 0)) &&
+ request_mem_region(r->start, MV64XXX_I2C_REG_BLOCK_SIZE,
+ drv_data->adapter.name)) {
+
+ drv_data->reg_base = ioremap(r->start,
+ MV64XXX_I2C_REG_BLOCK_SIZE);
+ drv_data->reg_base_p = r->start;
+ }
+ else
+ return -ENOMEM;
+
+ return 0;
+}
+
+static void __devexit
+mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data)
+{
+ if (!drv_data->reg_base) {
+ iounmap(drv_data->reg_base);
+ release_mem_region(drv_data->reg_base_p,
+ MV64XXX_I2C_REG_BLOCK_SIZE);
+ }
+
+ drv_data->reg_base = 0;
+ drv_data->reg_base_p = 0;
+ return;
+}
+
+static int __devinit
+mv64xxx_i2c_probe(struct device *dev)
+{
+ struct platform_device *pd = to_platform_device(dev);
+ struct mv64xxx_i2c_data *drv_data;
+ struct mv64xxx_i2c_pdata *pdata = dev->platform_data;
+ int rc;
+
+ if ((pd->id == 0) && pdata) {
+ drv_data = kmalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL);
+
+ if (!drv_data)
+ return -ENOMEM;
+
+ memset(drv_data, 0, sizeof(struct mv64xxx_i2c_data));
+
+ if (mv64xxx_i2c_map_regs(pd, drv_data)) {
+ kfree(drv_data);
+ return -ENODEV;
+ }
+
+ strncpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME "adapter",
+ I2C_NAME_SIZE);
+
+ init_waitqueue_head(&drv_data->waitq);
+ spin_lock_init(&drv_data->lock);
+
+ drv_data->freq_m = pdata->freq_m;
+ drv_data->freq_n = pdata->freq_n;
+ drv_data->irq = platform_get_irq(pd, 0);
+ drv_data->adapter.id = I2C_ALGO_MV64XXX | I2C_HW_MV64XXX;
+ drv_data->adapter.algo = &mv64xxx_i2c_algo;
+ drv_data->adapter.timeout = pdata->timeout;
+ drv_data->adapter.retries = pdata->retries;
+ dev_set_drvdata(dev, drv_data);
+ i2c_set_adapdata(&drv_data->adapter, drv_data);
+
+ if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
+ MV64XXX_I2C_CTLR_NAME, drv_data)) {
+
+ printk(KERN_ERR "mv64xxx: Can't register intr handler "
+ "irq: %d\\n", drv_data->irq);
+
+ mv64xxx_i2c_unmap_regs(drv_data);
+ kfree(drv_data);
+ return -EINVAL;
+ }
+ else if ((rc = i2c_add_adapter(&drv_data->adapter)) != 0) {
+ printk(KERN_WARNING "mv64xxx: Can't add i2c adapter "
+ "rc: %d\n", -rc);
+ free_irq(drv_data->irq, drv_data);
+ mv64xxx_i2c_unmap_regs(drv_data);
+ kfree(drv_data);
+ return rc;
+ }
+
+ mv64xxx_i2c_hw_init(drv_data);
+ }
+ else
+ return -ENODEV;
+
+ return 0;
+}
+
+static int __devexit
+mv64xxx_i2c_remove(struct device *dev)
+{
+ struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
+ int rc;
+
+ rc = i2c_del_adapter(&drv_data->adapter);
+ free_irq(drv_data->irq, drv_data);
+ mv64xxx_i2c_unmap_regs(drv_data);
+ kfree(drv_data);
+
+ return rc;
+}
+
+static struct device_driver mv64xxx_i2c_driver = {
+ .name = MV64XXX_I2C_CTLR_NAME,
+ .bus = &platform_bus_type,
+ .probe = mv64xxx_i2c_probe,
+ .remove = mv64xxx_i2c_remove,
+};
+
+static int __devinit
+mv64xxx_i2c_init(void)
+{
+ return driver_register(&mv64xxx_i2c_driver);
+}
+
+static void __devexit
+mv64xxx_i2c_exit(void)
+{
+ driver_unregister(&mv64xxx_i2c_driver);
+ return;
+}
+
+module_init(mv64xxx_i2c_init);
+module_exit(mv64xxx_i2c_exit);
+
+MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
+MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
+MODULE_LICENSE("GPL");
diff -Nru a/drivers/i2c/busses/i2c-mv64xxx.h b/drivers/i2c/busses/i2c-mv64xxx.h
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/drivers/i2c/busses/i2c-mv64xxx.h 2005-01-25 18:15:24 -07:00
@@ -0,0 +1,99 @@
+/*
+ * drivers/i2c/busses/i2c-mv64xxx.h
+ *
+ * Driver for the i2c controller on the Marvell line of host bridges for MIPS
+ * and PPC (e.g, gt642[46]0, mv643[46]0, mv644[46]0).
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2005 (c) MontaVista, Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef I2C_MV64XXX_H
+#define I2C_MV64XXX_H
+
+/* Register defines */
+#define MV64XXX_I2C_REG_SLAVE_ADDR 0x00
+#define MV64XXX_I2C_REG_DATA 0x04
+#define MV64XXX_I2C_REG_CONTROL 0x08
+#define MV64XXX_I2C_REG_STATUS 0x0c
+#define MV64XXX_I2C_REG_BAUD 0x0c
+#define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10
+#define MV64XXX_I2C_REG_SOFT_RESET 0x1c
+
+#define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004
+#define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008
+#define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010
+#define MV64XXX_I2C_REG_CONTROL_START 0x00000020
+#define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040
+#define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080
+
+/* Ctlr status values */
+#define MV64XXX_I2C_STATUS_BUS_ERR 0x00
+#define MV64XXX_I2C_STATUS_MAST_START 0x08
+#define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
+#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
+#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
+#define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
+#define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
+#define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
+#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
+#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
+#define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
+#define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
+#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
+#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
+#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
+#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
+#define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
+
+/* Driver states */
+enum {
+ MV64XXX_I2C_STATE_INVALID,
+ MV64XXX_I2C_STATE_IDLE,
+ MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
+ MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
+ MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
+ MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
+ MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
+ MV64XXX_I2C_STATE_ABORTING,
+};
+
+/* Driver actions */
+enum {
+ MV64XXX_I2C_ACTION_INVALID,
+ MV64XXX_I2C_ACTION_CONTINUE,
+ MV64XXX_I2C_ACTION_SEND_START,
+ MV64XXX_I2C_ACTION_SEND_ADDR_1,
+ MV64XXX_I2C_ACTION_SEND_ADDR_2,
+ MV64XXX_I2C_ACTION_SEND_DATA,
+ MV64XXX_I2C_ACTION_RCV_DATA,
+ MV64XXX_I2C_ACTION_RCV_DATA_STOP,
+ MV64XXX_I2C_ACTION_SEND_STOP,
+};
+
+struct mv64xxx_i2c_data {
+ int irq;
+ uint state;
+ uint action;
+ u32 cntl_bits;
+ void *reg_base;
+ ulong reg_base_p;
+ u32 addr1;
+ u32 addr2;
+ uint bytes_left;
+ uint byte_posn;
+ uint block;
+ int rc;
+ u32 freq_m;
+ u32 freq_n;
+ wait_queue_head_t waitq;
+ spinlock_t lock;
+ struct i2c_msg *msg;
+ struct i2c_adapter adapter;
+};
+
+#endif /* I2C_MV64XXX_H */
diff -Nru a/include/linux/i2c-id.h b/include/linux/i2c-id.h
--- a/include/linux/i2c-id.h 2005-01-25 18:15:24 -07:00
+++ b/include/linux/i2c-id.h 2005-01-25 18:15:24 -07:00
@@ -200,6 +200,7 @@
#define I2C_ALGO_SIBYTE 0x150000 /* Broadcom SiByte SOCs */
#define I2C_ALGO_SGI 0x160000 /* SGI algorithm */
+#define I2C_ALGO_MV64XXX 0x170000 /* Marvell mv64xxx i2c ctlr */
#define I2C_ALGO_EXP 0x800000 /* experimental */
@@ -304,5 +305,8 @@
/* --- MCP107 adapter */
#define I2C_HW_MPC107 0x00
+
+/* --- Marvell mv64xxx i2c adapter */
+#define I2C_HW_MV64XXX 0x00
#endif /* LINUX_I2C_ID_H */
diff -Nru a/include/linux/mv643xx.h b/include/linux/mv643xx.h
--- a/include/linux/mv643xx.h 2005-01-25 18:15:24 -07:00
+++ b/include/linux/mv643xx.h 2005-01-25 18:15:24 -07:00
@@ -977,12 +977,9 @@
/* I2C Registers */
/****************************************/
-#define MV64340_I2C_SLAVE_ADDR 0xc000
-#define MV64340_I2C_EXTENDED_SLAVE_ADDR 0xc010
-#define MV64340_I2C_DATA 0xc004
-#define MV64340_I2C_CONTROL 0xc008
-#define MV64340_I2C_STATUS_BAUDE_RATE 0xc00C
-#define MV64340_I2C_SOFT_RESET 0xc01c
+#define MV64XXX_I2C_CTLR_NAME "mv64xxx i2c"
+#define MV64XXX_I2C_OFFSET 0xc000
+#define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020
/****************************************/
/* GPP Interface Registers */
@@ -1083,6 +1080,14 @@
u8 brg_can_tune;
u8 brg_clk_src;
u32 brg_clk_freq;
+};
+
+/* i2c Platform Device, Driver Data */
+struct mv64xxx_i2c_pdata {
+ u32 freq_m;
+ u32 freq_n;
+ u32 timeout; /* In milliseconds */
+ u32 retries;
};
#endif /* __ASM_MV64340_H */
^ permalink raw reply
* 8xx bus monitoring
From: Robin Gilks @ 2005-01-26 2:31 UTC (permalink / raw)
To: ppc embedded list
Greetings
System is a MPC859 based controller.
I'm trying to determine whether a peripheral is not responding to memory
fetches by using the bus monitor feature on the Transfer Acknowledge
(TA) signal. This is set to the maximum count in the Bus Monitor Timeout
(BMT) in the System Protect Control Register (SYPCR). The monitoring is
enabled by setting the Bus Monitor Enable (BME) bit in SYPCR as well.
I understand that I can use the Transfer Error Status Register (TESR) to
read the fact that I have had a timeout by checking the Data Transfer
Monitor Timeout (DTMT) bit in this register.
The problem is, how do I know any error has occured so I know to look at
the TESR. I can't see a way of generating an exception from this
condition.
Any help appreciated.
--
Robin Gilks
Senior Design Engineer Phone: (+64)(3) 357 1569
Tait Electronics Fax : (+64)(3) 359 4632
PO Box 1645 Christchurch Email : robin.gilks@tait.co.nz
New Zealand
=======================================================================
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addressee. It is subject to copyright, is confidential and may be
the subject of legal or other privilege, none of which is waived or
lost by reason of this transmission.
If the receiver is not the intended addressee, please accept our
apologies, notify us by return, delete all copies and perform no
other act on the email.
Unfortunately, we cannot warrant that the email has not been
altered or corrupted during transmission.
=======================================================================
^ permalink raw reply
* Re: [PATCH] ppc32: (Updated) Pegasos support
From: Andrew Morton @ 2005-01-26 6:15 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, luther
In-Reply-To: <1106696607.6249.18.camel@gaston>
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
>
> Here's an updated version of the pegasos support patch for ppc32, fixing
> a typo in the previous one.
I already sent the first version to Linus. That's reason 42 for preferring
incremental diffs ;)
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Here's an updated version of the pegasos support patch for ppc32, fixing a
typo in the previous one. Driver patches to come soon.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---
25-akpm/arch/ppc/platforms/chrp_pci.c | 2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
diff -puN arch/ppc/platforms/chrp_pci.c~ppc32-updated-pegasos-support arch/ppc/platforms/chrp_pci.c
--- 25/arch/ppc/platforms/chrp_pci.c~ppc32-updated-pegasos-support 2005-01-25 22:14:12.685346992 -0800
+++ 25-akpm/arch/ppc/platforms/chrp_pci.c 2005-01-25 22:14:12.688346536 -0800
@@ -304,6 +304,6 @@ chrp_find_bridges(void)
}
/* Do not fixup interrupts from OF tree on pegasos */
- if (is_pegasos != 0)
+ if (is_pegasos == 0)
ppc_md.pcibios_fixup = chrp_pcibios_fixup;
}
_
^ permalink raw reply
* Re: [PATCH] sungem update
From: David S. Miller @ 2005-01-26 6:42 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, jgarzik
In-Reply-To: <1106028614.4533.69.camel@gaston>
On Tue, 18 Jan 2005 17:10:14 +1100
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> This patch updates the sungem driver. I reworked all of the PM stuff, making it
> less prone to races, probably simpler to read as well, and I no longer shut the
> PHY down when the interface is down so that things like laptop-net no longer
> die (the gain in power consumption was minimal, not worth the pain). I also
> implemented basic WOL support.
>
> There is still something I'm not totally happy with in the locking
> (explained in the comment at the beginning), basically too much locking and a
> couple of places with delays in locks. I will try to improve these later on.
>
> If you are happy with this, please forward to Linus/Andrew asap
Sorry for taking so long. I'll try to quick review and sanity
test this on my sparc sungem chips tomorrow Ben.
^ permalink raw reply
* Re: 8xx bus monitoring
From: Pantelis Antoniou @ 2005-01-26 7:06 UTC (permalink / raw)
To: robin.gilks; +Cc: ppc embedded list
In-Reply-To: <41F70114.5040200@tait.co.nz>
Robin Gilks wrote:
> Greetings
>
> System is a MPC859 based controller.
>
> I'm trying to determine whether a peripheral is not responding to memory
> fetches by using the bus monitor feature on the Transfer Acknowledge
> (TA) signal. This is set to the maximum count in the Bus Monitor Timeout
> (BMT) in the System Protect Control Register (SYPCR). The monitoring is
> enabled by setting the Bus Monitor Enable (BME) bit in SYPCR as well.
>
> I understand that I can use the Transfer Error Status Register (TESR) to
> read the fact that I have had a timeout by checking the Data Transfer
> Monitor Timeout (DTMT) bit in this register.
>
> The problem is, how do I know any error has occured so I know to look at
> the TESR. I can't see a way of generating an exception from this
> condition.
>
> Any help appreciated.
>
You get a machine check exception.
It's pretty obvious then :)
Regards
Pantelis
^ permalink raw reply
* Re: BUG: 2.6.11-rc2 and -rc1 hang during boot on PowerMacs
From: Mikael Pettersson @ 2005-01-26 10:02 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev list, Paul Mackerras, Linux Kernel list,
Mikael Pettersson
In-Reply-To: <1106696846.6250.20.camel@gaston>
Benjamin Herrenschmidt writes:
> On Tue, 2005-01-25 at 09:56 +0100, Mikael Pettersson wrote:
>
> > On the eMac:
> > /proc/sys/kernel/powersave-nap exists and contains "0".
> > /proc/device-tree/cpus/PowerPC,G4/flush-on-lock exists as an empty file.
>
> Ok, that is weird... so for some reason, Apple decided not to allow the
> eMac to do NAP mode, and thus to power manage the CPU when idle...
I assumed it was due to the UniNorth issue that pmac_feature.c mentions.
/Mikael
^ permalink raw reply
* Re: [PATCH] Heartbeat LED for iBook
From: Nico Schottelius @ 2005-01-26 11:35 UTC (permalink / raw)
To: Joerg Dorchain; +Cc: linuxppc-dev list
In-Reply-To: <20050118094216.GB25470@Redstar.dorchain.net>
[-- Attachment #1: Type: text/plain, Size: 346 bytes --]
Hello!
Joerg Dorchain [Tue, Jan 18, 2005 at 10:42:16AM +0100]:
> [heartbeat blink patch]
Well, wouldn't it make much more sense to write a
/dev/frontled to access it via userspace?
Then one could enable much more features like
- xmms plugins
- num-lock led
- network-traffic
- morse-codes
- glowing when typing
- ...
Nico
[-- Attachment #2: Type: application/pgp-signature, Size: 827 bytes --]
^ permalink raw reply
* target board NFS mounting timeout
From: Alireza Sadri @ 2005-01-26 13:00 UTC (permalink / raw)
To: Linuxppc-embedded
Hi ,
I have a problem with mounting NFS by an external
board on my host.
kernel doesn't mount NFS for the first time it boots
(or sometimes for second time ) but when i reset the
board another time , it can find the server , i must
add that if the time between two tryings gets too much
, it will fail to mount it even for the second time i
reset.
I used ethereal (watched the packets of Ethernet) and
saw that server sends status of last packet OK for
mounting NFS , but the client didn't mount it . I
think it is because , the timeout of client (kernel)
is not enough. or maybe the problem is due to my
server's settings.
has anyone faced similar problem , or can anyone help
me please?
i use a 82xx and ELDKv3 kernel v2.4.24 as target , and
a SuSE9.1 as my host . i have stablished my NFS server
using YAST2.
Best regards,
Alireza Sadri.
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^ permalink raw reply
* Re: [PATCH] ppc32: (Updated) Pegasos support
From: Benjamin Herrenschmidt @ 2005-01-26 13:39 UTC (permalink / raw)
To: Andrew Morton; +Cc: linuxppc-dev list, Sven Luther
In-Reply-To: <20050125221517.6ec13d0f.akpm@osdl.org>
On Tue, 2005-01-25 at 22:15 -0800, Andrew Morton wrote:
> Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> >
> > Here's an updated version of the pegasos support patch for ppc32, fixing
> > a typo in the previous one.
>
> I already sent the first version to Linus. That's reason 42 for preferring
> incremental diffs ;)
Heh, no worries, it's a oneliner fix anyway, I'll send it tomorrow.
Ben.
^ permalink raw reply
* Re: [PATCH] sungem update
From: Benjamin Herrenschmidt @ 2005-01-26 13:40 UTC (permalink / raw)
To: David S. Miller; +Cc: linuxppc-dev list, Jeff Garzik
In-Reply-To: <20050125224248.276080b7.davem@davemloft.net>
> > If you are happy with this, please forward to Linus/Andrew asap
>
> Sorry for taking so long. I'll try to quick review and sanity
> test this on my sparc sungem chips tomorrow Ben.
Thanks. There is no real hurry as the bulk of the powermac PM updates
won't make it until 2.6.12 anyway, so feel free to comment. I know I
still take too much locks for too long, and I do intend to fix that,
though the fact that set_multicast is called with a lock doesn't quite
help here ... :) Hopefully, this new version makes the whole stuff more
simple tho and easier to follow.
Ben.
^ permalink raw reply
* Re: [PATCH] Heartbeat LED for iBook
From: Benjamin Herrenschmidt @ 2005-01-26 13:42 UTC (permalink / raw)
To: Nico Schottelius; +Cc: linuxppc-dev list
In-Reply-To: <20050126113554.GD19633@schottelius.org>
On Wed, 2005-01-26 at 12:35 +0100, Nico Schottelius wrote:
> Hello!
>
>
> Joerg Dorchain [Tue, Jan 18, 2005 at 10:42:16AM +0100]:
> > [heartbeat blink patch]
>
> Well, wouldn't it make much more sense to write a
> /dev/frontled to access it via userspace?
>
> Then one could enable much more features like
> - xmms plugins
> - num-lock led
> - network-traffic
> - morse-codes
> - glowing when typing
> - ...
One can always control the led by sending PMU command directly
via /dev/adb :) Ok, that sort-of sucks, especially since the command is
only supported by some versions of the PMU. On the other hand, I dislike
cluttering /dev ... maybe I can find some better mecanism via sysfs...
Ben.
^ permalink raw reply
* Re: BUG: 2.6.11-rc2 and -rc1 hang during boot on PowerMacs
From: Benjamin Herrenschmidt @ 2005-01-26 13:51 UTC (permalink / raw)
To: Mikael Pettersson; +Cc: linuxppc-dev list, Paul Mackerras, Linux Kernel list
In-Reply-To: <16887.27336.161685.55774@alkaid.it.uu.se>
On Wed, 2005-01-26 at 11:02 +0100, Mikael Pettersson wrote:
> Benjamin Herrenschmidt writes:
> > On Tue, 2005-01-25 at 09:56 +0100, Mikael Pettersson wrote:
> >
> > > On the eMac:
> > > /proc/sys/kernel/powersave-nap exists and contains "0".
> > > /proc/device-tree/cpus/PowerPC,G4/flush-on-lock exists as an empty file.
> >
> > Ok, that is weird... so for some reason, Apple decided not to allow the
> > eMac to do NAP mode, and thus to power manage the CPU when idle...
>
> I assumed it was due to the UniNorth issue that pmac_feature.c mentions.
Not clear. I would expect the eMac to run with a fairly recent revision
of UniNorth with no issue, and since it's not an SMP machine there
should be no problem...
On the other hand, I also suspect that the whole NAP thing does have a
small impact on performances, so that may be the reason they chose not
to do it on this HW...
Ben.
^ permalink raw reply
* PPC405 restart
From: Michael Platov @ 2005-01-26 14:19 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 459 bytes --]
Hi, All!
Is it possible to restart PPC405 proccessor while running linux, but without restarting the kernel? I mean save it's state, restart proccessor (without resetting other stuff), restore state and continue running linux from the place where I stop? (something like hibernation, but without saving RAM to disk). If it is possible could anyone tell what exactly must be saved and then restored normal kernel operation?
With regards,
Michael Platov
[-- Attachment #2: Type: text/html, Size: 1022 bytes --]
^ permalink raw reply
* [PATCH][PPC32] cpci690 update
From: Mark A. Greer @ 2005-01-26 18:13 UTC (permalink / raw)
To: akpm; +Cc: Embedded PPC Linux list
[-- Attachment #1: Type: text/plain, Size: 190 bytes --]
Hi Andrew,
This patch updates the cpci690 platform file. The platform file now
uses the platform_notify hook to update platform_data.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
--
[-- Attachment #2: cpci690.patch --]
[-- Type: text/plain, Size: 2232 bytes --]
diff -Nru a/arch/ppc/platforms/cpci690.c b/arch/ppc/platforms/cpci690.c
--- a/arch/ppc/platforms/cpci690.c 2005-01-26 11:11:50 -07:00
+++ b/arch/ppc/platforms/cpci690.c 2005-01-26 11:11:50 -07:00
@@ -289,35 +289,6 @@
return;
}
-static int __init
-cpci690_fixup_pd(void)
-{
-#if defined(CONFIG_SERIAL_MPSC)
- struct list_head *entry;
- struct platform_device *pd;
- struct device *dev;
- struct mpsc_pd_dd *dd;
-
- list_for_each(entry, &platform_bus_type.devices.list) {
- dev = container_of(entry, struct device, bus_list);
- pd = container_of(dev, struct platform_device, dev);
-
- if (!strncmp(pd->name, MPSC_CTLR_NAME, BUS_ID_SIZE)) {
- dd = (struct mpsc_pd_dd *) dev_get_drvdata(&pd->dev);
-
- dd->max_idle = 40;
- dd->default_baud = 9600;
- dd->brg_clk_src = 8;
- dd->brg_clk_freq = 133000000;
- }
- }
-#endif
-
- return 0;
-}
-
-subsys_initcall(cpci690_fixup_pd);
-
static void __init
cpci690_setup_arch(void)
{
@@ -359,6 +330,50 @@
return;
}
+/* Platform device data fixup routines. */
+#if defined(CONFIG_SERIAL_MPSC)
+static void __init
+cpci690_fixup_mpsc_pdata(struct platform_device *pdev)
+{
+ struct mpsc_pdata *pdata;
+
+ pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
+
+ pdata->max_idle = 40;
+ pdata->default_baud = 9600;
+ pdata->brg_clk_src = 8;
+ pdata->brg_clk_freq = 133000000;
+
+ return;
+}
+
+static int __init
+cpci690_platform_notify(struct device *dev)
+{
+ static struct {
+ char *bus_id;
+ void ((*rtn)(struct platform_device *pdev));
+ } dev_map[] = {
+ { MPSC_CTLR_NAME "0", cpci690_fixup_mpsc_pdata },
+ { MPSC_CTLR_NAME "1", cpci690_fixup_mpsc_pdata },
+ };
+ struct platform_device *pdev;
+ int i;
+
+ if (dev && dev->bus_id)
+ for (i=0; i<ARRAY_SIZE(dev_map); i++)
+ if (!strncmp(dev->bus_id, dev_map[i].bus_id,
+ BUS_ID_SIZE)) {
+
+ pdev = container_of(dev,
+ struct platform_device, dev);
+ dev_map[i].rtn(pdev);
+ }
+
+ return 0;
+}
+#endif
+
static void
cpci690_reset_board(void)
{
@@ -488,6 +503,10 @@
ppc_md.setup_io_mappings = cpci690_map_io;
ppc_md.early_serial_map = cpci690_early_serial_map;
#endif /* CONFIG_KGDB */
+
+#if defined(CONFIG_SERIAL_MPSC)
+ platform_notify = cpci690_platform_notify;
+#endif
return;
}
^ permalink raw reply
* Re: Is there a DER for the MPC82xx?
From: annamaya @ 2005-01-26 18:53 UTC (permalink / raw)
To: annamaya, linuxppc-embedded
In-Reply-To: <20050125225405.69774.qmail@web53802.mail.yahoo.com>
Can someone tell me if the BDI will be able to catch
all different kinds of exceptions/interrupts on the
MPC82xx without requiring any special register
programming? I am unable to find anything that that
resembles the DER register on the MPC8280.
--- annamaya <annamaya@yahoo.com> wrote:
> Is there something similar to a DER (debug enable
> register on a MPC8xx) on the MPC82xx processor? I
> was
> unable to find anything similar to that on this
> processor. According to the MPC8280 Reference
> Manual,
> Appendix A.3, it says something about Chapter 36
> being
> the "System Development and Debugging" chapter.
> Well,
> chapter 36 happens to be FCC ethernet stuff. Can
> someone point me in the right direction here?
>
>
>
> __________________________________
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> _______________________________________________
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> Linuxppc-embedded@ozlabs.org
>
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>
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^ permalink raw reply
* cmd_line and cmd_preset in arch/ppc/boot/simple/misc.c
From: Leigh Brown @ 2005-01-26 18:55 UTC (permalink / raw)
To: linuxppc-dev list
Hi,
Could someone please confirm that I'm not going mad? At least wrt
this ;-) We have this code in misc.c:
#ifdef CONFIG_GEMINI
/*
* If cmd_line is empty and cmd_preset is not, copy cmd_preset
* to cmd_line. This way we can override cmd_preset with the
* command line from Smon.
*/
if ( (cmd_line[0] == '\0') && (cmd_preset[0] != '\0'))
memcpy (cmd_line, cmd_preset, sizeof(cmd_preset));
#endif
/* Display standard Linux/PPC boot prompt for kernel args */
puts("\nLinux/PPC load: ");
cp = cmd_line;
memcpy (cmd_line, cmd_preset, sizeof(cmd_preset));
Surely the bit in the #ifdef is ineffective? Also, as cmd_line is
initialised to zeros, I think this is better:
/*
* If cmd_line is empty and cmd_preset is not, copy cmd_preset
* to cmd_line. This way we can override cmd_preset with the
* command line from Smon.
*/
if ( (cmd_line[0] == '\0') && (cmd_preset[0] != '\0'))
memcpy (cmd_line, cmd_preset, sizeof(cmd_preset));
/* Display standard Linux/PPC boot prompt for kernel args */
puts("\nLinux/PPC load: ");
cp = cmd_line;
As, in the general case, cmd_line[0] will always be zero and
cmd_preset[0] will always be filled, so no need for an #ifdef.
If someone can confirm I'm not mistaken, I can send a patch...
^ permalink raw reply
* Re: Is there a DER for the MPC82xx?
From: Dan Malek @ 2005-01-26 19:01 UTC (permalink / raw)
To: annamaya; +Cc: linuxppc-embedded
In-Reply-To: <20050126185350.20232.qmail@web53804.mail.yahoo.com>
On Jan 26, 2005, at 10:53 AM, annamaya wrote:
> Can someone tell me if the BDI will be able to catch
> all different kinds of exceptions/interrupts on the
> MPC82xx without requiring any special register
> programming? I am unable to find anything that that
> resembles the DER register on the MPC8280.
The BDI2000 works very nicely on 82xx processors.
The 82xx debug unit is the standard COP interface,
completely different from the 8xx debug interface.
Stop looking for a DER on the 82xx, plug in the
BDI2000 and use it. Make sure you understand all
of the features of the BDI2000, as even on the 8xx
you should not be worrying about the DER. Let the
BDI2000 configure all of that accordingly based upon
what you are asking it to do.
-- Dan
^ permalink raw reply
* Re: [PATCH] oprofile: falling back on timer interrupt mode
From: Olaf Hering @ 2005-01-26 19:05 UTC (permalink / raw)
To: Linux Kernel Mailing List, Akinobu Mita; +Cc: linuxppc-dev
In-Reply-To: <200501260512.j0Q5CAhd016730@hera.kernel.org>
On Wed, Jan 26, Linux Kernel Mailing List wrote:
> ChangeSet 1.2038, 2005/01/25 20:31:01-08:00, amgta@yacht.ocn.ne.jp
>
> [PATCH] oprofile: falling back on timer interrupt mode
>
> arch/alpha/oprofile/common.c | 6 ++++--
> arch/arm/oprofile/common.c | 7 +++++--
> arch/arm/oprofile/init.c | 8 ++++++--
> arch/i386/oprofile/init.c | 4 +++-
> arch/ia64/oprofile/init.c | 8 ++++++--
> arch/m32r/oprofile/init.c | 3 ++-
> arch/parisc/oprofile/init.c | 3 ++-
> arch/ppc64/oprofile/common.c | 6 ++++--
> arch/s390/oprofile/init.c | 3 ++-
> arch/sh/oprofile/op_model_null.c | 3 ++-
> arch/sparc64/oprofile/init.c | 3 ++-
> drivers/oprofile/oprof.c | 6 +++---
> include/linux/oprofile.h | 2 +-
> 13 files changed, 42 insertions(+), 20 deletions(-)
This misses arch/ppc
^ permalink raw reply
* Re: Is there a DER for the MPC82xx?
From: annamaya @ 2005-01-26 19:15 UTC (permalink / raw)
To: Dan Malek; +Cc: linuxppc-embedded
In-Reply-To: <BD936D78-6FCC-11D9-A0FB-003065F9B7DC@embeddededge.com>
Dan,
Thanks for the reply. I do not understand the standard
COP interface very well, and hence the confusion.
On the 8xx, I had to worry about the DER cause that
was exactly what was set in the config file early on.
For example, if I did not have the external interrupt
bit set, I could not see that an external reset signal
was being asserted. Instead, all I would see is a
machine check somewhere else in the code.
I guess I am fine on the 82xx then. Great!
--- Dan Malek <dan@embeddededge.com> wrote:
>
> On Jan 26, 2005, at 10:53 AM, annamaya wrote:
>
> > Can someone tell me if the BDI will be able to
> catch
> > all different kinds of exceptions/interrupts on
> the
> > MPC82xx without requiring any special register
> > programming? I am unable to find anything that
> that
> > resembles the DER register on the MPC8280.
>
> The BDI2000 works very nicely on 82xx processors.
> The 82xx debug unit is the standard COP interface,
> completely different from the 8xx debug interface.
> Stop looking for a DER on the 82xx, plug in the
> BDI2000 and use it. Make sure you understand all
> of the features of the BDI2000, as even on the 8xx
> you should not be worrying about the DER. Let the
> BDI2000 configure all of that accordingly based upon
> what you are asking it to do.
>
>
> -- Dan
>
>
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^ permalink raw reply
* Re: Is there a DER for the MPC82xx?
From: Mark Chambers @ 2005-01-26 20:33 UTC (permalink / raw)
To: Dan Malek, annamaya; +Cc: linuxppc-embedded
In-Reply-To: <BD936D78-6FCC-11D9-A0FB-003065F9B7DC@embeddededge.com>
From: "Dan Malek" <dan@embeddededge.com>
>
> On Jan 26, 2005, at 10:53 AM, annamaya wrote:
>
> > Can someone tell me if the BDI will be able to catch
> > all different kinds of exceptions/interrupts on the
> > MPC82xx without requiring any special register
> > programming? I am unable to find anything that that
> > resembles the DER register on the MPC8280.
>
> The BDI2000 works very nicely on 82xx processors.
> The 82xx debug unit is the standard COP interface,
> completely different from the 8xx debug interface.
> Stop looking for a DER on the 82xx, plug in the
> BDI2000 and use it. Make sure you understand all
> of the features of the BDI2000, as even on the 8xx
> you should not be worrying about the DER. Let the
> BDI2000 configure all of that accordingly based upon
> what you are asking it to do.
>
>
Well, the DER lets you look for multiple conditions at
once. Your program is blowing up, the memory is
getting trashed and you don't even know if the hardware
is valid - that's where BDM really shines. I don't see
where COP let's you do the equivalent of setting a
bunch of bits in the DER, so please enlighten us if
we're missing it!
Mark Chambers
P.S. I've read the BDI manual - I don't see it. My manual
says the BDI can only set one hardware breakpoint, and
stuff like VECTOR CATCH assumes valid memory.
^ permalink raw reply
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