* Re: [PATCH] Ebony's UBoot awareness
From: Matt Porter @ 2005-02-24 22:27 UTC (permalink / raw)
To: Shawn Jin; +Cc: ppcembed
In-Reply-To: <c3d0340b05022413437aa5b729@mail.gmail.com>
On Thu, Feb 24, 2005 at 01:43:57PM -0800, Shawn Jin wrote:
> Hi Matt,
>
> > Can you use the ocotea/luan approach and create an openbios stub
> > in arch/ppc/boot to create the bi_enetaddr infos? The PIBS stub
> > in arch/ppc/boot does this so we can have one path in the platform
> > file that parses the bootinfos.
>
> I'd like to help if I can follow you. What does PIBS stand for? What
> is the ocotea/luan approach you were talking about? I thought I
> followed the ocotea approach to set up mac addresses.
PIBS is the firmware on all post 440GP ref brds from IBM/AMCC. Take
a look at how both the stock PIBS f/w and U-Boot are supported on
Ocotea by reviewing arch/ppc/boot/simple/pibs.c and
arch/ppc/platforms/4xx/ocotea.c
In this implementation, ocotea.c always expects the enetaddrs in
a birec. Whether they come direct from U-Boot or from some massaging
by the arch/ppc/boot/simple/pibs.c shim doesn't matter. I suggest
following that model which requires creating something like
arch/ppc/boot/simple/openbios.c with a strong symboled load_kernel()
routine that builds the bi-rec for the stock firmware case.
This hides the ugliness in the boot wrapper glue.
-Matt
^ permalink raw reply
* Re: iBook G4: first wakeup has black screen
From: Olof Johansson @ 2005-02-24 21:50 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20050216181430.GA27031@austin.ibm.com>
On Wed, Feb 16, 2005 at 12:14:30PM -0600, Olof Johansson wrote:
> I've noticed one thing though: The very first time I wake the machine up
> after sleeping the screen is dark (backlight off?). If I put it to sleep
> and wake it up again everything goes back to normal.
... seems fixed in 2.6.11-rc5, at least I have yet to reproduce it.
-Olof
^ permalink raw reply
* Re: [PATCH] Ebony's UBoot awareness
From: Shawn Jin @ 2005-02-24 21:43 UTC (permalink / raw)
To: Matt Porter; +Cc: ppcembed
In-Reply-To: <20050223142426.B13087@cox.net>
Hi Matt,
> Can you use the ocotea/luan approach and create an openbios stub
> in arch/ppc/boot to create the bi_enetaddr infos? The PIBS stub
> in arch/ppc/boot does this so we can have one path in the platform
> file that parses the bootinfos.
I'd like to help if I can follow you. What does PIBS stand for? What
is the ocotea/luan approach you were talking about? I thought I
followed the ocotea approach to set up mac addresses.
Thanks,
-Shawn.
^ permalink raw reply
* Re: [PATCH 2.6.10-rc3][PPC32] Fix Motorola PReP (PowerstackII Utah) PCI IRQ map
From: Meelis Roos @ 2005-02-24 20:51 UTC (permalink / raw)
To: Sven Luther
Cc: Tom Rini, Sven Hartge, Kernel Mailing List, Christian Kujau,
linuxppc-dev
In-Reply-To: <20050224170150.GA7746@pegasos>
> Then just dd your /boot/vmlinuz-2.6.10-powerpc to your prep partition, or
> better yet to a tftp server, and try it out. If the scsi problems are there,
> can you fill a bug report against kernel-source-2.6.10 ?
Thanks for the new kernel. Just filed a bug report on
kernel-source-2.6.10.
> You may probably want also to modify /etc/mkinitrd/mkinitrd:MODULES_DEP to dep
> instead of MOST, or you may hit size problems with your initrd, i would be
> interested in knowing that.
It worked without changing the module list, with 5.2M resulting vmlinuz.
--
Meelis Roos (mroos@linux.ee)
^ permalink raw reply
* [PATCH] ppc32: Move from using #define SVR_ to cur_ppc_sys_spec name for 85xx platform
From: Kumar Gala @ 2005-02-24 20:22 UTC (permalink / raw)
To: akpm; +Cc: linuxppc-embedded
Andrew,
This patch is for post 2.6.11 and supercedes previous patches on this
subject (excluding the proper final whitespace patch)
Removes explicit defines for SVR_85xx and use the information in the
ppc_sys_specs table in platform code. Changed the ppc_sys_name strings to
be a bit more generic so we have a bit more flexilibity when we display
them.
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
diff -Nru a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c
--- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c 2005-02-24 10:57:54 -06:00
+++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c 2005-02-24 10:57:54 -06:00
@@ -43,6 +43,7 @@
#include <asm/mpc85xx.h>
#include <asm/irq.h>
#include <asm/immap_85xx.h>
+#include <asm/ppc_sys.h>
#include <mm/mmu_decl.h>
@@ -128,19 +129,9 @@
pvid = mfspr(PVR);
svid = mfspr(SVR);
+ seq_printf(m, "chip\t\t: MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
-
- switch (svid & 0xffff0000) {
- case SVR_8540:
- seq_printf(m, "Machine\t\t: mpc8540ads\n");
- break;
- case SVR_8560:
- seq_printf(m, "Machine\t\t: mpc8560ads\n");
- break;
- default:
- seq_printf(m, "Machine\t\t: unknown\n");
- break;
- }
+ seq_printf(m, "Machine\t\t: mpc%sads\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
seq_printf(m, "SVR\t\t: 0x%x\n", svid);
diff -Nru a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c 2005-02-24 10:57:54 -06:00
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c 2005-02-24 10:57:54 -06:00
@@ -145,8 +145,9 @@
pvid = mfspr(PVR);
svid = mfspr(SVR);
+ seq_printf(m, "chip\t\t: MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
- seq_printf(m, "Machine\t\t: CDS (%x)\n", cadmus[CM_VER]);
+ seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]);
seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
seq_printf(m, "SVR\t\t: 0x%x\n", svid);
diff -Nru a/arch/ppc/platforms/85xx/mpc85xx_sys.c b/arch/ppc/platforms/85xx/mpc85xx_sys.c
--- a/arch/ppc/platforms/85xx/mpc85xx_sys.c 2005-02-24 10:57:54 -06:00
+++ b/arch/ppc/platforms/85xx/mpc85xx_sys.c 2005-02-24 10:57:54 -06:00
@@ -21,7 +21,7 @@
struct ppc_sys_spec *cur_ppc_sys_spec;
struct ppc_sys_spec ppc_sys_specs[] = {
{
- .ppc_sys_name = "MPC8540",
+ .ppc_sys_name = "8540",
.mask = 0xFFFF0000,
.value = 0x80300000,
.num_devices = 10,
@@ -33,7 +33,7 @@
},
},
{
- .ppc_sys_name = "MPC8560",
+ .ppc_sys_name = "8560",
.mask = 0xFFFF0000,
.value = 0x80700000,
.num_devices = 19,
@@ -49,7 +49,7 @@
},
},
{
- .ppc_sys_name = "MPC8541",
+ .ppc_sys_name = "8541",
.mask = 0xFFFF0000,
.value = 0x80720000,
.num_devices = 13,
@@ -63,7 +63,7 @@
},
},
{
- .ppc_sys_name = "MPC8541E",
+ .ppc_sys_name = "8541E",
.mask = 0xFFFF0000,
.value = 0x807A0000,
.num_devices = 14,
@@ -77,7 +77,7 @@
},
},
{
- .ppc_sys_name = "MPC8555",
+ .ppc_sys_name = "8555",
.mask = 0xFFFF0000,
.value = 0x80710000,
.num_devices = 20,
@@ -94,7 +94,7 @@
},
},
{
- .ppc_sys_name = "MPC8555E",
+ .ppc_sys_name = "8555E",
.mask = 0xFFFF0000,
.value = 0x80790000,
.num_devices = 21,
diff -Nru a/arch/ppc/platforms/85xx/sbc85xx.c b/arch/ppc/platforms/85xx/sbc85xx.c
--- a/arch/ppc/platforms/85xx/sbc85xx.c 2005-02-24 10:57:54 -06:00
+++ b/arch/ppc/platforms/85xx/sbc85xx.c 2005-02-24 10:57:54 -06:00
@@ -42,6 +42,7 @@
#include <asm/mpc85xx.h>
#include <asm/irq.h>
#include <asm/immap_85xx.h>
+#include <asm/ppc_sys.h>
#include <mm/mmu_decl.h>
@@ -128,19 +129,9 @@
pvid = mfspr(PVR);
svid = mfspr(SVR);
+ seq_printf(m, "chip\t\t: MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "Vendor\t\t: Wind River\n");
-
- switch (svid & 0xffff0000) {
- case SVR_8540:
- seq_printf(m, "Machine\t\t: hhmmm, this board isn't made yet!\n");
- break;
- case SVR_8560:
- seq_printf(m, "Machine\t\t: SBC8560\n");
- break;
- default:
- seq_printf(m, "Machine\t\t: unknown\n");
- break;
- }
+ seq_printf(m, "Machine\t\t: SBC%s\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
seq_printf(m, "SVR\t\t: 0x%x\n", svid);
diff -Nru a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c
--- a/arch/ppc/platforms/85xx/stx_gp3.c 2005-02-24 10:57:54 -06:00
+++ b/arch/ppc/platforms/85xx/stx_gp3.c 2005-02-24 10:57:54 -06:00
@@ -34,8 +34,10 @@
#include <linux/root_dev.h>
#include <linux/seq_file.h>
#include <linux/serial.h>
+#include <linux/initrd.h>
#include <linux/module.h>
#include <linux/fsl_devices.h>
+#include <linux/interrupt.h>
#include <asm/system.h>
#include <asm/pgtable.h>
@@ -266,19 +268,9 @@
memsize = total_memory;
+ seq_printf(m, "chip\t\t: MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "Vendor\t\t: RPC Electronics STx \n");
-
- switch (svid & 0xffff0000) {
- case SVR_8540:
- seq_printf(m, "Machine\t\t: GP3 - MPC8540\n");
- break;
- case SVR_8560:
- seq_printf(m, "Machine\t\t: GP3 - MPC8560\n");
- break;
- default:
- seq_printf(m, "Machine\t\t: unknown\n");
- break;
- }
+ seq_printf(m, "Machine\t\t: GP3 - MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000,
freq % 1000000);
seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
diff -Nru a/include/asm-ppc/reg.h b/include/asm-ppc/reg.h
--- a/include/asm-ppc/reg.h 2005-02-24 10:57:54 -06:00
+++ b/include/asm-ppc/reg.h 2005-02-24 10:57:54 -06:00
@@ -488,12 +488,6 @@
#define PVR_8245 0x80811014
#define PVR_8260 PVR_8240
-/* System Version Numbers */
-#define SVR_8540 0x80300000
-#define SVR_8541E 0x807A0000
-#define SVR_8555E 0x80790000
-#define SVR_8560 0x80700000
-
#if 0
/* Segment Registers */
#define SR0 0
^ permalink raw reply
* [PATCH] [FINAL] ppc32: fix whitespace for 85xx CDS common platform
From: Kumar Gala @ 2005-02-24 19:19 UTC (permalink / raw)
To: akpm; +Cc: linuxppc-embedded
Andrew,
I clearly need a vacation, thankful I'm headed to las vegas today for one.
Seeing as I sent the wrong version of the patch in the last email, please
ignore it. This one is correct, and hopefully the final time I will send
this.
Here is the cleaned up version of the whitespace patch. Apply this first
for post 2.6.11.
Fix whitespace in arch/ppc/platforms/85xx/mpc85xx_cds_common.c
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
diff -Nru a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c 2005-02-24 10:45:45 -06:00
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c 2005-02-24 10:45:45 -06:00
@@ -73,60 +73,60 @@
/* Internal interrupts are all Level Sensitive, and Positive Polarity */
static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
#if defined(CONFIG_PCI)
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
#else
- 0x0, /* External 0: */
- 0x0, /* External 1: */
- 0x0, /* External 2: */
- 0x0, /* External 3: */
-#endif
- 0x0, /* External 4: */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
- 0x0, /* External 6: */
- 0x0, /* External 7: */
- 0x0, /* External 8: */
- 0x0, /* External 9: */
- 0x0, /* External 10: */
+ 0x0, /* External 0: */
+ 0x0, /* External 1: */
+ 0x0, /* External 2: */
+ 0x0, /* External 3: */
+#endif
+ 0x0, /* External 4: */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
+ 0x0, /* External 6: */
+ 0x0, /* External 7: */
+ 0x0, /* External 8: */
+ 0x0, /* External 9: */
+ 0x0, /* External 10: */
#if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
#else
- 0x0, /* External 11: */
+ 0x0, /* External 11: */
#endif
};
@@ -134,31 +134,31 @@
int
mpc85xx_cds_show_cpuinfo(struct seq_file *m)
{
- uint pvid, svid, phid1;
- uint memsize = total_memory;
- bd_t *binfo = (bd_t *) __res;
- unsigned int freq;
+ uint pvid, svid, phid1;
+ uint memsize = total_memory;
+ bd_t *binfo = (bd_t *) __res;
+ unsigned int freq;
- /* get the core frequency */
- freq = binfo->bi_intfreq;
+ /* get the core frequency */
+ freq = binfo->bi_intfreq;
- pvid = mfspr(PVR);
- svid = mfspr(SVR);
+ pvid = mfspr(PVR);
+ svid = mfspr(SVR);
- seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
+ seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
seq_printf(m, "Machine\t\t: CDS (%x)\n", cadmus[CM_VER]);
seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
- seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
- seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+ seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
+ seq_printf(m, "SVR\t\t: 0x%x\n", svid);
- /* Display cpu Pll setting */
- phid1 = mfspr(HID1);
- seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
+ /* Display cpu Pll setting */
+ phid1 = mfspr(HID1);
+ seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
- /* Display the amount of memory */
- seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+ /* Display the amount of memory */
+ seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
- return 0;
+ return 0;
}
#ifdef CONFIG_CPM2
@@ -185,21 +185,21 @@
int i;
#endif
- /* Determine the Physical Address of the OpenPIC regs */
- phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
- OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
- OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
- OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
-
- /* Skip reserved space and internal sources */
- openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
- /* Map PIC IRQs 0-11 */
- openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
-
- /* we let openpic interrupts starting from an offset, to
- * leave space for cascading interrupts underneath.
- */
- openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
+ /* Determine the Physical Address of the OpenPIC regs */
+ phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
+ OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
+ OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
+ OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
+
+ /* Skip reserved space and internal sources */
+ openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
+ /* Map PIC IRQs 0-11 */
+ openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
+
+ /* we let openpic interrupts starting from an offset, to
+ * leave space for cascading interrupts underneath.
+ */
+ openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
#ifdef CONFIG_CPM2
/* disable all CPM interupts */
@@ -219,7 +219,7 @@
setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
#endif
- return;
+ return;
}
#ifdef CONFIG_PCI
@@ -278,8 +278,8 @@
}
}
-#define ARCADIA_HOST_BRIDGE_IDSEL 17
-#define ARCADIA_2ND_BRIDGE_IDSEL 3
+#define ARCADIA_HOST_BRIDGE_IDSEL 17
+#define ARCADIA_2ND_BRIDGE_IDSEL 3
extern int mpc85xx_pci1_last_busno;
@@ -289,7 +289,7 @@
if (bus == 0 && PCI_SLOT(devfn) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
#ifdef CONFIG_85xx_PCI2
- if (mpc85xx_pci1_last_busno)
+ if (mpc85xx_pci1_last_busno)
if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
#endif
@@ -311,14 +311,14 @@
static void __init
mpc85xx_cds_setup_arch(void)
{
- bd_t *binfo = (bd_t *) __res;
- unsigned int freq;
+ bd_t *binfo = (bd_t *) __res;
+ unsigned int freq;
struct gianfar_platform_data *pdata;
- /* get the core frequency */
- freq = binfo->bi_intfreq;
+ /* get the core frequency */
+ freq = binfo->bi_intfreq;
- printk("mpc85xx_cds_setup_arch\n");
+ printk("mpc85xx_cds_setup_arch\n");
#ifdef CONFIG_CPM2
cpm2_reset();
@@ -328,17 +328,17 @@
cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
- /* Set loops_per_jiffy to a half-way reasonable value,
- for use until calibrate_delay gets called. */
- loops_per_jiffy = freq / HZ;
+ /* Set loops_per_jiffy to a half-way reasonable value,
+ for use until calibrate_delay gets called. */
+ loops_per_jiffy = freq / HZ;
#ifdef CONFIG_PCI
- /* setup PCI host bridges */
- mpc85xx_setup_hose();
+ /* setup PCI host bridges */
+ mpc85xx_setup_hose();
#endif
#ifdef CONFIG_SERIAL_8250
- mpc85xx_early_serial_map();
+ mpc85xx_early_serial_map();
#endif
#ifdef CONFIG_SERIAL_TEXT_DEBUG
@@ -366,14 +366,14 @@
#ifdef CONFIG_BLK_DEV_INITRD
- if (initrd_start)
- ROOT_DEV = Root_RAM0;
- else
+ if (initrd_start)
+ ROOT_DEV = Root_RAM0;
+ else
#endif
#ifdef CONFIG_ROOT_NFS
- ROOT_DEV = Root_NFS;
+ ROOT_DEV = Root_NFS;
#else
- ROOT_DEV = Root_HDA1;
+ ROOT_DEV = Root_HDA1;
#endif
}
@@ -382,18 +382,18 @@
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
- /* parse_bootinfo must always be called first */
- parse_bootinfo(find_bootinfo());
+ /* parse_bootinfo must always be called first */
+ parse_bootinfo(find_bootinfo());
- /*
- * If we were passed in a board information, copy it into the
- * residual data area.
- */
- if (r3) {
- memcpy((void *) __res, (void *) (r3 + KERNELBASE),
- sizeof (bd_t));
+ /*
+ * If we were passed in a board information, copy it into the
+ * residual data area.
+ */
+ if (r3) {
+ memcpy((void *) __res, (void *) (r3 + KERNELBASE),
+ sizeof (bd_t));
- }
+ }
#ifdef CONFIG_SERIAL_TEXT_DEBUG
{
bd_t *binfo = (bd_t *) __res;
@@ -401,7 +401,7 @@
/* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
settlbcam(NUM_TLBCAMS - 1, binfo->bi_immr_base,
- binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
+ binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
memset(&p, 0, sizeof (p));
p.iotype = SERIAL_IO_MEM;
@@ -420,49 +420,49 @@
#endif
#if defined(CONFIG_BLK_DEV_INITRD)
- /*
- * If the init RAM disk has been configured in, and there's a valid
- * starting address for it, set it up.
- */
- if (r4) {
- initrd_start = r4 + KERNELBASE;
- initrd_end = r5 + KERNELBASE;
- }
-#endif /* CONFIG_BLK_DEV_INITRD */
-
- /* Copy the kernel command line arguments to a safe place. */
-
- if (r6) {
- *(char *) (r7 + KERNELBASE) = 0;
- strcpy(cmd_line, (char *) (r6 + KERNELBASE));
- }
+ /*
+ * If the init RAM disk has been configured in, and there's a valid
+ * starting address for it, set it up.
+ */
+ if (r4) {
+ initrd_start = r4 + KERNELBASE;
+ initrd_end = r5 + KERNELBASE;
+ }
+#endif /* CONFIG_BLK_DEV_INITRD */
+
+ /* Copy the kernel command line arguments to a safe place. */
+
+ if (r6) {
+ *(char *) (r7 + KERNELBASE) = 0;
+ strcpy(cmd_line, (char *) (r6 + KERNELBASE));
+ }
identify_ppc_sys_by_id(mfspr(SVR));
- /* setup the PowerPC module struct */
- ppc_md.setup_arch = mpc85xx_cds_setup_arch;
- ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
-
- ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
- ppc_md.get_irq = openpic_get_irq;
-
- ppc_md.restart = mpc85xx_restart;
- ppc_md.power_off = mpc85xx_power_off;
- ppc_md.halt = mpc85xx_halt;
-
- ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
-
- ppc_md.time_init = NULL;
- ppc_md.set_rtc_time = NULL;
- ppc_md.get_rtc_time = NULL;
- ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
+ /* setup the PowerPC module struct */
+ ppc_md.setup_arch = mpc85xx_cds_setup_arch;
+ ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
+
+ ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
+ ppc_md.get_irq = openpic_get_irq;
+
+ ppc_md.restart = mpc85xx_restart;
+ ppc_md.power_off = mpc85xx_power_off;
+ ppc_md.halt = mpc85xx_halt;
+
+ ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
+
+ ppc_md.time_init = NULL;
+ ppc_md.set_rtc_time = NULL;
+ ppc_md.get_rtc_time = NULL;
+ ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
- ppc_md.progress = gen550_progress;
+ ppc_md.progress = gen550_progress;
#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
- if (ppc_md.progress)
- ppc_md.progress("mpc85xx_cds_init(): exit", 0);
+ if (ppc_md.progress)
+ ppc_md.progress("mpc85xx_cds_init(): exit", 0);
- return;
+ return;
}
^ permalink raw reply
* [PATCH] ppc32: fix whitespace for 85xx CDS common platform
From: Kumar Gala @ 2005-02-24 19:05 UTC (permalink / raw)
To: akpm; +Cc: linuxppc-embedded
Andrew,
Here is the cleaned up version of the whitespace patch. Apply this
first for post 2.6.11.
Fix whitespace in arch/ppc/platforms/85xx/mpc85xx_cds_common.c
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
---
diff -Nru a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c 2005-02-22 13:35:18 -06:00
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c 2005-02-22 13:35:18 -06:00
@@ -73,60 +73,60 @@
/* Internal interrupts are all Level Sensitive, and Positive Polarity */
static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0: L2 Cache */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1: ECM */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2: DDR DRAM */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3: LBIU */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4: DMA 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5: DMA 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6: DMA 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7: DMA 3 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8: PCI/PCI-X */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9: RIO Inbound Port Write Error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10: RIO Doorbell Inbound */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11: RIO Outbound Message */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12: RIO Inbound Message */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13: TSEC 0 Transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14: TSEC 0 Receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18: TSEC 0 Receive/Transmit Error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19: TSEC 1 Transmit */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20: TSEC 1 Receive */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24: TSEC 1 Receive/Transmit Error */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25: Fast Ethernet */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26: DUART */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27: I2C */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28: Performance Monitor */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29: Unused */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30: CPM */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31: Unused */
#if defined(CONFIG_PCI)
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
#else
- 0x0, /* External 0: */
- 0x0, /* External 1: */
- 0x0, /* External 2: */
- 0x0, /* External 3: */
-#endif
- 0x0, /* External 4: */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
- 0x0, /* External 6: */
- 0x0, /* External 7: */
- 0x0, /* External 8: */
- 0x0, /* External 9: */
- 0x0, /* External 10: */
+ 0x0, /* External 0: */
+ 0x0, /* External 1: */
+ 0x0, /* External 2: */
+ 0x0, /* External 3: */
+#endif
+ 0x0, /* External 4: */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
+ 0x0, /* External 6: */
+ 0x0, /* External 7: */
+ 0x0, /* External 8: */
+ 0x0, /* External 9: */
+ 0x0, /* External 10: */
#if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
#else
- 0x0, /* External 11: */
+ 0x0, /* External 11: */
#endif
};
@@ -134,32 +134,32 @@
int
mpc85xx_cds_show_cpuinfo(struct seq_file *m)
{
- uint pvid, svid, phid1;
- uint memsize = total_memory;
- bd_t *binfo = (bd_t *) __res;
- unsigned int freq;
+ uint pvid, svid, phid1;
+ uint memsize = total_memory;
+ bd_t *binfo = (bd_t *) __res;
+ unsigned int freq;
- /* get the core frequency */
- freq = binfo->bi_intfreq;
+ /* get the core frequency */
+ freq = binfo->bi_intfreq;
- pvid = mfspr(PVR);
- svid = mfspr(SVR);
+ pvid = mfspr(PVR);
+ svid = mfspr(SVR);
seq_printf(m, "chip\t\t: %s\n", cur_ppc_sys_spec->ppc_sys_name);
- seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
+ seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
seq_printf(m, "Machine\t\t: CDS (%x)\n", cadmus[CM_VER]);
seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
- seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
- seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+ seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
+ seq_printf(m, "SVR\t\t: 0x%x\n", svid);
- /* Display cpu Pll setting */
- phid1 = mfspr(HID1);
- seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
+ /* Display cpu Pll setting */
+ phid1 = mfspr(HID1);
+ seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
- /* Display the amount of memory */
- seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+ /* Display the amount of memory */
+ seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
- return 0;
+ return 0;
}
#ifdef CONFIG_CPM2
@@ -186,21 +186,21 @@
int i;
#endif
- /* Determine the Physical Address of the OpenPIC regs */
- phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
- OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
- OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
- OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
-
- /* Skip reserved space and internal sources */
- openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
- /* Map PIC IRQs 0-11 */
- openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
-
- /* we let openpic interrupts starting from an offset, to
- * leave space for cascading interrupts underneath.
- */
- openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
+ /* Determine the Physical Address of the OpenPIC regs */
+ phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
+ OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
+ OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
+ OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
+
+ /* Skip reserved space and internal sources */
+ openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
+ /* Map PIC IRQs 0-11 */
+ openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
+
+ /* we let openpic interrupts starting from an offset, to
+ * leave space for cascading interrupts underneath.
+ */
+ openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
#ifdef CONFIG_CPM2
/* disable all CPM interupts */
@@ -220,7 +220,7 @@
setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
#endif
- return;
+ return;
}
#ifdef CONFIG_PCI
@@ -279,8 +279,8 @@
}
}
-#define ARCADIA_HOST_BRIDGE_IDSEL 17
-#define ARCADIA_2ND_BRIDGE_IDSEL 3
+#define ARCADIA_HOST_BRIDGE_IDSEL 17
+#define ARCADIA_2ND_BRIDGE_IDSEL 3
extern int mpc85xx_pci1_last_busno;
@@ -290,7 +290,7 @@
if (bus == 0 && PCI_SLOT(devfn) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
#ifdef CONFIG_85xx_PCI2
- if (mpc85xx_pci1_last_busno)
+ if (mpc85xx_pci1_last_busno)
if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0)
return PCIBIOS_DEVICE_NOT_FOUND;
#endif
@@ -312,14 +312,14 @@
static void __init
mpc85xx_cds_setup_arch(void)
{
- bd_t *binfo = (bd_t *) __res;
- unsigned int freq;
+ bd_t *binfo = (bd_t *) __res;
+ unsigned int freq;
struct gianfar_platform_data *pdata;
- /* get the core frequency */
- freq = binfo->bi_intfreq;
+ /* get the core frequency */
+ freq = binfo->bi_intfreq;
- printk("mpc85xx_cds_setup_arch\n");
+ printk("mpc85xx_cds_setup_arch\n");
#ifdef CONFIG_CPM2
cpm2_reset();
@@ -329,17 +329,17 @@
cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
- /* Set loops_per_jiffy to a half-way reasonable value,
- for use until calibrate_delay gets called. */
- loops_per_jiffy = freq / HZ;
+ /* Set loops_per_jiffy to a half-way reasonable value,
+ for use until calibrate_delay gets called. */
+ loops_per_jiffy = freq / HZ;
#ifdef CONFIG_PCI
- /* setup PCI host bridges */
- mpc85xx_setup_hose();
+ /* setup PCI host bridges */
+ mpc85xx_setup_hose();
#endif
#ifdef CONFIG_SERIAL_8250
- mpc85xx_early_serial_map();
+ mpc85xx_early_serial_map();
#endif
#ifdef CONFIG_SERIAL_TEXT_DEBUG
@@ -367,14 +367,14 @@
#ifdef CONFIG_BLK_DEV_INITRD
- if (initrd_start)
- ROOT_DEV = Root_RAM0;
- else
+ if (initrd_start)
+ ROOT_DEV = Root_RAM0;
+ else
#endif
#ifdef CONFIG_ROOT_NFS
- ROOT_DEV = Root_NFS;
+ ROOT_DEV = Root_NFS;
#else
- ROOT_DEV = Root_HDA1;
+ ROOT_DEV = Root_HDA1;
#endif
}
@@ -383,18 +383,18 @@
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
- /* parse_bootinfo must always be called first */
- parse_bootinfo(find_bootinfo());
+ /* parse_bootinfo must always be called first */
+ parse_bootinfo(find_bootinfo());
- /*
- * If we were passed in a board information, copy it into the
- * residual data area.
- */
- if (r3) {
- memcpy((void *) __res, (void *) (r3 + KERNELBASE),
- sizeof (bd_t));
+ /*
+ * If we were passed in a board information, copy it into the
+ * residual data area.
+ */
+ if (r3) {
+ memcpy((void *) __res, (void *) (r3 + KERNELBASE),
+ sizeof (bd_t));
- }
+ }
#ifdef CONFIG_SERIAL_TEXT_DEBUG
{
bd_t *binfo = (bd_t *) __res;
@@ -402,7 +402,7 @@
/* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
settlbcam(NUM_TLBCAMS - 1, binfo->bi_immr_base,
- binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
+ binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
memset(&p, 0, sizeof (p));
p.iotype = SERIAL_IO_MEM;
@@ -421,49 +421,49 @@
#endif
#if defined(CONFIG_BLK_DEV_INITRD)
- /*
- * If the init RAM disk has been configured in, and there's a valid
- * starting address for it, set it up.
- */
- if (r4) {
- initrd_start = r4 + KERNELBASE;
- initrd_end = r5 + KERNELBASE;
- }
-#endif /* CONFIG_BLK_DEV_INITRD */
-
- /* Copy the kernel command line arguments to a safe place. */
-
- if (r6) {
- *(char *) (r7 + KERNELBASE) = 0;
- strcpy(cmd_line, (char *) (r6 + KERNELBASE));
- }
+ /*
+ * If the init RAM disk has been configured in, and there's a valid
+ * starting address for it, set it up.
+ */
+ if (r4) {
+ initrd_start = r4 + KERNELBASE;
+ initrd_end = r5 + KERNELBASE;
+ }
+#endif /* CONFIG_BLK_DEV_INITRD */
+
+ /* Copy the kernel command line arguments to a safe place. */
+
+ if (r6) {
+ *(char *) (r7 + KERNELBASE) = 0;
+ strcpy(cmd_line, (char *) (r6 + KERNELBASE));
+ }
identify_ppc_sys_by_id(mfspr(SVR));
- /* setup the PowerPC module struct */
- ppc_md.setup_arch = mpc85xx_cds_setup_arch;
- ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
-
- ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
- ppc_md.get_irq = openpic_get_irq;
-
- ppc_md.restart = mpc85xx_restart;
- ppc_md.power_off = mpc85xx_power_off;
- ppc_md.halt = mpc85xx_halt;
-
- ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
-
- ppc_md.time_init = NULL;
- ppc_md.set_rtc_time = NULL;
- ppc_md.get_rtc_time = NULL;
- ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
+ /* setup the PowerPC module struct */
+ ppc_md.setup_arch = mpc85xx_cds_setup_arch;
+ ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
+
+ ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
+ ppc_md.get_irq = openpic_get_irq;
+
+ ppc_md.restart = mpc85xx_restart;
+ ppc_md.power_off = mpc85xx_power_off;
+ ppc_md.halt = mpc85xx_halt;
+
+ ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
+
+ ppc_md.time_init = NULL;
+ ppc_md.set_rtc_time = NULL;
+ ppc_md.get_rtc_time = NULL;
+ ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
#if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
- ppc_md.progress = gen550_progress;
+ ppc_md.progress = gen550_progress;
#endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
- if (ppc_md.progress)
- ppc_md.progress("mpc85xx_cds_init(): exit", 0);
+ if (ppc_md.progress)
+ ppc_md.progress("mpc85xx_cds_init(): exit", 0);
- return;
+ return;
}
^ permalink raw reply
* Re: [PATCH][PPC32] mv64x60 updates
From: Dale Farnsworth @ 2005-02-24 17:24 UTC (permalink / raw)
To: Sven Luther, linuxppc-embedded; +Cc: Nicolas DET
In-Reply-To: <20050224160411.GA11197@pegasos>
On Thu, Feb 24, 2005 at 04:04:11PM +0000, Sven Luther wrote:
> > >I am a bit bewildered by what you are doing here. How does this mv64x60
> > >code relate to the mv643xx_eth driver from the mips folk ?
>
> [...]
>
> On Thu, Feb 24, 2005 at 08:28:56AM -0700, Mark A. Greer wrote:
> > has spent a lot of time making it work on both MIPS and PPC. The code
> > you see in the mv64x60.c file is a part of that. I believe that Dale's
>
> Ok, so the code in question is in addition to the existing driver from the
> mips guys and works with it ? I had the impression that it was a separate
> driver development or something.
The code in mv64x60.c is related to but separate from the ethernet driver.
It is platform-specific code that passes register addresses, irqs,
mac addrs, phy addrs, etc. to the arch-agnostic ethernet driver.
All of my changes to the mv643xx ethernet driver have been posted to
LKML or the netdev list. I have removed all arch-specific code from
the ethernet driver itself.
> Ok. Do you know if Dale's patches are available separatedly while they are not
> yet in mainline, so Nicolas Det can work on them and make sure they also work
> on the Pegasos board, which is not an embedded board but from the chrp
See bk://dfarnsworth.bkbits.net/linux-2.5-mv643xx-enet
> lineage. Nicolas already did some mv643xx ethernet driver work last summer,
> but apparently had trouble integrating this in the mainline kernel, and it
I'm sorry I wasn't aware of Nicolas' work on the driver.
> seems his work has now been redone by Dale or something. Do you know who the
> right person to communicate with about this would be ? The MIPS folk didn't
> reply to any of our mails about this subject.
Sounds familiar. Fortunately, Jeff Garzik picked up my changes.
I would appreciate feedback from you or Nicolas on the current driver.
Thanks,
-Dale
^ permalink raw reply
* Re: [PATCH][PPC32] mv64x60 updates
From: Sven Luther @ 2005-02-24 17:05 UTC (permalink / raw)
To: Mark A. Greer; +Cc: nd, Embedded PPC Linux list
In-Reply-To: <421E0A13.7060309@mvista.com>
On Thu, Feb 24, 2005 at 10:08:35AM -0700, Mark A. Greer wrote:
> Sven Luther wrote:
> >Ok. Do you know if Dale's patches are available separatedly while they are
> >not
> >yet in mainline, so Nicolas Det can work on them and make sure they also
> >work
> >on the Pegasos board, which is not an embedded board but from the chrp
> >lineage. Nicolas already did some mv643xx ethernet driver work last summer,
> >but apparently had trouble integrating this in the mainline kernel, and it
> >seems his work has now been redone by Dale or something. Do you know who
> >the
> >right person to communicate with about this would be ? The MIPS folk didn't
> >reply to any of our mails about this subject.
> >
>
> Nicolas has emailed me off-line and he & Dale are now in contact. FYI,
> this is part of the email from Dale to Nicolas:
Ok, cool, i really only mailed so that Nicolas could take over from there on.
Friendly,
Sven Luther
^ permalink raw reply
* Re: [PATCH 2.6.10-rc3][PPC32] Fix Motorola PReP (PowerstackII Utah) PCI IRQ map
From: Sven Luther @ 2005-02-24 17:01 UTC (permalink / raw)
To: Meelis Roos
Cc: Tom Rini, Christian Kujau, Kernel Mailing List, linuxppc-dev,
Sven Hartge
In-Reply-To: <Pine.SOC.4.61.0502241832510.21289@math.ut.ee>
On Thu, Feb 24, 2005 at 06:34:03PM +0200, Meelis Roos wrote:
> >Oh, damn, need to fix my daily builder, should be ok for tomorrow. IN the
> >meanwhile, you can try :
> >
> > http://people.debian.org/~luther/d-i/images/2005-02-23/powerpc/netboot/vmlinuz-prep.initrd
>
> This seems to work fine: onboard scsi is OK, pci nic with de4x5 is OK
> too. Haven't got more PCI cards in there currently.
Ok, can you now install the 2.6.10-3 package from :
http://people.debian.org/~luther/powerpc/2.6.10-3
(you need kernel-image-2.6.10-powerpc and mkvmlinuz), call mkvmlinuz on it (or
add it to kernel-img.conf as postinst_hook=/usr/sbin/mkvmlinuz).
You may probably want also to modify /etc/mkinitrd/mkinitrd:MODULES_DEP to dep
instead of MOST, or you may hit size problems with your initrd, i would be
interested in knowing that.
Then just dd your /boot/vmlinuz-2.6.10-powerpc to your prep partition, or
better yet to a tftp server, and try it out. If the scsi problems are there,
can you fill a bug report against kernel-source-2.6.10 ?
Friendly,
Sven Luther
^ permalink raw reply
* Re: [PATCH][PPC32] mv64x60 updates
From: Mark A. Greer @ 2005-02-24 17:08 UTC (permalink / raw)
To: Sven Luther; +Cc: nd, Embedded PPC Linux list
In-Reply-To: <20050224160411.GA11197@pegasos>
Sven Luther wrote:
>On Thu, Feb 24, 2005 at 08:28:56AM -0700, Mark A. Greer wrote:
>
>
>>Sven Luther wrote:
>>
>>
>>
>>>On Tue, Jan 25, 2005 at 05:14:25PM -0700, Mark A. Greer wrote:
>>>
>>>
>>>
>>>
>>has spent a lot of time making it work on both MIPS and PPC. The code
>>you see in the mv64x60.c file is a part of that. I believe that Dale's
>>
>>
>
>Ok, so the code in question is in addition to the existing driver from the
>mips guys and works with it ?
>
If "the code in question" == the enet related code in mv64x60.c then
yes. However, the only enet related code in mv64x60 is platform_data
setup and setup of the bridge's windows between the enet ctlr and system
memory.
> I had the impression that it was a separate
>driver development or something.
>
Nope.
>
>
>
>>patch(es) have been accepted and are queued to go into the mainline tree
>>at some point.
>>
>>
>
>Ok. Do you know if Dale's patches are available separatedly while they are not
>yet in mainline, so Nicolas Det can work on them and make sure they also work
>on the Pegasos board, which is not an embedded board but from the chrp
>lineage. Nicolas already did some mv643xx ethernet driver work last summer,
>but apparently had trouble integrating this in the mainline kernel, and it
>seems his work has now been redone by Dale or something. Do you know who the
>right person to communicate with about this would be ? The MIPS folk didn't
>reply to any of our mails about this subject.
>
Nicolas has emailed me off-line and he & Dale are now in contact. FYI,
this is part of the email from Dale to Nicolas:
> Please see bk://dfarnsworth@bkbits.net/linux-2.5-mv643xx-enet. Most of this is
> in netdev and mm, and on track to go into linux-2.5.
>>Did I answer your question?
>>
>>
>
>I think so. I was just surprised to see this 64x6x work go to arch/ppc instead
>to drivers/net.
>
There is no "driver" functionality in arch/ppc. There is only
platform_data setup which is used by the driver and the ensuring the
bridge's windows between the enet ctlr and system memory are set up
correctly.
Mark
^ permalink raw reply
* looking for help with scomc/scomd registers on 970
From: Chris Friesen @ 2005-02-24 16:54 UTC (permalink / raw)
To: linuxppc-dev, linuxppc64-dev
Not strictly linux related, but I thought someone might know the answer.
I've got a request from someone that wants to be able to flush the L2 on
the 970.
The user manual has a procedure to do this, but it involves first
flipping the cache to direct-mapped mode by setting SCOM register
0x43000 bit 0x8000. The only thing is, I can't find any linux code that
ever touches the SCOM stuff, and the manual has no examples of *reading*
from the SCOM area, just writing to it, so I'm not entirely sure how to
do that.
A google search found the following snippet of darwin code:
lis r8,cFIR ; Get the Core FIR register address
ori r8,r8,0x8000 ; Set to read data
sync
mtspr scomc,r8 ; Request the Core FIR
mfspr r25,scomd ; Get the source
mfspr r8,scomc ; Get back the status (we just ignore it)
sync
isync
This implies that bit 0x8000 needs to be set to specify a read command,
and that we need to read the status after the read. Does anyone know if
this is in fact the case?
Also, in that code they make reference to early chip revisions that
returned scom reads shifted by one bit. Does anyone know which versions
are affected?
Thanks,
Chris
^ permalink raw reply
* Re: [PATCH 2.6.10-rc3][PPC32] Fix Motorola PReP (PowerstackII Utah) PCI IRQ map
From: Meelis Roos @ 2005-02-24 16:34 UTC (permalink / raw)
To: Sven Luther
Cc: Tom Rini, Sven Hartge, Kernel Mailing List, Christian Kujau,
linuxppc-dev
In-Reply-To: <20050224160657.GB11197@pegasos>
> Oh, damn, need to fix my daily builder, should be ok for tomorrow. IN the
> meanwhile, you can try :
>
> http://people.debian.org/~luther/d-i/images/2005-02-23/powerpc/netboot/vmlinuz-prep.initrd
This seems to work fine: onboard scsi is OK, pci nic with de4x5 is OK
too. Haven't got more PCI cards in there currently.
--
Meelis Roos (mroos@linux.ee)
^ permalink raw reply
* Re: [PATCH 2.6.10-rc3][PPC32] Fix Motorola PReP (PowerstackII Utah) PCI IRQ map
From: Sven Luther @ 2005-02-24 16:06 UTC (permalink / raw)
To: Meelis Roos
Cc: Tom Rini, Christian Kujau, Kernel Mailing List, linuxppc-dev,
Sven Hartge
In-Reply-To: <Pine.SOC.4.61.0502241746450.21289@math.ut.ee>
On Thu, Feb 24, 2005 at 05:47:15PM +0200, Meelis Roos wrote:
> >Can you try :
> >
> > http://people.debian.org/~luther/d-i/images/daily/powerpc/netboot/vmlinuz-prep.initrd
>
> Unfortunately there are only floppy and floppy-2.4 dirs under powerpc.
Oh, damn, need to fix my daily builder, should be ok for tomorrow. IN the
meanwhile, you can try :
http://people.debian.org/~luther/d-i/images/2005-02-23/powerpc/netboot/vmlinuz-prep.initrd
This is a zImage.prep kernel with builtin initrd, you just put it somewhere
where you can boot it from, usually a tftp server.
Friendly,
Sven Luther
^ permalink raw reply
* Re: [PATCH][PPC32] mv64x60 updates
From: Sven Luther @ 2005-02-24 16:04 UTC (permalink / raw)
To: Mark A. Greer; +Cc: nd, Embedded PPC Linux list
In-Reply-To: <421DF2B8.6040007@mvista.com>
On Thu, Feb 24, 2005 at 08:28:56AM -0700, Mark A. Greer wrote:
> Sven Luther wrote:
>
> >On Tue, Jan 25, 2005 at 05:14:25PM -0700, Mark A. Greer wrote:
> >
> >
> >>Hi Andrew.
> >>
> >>This patch briges the mv64x60 related code up to the latest that I have.
> >>
> >>
> >
> >Mark, ...
> >
> >I am a bit bewildered by what you are doing here. How does this mv64x60
> >code
> >relate to the mv643xx_eth driver from the mips folk ?
> >
> >Friendly,
> >
> >Sven Luther
> >
>
> Hi Sven.
Hi Mark :)
> The mv64x60 is a Marvell host bridge with some I/O ctlrs including 3
Yeah, i know, as we use the MV64361 in the Pegasos 2 motherboards here at
Genesi/Bplan.
> enet cltrs. There are virtually identical versions for MIPS (called
> mv64x4x) and PPC (called mv64x6x). The mv643xx_eth driver was
> originally written by the MIPS folks, as you note, but Dale Farnsworth
Yes, and is in drivers/net.
> has spent a lot of time making it work on both MIPS and PPC. The code
> you see in the mv64x60.c file is a part of that. I believe that Dale's
Ok, so the code in question is in addition to the existing driver from the
mips guys and works with it ? I had the impression that it was a separate
driver development or something.
> patch(es) have been accepted and are queued to go into the mainline tree
> at some point.
Ok. Do you know if Dale's patches are available separatedly while they are not
yet in mainline, so Nicolas Det can work on them and make sure they also work
on the Pegasos board, which is not an embedded board but from the chrp
lineage. Nicolas already did some mv643xx ethernet driver work last summer,
but apparently had trouble integrating this in the mainline kernel, and it
seems his work has now been redone by Dale or something. Do you know who the
right person to communicate with about this would be ? The MIPS folk didn't
reply to any of our mails about this subject.
> Did I answer your question?
I think so. I was just surprised to see this 64x6x work go to arch/ppc instead
to drivers/net. I haven't really looked at the code though. Nicolas could you
comment on this ?
Friendly,
Sven Luther
>
> Mark
>
>
^ permalink raw reply
* Re: ppc32 weirdness with gcc-4.0 in 2.6.11-rc4
From: Jakub Jelinek @ 2005-02-24 16:01 UTC (permalink / raw)
To: Mikael Pettersson; +Cc: Linux Kernel list, linuxppc-dev list
In-Reply-To: <16925.60927.49095.758660@alkaid.it.uu.se>
On Thu, Feb 24, 2005 at 04:08:47PM +0100, Mikael Pettersson wrote:
> _However_, the 0k data message is due to a gcc-4.0 bug, and below
> you'll find a test program which illustrates it.
http://gcc.gnu.org/PR20196
Jakub
^ permalink raw reply
* Re: PATCH: add ppc PVR register values for 7447A and 7457 CPUs
From: James Chapman @ 2005-02-24 15:50 UTC (permalink / raw)
To: Tom Rini; +Cc: linuxppc-dev
In-Reply-To: <20050224141809.GP345@smtp.west.cox.net>
Tom Rini wrote:
> Is there something you can't get from cur_cpu_spec[0] ? That's why all
> of the PVR definitions _should_ be unneeded now.
No, I'll use cur_cpu_spec[]. Thanks
--
James Chapman
PGP key : http://www.katalix.com/~jchapman/pgpkey.txt
^ permalink raw reply
* Re: [PATCH 2.6.10-rc3][PPC32] Fix Motorola PReP (PowerstackII Utah) PCI IRQ map
From: Meelis Roos @ 2005-02-24 15:47 UTC (permalink / raw)
To: Sven Luther
Cc: Tom Rini, Sven Hartge, Kernel Mailing List, Christian Kujau,
linuxppc-dev
In-Reply-To: <20050224074728.GA31434@pegasos>
> Can you try :
>
> http://people.debian.org/~luther/d-i/images/daily/powerpc/netboot/vmlinuz-prep.initrd
Unfortunately there are only floppy and floppy-2.4 dirs under powerpc.
--
Meelis Roos (mroos@linux.ee)
^ permalink raw reply
* Re: ppc32 weirdness with gcc-4.0 in 2.6.11-rc4
From: Jakub Jelinek @ 2005-02-24 15:37 UTC (permalink / raw)
To: Mikael Pettersson; +Cc: Linux Kernel list, linuxppc-dev list
In-Reply-To: <16925.60927.49095.758660@alkaid.it.uu.se>
On Thu, Feb 24, 2005 at 04:08:47PM +0100, Mikael Pettersson wrote:
> /* gcc4bug.c
> * Written by Mikael Pettersson <mikpe@csd.uu.se>, 2005-02-24.
...
Reproduced, thanks for the testcase. Looking into it...
Jakub
^ permalink raw reply
* Re: [PATCH][PPC32] mv64x60 updates
From: Mark A. Greer @ 2005-02-24 15:28 UTC (permalink / raw)
To: Sven Luther; +Cc: nd, Embedded PPC Linux list
In-Reply-To: <20050224082508.GA30005@pegasos>
Sven Luther wrote:
>On Tue, Jan 25, 2005 at 05:14:25PM -0700, Mark A. Greer wrote:
>
>
>>Hi Andrew.
>>
>>This patch briges the mv64x60 related code up to the latest that I have.
>>
>>
>
>Mark, ...
>
>I am a bit bewildered by what you are doing here. How does this mv64x60 code
>relate to the mv643xx_eth driver from the mips folk ?
>
>Friendly,
>
>Sven Luther
>
Hi Sven.
The mv64x60 is a Marvell host bridge with some I/O ctlrs including 3
enet cltrs. There are virtually identical versions for MIPS (called
mv64x4x) and PPC (called mv64x6x). The mv643xx_eth driver was
originally written by the MIPS folks, as you note, but Dale Farnsworth
has spent a lot of time making it work on both MIPS and PPC. The code
you see in the mv64x60.c file is a part of that. I believe that Dale's
patch(es) have been accepted and are queued to go into the mainline tree
at some point.
Did I answer your question?
Mark
^ permalink raw reply
* Re: ppc32 weirdness with gcc-4.0 in 2.6.11-rc4
From: Mikael Pettersson @ 2005-02-24 15:08 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list, Linux Kernel list
In-Reply-To: <1109210688.15027.2.camel@gaston>
Benjamin Herrenschmidt writes:
> > -Memory: 255872k available (1788k kernel code, 976k data, 144k init, 0k highmem)
> > +Memory: 255872k available (1776k kernel code, 0k data, 144k init, 0k highmem)
>
> That is weird... (0k data)
>
> > AGP special page: 0xcffff000
> > Calibrating delay loop... 830.66 BogoMIPS (lpj=4153344)
> > Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
> > @@ -132,13 +132,7 @@
> > VFS: Mounted root (ext3 filesystem) readonly.
> > Freeing unused kernel memory: 144k init 4k chrp 8k prep
> > usb 3-2: new full speed USB device using ohci_hcd and address 2
> > -hub 3-2:1.0: USB hub found
> > -hub 3-2:1.0: 3 ports detected
> > -usb 3-2.1: new low speed USB device using ohci_hcd and address 3
> > -input: USB HID v1.10 Mouse [Logitech Apple Optical USB Mouse] on usb-0001:10:1b.0-2.1
> > -usb 3-2.3: new full speed USB device using ohci_hcd and address 4
> > -input: USB HID v1.10 Keyboard [Mitsumi Electric Apple Extended USB Keyboard] on usb-0001:10:1b.0-2.3
> > -input: USB HID v1.10 Device [Mitsumi Electric Apple Extended USB Keyboard] on usb-0001:10:1b.0-2.3
> > +usb 3-2: can't connect bus-powered hub to this port
> > EXT3 FS on hda5, internal journal
> > Adding 1048568k swap on /dev/hda3. Priority:-1 extents:1
> > SCSI subsystem initialized
> >
> > Note: "Memory: ... 0k data ..." !? Surely that can't be correct.
>
> Not sure what's up, but it's probably something beeing miscompiled. Can
> you check if the udelay/medlay loops are correct ?
Both __delay and a few test functions using udelay/mdelay look Ok.
_However_, the 0k data message is due to a gcc-4.0 bug, and below
you'll find a test program which illustrates it.
/Mikael
/* gcc4bug.c
* Written by Mikael Pettersson <mikpe@csd.uu.se>, 2005-02-24.
*
* This program is abstracted from arch/ppc/mm/init.c in
* the 2.6.11-rc4 Linux kernel sources.
*
* With gcc-3.4.3, gcc-3.3.5, or gcc-3.2.3, mem_init()
* correctly returns 245.
*
* With gcc-4.0.0 20050220, mem_init() erroneously returns 0.
* The error occurs with -O1, and -O2.
* Compiling at -O0, or -O3 or higher, hides the error.
*
* All gcc versions were configured for powerpc-unknown-linux-gnu.
*/
#include <stdio.h>
#define PAGE_SIZE 4096
unsigned long PAGE_OFFSET;
unsigned long high_memory;
unsigned long etext;
unsigned long init_begin;
unsigned long init_end;
unsigned long klimit;
int mem_init(void)
{
unsigned long addr;
int codepages = 0;
int datapages = 0;
int initpages = 0;
for (addr = PAGE_OFFSET; addr < high_memory; addr += PAGE_SIZE) {
if (addr < etext)
codepages++;
else if (addr >= init_begin && addr < init_end)
initpages++;
else if (addr < klimit)
datapages++;
}
printf("datapages == %d, initpages == %d, codepages == %d\n", datapages, initpages, codepages);
return datapages;
}
int main(void)
{
int datapages;
PAGE_OFFSET = 0xc0000000;
etext = 0xc01bb958;
init_begin = 0xc0264000;
init_end = 0xc0288000;
klimit = 0xc02d4378;
high_memory = 0xd0000000;
datapages = mem_init();
if (datapages != 245) {
fprintf(stderr, "gcc bug! mem_init() returned %d\n", datapages);
return 1;
} else
return 0;
}
^ permalink raw reply
* Re: PATCH: add ppc PVR register values for 7447A and 7457 CPUs
From: Tom Rini @ 2005-02-24 14:18 UTC (permalink / raw)
To: James Chapman; +Cc: linuxppc-dev
In-Reply-To: <421D97FE.4080100@katalix.com>
On Thu, Feb 24, 2005 at 09:01:50AM +0000, James Chapman wrote:
> Tom Rini wrote:
>
> >On Wed, Feb 23, 2005 at 08:48:25PM +0000, James Chapman wrote:
> >
> >>Signed-off-by: James Chapman <jchapman@katalix.com>
> >>
> >>Trivial patch to add 7447A and 7457 CPU defs.
> >
> >
> >Why? Most of the PVR definitions here can be removed (*muttering about
> >85xx ones being added).
> >
>
> I'm in the process of submitting a patch for a new board (Radstone
> PPC7D). Since other boards test CPU type using definitions in this file,
> I was trying to be consistent.
>
> If the community don't think those definitions are useful, I'll just
> move the ones I need into my board support stuff.
Is there something you can't get from cur_cpu_spec[0] ? That's why all
of the PVR definitions _should_ be unneeded now.
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply
* RE: Power PC 440GX Jumbo Packets EMAC2/3
From: zDL Linux PPC @ 2005-02-24 13:55 UTC (permalink / raw)
To: 'Gerhard Jaeger'; +Cc: zML Linux PPC Dev, zML Linux PPC Embedded
Gerhard,
> [SNIPSNAP]
> > > > Any suggestions on how to overcome this problem??? My only
> > > idea is to either
> > > > add data to the packet (don't think this will work) or
> > > forceably fragment
> > > > the packet (if it is 2K in size) to ensure that it never
> > > uses the exact size
> > > > of the tx fifo.....
> > >
> > > Have you applied Matt Porters patch? It has been submitted at
> > > the beginning
> > > of this month?
> >
> > No I haven't seen it on either of these lists, do you know
> where I can find
> > it
> >
> > Thanks
>
> Browse the linuxpp-embedded archive list, I think it was
> around the 9th
> of february...
> or try this one
> http://ozlabs.org/pipermail/linuxppc-embedded/2005-February/00
1260.html
Thanks for this however it is not the problem I am experiencing at present,
my problem is with the TX and not the RX side of things, I have added debug
and the ibm_emac_core prints out that the packet has been transmitted,
however I see nothing at the other end when you transmit a packet of tx fifo
size bytes from the PPC 440 GX, packets of <tx fifo size or >tx fifo size
are transmitted fine from the PPC 440 GX, so long as you do not transmit a
packet of Tx fifo size.
Thanks
^ permalink raw reply
* Re: Power PC 440GX Jumbo Packets EMAC2/3
From: Gerhard Jaeger @ 2005-02-24 13:45 UTC (permalink / raw)
To: linuxppc; +Cc: linuxppc-dev, linuxppc-embedded
In-Reply-To: <C18BA5DDB58DD511BD0700C0DF0DD450294286@NTSERVER4>
On Thursday 24 February 2005 14:12, zDL Linux PPC wrote:
[SNIPSNAP]
> > > Any suggestions on how to overcome this problem??? My only
> > idea is to either
> > > add data to the packet (don't think this will work) or
> > forceably fragment
> > > the packet (if it is 2K in size) to ensure that it never
> > uses the exact size
> > > of the tx fifo.....
> >
> > Have you applied Matt Porters patch? It has been submitted at
> > the beginning
> > of this month?
>
> No I haven't seen it on either of these lists, do you know where I can find
> it
>
> Thanks
Browse the linuxpp-embedded archive list, I think it was around the 9th
of february...
or try this one
http://ozlabs.org/pipermail/linuxppc-embedded/2005-February/001260.html
Gerhard
--
Gerhard Jaeger <gjaeger@sysgo.com>
SYSGO AG Embedded and Real-Time Software
www.sysgo.com | www.elinos.com | www.pikeos.com | www.osek.de
^ permalink raw reply
* RE: Power PC 440GX Jumbo Packets EMAC2/3
From: zDL Linux PPC @ 2005-02-24 13:12 UTC (permalink / raw)
To: 'Gerhard Jaeger', zML Linux PPC Dev; +Cc: zML Linux PPC Embedded
> On Thursday 24 February 2005 12:46, zDL Linux PPC wrote:
> > I have been doing some experiments with Jumbo packets (MTU
> 9000) and have
> > noticed that once you exceed the 2KB fifo size, I end up
> with no response
> > from the box.
> >
> > I can ping the box with no problem at all at sizes greater
> than 2KB, however
> > upon further investigation I noticed packets of size 2006
> bytes causes no
> > further packet to be transmitted (adding debug prints to
> ibm_emac_core.c,
> > the driver believes the packet has been transmitted), after
> adding a further
> > 42 bytes of header information this comes to the exact size
> of the Transmit
> > Fifo 2048 (2KB). I have also changed the Transmit Fifo
> Register to 1024
> > bytes, this solves the problem at 2006 bytes however now it
> has moved to 982
> > bytes of data (+42bytes of header = 1024)
> >
> > Has anyone else experienced this problem while either using
> a smaller
> > transmit fifo (512 or 1024 bytes) and MTU 1500 or a larger
> MTU (>2033) and
> > EMAC transmit fifo of 2048. I guess this will really apply
> to people with
> > larger MTU not many will decrease the Tx fifo, and I am
> further guessing
> > that not many are using 9000 MTU as not much hardware seems
> to support it, I
> > can only use it through a direct connection between PC's
> and not through a
> > switch!
> >
> > Any suggestions on how to overcome this problem??? My only
> idea is to either
> > add data to the packet (don't think this will work) or
> forceably fragment
> > the packet (if it is 2K in size) to ensure that it never
> uses the exact size
> > of the tx fifo.....
>
> Have you applied Matt Porters patch? It has been submitted at
> the beginning
> of this month?
No I haven't seen it on either of these lists, do you know where I can find
it
Thanks
^ permalink raw reply
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