* Re: Linux Kernel Issue: MPC8540 Errata (CPU29)
From: Kumar Gala @ 2005-04-27 18:36 UTC (permalink / raw)
To: Chiradeep Vittal; +Cc: linuxppc-embedded
In-Reply-To: <F237EFC9919B064C8BF5A44CDA5DA0C212F678@matisse01.matissenetworks.com>
On Apr 27, 2005, at 12:46 PM, Chiradeep Vittal wrote:
> We're running Linux Kernel 2.4.26 on an 8540 ADS derivative. We're
> seeing an
> "illegal instruction"=A0 (SIGILL) exception under some circumstances
> (during a pthread_create call). We were wondering if this could be a
> symptom of
> CPU29 and if there is a patch available for CPU29.
>
> "CPU29 L1 instruction cache gets multiple entries for same line after
> change
> in MSR[IS] bit "
>
> www.freescale.com/files/32bit/doc/errata/MPC8540CE.pdf
The way the Linux kernel manages the MMU on e500 it doesn't actually=20
ever modify MSR[IS] or MSR[DS]. They are always zero so I dont believe=20=
you are hitting this errata.
Are you running with math emulation turned on? Do you know what the=20
instruction is that causes the SIGILL?
- kumar
^ permalink raw reply
* Re: OLS 2005
From: Matt Porter @ 2005-04-27 18:41 UTC (permalink / raw)
To: Kumar Gala; +Cc: David Ho, linuxppc-embedded
In-Reply-To: <caa74808cb385f021bedcf5769502e1d@freescale.com>
On Wed, Apr 27, 2005 at 01:35:32PM -0500, Kumar Gala wrote:
> > > I'm only worried about the weather. I was told it's pretty hot
> > > there in July :).
> >
> > Haha...come visit us in Phoenix. Weather is definitely near
> > perfect in Ottawa, IMHO.
>
> Agreed, I'd rather be in Ottawa in July. Which was nice last year and
> hopefully this year as well.
>
> > > If you can give more info about what to do in Ottawa in addition
> > > to drinking beer and attending OLS it'd be great :P
>
> I wondering if we can get a PPC BoF together, however not sure exactly
> what we would talk about. Any ideas?
We can talk about the elusive flattened OF tree for ppc32. :) It's
probably smart just to gather for a pub BoF about embedded Linux/PPC
stuff in general. We always have plenty of things...
-Matt
^ permalink raw reply
* Re: Status of Linux 2.6 for 40x and 44x CPUs
From: Roger Larsson @ 2005-04-27 22:29 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <200504271233.18856.glenn@aoi-industries.com>
On Wednesday 27 April 2005 18.33, Glenn Burkhardt wrote:
> From the looks of the benchmarks described here:
>
> http://www.denx.de/twiki/bin/view/Know/Linux24vs26
>
> and the results are basically confirmed here:
>
> http://www.2cpu.com/articles/98_1.html
>
> there are good reasons to avoid using the 2.6 kernel. Frankly, I'm
> surprised and would have thought that the changes in the scheduler would
> have brought improvements, as did the report here:
>
> http://www.lynuxworks.com/corporate/news/2004/linux-kernel-2.6.php
At all depends on what you measure (and that you actually measure
what you think you are measuring :-)
"A PREEMPTIBLE KERNEL."
This is about how quick your higher priority thread actually gets to run
after an event (i.e. driver to application). It is not about how fast the
context switch itself is.
Why 2.4 might be faster:
Measure context switch time where one process wakes up another
while going to sleep has less overhead.
Modified test
Let the above processes run with SCHED_RR or SCHED_FIFO
add a third process that uses the kernel a lot - like memory management.
"AN EFFICIENT SCHEDULER"
This is more about what will happen if you have more than a few processes
in the run queue - avoids searching all of them...
Why 2.4 might be faster:
A search of a list with only one element is hard to beat!
But try to measure using lots of processes running at the same time.
/RogerL
^ permalink raw reply
* Re: Status of Linux 2.6 for 40x and 44x CPUs
From: Wolfgang Denk @ 2005-04-27 23:17 UTC (permalink / raw)
To: Roger Larsson; +Cc: linuxppc-embedded
In-Reply-To: <200504280029.35461.roger.larsson@norran.net>
In message <200504280029.35461.roger.larsson@norran.net> you wrote:
>
> At all depends on what you measure (and that you actually measure
> what you think you are measuring :-)
Can you recommend another benchmark test that would provide a better
representation of typical user space workloads than lmbench does?
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Old programmers never die, they just branch to a new address.
^ permalink raw reply
* DHCP problem
From: Srivatsan @ 2005-04-28 9:15 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <20050428020004.1A7EF67B28@ozlabs.org>
[-- Attachment #1: Type: text/plain, Size: 2835 bytes --]
Hi all,
I am having a MPC8280 based Freescale evaluation board (A & M
rattler) running U-boot. It is successfully getting the ip address using
DHCP. (in Uboot).
When I am trying to boot the board with Linux, it continuously sends
DHCP request. The boot args which I am giving are:
bootargs=root=/dev/nfs nfsroot=10.203.105.123:/tftpboot/ppc_root ip=on
Linux Boot sequence problem at:
ide: Assuming 50MHz system bus speed for PIO modes; override with
idebus=xx
NET4: Linux TCP/IP 1.0 for NET4.0
IP Protocols: ICMP, UDP, TCP, IGMP
IP: routing cache hash table of 512 buckets, 4Kbytes
TCP: Hash tables configured (established 1024 bind 2048)
Sending DHCP requests ...... timed out!
IP-Config: Retrying forever (NFS root)...
Sending DHCP requests ...... timed out!
IP-Config: Retrying forever (NFS root)...
Sending DHCP requests ...... timed out!
If bootargs is set as follows:
bootargs=root=/dev/nfs nfsroot=10.203.105.123:/tftpboot/ppc_root
ip=10.203.105.1
18:10.203.106.3:10.203.105.1:255.255.255.128:rattler:eth0:off
Linux boot sequence problem at:
IP-Config: Complete:
device=eth0, addr=10.203.105.118, mask=255.255.255.128,
gw=10.203.105.1,
host=rattler, domain=, nis-domain=(none),
bootserver=10.203.106.3, rootserver=10.203.105.123, rootpath=
NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
Looking up port of RPC 100003/2 on 10.203.105.123
portmap: server 10.203.105.123 not responding, timed out
Root-NFS: Unable to get nfsd port number from server, using default
Looking up port of RPC 100005/1 on 10.203.105.123
portmap: server 10.203.105.123 not responding, timed out
Root-NFS: Unable to get mountd port number from server, using default
The system is not able to get the DNS domain name properly. Can anybody
tell me why is this happening? When I switched on ETHEREAL I am able to
see a DHCP discover packet corresponding to my targets MAC address. Any
pointers would be highly appreciated.
With Regards,
C.R.Srivatsan
***************************NOTE***********************************************
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******************************************************************************
*************************DISCLAIMER*******************************************
This e-mail and any attachment is for authorised use by the intended
recipient(s) only. It may contain proprietary material, confidential
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^ permalink raw reply
* connecting BDI2000 to ML403
From: Peter 'p2' De Schrijver @ 2005-04-28 9:47 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 270 bytes --]
Hi,
I'm trying to figure out how to connect the BDI 2000 with a Xilinx ML403
development board. As far as I can see in the ML403 schematics, the JTAG
connector lacks the nTRST and the HALT signals needed for JTAG
debugging. Any ideas ?
Thanks,
Peter (p2).
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* RE : Booting linux for 405EP --> mem_pieces_find( ) nightmare
From: Garcia Jérémie @ 2005-04-28 10:36 UTC (permalink / raw)
To: Conn Clark; +Cc: linuxppc-dev
First of all tks everybody for your answers but I found a way to solve =
my problem.
I know it's not a very clean solution but it could help for people in =
emergency as me ...lol
In fact the problem had its roots much earlier.=20
I had to have a look in the file "arch/ppc/kernel/ppc_4xx_setup.c" in =
the platform_init() function.
I saw that the residual structure given traditionnaly by the bootloader =
is retreived there as below:
/*
* If we were passed in a board information, copy it into the
* residual data area.
*/
if (r3) {
memcpy((void *) __res, (void *) (r3 + KERNELBASE),sizeof (bd_t));
}=20
This variable "__res" is used after that in several actions. In my case, =
that was directly linked to my mapping problem cause=20
the kernel wasn't able to get the quantity of ram available. In ordr to =
do that, it uses the following function in my case:
ppc4xx_find_end_of_memory(void)
{
bd_t *bip =3D (bd_t *) __res;
return ((unsigned long) bip->bi_memsize);
}
So the return of this function was incoherent and drove me to a kernel =
panic.
As a conclusion I just defined my own board info structure in the =
platform_init() function:
bd_t my_bd_t;
=20
strcpy(my_bd_t.bi_s_version,"v1"); /* Version of =
this structure */
strcpy(my_bd_t.bi_r_version,"bootrom linux 1.0") ; /* Version of the =
IBM ROM */
my_bd_t.bi_memsize =3D 16000000 ; /* DRAM =
installed, in bytes */
my_bd_t.bi_enetaddr[0][0] =3D 0x00; /* Local =
Ethernet MAC address 1 */
my_bd_t.bi_enetaddr[0][1] =3D 0x01;
my_bd_t.bi_enetaddr[0][2] =3D 0x73;
my_bd_t.bi_enetaddr[0][3] =3D 0x01;
my_bd_t.bi_enetaddr[0][4] =3D 0xC1;
my_bd_t.bi_enetaddr[0][5] =3D 0x3B;
my_bd_t.bi_enetaddr[1][0] =3D 0x00; /* Local =
Ethernet MAC address 2 */
my_bd_t.bi_enetaddr[1][1] =3D 0x01;
my_bd_t.bi_enetaddr[1][2] =3D 0x73;
my_bd_t.bi_enetaddr[1][3] =3D 0x01;
my_bd_t.bi_enetaddr[1][4] =3D 0xC1;
my_bd_t.bi_enetaddr[1][5] =3D 0x3C;
my_bd_t.bi_intfreq =3D 200000000 ; /* Processor speed, in Hz =
*/
my_bd_t.bi_busfreq =3D 100000000 ; /* PLB Bus speed, in Hz =
*/
my_bd_t.bi_pllouta_freq =3D 800000000 ; /* PLL OUTA speed, in Hz =
*/
my_bd_t.bi_opb_busfreq =3D 50000000 ; /* OPB Bus speed, in Hz =
*/
my_bd_t.bi_iic_fast[0] =3D 0 ; /* Use fast i2c mode =
*/ =20
memcpy((void *) __res, (void *) &my_bd_t,sizeof (bd_t)); =20
And here we go!
I know that this is a terrible hack but I haven't find better =
solution.
Regards, J=E9r=E9mie
-------- Message d'origine--------
De: Conn Clark [mailto:clark@esteem.com]
Date: mer. 27/04/2005 11:21
=C0: Garcia J=E9r=E9mie
Cc: linuxppc-dev@ozlabs.org
Objet : Re: Booting linux for 405EP --> mem_pieces_find( ) nightmare
=20
Hi J=E9r=E9mie,
/
Garcia J=E9r=E9mie wrote:
> Hi everybody,
> I'm tryin to adapt a linux LSP deom Montavista (the one for the 405EP =
evaluation board) to a proprietary hardware using a 405EP.
> Unfortunately, it is not as easy as I thought. Here is my problem:
> To load our linux image (zImage.treeboot), we use the "VxWorks =
bootrom" bootloader which download the image via tftp.
> That works well except the fact that in the LSP, linux tried to get a =
board info structure in flash memory at an address where we have =
nothing. So we replace this behavior in "embed_config.c" with the =
following lines (note: I had to re-code the strcpy although there is the =
#include<string.h> because it cannot find the reference at the link =
level... why???):
>=20
I would recomend using u-boot for a boot rom. It was a god send to us in =
getting our MPC850 board up and going the first time. On our 405EP board =
we did have to do some slight hacking but nothing really major.
> /* We use VxWorks bootrom, so we have to create ourselves the boot =
info structure */
<snip>
> J=E9r=E9mie \\ (=B0.=B0) //~ ~ ~ HELP ~ ~ ~ \\ (=B0.=B0) //
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>=20
-- Conn
*****************************************************************
Blessed be the heretic, for he causes some to think and unites
the rest against him.
*****************************************************************
Conn Clark
Engineering Assistant clark@esteem.com
Electronic Systems Technology Inc. www.esteem.com
Stock Ticker Symbol ELST
^ permalink raw reply
* Re: connecting BDI2000 to ML403
From: Mark Chambers @ 2005-04-28 12:04 UTC (permalink / raw)
To: linuxppc-embedded, Peter 'p2' De Schrijver
In-Reply-To: <20050428094716.GA17582@mind.be>
>Hi,
>
>I'm trying to figure out how to connect the BDI 2000 with a Xilinx ML403
>development board. As far as I can see in the ML403 schematics, the JTAG
>connector lacks the nTRST and the HALT signals needed for JTAG
>debugging. Any ideas ?
>
>Thanks,
>
>Peter (p2).
The BDI doesn't need nTRST or HALT, so that's not your problem. nTRST
must be pulled high, but the BDI doesn't need to drive that signal.
Mark Chambers
^ permalink raw reply
* Re: connecting BDI2000 to ML403
From: Peter Ryser @ 2005-04-28 14:16 UTC (permalink / raw)
To: Peter 'p2' De Schrijver; +Cc: linuxppc-embedded
In-Reply-To: <20050428094716.GA17582@mind.be>
If your debugger needs nTRST and HALT you can route the JTAG signals of
the PPC405 processor through user IO pins to the expansion connector.
- Peter
Peter 'p2' De Schrijver wrote:
>Hi,
>
>I'm trying to figure out how to connect the BDI 2000 with a Xilinx ML403
>development board. As far as I can see in the ML403 schematics, the JTAG
>connector lacks the nTRST and the HALT signals needed for JTAG
>debugging. Any ideas ?
>
>Thanks,
>
>Peter (p2).
>
>
>------------------------------------------------------------------------
>
>_______________________________________________
>Linuxppc-embedded mailing list
>Linuxppc-embedded@ozlabs.org
>https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
^ permalink raw reply
* rsync mirrors of linuxppc-* on source.mvista.com
From: Tom Rini @ 2005-04-28 15:37 UTC (permalink / raw)
To: linuxppc-dev, linuxppc-embedded
With the shift away from BitKeeper, and with PowerPC work having long
shifted away from the linuxppc-* bitkeeper trees and towards a more
direct relationship with Andrew / et al, is there any value in keeping
the rsync mirrors of the last state of the linuxppc-* trees available?
As there's no metadata, my slant is towards no. But it wouldn't be hard
to have these still exist, if people speak up.
Thanks.
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply
* Re: rsync mirrors of linuxppc-* on source.mvista.com
From: Dan Malek @ 2005-04-28 16:02 UTC (permalink / raw)
To: Tom Rini; +Cc: linuxppc-dev, linuxppc-embedded
In-Reply-To: <20050428153733.GD1221@smtp.west.cox.net>
On Apr 28, 2005, at 11:37 AM, Tom Rini wrote:
> .... is there any value in keeping
> the rsync mirrors of the last state of the linuxppc-* trees available?
Have you been pulling any updates into these trees?
I would like to keep an archive copy, as there is still code in them
that hasn't migrated into main trees. I guess the longer we wait
the less value that has, but I'd like to not lose it. I don' t have
any problem hosting the archives if people still want to use them
for future reference.
Thanks.
-- Dan
^ permalink raw reply
* Re: rsync mirrors of linuxppc-* on source.mvista.com
From: Tom Rini @ 2005-04-28 16:13 UTC (permalink / raw)
To: Dan Malek; +Cc: linuxppc-dev, linuxppc-embedded
In-Reply-To: <22dae1b19bcada0dd96405d13454b6bf@embeddededge.com>
On Thu, Apr 28, 2005 at 12:02:13PM -0400, Dan Malek wrote:
>
> On Apr 28, 2005, at 11:37 AM, Tom Rini wrote:
>
> >.... is there any value in keeping
> >the rsync mirrors of the last state of the linuxppc-* trees available?
>
> Have you been pulling any updates into these trees?
They are semi current with the linux-2.[46] versions, but probably not
100% up to date.
> I would like to keep an archive copy, as there is still code in them
> that hasn't migrated into main trees. I guess the longer we wait
> the less value that has, but I'd like to not lose it. I don' t have
> any problem hosting the archives if people still want to use them
> for future reference.
For the linuxppc-2.5 tree, I did a dirdiff'ing prior
to the BK thing comming up and either submitted things, or gave to Paul
/ Matt Porter what I found (as it was 4xx things) to deal with.
For the linuxppc-2.4 tre, I know there's stuff that never went to
Marcelo.
I'll go re-activate rsync for the trees and have a comment about them
being historical archives.
--
Tom Rini
http://gate.crashing.org/~trini/
^ permalink raw reply
* Re: RE : Booting linux for 405EP --> mem_pieces_find( ) nightmare
From: Jon Loeliger @ 2005-04-28 16:25 UTC (permalink / raw)
To: Garcia Jérémie; +Cc: linuxppc-dev@ozlabs.org
In-Reply-To: <D4FDDD1349B5AC46B68FC26AD8AF42D6226B25@exnet.3il.fr>
On Thu, 2005-04-28 at 05:36, Garcia Jérémie wrote:
> So the return of this function was incoherent and drove me to a kernel
> panic.
> As a conclusion I just defined my own board info structure in the
> platform_init() function:
Oh no!
We're going to have to work on isolating the bd_t virus
with my patch on the linuxppc-embedded list...
*sigh*
jdl
^ permalink raw reply
* Re: rsync mirrors of linuxppc-* on source.mvista.com
From: Mark Guertin @ 2005-04-28 17:30 UTC (permalink / raw)
To: Tom Rini; +Cc: linuxppc-dev, linuxppc-embedded
In-Reply-To: <20050428153733.GD1221@smtp.west.cox.net>
Hi Tom
I know of quite a few setups that still use these trees, so they might
be worth keeping around for that sake at the least if it's not too much
work.
Mark
Tom Rini wrote:
>With the shift away from BitKeeper, and with PowerPC work having long
>shifted away from the linuxppc-* bitkeeper trees and towards a more
>direct relationship with Andrew / et al, is there any value in keeping
>the rsync mirrors of the last state of the linuxppc-* trees available?
>
>As there's no metadata, my slant is towards no. But it wouldn't be hard
>to have these still exist, if people speak up.
>
>Thanks.
>
>
>
^ permalink raw reply
* RE: Linux Kernel Issue: MPC8540 Errata (CPU29)
From: Chiradeep Vittal @ 2005-04-28 18:31 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-embedded
It turns out to be a compiler issue.
We're using gcc 3.4.3 with optimization level -Os. The following program =
will generate the illegal instruction with -Os but not with -O2
int main (int argc, char** argv)
{=09
int seq[] =3D {0, 1, 2};
return 0;
}
The reason is that the compiler generates code with the stswi =
instruction which is not supported by the e500. Here's our compiler =
configuration:
Configured with: =
/home/steve/perforce/sw/opt/crosstool/build/powerpc-8540-linux-gnu/gcc-3.=
4.3-glibc-2.3.2/gcc-3.4.3/configure --target=3Dpowerpc-8540-linux-gnu =
--host=3Di686-host_pc-linux-gnu =
--prefix=3D/home/steve/perforce/sw/opt/cross-compile/powerpc-8540-linux-g=
nu/gcc-3.4.3-glibc-2.3.2 --with-cpu=3D8540 =
--enable-cxx-flags=3D-mcpu=3D8540 =
--with-headers=3D/home/steve/perforce/sw/opt/cross-compile/powerpc-8540-l=
inux-gnu/gcc-3.4.3-glibc-2.3.2/powerpc-8540-linux-gnu/include =
--with-local-prefix=3D/home/steve/perforce/sw/opt/cross-compile/powerpc-8=
540-linux-gnu/gcc-3.4.3-glibc-2.3.2/powerpc-8540-linux-gnu --disable-nls =
--enable-threads=3Dposix --enable-symvers=3Dgnu --enable-__cxa_atexit =
--enable-languages=3Dc,c++ --enable-shared --enable-c99 =
--enable-long-long
Any recommendations?
Thanks
--
Chiradeep
-----Original Message-----
From: Kumar Gala [mailto:kumar.gala@freescale.com]=20
Sent: Wednesday, April 27, 2005 11:37 AM
To: Chiradeep Vittal
Cc: linuxppc-embedded@ozlabs.org
Subject: Re: Linux Kernel Issue: MPC8540 Errata (CPU29)
On Apr 27, 2005, at 12:46 PM, Chiradeep Vittal wrote:
> We're running Linux Kernel 2.4.26 on an 8540 ADS derivative. We're
> seeing an
> "illegal instruction"=A0 (SIGILL) exception under some circumstances
> (during a pthread_create call). We were wondering if this could be a
> symptom of
> CPU29 and if there is a patch available for CPU29.
>
> "CPU29 L1 instruction cache gets multiple entries for same line after
> change
> in MSR[IS] bit "
>
> www.freescale.com/files/32bit/doc/errata/MPC8540CE.pdf
The way the Linux kernel manages the MMU on e500 it doesn't actually=20
ever modify MSR[IS] or MSR[DS]. They are always zero so I dont believe=20
you are hitting this errata.
Are you running with math emulation turned on? Do you know what the=20
instruction is that causes the SIGILL?
- kumar
^ permalink raw reply
* Re: Linux Kernel Issue: MPC8540 Errata (CPU29)
From: Greg Weeks @ 2005-04-28 18:50 UTC (permalink / raw)
To: Chiradeep Vittal; +Cc: linuxppc-embedded
In-Reply-To: <F237EFC9919B064C8BF5A44CDA5DA0C212F681@matisse01.matissenetworks.com>
Chiradeep Vittal wrote:
>It turns out to be a compiler issue.
>We're using gcc 3.4.3 with optimization level -Os. The following program will generate the illegal instruction with -Os but not with -O2
> int main (int argc, char** argv)
> {
> int seq[] = {0, 1, 2};
> return 0;
> }
>The reason is that the compiler generates code with the stswi instruction which is not supported by the e500. Here's our compiler configuration:
>Configured with: /home/steve/perforce/sw/opt/crosstool/build/powerpc-8540-linux-gnu/gcc-3.4.3-glibc-2.3.2/gcc-3.4.3/configure --target=powerpc-8540-linux-gnu --host=i686-host_pc-linux-gnu --prefix=/home/steve/perforce/sw/opt/cross-compile/powerpc-8540-linux-gnu/gcc-3.4.3-glibc-2.3.2 --with-cpu=8540 --enable-cxx-flags=-mcpu=8540 --with-headers=/home/steve/perforce/sw/opt/cross-compile/powerpc-8540-linux-gnu/gcc-3.4.3-glibc-2.3.2/powerpc-8540-linux-gnu/include --with-local-prefix=/home/steve/perforce/sw/opt/cross-compile/powerpc-8540-linux-gnu/gcc-3.4.3-glibc-2.3.2/powerpc-8540-linux-gnu --disable-nls --enable-threads=posix --enable-symvers=gnu --enable-__cxa_atexit --enable-languages=c,c++ --enable-shared --enable-c99 --enable-long-long
>
>Any recommendations?
>
>
Here's the patch we use to get GCC to stop generating the invalid
intructions.
Greg Weeks
--- gcc-orig/gcc/config/rs6000/rs6000.h 2003-12-08 20:57:45.000000000
-0500
+++ gcc-new/gcc/config/rs6000/rs6000.h 2004-09-15 14:23:36.680978222
-0400
@@ -550,10 +550,10 @@
#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
#define TARGET_ALTIVEC_ABI rs6000_altivec_abi
#define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
+#define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540)
#define TARGET_SPE_ABI 0
#define TARGET_SPE 0
-#define TARGET_E500 0
#define TARGET_ISEL 0
#define TARGET_FPRS 1
^ permalink raw reply
* Re: Linux Kernel Issue: MPC8540 Errata (CPU29)
From: Kylo Ginsberg @ 2005-04-28 22:21 UTC (permalink / raw)
To: Chiradeep Vittal; +Cc: linuxppc-embedded
In-Reply-To: <F237EFC9919B064C8BF5A44CDA5DA0C212F681@matisse01.matissenetworks.com>
Chiradeep,
I have the same issue with gcc3.4.3 and an e500 target. You can give
gcc the -mno-string to inhibit generation of those load/store string
instructions. I don't know if gcc can be configured such that its
default is not to generate those instructions.
Cheers,
Kylo
On 4/28/05, Chiradeep Vittal <chiradeep@matissenetworks.com> wrote:
> It turns out to be a compiler issue.
> We're using gcc 3.4.3 with optimization level -Os. The following program =
will generate the illegal instruction with -Os but not with -O2
> int main (int argc, char** argv)
> {
> int seq[] =3D {0, 1, 2};
> return 0;
> }
> The reason is that the compiler generates code with the stswi instruction=
which is not supported by the e500. Here's our compiler configuration:
> Configured with: /home/steve/perforce/sw/opt/crosstool/build/powerpc-8540=
-linux-gnu/gcc-3.4.3-glibc-2.3.2/gcc-3.4.3/configure --target=3Dpowerpc-854=
0-linux-gnu --host=3Di686-host_pc-linux-gnu --prefix=3D/home/steve/perforce=
/sw/opt/cross-compile/powerpc-8540-linux-gnu/gcc-3.4.3-glibc-2.3.2 --with-c=
pu=3D8540 --enable-cxx-flags=3D-mcpu=3D8540 --with-headers=3D/home/steve/pe=
rforce/sw/opt/cross-compile/powerpc-8540-linux-gnu/gcc-3.4.3-glibc-2.3.2/po=
werpc-8540-linux-gnu/include --with-local-prefix=3D/home/steve/perforce/sw/=
opt/cross-compile/powerpc-8540-linux-gnu/gcc-3.4.3-glibc-2.3.2/powerpc-8540=
-linux-gnu --disable-nls --enable-threads=3Dposix --enable-symvers=3Dgnu --=
enable-__cxa_atexit --enable-languages=3Dc,c++ --enable-shared --enable-c99=
--enable-long-long
>=20
> Any recommendations?
>=20
> Thanks
> --
> Chiradeep
>=20
> -----Original Message-----
> From: Kumar Gala [mailto:kumar.gala@freescale.com]
> Sent: Wednesday, April 27, 2005 11:37 AM
> To: Chiradeep Vittal
> Cc: linuxppc-embedded@ozlabs.org
> Subject: Re: Linux Kernel Issue: MPC8540 Errata (CPU29)
>=20
> On Apr 27, 2005, at 12:46 PM, Chiradeep Vittal wrote:
>=20
> > We're running Linux Kernel 2.4.26 on an 8540 ADS derivative. We're
> > seeing an
> > "illegal instruction" (SIGILL) exception under some circumstances
> > (during a pthread_create call). We were wondering if this could be a
> > symptom of
> > CPU29 and if there is a patch available for CPU29.
> >
> > "CPU29 L1 instruction cache gets multiple entries for same line after
> > change
> > in MSR[IS] bit "
> >
> > www.freescale.com/files/32bit/doc/errata/MPC8540CE.pdf
>=20
> The way the Linux kernel manages the MMU on e500 it doesn't actually
> ever modify MSR[IS] or MSR[DS]. They are always zero so I dont believe
> you are hitting this errata.
>=20
> Are you running with math emulation turned on? Do you know what the
> instruction is that causes the SIGILL?
>=20
> - kumar
>=20
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
^ permalink raw reply
* Re: Linux Kernel Issue: MPC8540 Errata (CPU29)
From: Kumar Gala @ 2005-04-28 23:18 UTC (permalink / raw)
To: kylo; +Cc: Chiradeep Vittal, linuxppc-embedded
In-Reply-To: <61cc712d05042815211d84e870@mail.gmail.com>
All of the suggestions are good ones.. Also, in 2.6 I've recently =20
submitted patches that add emulation of these instructions in the =20
kernel.
Its odd, but I would have expected a GCC configured for e500 not to =20
generate the ld/st string instructions by default, but the -mno-string =20=
is what we do in the kernel to ensure that.
- kumar
On Apr 28, 2005, at 5:21 PM, Kylo Ginsberg wrote:
> Chiradeep,
>
> I have the same issue with gcc3.4.3 and an e500 target.=A0 You can =
give
> gcc the -mno-string to inhibit generation of those load/store string
> instructions.=A0 I don't know if gcc can be configured such that its
> default is not to generate those instructions.
>
> Cheers,
> Kylo
>
> On 4/28/05, Chiradeep Vittal <chiradeep@matissenetworks.com> wrote:
> > It turns out to be a compiler issue.
> > We're using gcc 3.4.3 with optimization level -Os. The following =20
> program will generate the illegal instruction with -Os but not with =20=
> -O2
>
> >=A0=A0=A0=A0=A0=A0=A0=A0 int main (int argc, char** argv)
> >=A0=A0=A0=A0=A0=A0=A0=A0 {
> >=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 int seq[] =3D {0, 1, 2};
> >=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return 0;
> >=A0=A0=A0=A0=A0=A0=A0=A0 }
> > The reason is that the compiler generates code with the stswi =20
> instruction which is not supported by the e500. Here's our compiler =20=
> configuration:
>
> > Configured with: =20
> /home/steve/perforce/sw/opt/crosstool/build/powerpc-8540-linux-gnu/=20
> gcc-3.4.3-glibc-2.3.2/gcc-3.4.3/configure =20
> --target=3Dpowerpc-8540-linux-gnu --host=3Di686-host_pc-linux-gnu =20
> --prefix=3D/home/steve/perforce/sw/opt/cross-compile/powerpc-8540-linux-=
=20
> gnu/gcc-3.4.3-glibc-2.3.2 --with-cpu=3D8540 =20
> --enable-cxx-flags=3D-mcpu=3D8540 =20
> --with-headers=3D/home/steve/perforce/sw/opt/cross-compile/powerpc-8540-=
=20
> linux-gnu/gcc-3.4.3-glibc-2.3.2/powerpc-8540-linux-gnu/include =20
> --with-local-prefix=3D/home/steve/perforce/sw/opt/cross-compile/powerpc=20=
> -8540-linux-gnu/gcc-3.4.3-glibc-2.3.2/powerpc-8540-linux-gnu =20
> --disable-nls --enable-threads=3Dposix --enable-symvers=3Dgnu =20
> --enable-__cxa_atexit --enable-languages=3Dc,c++ --enable-shared =20
> --enable-c99 --enable-long-long
>
> >
> > Any recommendations?
> >
> > Thanks
> > --
> > Chiradeep
> >
> > -----Original Message-----
> > From: Kumar Gala [mailto:kumar.gala@freescale.com]
> > Sent: Wednesday, April 27, 2005 11:37 AM
> > To: Chiradeep Vittal
> > Cc: linuxppc-embedded@ozlabs.org
> > Subject: Re: Linux Kernel Issue: MPC8540 Errata (CPU29)
> >
> > On Apr 27, 2005, at 12:46 PM, Chiradeep Vittal wrote:
> >
> > > We're running Linux Kernel 2.4.26 on an 8540 ADS derivative. We're
> > >=A0 seeing an
> > > "illegal instruction" (SIGILL) exception under some circumstances
> > > (during a pthread_create call). We were wondering if this could =20=
> be a
> > > symptom of
> > > CPU29 and if there is a patch available for CPU29.
> > >
> > > "CPU29 L1 instruction cache gets multiple entries for same line =20=
> after
> > >=A0 change
> > > in MSR[IS] bit "
> > >
> > > www.freescale.com/files/32bit/doc/errata/MPC8540CE.pdf
> >
> > The way the Linux kernel manages the MMU on e500 it doesn't actually
> > ever modify MSR[IS] or MSR[DS].=A0 They are always zero so I dont =20=
> believe
> > you are hitting this errata.
> >
> > Are you running with math emulation turned on?=A0 Do you know what =
the
> > instruction is that causes the SIGILL?
> >
> > - kumar
> >
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> >
^ permalink raw reply
* Re: 824x sandpoint and 2.6.x
From: Mark A. Greer @ 2005-04-29 0:44 UTC (permalink / raw)
To: Sam Song; +Cc: linuxppc-embedded
In-Reply-To: <20050423121645.63553.qmail@web15810.mail.cnb.yahoo.com>
[-- Attachment #1: Type: text/plain, Size: 352 bytes --]
Sam Song wrote:
>If possible, could you pls show me a right 2.6 boot
>process of
> sandpoint X3/2? I wanna to find out some nice hints
>of it. This
>is the first time to me so hard to debug a kernel
>before normal
>console.
>
Here is the output of a 7457 sandpoint on a very old root filesystem.
Output for any other processor will be the same.
--
[-- Attachment #2: sandpoint.log --]
[-- Type: text/plain, Size: 3593 bytes --]
loaded at: 01100000 01228134
relocated to: 00800000 00928134
zimage at: 00805831 0092546C
avail ram: 00400000 00800000
Linux/PPC load: ip=on
Uncompressing Linux...done.
Now booting the kernel
Total memory = 32MB; using 64kB for hash table (at c0280000)
Linux version 2.6.12-rc2 (mgreer@mag.az.mvista.com) (gcc version 3.4.3 (MontaVis
ta 3.4.3-11.0.0.0500150 2005-02-07)) #1 Thu Apr 28 11:53:45 MST 2005
Motorola SPS Sandpoint Test Platform
Port by MontaVista Software, Inc. (source@mvista.com)
Built 1 zonelists
Kernel command line: ip=on
OpenPIC Version 1.2 (1 CPUs and 20 IRQ sources) at fdfd0000
OpenPIC timer frequency is 100.000000 MHz
PID hash table entries: 256 (order: 8, 4096 bytes)
time_init: decrementer frequency = 24.357945 MHz
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 29824k available (1828k kernel code, 568k data, 108k init, 0k highmem)
Mount-cache hash table entries: 512
NET: Registered protocol family 16
PCI: Probing PCI hardware
PCI: Cannot allocate resource region 1 of device 0000:00:00.0
usbcore: registered new driver usbfs
usbcore: registered new driver hub
Generic RTC Driver v1.07
Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled
ttyS0 at MMIO 0x0 (irq = 4) is a NS16550A
ttyS1 at MMIO 0x0 (irq = 3) is a NS16550A
io scheduler noop registered
io scheduler anticipatory registered
io scheduler deadline registered
io scheduler cfq registered
RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
loop: loaded (max 8 devices)
e100: Intel(R) PRO/100 Network Driver, 3.3.6-k2-NAPI
e100: Copyright(c) 1999-2004 Intel Corporation
e100: eth0: e100_probe: addr 0xbffff000, irq 21, MAC addr 00:00:82:58:50:02
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
usbmon: debugs is not available
NET: Registered protocol family 2
IP: routing cache hash table of 512 buckets, 4Kbytes
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
NET: Registered protocol family 1
NET: Registered protocol family 17
e100: eth0: e100_watchdog: link up, 100Mbps, half-duplex
Sending BOOTP requests . OK
IP-Config: Got BOOTP answer from 192.168.1.1, my address is 192.168.1.65
IP-Config: Complete:
device=eth0, addr=192.168.1.65, mask=255.255.255.0, gw=255.255.255.255,
host=eepro_6, domain=, nis-domain=(none),
bootserver=192.168.1.1, rootserver=192.168.1.1, rootpath=/opt/hardhat/devki
t/ppc/74xx/target/
Looking up port of RPC 100003/2 on 192.168.1.1
Looking up port of RPC 100005/1 on 192.168.1.1
VFS: Mounted root (nfs filesystem) readonly.
Freeing unused kernel memory: 108k init
INIT: version 2.78 booting
Activating swap...
Checking all file systems...
Parallelizing fsck version 1.22 (22-Jun-2001)
Calculating module dependencies... depmod: QM_MODULES: Function not implemented
done.
Loading modules:
modprobe: Can't open dependencies file /lib/modules/2.6.12-rc2/modules.dep (No s
uch file or directory)
mkdir: cannot create directory `/dev/pts': File exists
Mounting local filesystems...
nothing was mounted
Cleaning: /etc/network/ifstate.
Setting up IP spoofing protection: rp_filter.
Disable TCP/IP Explicit Congestion Notification: done.
INIT: Entering runlevel: 3
Starting system log daemon: syslogd klogd.
Starting internet superserver: inetd.
MontaVista Linux 3.0, Professional Edition
eepro_6 login:
^ permalink raw reply
* Re: kernel BUG at page_alloc.c:225 on PPC440GP
From: ming lei @ 2005-04-29 2:04 UTC (permalink / raw)
To: Glenn Burkhardt; +Cc: linuxppc-embedded
I cannot remember everything right now. There was a
problem with the init bootmem reservation that caused
this BUG. Two region of bootmem got overlapped
somehow.
--- Glenn Burkhardt <glenn@aoi-industries.com> wrote:
> I know it's been a year and a half since you
> submitted this report to the
> mailing list, but was this problem ever resolved? I
> think I'm seeing
> something similar in the 2.4.23 kernel.
>
> Thanks!
>
__________________________________________________
Do You Yahoo!?
Tired of spam? Yahoo! Mail has the best spam protection around
http://mail.yahoo.com
^ permalink raw reply
* Re: Linux Kernel Issue: MPC8540 Errata (CPU29)
From: Wolfgang Denk @ 2005-04-29 6:02 UTC (permalink / raw)
To: kylo; +Cc: Chiradeep Vittal, linuxppc-embedded
In-Reply-To: <61cc712d05042815211d84e870@mail.gmail.com>
In message <61cc712d05042815211d84e870@mail.gmail.com> you wrote:
>
> I have the same issue with gcc3.4.3 and an e500 target. You can give
> gcc the -mno-string to inhibit generation of those load/store string
> instructions. I don't know if gcc can be configured such that its
> default is not to generate those instructions.
Yes, it can. In config/rs6000/rs6000.c replace
if (BYTES_BIG_ENDIAN && optimize_size)
target_flags |= MASK_MULTIPLE | MASK_STRING;
by
if (BYTES_BIG_ENDIAN && optimize_size)
target_flags |=
(MASK_MULTIPLE | MASK_STRING) & ~processor_target_table[j].target_disable;
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Do you suppose the reason the ends of the `Intel Inside' logo don't
match up is that it was drawn on a Pentium?
^ permalink raw reply
* Re: Flash Statistics
From: Jörn Engel @ 2005-04-29 6:48 UTC (permalink / raw)
To: Josh Boyer; +Cc: Jeff.Fellin, linuxppc-embedded
In-Reply-To: <1114207484.27280.9.camel@jdub.homelinux.org>
On Fri, 22 April 2005 17:04:44 -0500, Josh Boyer wrote:
> >
> > Flash datasheet must have this information.
>
> They have information on the maximum number of writes per eraseblock,
> yes. But I think Jeff is looking for some statistic gathering tools he
> can use to figure out how his application workload is effecting flash.
> I doubt that is in any datasheets ;).
Or in any currently existing mtd driver, for that matter.
Jörn
--
Fancy algorithms are buggier than simple ones, and they're much harder
to implement. Use simple algorithms as well as simple data structures.
-- Rob Pike
^ permalink raw reply
* porting linux on power pc mpc8xx
From: prinson varghese @ 2005-04-29 10:32 UTC (permalink / raw)
To: linuxppc-embedded
Dear Sir,
I am new to the embedded system development .How i can port linux kenel to
power pc MPC 8XX
and where i can get the kernel for the same?
awaiting rpaly ASAP
_________________________________________________________________
Your zone@MSN Spaces! http://www.msn.co.in/spaces Blogs, albums, music
lists.
^ permalink raw reply
* Re: [PATCH 2.6.12-rc2] Freescale 8272ADS PCI bridge support to thestock linux-2.5 (updated)
From: Vitaly Bordug @ 2005-04-29 11:28 UTC (permalink / raw)
To: Kumar Gala; +Cc: Tom Rini, linuxppc-embedded list
In-Reply-To: <7c4c26a737f9d366040482e49f3ca004@freescale.com>
[-- Attachment #1: Type: text/plain, Size: 758 bytes --]
Kumar,
This is what currently intended to represent on-chip PCI bridge support
for PQ2 family.
It's approved working on my 8272 and have a very good probably of the
same on the PQ2FADS-VR board. It contains low-level (SIUMCR & CPLD IC
chip select ) setup only for 8272 and PQ2FADS, considering that u-boot
does this stuff for 8266 boards. The actual source files are renamed to
m82xx_pci.[ch].
Rune, can you test this for m8266/8265 ? I guess while IRQ stuff is
nearly the same, this _should_ work as is or with minimum effort. Note
that you'll need to define PCI_INT_TO_SIU in platforms/pq2ads.h (I
suppose it's the same as PQ2FADS - SIU_INT_IRQ6, but I'm not sure).
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
--
Sincerely,
Vitaly
[-- Attachment #2: PQII_pci.patch --]
[-- Type: text/x-patch, Size: 32879 bytes --]
diff -Nru a/arch/ppc/Kconfig b/arch/ppc/Kconfig
--- a/arch/ppc/Kconfig 2005-04-29 15:26:43 +04:00
+++ b/arch/ppc/Kconfig 2005-04-29 15:26:43 +04:00
@@ -1123,7 +1123,7 @@
config PCI_8260
bool
- depends on PCI && 8260 && !8272
+ depends on PCI && 8260
default y
config 8260_PCI9
diff -Nru a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h
--- a/arch/ppc/platforms/pq2ads.h 2005-04-29 15:26:43 +04:00
+++ b/arch/ppc/platforms/pq2ads.h 2005-04-29 15:26:43 +04:00
@@ -49,10 +49,10 @@
/* PCI interrupt controller */
#define PCI_INT_STAT_REG 0xF8200000
#define PCI_INT_MASK_REG 0xF8200004
-#define PIRQA (NR_SIU_INTS + 0)
-#define PIRQB (NR_SIU_INTS + 1)
-#define PIRQC (NR_SIU_INTS + 2)
-#define PIRQD (NR_SIU_INTS + 3)
+#define PIRQA (NR_CPM_INTS + 0)
+#define PIRQB (NR_CPM_INTS + 1)
+#define PIRQC (NR_CPM_INTS + 2)
+#define PIRQD (NR_CPM_INTS + 3)
/*
* PCI memory map definitions for MPC8266ADS-PCI.
@@ -68,28 +68,23 @@
* 0x00000000-0x1FFFFFFF 0x00000000-0x1FFFFFFF MPC8266 local memory
*/
-/* window for a PCI master to access MPC8266 memory */
-#define PCI_SLV_MEM_LOCAL 0x00000000 /* Local base */
-#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
+/* All the other PCI memory map definitions reside at syslib/m82xx_pci.h
+ Here we should redefine what is unique for this board */
+#define M82xx_PCI_SLAVE_MEM_LOCAL 0x00000000 /* Local base */
+#define M82xx_PCI_SLAVE_MEM_BUS 0x00000000 /* PCI base */
+#define M82xx_PCI_SLAVE_MEM_SIZE 0x10000000 /* 256 Mb */
+
+#define M82xx_PCI_SLAVE_SEC_WND_SIZE ~(0x40000000 - 1U) /* 2 x 512Mb */
+#define M82xx_PCI_SLAVE_SEC_WND_BASE 0x80000000 /* PCI Memory base */
+
+#if defined(CONFIG_ADS8272)
+#define PCI_INT_TO_SIU SIU_INT_IRQ2
+#elif defined(CONFIG_PQ2FADS)
+#define PCI_INT_TO_SIU SIU_INT_IRQ6
+#else
+#warning PCI Bridge will be without interrupts support
+#endif
-/* window for the processor to access PCI memory with prefetching */
-#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
-#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
-#define PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
-
-/* window for the processor to access PCI memory without prefetching */
-#define PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
-#define PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
-#define PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
-
-/* window for the processor to access PCI I/O */
-#define PCI_MSTR_IO_LOCAL 0xF4000000 /* Local base */
-#define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
-#define PCI_MSTR_IO_SIZE 0x04000000 /* 64MB */
-
-#define _IO_BASE PCI_MSTR_IO_LOCAL
-#define _ISA_MEM_BASE PCI_MSTR_MEMIO_LOCAL
-#define PCI_DRAM_OFFSET PCI_SLV_MEM_BUS
#endif /* CONFIG_PCI */
#endif /* __MACH_ADS8260_DEFS */
diff -Nru a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
--- a/arch/ppc/syslib/Makefile 2005-04-29 15:26:43 +04:00
+++ b/arch/ppc/syslib/Makefile 2005-04-29 15:26:43 +04:00
@@ -81,7 +81,7 @@
obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \
todc_time.o
obj-$(CONFIG_8260) += m8260_setup.o
-obj-$(CONFIG_PCI_8260) += m8260_pci.o indirect_pci.o
+obj-$(CONFIG_PCI_8260) += m82xx_pci.o indirect_pci.o pci_auto.o
obj-$(CONFIG_8260_PCI9) += m8260_pci_erratum9.o
obj-$(CONFIG_CPM2) += cpm2_common.o cpm2_pic.o
ifeq ($(CONFIG_PPC_GEN550),y)
diff -Nru a/arch/ppc/syslib/m8260_pci.c b/arch/ppc/syslib/m8260_pci.c
--- a/arch/ppc/syslib/m8260_pci.c 2005-04-29 15:26:43 +04:00
+++ /dev/null Wed Dec 31 16:00:00 196900
@@ -1,194 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004 Red Hat, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <linux/slab.h>
-#include <linux/delay.h>
-
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <asm/immap_cpm2.h>
-#include <asm/mpc8260.h>
-
-#include "m8260_pci.h"
-
-
-/* PCI bus configuration registers.
- */
-
-static void __init m8260_setup_pci(struct pci_controller *hose)
-{
- volatile cpm2_map_t *immap = cpm2_immr;
- unsigned long pocmr;
- u16 tempShort;
-
-#ifndef CONFIG_ATC /* already done in U-Boot */
- /*
- * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
- * and local bus for PCI (SIUMCR [LBPC]).
- */
- immap->im_siu_conf.siu_82xx.sc_siumcr = 0x00640000;
-#endif
-
- /* Make PCI lowest priority */
- /* Each 4 bits is a device bus request and the MS 4bits
- is highest priority */
- /* Bus 4bit value
- --- ----------
- CPM high 0b0000
- CPM middle 0b0001
- CPM low 0b0010
- PCI reguest 0b0011
- Reserved 0b0100
- Reserved 0b0101
- Internal Core 0b0110
- External Master 1 0b0111
- External Master 2 0b1000
- External Master 3 0b1001
- The rest are reserved */
- immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
-
- /* Park bus on core while modifying PCI Bus accesses */
- immap->im_siu_conf.siu_82xx.sc_ppc_acr = 0x6;
-
- /*
- * Set up master window that allows the CPU to access PCI space. This
- * window is set up using the first SIU PCIBR registers.
- */
- immap->im_memctl.memc_pcimsk0 = MPC826x_PCI_MASK;
- immap->im_memctl.memc_pcibr0 = MPC826x_PCI_BASE | PCIBR_ENABLE;
-
- /* Disable machine check on no response or target abort */
- immap->im_pci.pci_emr = cpu_to_le32(0x1fe7);
- /* Release PCI RST (by default the PCI RST signal is held low) */
- immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
-
- /* give it some time */
- mdelay(1);
-
- /*
- * Set up master window that allows the CPU to access PCI Memory (prefetch)
- * space. This window is set up using the first set of Outbound ATU registers.
- */
- immap->im_pci.pci_potar0 = cpu_to_le32(MPC826x_PCI_LOWER_MEM >> 12);
- immap->im_pci.pci_pobar0 = cpu_to_le32((MPC826x_PCI_LOWER_MEM - MPC826x_PCI_MEM_OFFSET) >> 12);
- pocmr = ((MPC826x_PCI_UPPER_MEM - MPC826x_PCI_LOWER_MEM) >> 12) ^ 0xfffff;
- immap->im_pci.pci_pocmr0 = cpu_to_le32(pocmr | POCMR_ENABLE | POCMR_PREFETCH_EN);
-
- /*
- * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
- * space. This window is set up using the second set of Outbound ATU registers.
- */
- immap->im_pci.pci_potar1 = cpu_to_le32(MPC826x_PCI_LOWER_MMIO >> 12);
- immap->im_pci.pci_pobar1 = cpu_to_le32((MPC826x_PCI_LOWER_MMIO - MPC826x_PCI_MMIO_OFFSET) >> 12);
- pocmr = ((MPC826x_PCI_UPPER_MMIO - MPC826x_PCI_LOWER_MMIO) >> 12) ^ 0xfffff;
- immap->im_pci.pci_pocmr1 = cpu_to_le32(pocmr | POCMR_ENABLE);
-
- /*
- * Set up master window that allows the CPU to access PCI IO space. This window
- * is set up using the third set of Outbound ATU registers.
- */
- immap->im_pci.pci_potar2 = cpu_to_le32(MPC826x_PCI_IO_BASE >> 12);
- immap->im_pci.pci_pobar2 = cpu_to_le32(MPC826x_PCI_LOWER_IO >> 12);
- pocmr = ((MPC826x_PCI_UPPER_IO - MPC826x_PCI_LOWER_IO) >> 12) ^ 0xfffff;
- immap->im_pci.pci_pocmr2 = cpu_to_le32(pocmr | POCMR_ENABLE | POCMR_PCI_IO);
-
- /*
- * Set up slave window that allows PCI masters to access MPC826x local memory.
- * This window is set up using the first set of Inbound ATU registers
- */
-
- immap->im_pci.pci_pitar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_LOCAL >> 12);
- immap->im_pci.pci_pibar0 = cpu_to_le32(MPC826x_PCI_SLAVE_MEM_BUS >> 12);
- pocmr = ((MPC826x_PCI_SLAVE_MEM_SIZE-1) >> 12) ^ 0xfffff;
- immap->im_pci.pci_picmr0 = cpu_to_le32(pocmr | PICMR_ENABLE | PICMR_PREFETCH_EN);
-
- /* See above for description - puts PCI request as highest priority */
- immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
-
- /* Park the bus on the PCI */
- immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
-
- /* Host mode - specify the bridge as a host-PCI bridge */
- early_write_config_word(hose, 0, 0, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_HOST);
-
- /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
- early_read_config_word(hose, 0, 0, PCI_COMMAND, &tempShort);
- early_write_config_word(hose, 0, 0, PCI_COMMAND,
- tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-}
-
-void __init m8260_find_bridges(void)
-{
- extern int pci_assign_all_busses;
- struct pci_controller * hose;
-
- pci_assign_all_busses = 1;
-
- hose = pcibios_alloc_controller();
-
- if (!hose)
- return;
-
- ppc_md.pci_swizzle = common_swizzle;
-
- hose->first_busno = 0;
- hose->bus_offset = 0;
- hose->last_busno = 0xff;
-
- setup_m8260_indirect_pci(hose,
- (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
- (unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
-
- m8260_setup_pci(hose);
- hose->pci_mem_offset = MPC826x_PCI_MEM_OFFSET;
-
- isa_io_base =
- (unsigned long) ioremap(MPC826x_PCI_IO_BASE,
- MPC826x_PCI_IO_SIZE);
- hose->io_base_virt = (void *) isa_io_base;
-
- /* setup resources */
- pci_init_resource(&hose->mem_resources[0],
- MPC826x_PCI_LOWER_MEM,
- MPC826x_PCI_UPPER_MEM,
- IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory");
-
- pci_init_resource(&hose->mem_resources[1],
- MPC826x_PCI_LOWER_MMIO,
- MPC826x_PCI_UPPER_MMIO,
- IORESOURCE_MEM, "PCI memory");
-
- pci_init_resource(&hose->io_resource,
- MPC826x_PCI_LOWER_IO,
- MPC826x_PCI_UPPER_IO,
- IORESOURCE_IO, "PCI I/O");
-}
diff -Nru a/arch/ppc/syslib/m8260_pci.h b/arch/ppc/syslib/m8260_pci.h
--- a/arch/ppc/syslib/m8260_pci.h 2005-04-29 15:26:43 +04:00
+++ /dev/null Wed Dec 31 16:00:00 196900
@@ -1,76 +0,0 @@
-
-#ifndef _PPC_KERNEL_M8260_PCI_H
-#define _PPC_KERNEL_M8260_PCI_H
-
-#include <asm/m8260_pci.h>
-
-/*
- * Local->PCI map (from CPU) controlled by
- * MPC826x master window
- *
- * 0x80000000 - 0xBFFFFFFF Total CPU2PCI space PCIBR0
- *
- * 0x80000000 - 0x9FFFFFFF PCI Mem with prefetch (Outbound ATU #1)
- * 0xA0000000 - 0xAFFFFFFF PCI Mem w/o prefetch (Outbound ATU #2)
- * 0xB0000000 - 0xB0FFFFFF 32-bit PCI IO (Outbound ATU #3)
- *
- * PCI->Local map (from PCI)
- * MPC826x slave window controlled by
- *
- * 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1)
- */
-
-/*
- * Slave window that allows PCI masters to access MPC826x local memory.
- * This window is set up using the first set of Inbound ATU registers
- */
-
-#ifndef MPC826x_PCI_SLAVE_MEM_LOCAL
-#define MPC826x_PCI_SLAVE_MEM_LOCAL (((struct bd_info *)__res)->bi_memstart)
-#define MPC826x_PCI_SLAVE_MEM_BUS (((struct bd_info *)__res)->bi_memstart)
-#define MPC826x_PCI_SLAVE_MEM_SIZE (((struct bd_info *)__res)->bi_memsize)
-#endif
-
-/*
- * This is the window that allows the CPU to access PCI address space.
- * It will be setup with the SIU PCIBR0 register. All three PCI master
- * windows, which allow the CPU to access PCI prefetch, non prefetch,
- * and IO space (see below), must all fit within this window.
- */
-#ifndef MPC826x_PCI_BASE
-#define MPC826x_PCI_BASE 0x80000000
-#define MPC826x_PCI_MASK 0xc0000000
-#endif
-
-#ifndef MPC826x_PCI_LOWER_MEM
-#define MPC826x_PCI_LOWER_MEM 0x80000000
-#define MPC826x_PCI_UPPER_MEM 0x9fffffff
-#define MPC826x_PCI_MEM_OFFSET 0x00000000
-#endif
-
-#ifndef MPC826x_PCI_LOWER_MMIO
-#define MPC826x_PCI_LOWER_MMIO 0xa0000000
-#define MPC826x_PCI_UPPER_MMIO 0xafffffff
-#define MPC826x_PCI_MMIO_OFFSET 0x00000000
-#endif
-
-#ifndef MPC826x_PCI_LOWER_IO
-#define MPC826x_PCI_LOWER_IO 0x00000000
-#define MPC826x_PCI_UPPER_IO 0x00ffffff
-#define MPC826x_PCI_IO_BASE 0xb0000000
-#define MPC826x_PCI_IO_SIZE 0x01000000
-#endif
-
-#ifndef _IO_BASE
-#define _IO_BASE isa_io_base
-#endif
-
-#ifdef CONFIG_8260_PCI9
-struct pci_controller;
-extern void setup_m8260_indirect_pci(struct pci_controller* hose,
- u32 cfg_addr, u32 cfg_data);
-#else
-#define setup_m8260_indirect_pci setup_indirect_pci
-#endif
-
-#endif /* _PPC_KERNEL_M8260_PCI_H */
diff -Nru a/arch/ppc/syslib/m8260_pci_erratum9.c b/arch/ppc/syslib/m8260_pci_erratum9.c
--- a/arch/ppc/syslib/m8260_pci_erratum9.c 2005-04-29 15:26:43 +04:00
+++ b/arch/ppc/syslib/m8260_pci_erratum9.c 2005-04-29 15:26:43 +04:00
@@ -248,11 +248,11 @@
static inline int is_pci_mem(unsigned long addr)
{
- if (addr >= MPC826x_PCI_LOWER_MMIO &&
- addr <= MPC826x_PCI_UPPER_MMIO)
+ if (addr >= M82xx_PCI_LOWER_MMIO &&
+ addr <= M82xx_PCI_UPPER_MMIO)
return 1;
- if (addr >= MPC826x_PCI_LOWER_MEM &&
- addr <= MPC826x_PCI_UPPER_MEM)
+ if (addr >= M82xx_PCI_LOWER_MEM &&
+ addr <= M82xx_PCI_UPPER_MEM)
return 1;
return 0;
}
diff -Nru a/arch/ppc/syslib/m8260_setup.c b/arch/ppc/syslib/m8260_setup.c
--- a/arch/ppc/syslib/m8260_setup.c 2005-04-29 15:26:43 +04:00
+++ b/arch/ppc/syslib/m8260_setup.c 2005-04-29 15:26:43 +04:00
@@ -34,7 +34,8 @@
unsigned char __res[sizeof(bd_t)];
extern void cpm2_reset(void);
-extern void m8260_find_bridges(void);
+extern void pq2_find_bridges(void);
+extern void pq2pci_init_irq(void);
extern void idma_pci9_init(void);
/* Place-holder for board-specific init */
@@ -56,7 +57,7 @@
idma_pci9_init();
#endif
#ifdef CONFIG_PCI_8260
- m8260_find_bridges();
+ pq2_find_bridges();
#endif
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start)
@@ -173,6 +174,12 @@
* in case the boot rom changed something on us.
*/
cpm2_immr->im_intctl.ic_siprr = 0x05309770;
+
+#if defined(CONFIG_PCI) && (defined(CONFIG_ADS8272) || defined(CONFIG_PQ2FADS))
+ /* Initialize stuff for the 82xx CPLD IC and install demux */
+ pq2pci_init_irq();
+#endif
+
}
/*
diff -Nru a/arch/ppc/syslib/m82xx_pci.c b/arch/ppc/syslib/m82xx_pci.c
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/syslib/m82xx_pci.c 2005-04-29 15:26:43 +04:00
@@ -0,0 +1,383 @@
+/*
+ *
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004 Red Hat, Inc.
+ *
+ * 2005 (c) MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <asm/immap_cpm2.h>
+#include <asm/mpc8260.h>
+#include <asm/cpm2.h>
+
+#include "m82xx_pci.h"
+
+/*
+ * Interrupt routing
+ */
+
+static inline int
+pq2pci_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ static char pci_irq_table[][4] =
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+ {
+ { PIRQA, PIRQB, PIRQC, PIRQD }, /* IDSEL 22 - PCI slot 0 */
+ { PIRQD, PIRQA, PIRQB, PIRQC }, /* IDSEL 23 - PCI slot 1 */
+ { PIRQC, PIRQD, PIRQA, PIRQB }, /* IDSEL 24 - PCI slot 2 */
+ };
+
+ const long min_idsel = 22, max_idsel = 24, irqs_per_slot = 4;
+ return PCI_IRQ_TABLE_LOOKUP;
+}
+
+static void
+pq2pci_mask_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_unmask_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_mask_and_ack(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= (1 << (31 - bit));
+ return;
+}
+
+static void
+pq2pci_end_irq(unsigned int irq)
+{
+ int bit = irq - NR_CPM_INTS;
+
+ *(volatile unsigned long *) PCI_INT_MASK_REG &= ~(1 << (31 - bit));
+ return;
+}
+
+struct hw_interrupt_type pq2pci_ic = {
+ "PQ2 PCI",
+ NULL,
+ NULL,
+ pq2pci_unmask_irq,
+ pq2pci_mask_irq,
+ pq2pci_mask_and_ack,
+ pq2pci_end_irq,
+ 0
+};
+
+static irqreturn_t
+pq2pci_irq_demux(int irq, void *dev_id, struct pt_regs *regs)
+{
+ unsigned long stat, mask, pend;
+ int bit;
+
+ for(;;) {
+ stat = *(volatile unsigned long *) PCI_INT_STAT_REG;
+ mask = *(volatile unsigned long *) PCI_INT_MASK_REG;
+ pend = stat & ~mask & 0xf0000000;
+ if (!pend)
+ break;
+ for (bit = 0; pend != 0; ++bit, pend <<= 1) {
+ if (pend & 0x80000000)
+ __do_IRQ(NR_CPM_INTS + bit, regs);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction pq2pci_irqaction = {
+ .handler = pq2pci_irq_demux,
+ .flags = SA_INTERRUPT,
+ .mask = CPU_MASK_NONE,
+ .name = "PQ2 PCI cascade",
+};
+
+
+void
+pq2pci_init_irq(void)
+{
+ int irq;
+ volatile cpm2_map_t *immap = cpm2_immr;
+#ifdef CONFIG_ADS8272
+ /* configure chip select for PCI interrupt controller */
+ immap->im_memctl.memc_br3 = PCI_INT_STAT_REG | 0x00001801;
+ immap->im_memctl.memc_or3 = 0xffff8010;
+#elif defined CONFIG_PQ2FADS
+ immap->im_memctl.memc_br8 = PCI_INT_STAT_REG | 0x00001801;
+ immap->im_memctl.memc_or8 = 0xffff8010;
+#endif
+ for (irq = NR_CPM_INTS; irq < NR_CPM_INTS + 4; irq++)
+ irq_desc[irq].handler = &pq2pci_ic;
+
+ /* make PCI IRQ level sensitive */
+ immap->im_intctl.ic_siexr &=
+ ~(1 << (14 - (PCI_INT_TO_SIU - SIU_INT_IRQ1)));
+
+ /* mask all PCI interrupts */
+ *(volatile unsigned long *) PCI_INT_MASK_REG |= 0xfff00000;
+
+ /* install the demultiplexer for the PCI cascade interrupt */
+ setup_irq(PCI_INT_TO_SIU, &pq2pci_irqaction);
+ return;
+}
+
+static int
+pq2pci_exclude_device(u_char bus, u_char devfn)
+{
+ return PCIBIOS_SUCCESSFUL;
+}
+
+/* PCI bus configuration registers.
+ */
+static void
+pq2ads_setup_pci(struct pci_controller *hose)
+{
+ __u32 val;
+ volatile cpm2_map_t *immap = cpm2_immr;
+ bd_t* binfo = (bd_t*) __res;
+ u32 sccr = immap->im_clkrst.car_sccr;
+ uint pci_div,freq,time;
+ /* PCI int lowest prio */
+ /* Each 4 bits is a device bus request and the MS 4bits
+ is highest priority */
+ /* Bus 4bit value
+ --- ----------
+ CPM high 0b0000
+ CPM middle 0b0001
+ CPM low 0b0010
+ PCI reguest 0b0011
+ Reserved 0b0100
+ Reserved 0b0101
+ Internal Core 0b0110
+ External Master 1 0b0111
+ External Master 2 0b1000
+ External Master 3 0b1001
+ The rest are reserved
+ */
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x61207893;
+ /* park bus on core */
+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_CORE;
+ /*
+ * Set up master windows that allow the CPU to access PCI space. These
+ * windows are set up using the two SIU PCIBR registers.
+ */
+
+ immap->im_memctl.memc_pcimsk0 = M82xx_PCI_PRIM_WND_SIZE;
+ immap->im_memctl.memc_pcibr0 = M82xx_PCI_PRIM_WND_BASE | PCIBR_ENABLE;
+
+#ifdef M82xx_PCI_SEC_WND_SIZE
+ immap->im_memctl.memc_pcimsk1 = M82xx_PCI_SEC_WND_SIZE;
+ immap->im_memctl.memc_pcibr1 = M82xx_PCI_SEC_WND_BASE | PCIBR_ENABLE;
+#endif
+
+#ifdef CONFIG_ADS8272
+ immap->im_siu_conf.siu_82xx.sc_siumcr =
+ (immap->im_siu_conf.siu_82xx.sc_siumcr &
+ ~(SIUMCR_BBD | SIUMCR_ESE | SIUMCR_PBSE |
+ SIUMCR_CDIS | SIUMCR_DPPC11 | SIUMCR_L2CPC11 |
+ SIUMCR_LBPC11 | SIUMCR_APPC11 |
+ SIUMCR_CS10PC11 | SIUMCR_BCTLC11 | SIUMCR_MMR11)) |
+ SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00 |
+ SIUMCR_APPC10 | SIUMCR_CS10PC00 |
+ SIUMCR_BCTLC00 | SIUMCR_MMR11 ;
+
+#elif defined CONFIG_PQ2FADS
+ /*
+ * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
+ * and local bus for PCI (SIUMCR [LBPC]).
+ */
+ immap->im_siu_conf.siu_82xx.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
+ ~(SIUMCR_L2PC11 | SIUMCR_LBPC11 | SIUMCR_CS10PC11 | SIUMCR_APPC11) |
+ SIUMCR_BBD | SIUMCR_LBPC01 | SIUMCR_DPPC11 | SIUMCR_APPC10;
+#endif
+ /* Enable PCI */
+ immap->im_pci.pci_gcr = cpu_to_le32(PCIGCR_PCI_BUS_EN);
+
+ pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
+ ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
+ freq = (uint)((2*binfo->bi_cpmfreq)/(pci_div));
+ time = (int)666666/freq;
+ /* due to PCI Local Bus spec, some devices needs to wait such a long
+ time after RST deassertion. More specifically, 0.508s for 66MHz & twice more for 33 */
+ printk("%s: The PCI bus is %d Mhz.\nWaiting %s after deasserting RST...\n",__FILE__,freq,
+ (time==1) ? "0.5 seconds":"1 second" );
+
+ {
+ int i;
+ for(i=0;i<(500*time);i++)
+ udelay(1000);
+ }
+
+ /* setup ATU registers */
+ immap->im_pci.pci_pocmr0 = cpu_to_le32(POCMR_ENABLE | POCMR_PCI_IO |
+ ((~(M82xx_PCI_IO_SIZE - 1U)) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar0 = cpu_to_le32(M82xx_PCI_LOWER_IO >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar0 = cpu_to_le32(M82xx_PCI_IO_BASE >> POTA_ADDR_SHIFT);
+
+ /* Set-up non-prefetchable window */
+ immap->im_pci.pci_pocmr1 = cpu_to_le32(POCMR_ENABLE | ((~(M82xx_PCI_MMIO_SIZE-1U)) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar1 = cpu_to_le32(M82xx_PCI_LOWER_MMIO >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar1 = cpu_to_le32((M82xx_PCI_LOWER_MMIO - M82xx_PCI_MMIO_OFFSET) >> POTA_ADDR_SHIFT);
+
+ /* Set-up prefetchable window */
+ immap->im_pci.pci_pocmr2 = cpu_to_le32(POCMR_ENABLE |POCMR_PREFETCH_EN |
+ (~(M82xx_PCI_MEM_SIZE-1U) >> POTA_ADDR_SHIFT));
+ immap->im_pci.pci_potar2 = cpu_to_le32(M82xx_PCI_LOWER_MEM >> POTA_ADDR_SHIFT);
+ immap->im_pci.pci_pobar2 = cpu_to_le32((M82xx_PCI_LOWER_MEM - M82xx_PCI_MEM_OFFSET) >> POTA_ADDR_SHIFT);
+
+ /* Inbound transactions from PCI memory space */
+ immap->im_pci.pci_picmr0 = cpu_to_le32(PICMR_ENABLE | PICMR_PREFETCH_EN |
+ ((~(M82xx_PCI_SLAVE_MEM_SIZE-1U)) >> PITA_ADDR_SHIFT));
+ immap->im_pci.pci_pibar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_BUS >> PITA_ADDR_SHIFT);
+ immap->im_pci.pci_pitar0 = cpu_to_le32(M82xx_PCI_SLAVE_MEM_LOCAL>> PITA_ADDR_SHIFT);
+
+#if defined CONFIG_ADS8272
+ /* PCI int highest prio */
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x01236745;
+#elif defined CONFIG_PQ2FADS
+ immap->im_siu_conf.siu_82xx.sc_ppc_alrh = 0x03124567;
+#endif
+ /* park bus on PCI */
+ immap->im_siu_conf.siu_82xx.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
+
+ /* Enable bus mastering and inbound memory transactions */
+ early_read_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, &val);
+ val &= 0xffff0000;
+ val |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
+ early_write_config_dword(hose, hose->first_busno, 0, PCI_COMMAND, val);
+
+}
+
+void __init pq2_find_bridges(void)
+{
+ extern int pci_assign_all_busses;
+ struct pci_controller * hose;
+ int host_bridge;
+
+ pci_assign_all_busses = 1;
+
+ hose = pcibios_alloc_controller();
+
+ if (!hose)
+ return;
+
+ ppc_md.pci_swizzle = common_swizzle;
+
+ hose->first_busno = 0;
+ hose->bus_offset = 0;
+ hose->last_busno = 0xff;
+
+#ifdef CONFIG_ADS8272
+ hose->set_cfg_type = 1;
+#endif
+
+ setup_m8260_indirect_pci(hose,
+ (unsigned long)&cpm2_immr->im_pci.pci_cfg_addr,
+ (unsigned long)&cpm2_immr->im_pci.pci_cfg_data);
+
+ /* Make sure it is a supported bridge */
+ early_read_config_dword(hose,
+ 0,
+ PCI_DEVFN(0,0),
+ PCI_VENDOR_ID,
+ &host_bridge);
+ switch (host_bridge) {
+ case PCI_DEVICE_ID_MPC8265:
+ break;
+ case PCI_DEVICE_ID_MPC8272:
+ break;
+ default:
+ printk("Attempting to use unrecognized host bridge ID"
+ " 0x%08x.\n", host_bridge);
+ break;
+ }
+
+ pq2ads_setup_pci(hose);
+
+ hose->io_space.start = M82xx_PCI_LOWER_IO;
+ hose->io_space.end = M82xx_PCI_UPPER_IO;
+ hose->mem_space.start = M82xx_PCI_LOWER_MEM;
+ hose->mem_space.end = M82xx_PCI_UPPER_MMIO;
+ hose->pci_mem_offset = M82xx_PCI_MEM_OFFSET;
+
+ isa_io_base =
+ (unsigned long) ioremap(M82xx_PCI_IO_BASE,
+ M82xx_PCI_IO_SIZE);
+ hose->io_base_virt = (void *) isa_io_base;
+
+ /* setup resources */
+ pci_init_resource(&hose->mem_resources[0],
+ M82xx_PCI_LOWER_MEM,
+ M82xx_PCI_UPPER_MEM,
+ IORESOURCE_MEM|IORESOURCE_PREFETCH, "PCI prefetchable memory");
+
+ pci_init_resource(&hose->mem_resources[1],
+ M82xx_PCI_LOWER_MMIO,
+ M82xx_PCI_UPPER_MMIO,
+ IORESOURCE_MEM, "PCI memory");
+
+ pci_init_resource(&hose->io_resource,
+ M82xx_PCI_LOWER_IO,
+ M82xx_PCI_UPPER_IO,
+ IORESOURCE_IO | 1, "PCI I/O");
+
+ ppc_md.pci_exclude_device = pq2pci_exclude_device;
+ hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
+
+ ppc_md.pci_map_irq = pq2pci_map_irq;
+ ppc_md.pcibios_fixup = NULL;
+ ppc_md.pcibios_fixup_bus = NULL;
+
+}
diff -Nru a/arch/ppc/syslib/m82xx_pci.h b/arch/ppc/syslib/m82xx_pci.h
--- /dev/null Wed Dec 31 16:00:00 196900
+++ b/arch/ppc/syslib/m82xx_pci.h 2005-04-29 15:26:43 +04:00
@@ -0,0 +1,92 @@
+
+#ifndef _PPC_KERNEL_M82XX_PCI_H
+#define _PPC_KERNEL_M82XX_PCI_H
+
+#include <asm/m8260_pci.h>
+/*
+ * Local->PCI map (from CPU) controlled by
+ * MPC826x master window
+ *
+ * 0xF6000000 - 0xF7FFFFFF IO space
+ * 0x80000000 - 0xBFFFFFFF CPU2PCI memory space PCIBR0
+ *
+ * 0x80000000 - 0x9FFFFFFF PCI Mem with prefetch (Outbound ATU #1)
+ * 0xA0000000 - 0xBFFFFFFF PCI Mem w/o prefetch (Outbound ATU #2)
+ * 0xF6000000 - 0xF7FFFFFF 32-bit PCI IO (Outbound ATU #3)
+ *
+ * PCI->Local map (from PCI)
+ * MPC826x slave window controlled by
+ *
+ * 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1)
+ */
+
+/*
+ * Slave window that allows PCI masters to access MPC826x local memory.
+ * This window is set up using the first set of Inbound ATU registers
+ */
+
+#ifndef M82xx_PCI_SLAVE_MEM_LOCAL
+#define M82xx_PCI_SLAVE_MEM_LOCAL (((struct bd_info *)__res)->bi_memstart)
+#define M82xx_PCI_SLAVE_MEM_BUS (((struct bd_info *)__res)->bi_memstart)
+#define M82xx_PCI_SLAVE_MEM_SIZE (((struct bd_info *)__res)->bi_memsize)
+#endif
+
+/*
+ * This is the window that allows the CPU to access PCI address space.
+ * It will be setup with the SIU PCIBR0 register. All three PCI master
+ * windows, which allow the CPU to access PCI prefetch, non prefetch,
+ * and IO space (see below), must all fit within this window.
+ */
+
+#ifndef M82xx_PCI_LOWER_MEM
+#define M82xx_PCI_LOWER_MEM 0x80000000
+#define M82xx_PCI_UPPER_MEM 0x9fffffff
+#define M82xx_PCI_MEM_OFFSET 0x00000000
+#define M82xx_PCI_MEM_SIZE 0x20000000
+#endif
+
+#ifndef M82xx_PCI_LOWER_MMIO
+#define M82xx_PCI_LOWER_MMIO 0xa0000000
+#define M82xx_PCI_UPPER_MMIO 0xafffffff
+#define M82xx_PCI_MMIO_OFFSET 0x00000000
+#define M82xx_PCI_MMIO_SIZE 0x20000000
+#endif
+
+#ifndef M82xx_PCI_LOWER_IO
+#define M82xx_PCI_LOWER_IO 0x00000000
+#define M82xx_PCI_UPPER_IO 0x01ffffff
+#define M82xx_PCI_IO_BASE 0xf6000000
+#define M82xx_PCI_IO_SIZE 0x02000000
+#endif
+
+#ifndef M82xx_PCI_PRIM_WND_SIZE
+#define M82xx_PCI_PRIM_WND_SIZE ~(M82xx_PCI_IO_SIZE - 1U)
+#define M82xx_PCI_PRIM_WND_BASE (M82xx_PCI_IO_BASE)
+#endif
+
+#ifndef M82xx_PCI_SEC_WND_SIZE
+#define M82xx_PCI_SEC_WND_SIZE ~(M82xx_PCI_MEM_SIZE + M82xx_PCI_MMIO_SIZE - 1U)
+#define M82xx_PCI_SEC_WND_BASE (M82xx_PCI_LOWER_MEM)
+#endif
+
+#ifndef POTA_ADDR_SHIFT
+#define POTA_ADDR_SHIFT 12
+#endif
+
+#ifndef PITA_ADDR_SHIFT
+#define PITA_ADDR_SHIFT 12
+#endif
+
+#ifndef _IO_BASE
+#define _IO_BASE isa_io_base
+#endif
+
+#ifdef CONFIG_8260_PCI9
+struct pci_controller;
+extern void setup_m8260_indirect_pci(struct pci_controller* hose,
+ u32 cfg_addr, u32 cfg_data);
+#else
+#define setup_m8260_indirect_pci setup_indirect_pci
+#endif
+
+#endif /* _PPC_KERNEL_M8260_PCI_H */
diff -Nru a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
--- a/include/asm-ppc/cpm2.h 2005-04-29 15:26:43 +04:00
+++ b/include/asm-ppc/cpm2.h 2005-04-29 15:26:43 +04:00
@@ -1039,6 +1039,52 @@
#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register 4-31
+ */
+#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
+#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
+#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
+#define SIUMCR_CDIS 0x10000000 /* Core Disable */
+#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
+#define SIUMCR_DPPC01 0x04000000 /* - " - */
+#define SIUMCR_DPPC10 0x08000000 /* - " - */
+#define SIUMCR_DPPC11 0x0c000000 /* - " - */
+#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
+#define SIUMCR_L2CPC01 0x01000000 /* - " - */
+#define SIUMCR_L2CPC10 0x02000000 /* - " - */
+#define SIUMCR_L2CPC11 0x03000000 /* - " - */
+#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
+#define SIUMCR_LBPC01 0x00400000 /* - " - */
+#define SIUMCR_LBPC10 0x00800000 /* - " - */
+#define SIUMCR_LBPC11 0x00c00000 /* - " - */
+#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
+#define SIUMCR_APPC01 0x00100000 /* - " - */
+#define SIUMCR_APPC10 0x00200000 /* - " - */
+#define SIUMCR_APPC11 0x00300000 /* - " - */
+#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
+#define SIUMCR_CS10PC01 0x00040000 /* - " - */
+#define SIUMCR_CS10PC10 0x00080000 /* - " - */
+#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
+#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
+#define SIUMCR_BCTLC01 0x00010000 /* - " - */
+#define SIUMCR_BCTLC10 0x00020000 /* - " - */
+#define SIUMCR_BCTLC11 0x00030000 /* - " - */
+#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
+#define SIUMCR_MMR01 0x00004000 /* - " - */
+#define SIUMCR_MMR10 0x00008000 /* - " - */
+#define SIUMCR_MMR11 0x0000c000 /* - " - */
+#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control Register 9-8
+ */
+#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
+#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
+#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
+#define SCCR_PCIDF_SHIFT 3
+
+
#endif /* __CPM2__ */
#endif /* __KERNEL__ */
diff -Nru a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h
--- a/include/asm-ppc/m8260_pci.h 2005-04-29 15:26:43 +04:00
+++ b/include/asm-ppc/m8260_pci.h 2005-04-29 15:26:43 +04:00
@@ -19,6 +19,7 @@
* Define the vendor/device ID for the MPC8265.
*/
#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
+#define PCI_DEVICE_ID_MPC8272 ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)
#define M8265_PCIBR0 0x101ac
#define M8265_PCIBR1 0x101b0
diff -Nru a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
--- a/include/asm-ppc/mpc8260.h 2005-04-29 15:26:43 +04:00
+++ b/include/asm-ppc/mpc8260.h 2005-04-29 15:26:43 +04:00
@@ -41,7 +41,7 @@
#endif
#ifdef CONFIG_PCI_8260
-#include <syslib/m8260_pci.h>
+#include <syslib/m82xx_pci.h>
#endif
/* Make sure the memory translation stuff is there if PCI not used.
^ permalink raw reply
* Re: porting linux on power pc mpc8xx
From: David Jander @ 2005-04-29 11:40 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <BAY17-F312F5680735EFB466C3993BE240@phx.gbl>
Hi Prinson,
On Friday 29 April 2005 12:32, prinson varghese wrote:
> I am new to the embedded system development .How i can port linux kenel to
> power pc MPC 8XX
It is already ported to most known mpc8xx devices. You should start off, going
through the archives of this mailing-list, and visit this site:
http://www.denx.de
There you can download actual sources of linux-2.4 kernels. My advice, use
linux_2_4_devel cvs tree if you have no particular reason to use another
tree.
What processor do you use? What board? Is it a custom design or an existing
board?
You might be interested in u-boot also (the most commonly used bootloader for
these kind of embedded processors).
> and where i can get the kernel for the same?
www.denx.de, but probably also from www.mvista.com, and many others.
> awaiting rpaly ASAP
I am OK with this, but "ASAP" does not sound as polite as you should be
addressing a mailing list ;-)
Sincerely,
--
David Jander
Protonic Holland.
^ permalink raw reply
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