* Re: MPC8555 USB host support
From: Vitaly Bordug @ 2005-11-15 15:40 UTC (permalink / raw)
To: Kumar Gala; +Cc: 'linuxppc-embedded@ozlabs.org'
In-Reply-To: <D95D5881-250C-4B54-BD5A-54C79D9E0496@kernel.crashing.org>
Kumar Gala wrote:
> Any reason not to get this driver into the kernel main line?
I guess because this device is known to work in some specific instance,
but bot generic one. The best we can do is to consolidate our efforts to
make it more usable or state that it is impossible.
>
> - kumar
>
> On Nov 15, 2005, at 12:59 AM, Mike Rapoport wrote:
>
>> Hans Schillstrom wrote:
>>
>>> Hi Mike
>>> I'm working with a 8270 board and 2.6.12 kernel and searching for USB
>>> drivers.
>>>
>>> Could you help me finding the files ?
>>>
>> I've opened a project on the SourceForge,
>> http://cpm2usb.sourceforge.net. The file containing patch against
>> 2.6.12.3 can be downloaded at http://sourceforge.net/projects/cpm2usb.
>>
>>> I can help you with the testing.
>>> What status do they have right now ?
>>>
>> The driver was developed on MPC8272ADS, but should go as well on 8270
>> since they have the same USB host controller AFAIK.
>> Currently, as far as I tested it works fine with full-speed single
>> device attached through hub, but fails is there are transfers from/to
>> several devices simultaneously.
>> As for the code itself, it's far from being perfect.
>>
>>> Regards Hans
>>>
>>
>>
>> --Sincerely yours,
>> Mike Rapoport
>>
>>
>> _______________________________________________
>> Linuxppc-embedded mailing list
>> Linuxppc-embedded@ozlabs.org
>> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
--
Sincerely,
Vitaly
^ permalink raw reply
* Re: MPC8555 USB host support
From: Mike Rapoport @ 2005-11-15 15:38 UTC (permalink / raw)
To: Kumar Gala; +Cc: 'linuxppc-embedded@ozlabs.org'
In-Reply-To: <D95D5881-250C-4B54-BD5A-54C79D9E0496@kernel.crashing.org>
Kumar Gala wrote:
> Any reason not to get this driver into the kernel main line?
In my opinion there is a lot of work to be done to get the driver
upstream. If you'd like to I can clean it up and post a patch here.
>
> - kumar
>
> On Nov 15, 2005, at 12:59 AM, Mike Rapoport wrote:
>
>
--
Sincerely yours,
Mike Rapoport
^ permalink raw reply
* Re: MPC8555 USB host support
From: Kumar Gala @ 2005-11-15 15:22 UTC (permalink / raw)
To: Mike Rapoport; +Cc: 'linuxppc-embedded@ozlabs.org'
In-Reply-To: <43798741.5070604@compulab.co.il>
Any reason not to get this driver into the kernel main line?
- kumar
On Nov 15, 2005, at 12:59 AM, Mike Rapoport wrote:
> Hans Schillstrom wrote:
>
>> Hi Mike
>> I'm working with a 8270 board and 2.6.12 kernel and searching for USB
>> drivers.
>>
>> Could you help me finding the files ?
>>
> I've opened a project on the SourceForge, http://
> cpm2usb.sourceforge.net. The file containing patch against 2.6.12.3
> can be downloaded at http://sourceforge.net/projects/cpm2usb.
>
>> I can help you with the testing.
>> What status do they have right now ?
>>
> The driver was developed on MPC8272ADS, but should go as well on
> 8270 since they have the same USB host controller AFAIK.
> Currently, as far as I tested it works fine with full-speed single
> device attached through hub, but fails is there are transfers from/
> to several devices simultaneously.
> As for the code itself, it's far from being perfect.
>
>> Regards Hans
>>
>
>
> --
> Sincerely yours,
> Mike Rapoport
>
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: interrupts limit??
From: Mark Chambers @ 2005-11-15 12:40 UTC (permalink / raw)
To: zjznliang, linuxppc-embedded
In-Reply-To: <20051115054109.CE1FD68763@ozlabs.org>
> Hi ,linuxppc-embedded ！
>
> I have done the interrupt request by request_irq() on the Linux 2.4.25
,when typing the 'cat /proc/interrupts', I can see the information as follow
:
>
> /proc # cat interrupts
> CPU0
> 2: 3420 8xx SIU Edge wbga_interrupt
> 5: 0 8xx SIU Edge CPM cascade
> 15: 0 8xx SIU Edge tbint
> 16: 0 CPM Edge error
> 20: 801 CPM Edge SMC1
>
> and I can see the number of wbga_interrupt is increasing. But a few
minutes later ,the number is locked at 128000 as follow:
>
> /proc # cat interrupts
> CPU0
> 2: 128000 8xx SIU Edge wbga_interrupt
> 5: 0 8xx SIU Edge CPM cascade
> 15: 0 8xx SIU Edge tbint
> 16: 0 CPM Edge error
> 20: 833 CPM Edge SMC1
>
> and there is no wbga_interrupt any more....what's the matter with the
interrupt?why is 128000???
>
>
The problem is not /proc/interrupts, if that's what you're thinking. The
number can go much
higher. Believe what it's telling you: Your driver has a problem and has
stopped generating
interrupts.
Mark Chambers
^ permalink raw reply
* Re: [PATCH] ppc: Fix boot with yaboot with ARCH=ppc
From: Mikael Pettersson @ 2005-11-15 12:33 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list, Linux Kernel list
In-Reply-To: <1132039305.5646.17.camel@gaston>
Benjamin Herrenschmidt writes:
> The merge of machine types broke boot with yaboot & ARCH=ppc due to the
> old code still retreiving the old-syle machine type passed in by yaboot.
> This patch fixes it by translating those old numbers. Since that whole
> mecanism is deprecated, this is a temporary fix until ARCH=ppc uses the
> new prom_init that the merged architecture now uses for both ppc32 and
> ppc64 (after 2.6.15)
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This fixed my eMac, thanks.
Acked-by: Mikael Pettersson <mikpe@csd.uu.se>
>
> Index: linux-work/arch/ppc/kernel/setup.c
> ===================================================================
> --- linux-work.orig/arch/ppc/kernel/setup.c 2005-11-15 18:15:23.000000000 +1100
> +++ linux-work/arch/ppc/kernel/setup.c 2005-11-15 18:18:37.000000000 +1100
> @@ -602,7 +602,19 @@
> #endif /* CONFIG_BLK_DEV_INITRD */
> #ifdef CONFIG_PPC_MULTIPLATFORM
> case BI_MACHTYPE:
> - _machine = data[0];
> + /* Machine types changed with the merge. Since the
> + * bootinfo are now deprecated, we can just hard code
> + * the appropriate conversion here for when we are
> + * called with yaboot which passes us a machine type
> + * this way.
> + */
> + switch(data[0]) {
> + case 1: _machine = _MACH_prep; break;
> + case 2: _machine = _MACH_Pmac; break;
> + case 4: _machine = _MACH_chrp; break;
> + default:
> + _machine = data[0];
> + }
> break;
> #endif
> case BI_MEMSIZE:
>
>
> -
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
>
^ permalink raw reply
* porting linux to new board type
From: Joachim Denil @ 2005-11-15 12:03 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 1138 bytes --]
Hi,
For an internship I have to port linux to custom made board. I assume I'll
have to set the memory-map right and make the hardware initialize, set IRQ,
.. Browsing trough the kernel source I found that all that happens within
/arch/ppc/platforms and there are separate files for each board. But how do
I start to write my own code. Can someone give me some pointers or is there
any documentation on this subject? This is what my board is made of:
* 64 Mb SDRAM (a PLD copy's the kernel to this location (0x00000000))
* 1 MB boot ram (a PLD copy's the boot loader from flash to this
location at the end of the memory map)
* MMC card reader
* Flash 8MB (don't have to use it though-> the PLD's use them to copy
boot loader and kernel there)
* Leds that I can use through a PLD-register
The processor is a 405Gr processor, 1 UART is connected to a V24 iface.
The boot loader is a striped version of ppcboot, and is now used to load a
self written RTOS. So I guess I can use that version.
Is there besides this something else I 'll have to adjust?
Thanks,
Joachim Denil
Student @ Karel De Grote hogeschool Antwerpen (Belgium)
[-- Attachment #2: Type: text/html, Size: 8979 bytes --]
^ permalink raw reply
* Re: MPC8555 USB host support
From: Alexandre BASTOS @ 2005-11-15 12:03 UTC (permalink / raw)
To: Mike Rapoport; +Cc: linuxppc-embedded
In-Reply-To: <43798741.5070604@compulab.co.il>
Mike,
> I've opened a project on the SourceForge,
> http://cpm2usb.sourceforge.net. The file containing patch against
> 2.6.12.3 can be downloaded at http://sourceforge.net/projects/cpm2usb.
>
> The driver was developed on MPC8272ADS, but should go as well on 8270
> since they have the same USB host controller AFAIK.
> Currently, as far as I tested it works fine with full-speed single
> device attached through hub, but fails is there are transfers from/to
> several devices simultaneously.
> As for the code itself, it's far from being perfect.
I have been testing your cpm2usb driver from sourceforge on my
MPC8272ADS and I couldn't get a usb 2.0 pendrive working.
usbcore tries to identify the device with both schemes, old and
new, but the hcd returns always a timeout. The output from console:
# modprobe usbcore
usbcore: registered new driver usbfs
usbcore: registered new driver hub
# modprobe m82xx-hcd
=> driver mpc82xx-hcd, 2005
mpc82xx-hcd mpc82xx-hcd.3: PQ2 intergrated USB controller v0.1
mpc82xx-hcd mpc82xx-hcd.3: new USB bus registered, assigned bus number 1
usb usb1: Product: PQ2 intergrated USB controller v0.1
usb usb1: Manufacturer: Linux 2.6.12 mpc82xx-hcd
usb usb1: SerialNumber: mpc82xx-hcd.3
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
PQ2USB: debug file creation
[... After pendrive insertion]
usb 1-1: new full speed USB device using mpc82xx-hcd and address 2
usb 1-1: device descriptor read/64, error -110
usb 1-1: device descriptor read/64, error -110
usb 1-1: new full speed USB device using mpc82xx-hcd and address 3
usb 1-1: device descriptor read/64, error -110
usb 1-1: device descriptor read/64, error -110
usb 1-1: new full speed USB device using mpc82xx-hcd and address 4
usb 1-1: device not accepting address 4, error -110
usb 1-1: new full speed USB device using mpc82xx-hcd and address 5
usb 1-1: device not accepting address 5, error -110
To compile the driver as a module, I made only a change in "tx_err"
function from m82xx-hcd.c, which shouldn't be affecting.
I have also commented out the re-definition of BCSR_ADDR, which is
already defined to f4500000 in pq2ads.h
--- m82xx-hcd.c.orig 2005-11-15 12:05:40.547987056 +0100
+++ m82xx-hcd.c 2005-11-14 18:15:13.000000000 +0100
@@ -98,7 +98,7 @@
hp->usb_clock = USB_CLOCK_PC24_CLK8;
{
-#define BCSR_ADDR ((uint)0xf8000000)
+//#define BCSR_ADDR ((uint)0xf8000000)
volatile uint* bcsr_usb = (volatile uint*)(BCSR_ADDR +
BCSR_USB_OFFSET);
@@ -281,7 +281,9 @@
static void tx_err(struct m8xxhci_private *hp, int ber)
{
volatile usbregs_t *usbregs = hp->usbregs;
- volatile cpm_cpm2_t *cp = cpmp;
+ //volatile cpm_cpm2_t *cp = cpmp;
+ volatile cpm2_map_t *immap = (volatile cpm2_map_t *)CPM_MAP_ADDR;
+ volatile cpm_cpm2_t *cp = &immap->im_cpm;
if ( hp->active_qe )
hp->stats.txe[hp->active_qe->qtype]++;
So, any idea which could be happening? I have little knowledge about usb
so I am quite lost.
Thanks.
Alex BASTOS
^ permalink raw reply
* Re: BDI2000 and Linux 2.6 kernel
From: Marcelo Tosatti @ 2005-11-15 5:46 UTC (permalink / raw)
To: Guillaume Autran; +Cc: support, linux-ppc-embedded
In-Reply-To: <437920D3.8020105@mrv.com>
On Mon, Nov 14, 2005 at 06:42:11PM -0500, Guillaume Autran wrote:
> Hi Marcelo,
>
> Despite your patch, I'm still having trouble getting my BDI2000 to
> translate kernel virtual address to physical address on a 2.6.13 kernel.
>
> What should I look for to make sure I set it up properly ?
Hi Guillaume,
Can you please describe what problems are you having in more detail?
Do you still get "*** MMU: address translation for 0xCxxxxxxx" messages?
^ permalink raw reply
* Re: [PATCH] m8xx_wdt: software watchdog reset/interrupt select
From: Marcelo Tosatti @ 2005-11-15 5:42 UTC (permalink / raw)
To: Florian Schirmer; +Cc: obi, carjay, linux-ppc-embedded
In-Reply-To: <43798327.70305@tuxbox.org>
Hi Florian!
On Tue, Nov 15, 2005 at 07:41:43AM +0100, Florian Schirmer wrote:
> Hi,
>
> >Note: From my reading of the documentation, even if the SWRI bit is
> >unset (interrupt select mode), an NMI at IRQ0 should cause the system to
> >jump to exception vector 0x100, resetting the system.
> >
> >So I'm wondering if the interrupt mode ever worked?
>
> Never tried the interrupt mode. IMHO doesn't make much sense for a
> watchdog. Why don't you simply set SWRI?
The SYPCR register can be set only _once_ at machine startup and the
bootloader in question does not have an option to change the mode. Many
bootloaders probably dont.
> >+static void m8xx_wdt_timer_func(unsigned long data)
> >+{
> >+ m8xx_wdt_reset();
> >+ m8xx_wdt_timer.expires = jiffies + 25;
> >+ add_timer(&m8xx_wdt_timer);
> >+}
> >+
> >+void m8xx_wdt_install_timer(volatile immap_t *imap)
> >+{
> >+ m8xx_wdt_timer.expires = jiffies + 25;
> >+ add_timer(&m8xx_wdt_timer);
> >+}
>
> m8xx_wdt_install_timer doesn't need imap and you could call it from
> m8xx_wdt_timer_func to re-engange the timer resulting in less duplicated
> code. Just a cosmetic thing though.
Indeed. Will update the patch and resend you for review.
Thanks
^ permalink raw reply
* Re: [PATCH] powerpc: put page page_to_virt for Book-e processors
From: Christoph Hellwig @ 2005-11-15 9:20 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, linuxppc64-dev
In-Reply-To: <Pine.LNX.4.44.0511141721190.9033-100000@gate.crashing.org>
On Mon, Nov 14, 2005 at 05:21:44PM -0600, Kumar Gala wrote:
> Book-E processors use page_to_virt since we have to always translate.
Why can't you use the proper page_address() macro?
^ permalink raw reply
* [PATCH] ppc: Fix boot with yaboot with ARCH=ppc
From: Benjamin Herrenschmidt @ 2005-11-15 7:21 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev list, Linux Kernel list
The merge of machine types broke boot with yaboot & ARCH=ppc due to the
old code still retreiving the old-syle machine type passed in by yaboot.
This patch fixes it by translating those old numbers. Since that whole
mecanism is deprecated, this is a temporary fix until ARCH=ppc uses the
new prom_init that the merged architecture now uses for both ppc32 and
ppc64 (after 2.6.15)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Index: linux-work/arch/ppc/kernel/setup.c
===================================================================
--- linux-work.orig/arch/ppc/kernel/setup.c 2005-11-15 18:15:23.000000000 +1100
+++ linux-work/arch/ppc/kernel/setup.c 2005-11-15 18:18:37.000000000 +1100
@@ -602,7 +602,19 @@
#endif /* CONFIG_BLK_DEV_INITRD */
#ifdef CONFIG_PPC_MULTIPLATFORM
case BI_MACHTYPE:
- _machine = data[0];
+ /* Machine types changed with the merge. Since the
+ * bootinfo are now deprecated, we can just hard code
+ * the appropriate conversion here for when we are
+ * called with yaboot which passes us a machine type
+ * this way.
+ */
+ switch(data[0]) {
+ case 1: _machine = _MACH_prep; break;
+ case 2: _machine = _MACH_Pmac; break;
+ case 4: _machine = _MACH_chrp; break;
+ default:
+ _machine = data[0];
+ }
break;
#endif
case BI_MEMSIZE:
^ permalink raw reply
* Re: MPC8555 USB host support
From: Mike Rapoport @ 2005-11-15 6:59 UTC (permalink / raw)
To: Hans Schillstrom; +Cc: 'linuxppc-embedded@ozlabs.org'
In-Reply-To: <1131960060.7748.9.camel@hawk.pwav.net>
Hans Schillstrom wrote:
>Hi Mike
>I'm working with a 8270 board and 2.6.12 kernel and searching for USB
>drivers.
>
>Could you help me finding the files ?
>
>
I've opened a project on the SourceForge,
http://cpm2usb.sourceforge.net. The file containing patch against
2.6.12.3 can be downloaded at http://sourceforge.net/projects/cpm2usb.
>I can help you with the testing.
>What status do they have right now ?
>
>
The driver was developed on MPC8272ADS, but should go as well on 8270
since they have the same USB host controller AFAIK.
Currently, as far as I tested it works fine with full-speed single
device attached through hub, but fails is there are transfers from/to
several devices simultaneously.
As for the code itself, it's far from being perfect.
>Regards
>Hans
>
>
--
Sincerely yours,
Mike Rapoport
^ permalink raw reply
* Re: [PATCH] m8xx_wdt: software watchdog reset/interrupt select
From: Florian Schirmer @ 2005-11-15 6:41 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: obi, carjay, linux-ppc-embedded
In-Reply-To: <20051114143821.GA28852@logos.cnet>
Hi,
> Note: From my reading of the documentation, even if the SWRI bit is
> unset (interrupt select mode), an NMI at IRQ0 should cause the system to
> jump to exception vector 0x100, resetting the system.
>
> So I'm wondering if the interrupt mode ever worked?
Never tried the interrupt mode. IMHO doesn't make much sense for a
watchdog. Why don't you simply set SWRI?
> +static void m8xx_wdt_timer_func(unsigned long data)
> +{
> + m8xx_wdt_reset();
> + m8xx_wdt_timer.expires = jiffies + 25;
> + add_timer(&m8xx_wdt_timer);
> +}
> +
> +void m8xx_wdt_install_timer(volatile immap_t *imap)
> +{
> + m8xx_wdt_timer.expires = jiffies + 25;
> + add_timer(&m8xx_wdt_timer);
> +}
m8xx_wdt_install_timer doesn't need imap and you could call it from
m8xx_wdt_timer_func to re-engange the timer resulting in less duplicated
code. Just a cosmetic thing though.
Best,
Florian
^ permalink raw reply
* Re: [PATCH] m8xx_wdt: software watchdog reset/interrupt select\
From: Florian Schirmer @ 2005-11-15 6:11 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: obi, carjay, linux-ppc-embedded
In-Reply-To: <20051114160302.GC29411@logos.cnet>
Hi,
> Actually, drivers/char/watchdog/mpc8xx_wdt.c is a module, while
> some of the initialization code must reside in the kernel image.
>
> Thats the reason for the split - not sure if merging the two
> files is worth?
If you have a short timeout (like the 2 secs we had) then you need to
have the handler ready long before the module could be loaded.
Best,
Florian
^ permalink raw reply
* interrupts limit??
From: zjznliang @ 2005-11-15 5:26 UTC (permalink / raw)
To: linuxppc-embedded
SGkgLGxpbnV4cHBjLWVtYmVkZGVkIKOhDQoNCgkJICBJIGhhdmUgZG9uZSB0aGUgaW50ZXJydXB0
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ZyB0aGUgJ2NhdCAvcHJvYy9pbnRlcnJ1cHRzJywgSSBjYW4gc2VlIHRoZSBpbmZvcm1hdGlvbiBh
cyBmb2xsb3cgOg0KDQovcHJvYyAjIGNhdCBpbnRlcnJ1cHRzDQogICAgICAgICAgIENQVTANCiAg
MjogICAgICAgMzQyMCAgIDh4eCBTSVUgICBFZGdlICAgICAgd2JnYV9pbnRlcnJ1cHQNCiAgNTog
ICAgICAgICAgMCAgIDh4eCBTSVUgICBFZGdlICAgICAgQ1BNIGNhc2NhZGUNCiAxNTogICAgICAg
ICAgMCAgIDh4eCBTSVUgICBFZGdlICAgICAgdGJpbnQNCiAxNjogICAgICAgICAgMCAgIENQTSAg
ICAgICBFZGdlICAgICAgZXJyb3INCiAyMDogICAgICAgIDgwMSAgIENQTSAgICAgICBFZGdlICAg
ICAgU01DMQ0KDQphbmQgSSBjYW4gc2VlIHRoZSBudW1iZXIgb2Ygd2JnYV9pbnRlcnJ1cHQgaXMg
aW5jcmVhc2luZy4gQnV0IGEgZmV3IG1pbnV0ZXMgbGF0ZXIgLHRoZSBudW1iZXIgaXMgbG9ja2Vk
IGF0IDEyODAwMCBhcyBmb2xsb3c6DQoNCi9wcm9jICMgY2F0IGludGVycnVwdHMNCiAgICAgICAg
ICAgQ1BVMA0KICAyOiAgICAgMTI4MDAwICAgOHh4IFNJVSAgIEVkZ2UgICAgICB3YmdhX2ludGVy
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IDE1OiAgICAgICAgICAwICAgOHh4IFNJVSAgIEVkZ2UgICAgICB0YmludA0KIDE2OiAgICAgICAg
ICAwICAgQ1BNICAgICAgIEVkZ2UgICAgICBlcnJvcg0KIDIwOiAgICAgICAgODMzICAgQ1BNICAg
ICAgIEVkZ2UgICAgICBTTUMxDQoNCmFuZCB0aGVyZSBpcyBubyB3YmdhX2ludGVycnVwdCBhbnkg
bW9yZS4uLi53aGF0J3MgdGhlIG1hdHRlciB3aXRoIHRoZSBpbnRlcnJ1cHQ/d2h5IGlzIDEyODAw
MD8/PyANCg0KDQqhoaGhemp6bmxpYW5nDQqhoaGhoaGhoaGhoaGhoaGhemp6bmxpYW5nX3BvcG9A
MTYzLmNvbQ0KoaGhoaGhoaGhoaGhoaGhoaGhoaEyMDA1LTExLTE1DQo=
^ permalink raw reply
* Re: [PATCH] powerpc: Merge align.c
From: Benjamin Herrenschmidt @ 2005-11-15 5:35 UTC (permalink / raw)
To: Becky Bruce; +Cc: linuxppc64-dev, linuxppc-dev list
In-Reply-To: <269d7972781989e47cc114f8e2124b80@freescale.com>
On Mon, 2005-11-14 at 23:10 -0600, Becky Bruce wrote:
> Ben,
>
> I've just done some basic testing of lmw/stmw, lwz/stw, lhx/sth,
> lfs/stfs, and lfd/stfd misaligned across a doubleword boundary, and
> everything looks good so far. I'll check out the byte reversals and a
> few other forms tomorrow.
Excellent, thanks ! BTW. Make sure you test these one CPUs that actually
trap on misaligned accesses :) Best is probably to do the misaligned
access accross a page boundary, that's what most CPUs can do.
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Merge align.c
From: Becky Bruce @ 2005-11-15 5:10 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc64-dev, linuxppc-dev list
In-Reply-To: <1132001719.5504.204.camel@gaston>
Ben,
I've just done some basic testing of lmw/stmw, lwz/stw, lhx/sth,=20
lfs/stfs, and lfd/stfd misaligned across a doubleword boundary, and=20
everything looks good so far. I'll check out the byte reversals and a=20=
few other forms tomorrow.
Cheers,
B
On Nov 14, 2005, at 2:55 PM, Benjamin Herrenschmidt wrote:
> On Mon, 2005-11-14 at 13:53 -0600, Becky Bruce wrote:
> > Ben,
> >
> > I talked to Kumar about this a little bit (I had started a merge of
> > this file, but got distracted!) and he doesn't have any test cases.=A0=
> > I'll put something together and test this out on some of the 32-bit
> > systems I have here in my lab.=A0 It won't be complete, but it will =
be
> > something.......
>
> Thanks,
> Ben.
>
^ permalink raw reply
* [PATCH] powerpc: Merge align.c (#2)
From: Benjamin Herrenschmidt @ 2005-11-15 3:34 UTC (permalink / raw)
To: linuxppc-dev list, linuxppc64-dev
Need testing !!!
This patch merges align.c, the result isn't quite what was in ppc64 nor
what was in ppc32 :) It should implement all the functionalities of both
though. Kumar, since you played with that in the past, I suppose you
have some test cases for verifying that it works properly before I dig
out the 601 machine ? :)
Since it's likely that I won't be able to test all scenario, code
inspection is much welcome.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
No difference, just rebased on current -git
Index: linux-work/arch/powerpc/kernel/Makefile
===================================================================
--- linux-work.orig/arch/powerpc/kernel/Makefile 2005-11-15 13:31:57.000000000 +1100
+++ linux-work/arch/powerpc/kernel/Makefile 2005-11-15 14:31:22.000000000 +1100
@@ -12,7 +12,7 @@
endif
obj-y := semaphore.o cputable.o ptrace.o syscalls.o \
- irq.o signal_32.o pmc.o vdso.o
+ irq.o align.o signal_32.o pmc.o vdso.o
obj-y += vdso32/
obj-$(CONFIG_PPC64) += setup_64.o binfmt_elf32.o sys_ppc32.o \
signal_64.o ptrace32.o systbl.o \
Index: linux-work/arch/powerpc/kernel/align.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/arch/powerpc/kernel/align.c 2005-11-15 14:31:22.000000000 +1100
@@ -0,0 +1,513 @@
+/* align.c - handle alignment exceptions for the Power PC.
+ *
+ * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
+ * Copyright (c) 1998-1999 TiVo, Inc.
+ * PowerPC 403GCX modifications.
+ * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
+ * PowerPC 403GCX/405GP modifications.
+ * Copyright (c) 2001-2002 PPC64 team, IBM Corp
+ * 64-bit and Power4 support
+ * Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp
+ * <benh@kernel.crashing.org>
+ * Merge ppc32 and ppc64 implementations
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <asm/processor.h>
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/cache.h>
+#include <asm/cputable.h>
+
+struct aligninfo {
+ unsigned char len;
+ unsigned char flags;
+};
+
+#define IS_XFORM(inst) (((inst) >> 26) == 31)
+#define IS_DSFORM(inst) (((inst) >> 26) >= 56)
+
+#define INVALID { 0, 0 }
+
+#define LD 1 /* load */
+#define ST 2 /* store */
+#define SE 4 /* sign-extend value */
+#define F 8 /* to/from fp regs */
+#define U 0x10 /* update index register */
+#define M 0x20 /* multiple load/store */
+#define SW 0x40 /* byte swap int or ... */
+#define S 0x40 /* ... single-precision fp */
+#define SX 0x40 /* byte count in XER */
+#define HARD 0x80 /* string, stwcx. */
+
+#define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
+
+#define SWAP(a, b) (t = (a), (a) = (b), (b) = t)
+
+/*
+ * The PowerPC stores certain bits of the instruction that caused the
+ * alignment exception in the DSISR register. This array maps those
+ * bits to information about the operand length and what the
+ * instruction would do.
+ */
+static struct aligninfo aligninfo[128] = {
+ { 4, LD }, /* 00 0 0000: lwz / lwarx */
+ INVALID, /* 00 0 0001 */
+ { 4, ST }, /* 00 0 0010: stw */
+ INVALID, /* 00 0 0011 */
+ { 2, LD }, /* 00 0 0100: lhz */
+ { 2, LD+SE }, /* 00 0 0101: lha */
+ { 2, ST }, /* 00 0 0110: sth */
+ { 4, LD+M }, /* 00 0 0111: lmw */
+ { 4, LD+F+S }, /* 00 0 1000: lfs */
+ { 8, LD+F }, /* 00 0 1001: lfd */
+ { 4, ST+F+S }, /* 00 0 1010: stfs */
+ { 8, ST+F }, /* 00 0 1011: stfd */
+ INVALID, /* 00 0 1100 */
+ { 8, LD }, /* 00 0 1101: ld/ldu/lwa */
+ INVALID, /* 00 0 1110 */
+ { 8, ST }, /* 00 0 1111: std/stdu */
+ { 4, LD+U }, /* 00 1 0000: lwzu */
+ INVALID, /* 00 1 0001 */
+ { 4, ST+U }, /* 00 1 0010: stwu */
+ INVALID, /* 00 1 0011 */
+ { 2, LD+U }, /* 00 1 0100: lhzu */
+ { 2, LD+SE+U }, /* 00 1 0101: lhau */
+ { 2, ST+U }, /* 00 1 0110: sthu */
+ { 4, ST+M }, /* 00 1 0111: stmw */
+ { 4, LD+F+S+U }, /* 00 1 1000: lfsu */
+ { 8, LD+F+U }, /* 00 1 1001: lfdu */
+ { 4, ST+F+S+U }, /* 00 1 1010: stfsu */
+ { 8, ST+F+U }, /* 00 1 1011: stfdu */
+ INVALID, /* 00 1 1100 */
+ INVALID, /* 00 1 1101 */
+ INVALID, /* 00 1 1110 */
+ INVALID, /* 00 1 1111 */
+ { 8, LD }, /* 01 0 0000: ldx */
+ INVALID, /* 01 0 0001 */
+ { 8, ST }, /* 01 0 0010: stdx */
+ INVALID, /* 01 0 0011 */
+ INVALID, /* 01 0 0100 */
+ { 4, LD+SE }, /* 01 0 0101: lwax */
+ INVALID, /* 01 0 0110 */
+ INVALID, /* 01 0 0111 */
+ { 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */
+ { 4, LD+M+HARD }, /* 01 0 1001: lswi */
+ { 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */
+ { 4, ST+M+HARD }, /* 01 0 1011: stswi */
+ INVALID, /* 01 0 1100 */
+ { 8, LD+U }, /* 01 0 1101: ldu */
+ INVALID, /* 01 0 1110 */
+ { 8, ST+U }, /* 01 0 1111: stdu */
+ { 8, LD+U }, /* 01 1 0000: ldux */
+ INVALID, /* 01 1 0001 */
+ { 8, ST+U }, /* 01 1 0010: stdux */
+ INVALID, /* 01 1 0011 */
+ INVALID, /* 01 1 0100 */
+ { 4, LD+SE+U }, /* 01 1 0101: lwaux */
+ INVALID, /* 01 1 0110 */
+ INVALID, /* 01 1 0111 */
+ INVALID, /* 01 1 1000 */
+ INVALID, /* 01 1 1001 */
+ INVALID, /* 01 1 1010 */
+ INVALID, /* 01 1 1011 */
+ INVALID, /* 01 1 1100 */
+ INVALID, /* 01 1 1101 */
+ INVALID, /* 01 1 1110 */
+ INVALID, /* 01 1 1111 */
+ INVALID, /* 10 0 0000 */
+ INVALID, /* 10 0 0001 */
+ INVALID, /* 10 0 0010: stwcx. */
+ INVALID, /* 10 0 0011 */
+ INVALID, /* 10 0 0100 */
+ INVALID, /* 10 0 0101 */
+ INVALID, /* 10 0 0110 */
+ INVALID, /* 10 0 0111 */
+ { 4, LD+SW }, /* 10 0 1000: lwbrx */
+ INVALID, /* 10 0 1001 */
+ { 4, ST+SW }, /* 10 0 1010: stwbrx */
+ INVALID, /* 10 0 1011 */
+ { 2, LD+SW }, /* 10 0 1100: lhbrx */
+ { 4, LD+SE }, /* 10 0 1101 lwa */
+ { 2, ST+SW }, /* 10 0 1110: sthbrx */
+ INVALID, /* 10 0 1111 */
+ INVALID, /* 10 1 0000 */
+ INVALID, /* 10 1 0001 */
+ INVALID, /* 10 1 0010 */
+ INVALID, /* 10 1 0011 */
+ INVALID, /* 10 1 0100 */
+ INVALID, /* 10 1 0101 */
+ INVALID, /* 10 1 0110 */
+ INVALID, /* 10 1 0111 */
+ INVALID, /* 10 1 1000 */
+ INVALID, /* 10 1 1001 */
+ INVALID, /* 10 1 1010 */
+ INVALID, /* 10 1 1011 */
+ INVALID, /* 10 1 1100 */
+ INVALID, /* 10 1 1101 */
+ INVALID, /* 10 1 1110 */
+ { 0, ST+HARD }, /* 10 1 1111: dcbz */
+ { 4, LD }, /* 11 0 0000: lwzx */
+ INVALID, /* 11 0 0001 */
+ { 4, ST }, /* 11 0 0010: stwx */
+ INVALID, /* 11 0 0011 */
+ { 2, LD }, /* 11 0 0100: lhzx */
+ { 2, LD+SE }, /* 11 0 0101: lhax */
+ { 2, ST }, /* 11 0 0110: sthx */
+ INVALID, /* 11 0 0111 */
+ { 4, LD+F+S }, /* 11 0 1000: lfsx */
+ { 8, LD+F }, /* 11 0 1001: lfdx */
+ { 4, ST+F+S }, /* 11 0 1010: stfsx */
+ { 8, ST+F }, /* 11 0 1011: stfdx */
+ INVALID, /* 11 0 1100 */
+ { 8, LD+M }, /* 11 0 1101: lmd */
+ INVALID, /* 11 0 1110 */
+ { 8, ST+M }, /* 11 0 1111: stmd */
+ { 4, LD+U }, /* 11 1 0000: lwzux */
+ INVALID, /* 11 1 0001 */
+ { 4, ST+U }, /* 11 1 0010: stwux */
+ INVALID, /* 11 1 0011 */
+ { 2, LD+U }, /* 11 1 0100: lhzux */
+ { 2, LD+SE+U }, /* 11 1 0101: lhaux */
+ { 2, ST+U }, /* 11 1 0110: sthux */
+ INVALID, /* 11 1 0111 */
+ { 4, LD+F+S+U }, /* 11 1 1000: lfsux */
+ { 8, LD+F+U }, /* 11 1 1001: lfdux */
+ { 4, ST+F+S+U }, /* 11 1 1010: stfsux */
+ { 8, ST+F+U }, /* 11 1 1011: stfdux */
+ INVALID, /* 11 1 1100 */
+ INVALID, /* 11 1 1101 */
+ INVALID, /* 11 1 1110 */
+ INVALID, /* 11 1 1111 */
+};
+
+/*
+ * Create a DSISR value from the instruction
+ */
+static inline unsigned make_dsisr(unsigned instr)
+{
+ unsigned dsisr;
+
+
+ /* bits 6:15 --> 22:31 */
+ dsisr = (instr & 0x03ff0000) >> 16;
+
+ if ( IS_XFORM(instr) ) {
+ /* bits 29:30 --> 15:16 */
+ dsisr |= (instr & 0x00000006) << 14;
+ /* bit 25 --> 17 */
+ dsisr |= (instr & 0x00000040) << 8;
+ /* bits 21:24 --> 18:21 */
+ dsisr |= (instr & 0x00000780) << 3;
+ }
+ else {
+ /* bit 5 --> 17 */
+ dsisr |= (instr & 0x04000000) >> 12;
+ /* bits 1: 4 --> 18:21 */
+ dsisr |= (instr & 0x78000000) >> 17;
+ /* bits 30:31 --> 12:13 */
+ if ( IS_DSFORM(instr) )
+ dsisr |= (instr & 0x00000003) << 18;
+ }
+
+ return dsisr;
+}
+
+/*
+ * The dcbz (data cache block zero) instruction
+ * gives an alignment fault if used on non-cacheable
+ * memory. We handle the fault mainly for the
+ * case when we are running with the cache disabled
+ * for debugging.
+ */
+static int emulate_dcbz(struct pt_regs *regs, unsigned char __user *addr)
+{
+ long __user *p;
+ int i, size;
+
+#ifdef __powerpc64__
+ size = ppc64_caches.dline_size;
+#else
+ size = L1_CACHE_BYTES;
+#endif
+ p = (long __user *) (regs->dar & -size);
+ if (user_mode(regs) && !access_ok(VERIFY_WRITE, p, size))
+ return -EFAULT;
+ for (i = 0; i < size / sizeof(long); ++i)
+ if (__put_user(0, p+i))
+ return -EFAULT;
+ return 1;
+}
+
+/*
+ * Emulate load & store multiple instructions
+ */
+static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr,
+ unsigned int reg, unsigned int nb,
+ unsigned int flags, unsigned int instr)
+{
+ unsigned char *rptr;
+ int nb0, i;
+
+ /*
+ * We do not try to emulate 8 bytes multiple as they aren't really
+ * available in our operating environments and we don't try to
+ * emulate multiples operations in kernel land as they should never
+ * be used/generated there at least not on unaligned boundaries
+ */
+ if (unlikely((nb > 4) || !user_mode(regs)))
+ return 0;
+
+ /* lmw, stmw, lswi/x, stswi/x */
+ nb0 = 0;
+ if (flags & HARD) {
+ if (flags & SX) {
+ nb = regs->xer & 127;
+ if (nb == 0)
+ return 1;
+ } else {
+ if (__get_user(instr,
+ (unsigned int __user *)regs->nip))
+ return -EFAULT;
+ nb = (instr >> 11) & 0x1f;
+ if (nb == 0)
+ nb = 32;
+ }
+ if (nb + reg * 4 > 128) {
+ nb0 = nb + reg * 4 - 128;
+ nb = 128 - reg * 4;
+ }
+ } else {
+ /* lwm, stmw */
+ nb = (32 - reg) * 4;
+ }
+
+ if (!access_ok((flags & ST ? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0))
+ return -EFAULT; /* bad address */
+
+ rptr = (unsigned char *) ®s->gpr[reg];
+ if (flags & LD) {
+ for (i = 0; i < nb; ++i)
+ if (__get_user(rptr[i], addr + i))
+ return -EFAULT;
+ if (nb0 > 0) {
+ rptr = (unsigned char *) ®s->gpr[0];
+ addr += nb;
+ for (i = 0; i < nb0; ++i)
+ if (__get_user(rptr[i], addr + i))
+ return -EFAULT;
+ }
+ for (; (i & 3) != 0; ++i)
+ rptr[i] = 0;
+ } else {
+ for (i = 0; i < nb; ++i)
+ if (__put_user(rptr[i], addr + i))
+ return -EFAULT;
+ if (nb0 > 0) {
+ rptr = (unsigned char *) ®s->gpr[0];
+ addr += nb;
+ for (i = 0; i < nb0; ++i)
+ if (__put_user(rptr[i], addr + i))
+ return -EFAULT;
+ }
+ }
+ return 1;
+}
+
+
+/*
+ * Called on alignment exception. Attempts to fixup
+ *
+ * Return 1 on success
+ * Return 0 if unable to handle the interrupt
+ * Return -EFAULT if data address is bad
+ */
+
+int fix_alignment(struct pt_regs *regs)
+{
+ unsigned int instr, nb, flags;
+ unsigned int reg, areg;
+ unsigned int dsisr;
+ unsigned char __user *addr;
+ unsigned char __user *p;
+ int ret, t;
+ union {
+ long ll;
+ double dd;
+ unsigned char v[8];
+ struct {
+ unsigned hi32;
+ int low32;
+ } x32;
+ struct {
+ unsigned char hi48[6];
+ short low16;
+ } x16;
+ } data;
+
+ /*
+ * We require a complete register set, if not, then our assembly
+ * is broken
+ */
+ CHECK_FULL_REGS(regs);
+
+ dsisr = regs->dsisr;
+
+ /* Some processors don't provide us with a DSISR we can use here,
+ * let's make one up from the instruction
+ */
+ if (cpu_has_feature(CPU_FTR_NODSISRALIGN)) {
+ unsigned int real_instr;
+ if (unlikely(__get_user(real_instr,
+ (unsigned int __user *)regs->nip)))
+ return -EFAULT;
+ dsisr = make_dsisr(real_instr);
+ }
+
+ /* extract the operation and registers from the dsisr */
+ reg = (dsisr >> 5) & 0x1f; /* source/dest register */
+ areg = dsisr & 0x1f; /* register to update */
+ instr = (dsisr >> 10) & 0x7f;
+ instr |= (dsisr >> 13) & 0x60;
+
+ /* Lookup the operation in our table */
+ nb = aligninfo[instr].len;
+ flags = aligninfo[instr].flags;
+
+ /* DAR has the operand effective address */
+ addr = (unsigned char __user *)regs->dar;
+
+ /* A size of 0 indicates an instruction we don't support, with
+ * the exception of DCBZ which is handled as a special case here
+ */
+ if (instr == DCBZ)
+ return emulate_dcbz(regs, addr);
+ if (unlikely(nb == 0))
+ return 0;
+
+ /* Load/Store Multiple instructions are handled in their own
+ * function
+ */
+ if (flags & M)
+ return emulate_multiple(regs, addr, reg, nb, flags, instr);
+
+ /* Verify the address of the operand */
+ if (unlikely(user_mode(regs) &&
+ !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
+ addr, nb)))
+ return -EFAULT;
+
+ /* Force the fprs into the save area so we can reference them */
+ if (flags & F) {
+ /* userland only */
+ if (unlikely(!user_mode(regs)))
+ return 0;
+ flush_fp_to_thread(current);
+ }
+
+ /* If we are loading, get the data from user space, else
+ * get it from register values
+ */
+ if (flags & LD) {
+ data.ll = 0;
+ ret = 0;
+ p = addr;
+ switch (nb) {
+ case 8:
+ ret |= __get_user(data.v[0], p++);
+ ret |= __get_user(data.v[1], p++);
+ ret |= __get_user(data.v[2], p++);
+ ret |= __get_user(data.v[3], p++);
+ case 4:
+ ret |= __get_user(data.v[4], p++);
+ ret |= __get_user(data.v[5], p++);
+ case 2:
+ ret |= __get_user(data.v[6], p++);
+ ret |= __get_user(data.v[7], p++);
+ if (unlikely(ret))
+ return -EFAULT;
+ }
+ } else if (flags & F)
+ data.dd = current->thread.fpr[reg];
+ else
+ data.ll = regs->gpr[reg];
+
+ /* Perform other misc operations like sign extension, byteswap,
+ * or floating point single precision conversion
+ */
+ switch (flags & ~U) {
+ case LD+SE: /* sign extend */
+ if ( nb == 2 )
+ data.ll = data.x16.low16;
+ else /* nb must be 4 */
+ data.ll = data.x32.low32;
+ break;
+ case LD+S: /* byte-swap */
+ case ST+S:
+ if (nb == 2) {
+ SWAP(data.v[6], data.v[7]);
+ } else {
+ SWAP(data.v[4], data.v[7]);
+ SWAP(data.v[5], data.v[6]);
+ }
+ break;
+
+ /* Single-precision FP load and store require conversions... */
+ case LD+F+S:
+#ifdef CONFIG_PPC_FPU
+ preempt_disable();
+ enable_kernel_fp();
+ cvt_fd((float *)&data.v[4], &data.dd, ¤t->thread);
+ preempt_enable();
+#else
+ return 0;
+#endif
+ break;
+ case ST+F+S:
+#ifdef CONFIG_PPC_FPU
+ preempt_disable();
+ enable_kernel_fp();
+ cvt_df(&data.dd, (float *)&data.v[4], ¤t->thread);
+ preempt_enable();
+#else
+ return 0;
+#endif
+ break;
+ }
+
+ /* Store result to memory or update registers */
+ if (flags & ST) {
+ ret = 0;
+ p = addr;
+ switch (nb) {
+ case 8:
+ ret |= __put_user(data.v[0], p++);
+ ret |= __put_user(data.v[1], p++);
+ ret |= __put_user(data.v[2], p++);
+ ret |= __put_user(data.v[3], p++);
+ case 4:
+ ret |= __put_user(data.v[4], p++);
+ ret |= __put_user(data.v[5], p++);
+ case 2:
+ ret |= __put_user(data.v[6], p++);
+ ret |= __put_user(data.v[7], p++);
+ }
+ if (unlikely(ret))
+ return -EFAULT;
+ } else if (flags & F)
+ current->thread.fpr[reg] = data.dd;
+ else
+ regs->gpr[reg] = data.ll;
+
+ /* Update RA as needed */
+ if (flags & U)
+ regs->gpr[areg] = regs->dar;
+
+ return 1;
+}
Index: linux-work/arch/ppc/kernel/Makefile
===================================================================
--- linux-work.orig/arch/ppc/kernel/Makefile 2005-11-11 10:14:48.000000000 +1100
+++ linux-work/arch/ppc/kernel/Makefile 2005-11-15 14:31:22.000000000 +1100
@@ -13,7 +13,7 @@
extra-y += vmlinux.lds
obj-y := entry.o traps.o idle.o time.o misc.o \
- process.o align.o \
+ process.o \
setup.o \
ppc_htab.o
obj-$(CONFIG_6xx) += l2cr.o cpu_setup_6xx.o
Index: linux-work/arch/ppc64/kernel/Makefile
===================================================================
--- linux-work.orig/arch/ppc64/kernel/Makefile 2005-11-15 14:30:34.000000000 +1100
+++ linux-work/arch/ppc64/kernel/Makefile 2005-11-15 14:31:37.000000000 +1100
@@ -2,6 +2,6 @@
# Makefile for the linux ppc64 kernel.
#
-obj-y += idle.o align.o
+obj-y += idle.o
obj-$(CONFIG_PPC_MULTIPLATFORM) += nvram.o
Index: linux-work/include/asm-powerpc/cputable.h
===================================================================
--- linux-work.orig/include/asm-powerpc/cputable.h 2005-11-11 10:14:49.000000000 +1100
+++ linux-work/include/asm-powerpc/cputable.h 2005-11-15 14:31:22.000000000 +1100
@@ -90,6 +90,7 @@
#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
+#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
#ifdef __powerpc64__
/* Add the 64b processor unique features in the top half of the word */
@@ -97,7 +98,6 @@
#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
-#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
#define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
@@ -113,7 +113,6 @@
#define CPU_FTR_16M_PAGE ASM_CONST(0x0)
#define CPU_FTR_TLBIEL ASM_CONST(0x0)
#define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
-#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0)
#define CPU_FTR_IABR ASM_CONST(0x0)
#define CPU_FTR_MMCRA ASM_CONST(0x0)
#define CPU_FTR_CTRL ASM_CONST(0x0)
@@ -273,18 +272,21 @@
CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
- CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
+ CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN,
CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
- CPU_FTR_MAYBE_CAN_NAP,
+ CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN,
CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
- CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
- CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
- CPU_FTRS_E200 = CPU_FTR_USE_TB,
- CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+ CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_NODSISRALIGN,
+ CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_NODSISRALIGN,
+ CPU_FTRS_E200 = CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN,
+ CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
+ CPU_FTR_NODSISRALIGN,
CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
- CPU_FTR_BIG_PHYS,
- CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON,
+ CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN,
+ CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN,
#ifdef __powerpc64__
CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
Index: linux-work/arch/ppc64/kernel/align.c
===================================================================
--- linux-work.orig/arch/ppc64/kernel/align.c 2005-11-15 14:30:34.000000000 +1100
+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
@@ -1,396 +0,0 @@
-/* align.c - handle alignment exceptions for the Power PC.
- *
- * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
- * Copyright (c) 1998-1999 TiVo, Inc.
- * PowerPC 403GCX modifications.
- * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
- * PowerPC 403GCX/405GP modifications.
- * Copyright (c) 2001-2002 PPC64 team, IBM Corp
- * 64-bit and Power4 support
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <asm/processor.h>
-#include <asm/uaccess.h>
-#include <asm/system.h>
-#include <asm/cache.h>
-#include <asm/cputable.h>
-
-struct aligninfo {
- unsigned char len;
- unsigned char flags;
-};
-
-#define IS_XFORM(inst) (((inst) >> 26) == 31)
-#define IS_DSFORM(inst) (((inst) >> 26) >= 56)
-
-#define INVALID { 0, 0 }
-
-#define LD 1 /* load */
-#define ST 2 /* store */
-#define SE 4 /* sign-extend value */
-#define F 8 /* to/from fp regs */
-#define U 0x10 /* update index register */
-#define M 0x20 /* multiple load/store */
-#define SW 0x40 /* byte swap */
-
-#define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
-
-/*
- * The PowerPC stores certain bits of the instruction that caused the
- * alignment exception in the DSISR register. This array maps those
- * bits to information about the operand length and what the
- * instruction would do.
- */
-static struct aligninfo aligninfo[128] = {
- { 4, LD }, /* 00 0 0000: lwz / lwarx */
- INVALID, /* 00 0 0001 */
- { 4, ST }, /* 00 0 0010: stw */
- INVALID, /* 00 0 0011 */
- { 2, LD }, /* 00 0 0100: lhz */
- { 2, LD+SE }, /* 00 0 0101: lha */
- { 2, ST }, /* 00 0 0110: sth */
- { 4, LD+M }, /* 00 0 0111: lmw */
- { 4, LD+F }, /* 00 0 1000: lfs */
- { 8, LD+F }, /* 00 0 1001: lfd */
- { 4, ST+F }, /* 00 0 1010: stfs */
- { 8, ST+F }, /* 00 0 1011: stfd */
- INVALID, /* 00 0 1100 */
- { 8, LD }, /* 00 0 1101: ld */
- INVALID, /* 00 0 1110 */
- { 8, ST }, /* 00 0 1111: std */
- { 4, LD+U }, /* 00 1 0000: lwzu */
- INVALID, /* 00 1 0001 */
- { 4, ST+U }, /* 00 1 0010: stwu */
- INVALID, /* 00 1 0011 */
- { 2, LD+U }, /* 00 1 0100: lhzu */
- { 2, LD+SE+U }, /* 00 1 0101: lhau */
- { 2, ST+U }, /* 00 1 0110: sthu */
- { 4, ST+M }, /* 00 1 0111: stmw */
- { 4, LD+F+U }, /* 00 1 1000: lfsu */
- { 8, LD+F+U }, /* 00 1 1001: lfdu */
- { 4, ST+F+U }, /* 00 1 1010: stfsu */
- { 8, ST+F+U }, /* 00 1 1011: stfdu */
- INVALID, /* 00 1 1100 */
- INVALID, /* 00 1 1101 */
- INVALID, /* 00 1 1110 */
- INVALID, /* 00 1 1111 */
- { 8, LD }, /* 01 0 0000: ldx */
- INVALID, /* 01 0 0001 */
- { 8, ST }, /* 01 0 0010: stdx */
- INVALID, /* 01 0 0011 */
- INVALID, /* 01 0 0100 */
- { 4, LD+SE }, /* 01 0 0101: lwax */
- INVALID, /* 01 0 0110 */
- INVALID, /* 01 0 0111 */
- { 0, LD }, /* 01 0 1000: lswx */
- { 0, LD }, /* 01 0 1001: lswi */
- { 0, ST }, /* 01 0 1010: stswx */
- { 0, ST }, /* 01 0 1011: stswi */
- INVALID, /* 01 0 1100 */
- { 8, LD+U }, /* 01 0 1101: ldu */
- INVALID, /* 01 0 1110 */
- { 8, ST+U }, /* 01 0 1111: stdu */
- { 8, LD+U }, /* 01 1 0000: ldux */
- INVALID, /* 01 1 0001 */
- { 8, ST+U }, /* 01 1 0010: stdux */
- INVALID, /* 01 1 0011 */
- INVALID, /* 01 1 0100 */
- { 4, LD+SE+U }, /* 01 1 0101: lwaux */
- INVALID, /* 01 1 0110 */
- INVALID, /* 01 1 0111 */
- INVALID, /* 01 1 1000 */
- INVALID, /* 01 1 1001 */
- INVALID, /* 01 1 1010 */
- INVALID, /* 01 1 1011 */
- INVALID, /* 01 1 1100 */
- INVALID, /* 01 1 1101 */
- INVALID, /* 01 1 1110 */
- INVALID, /* 01 1 1111 */
- INVALID, /* 10 0 0000 */
- INVALID, /* 10 0 0001 */
- { 0, ST }, /* 10 0 0010: stwcx. */
- INVALID, /* 10 0 0011 */
- INVALID, /* 10 0 0100 */
- INVALID, /* 10 0 0101 */
- INVALID, /* 10 0 0110 */
- INVALID, /* 10 0 0111 */
- { 4, LD+SW }, /* 10 0 1000: lwbrx */
- INVALID, /* 10 0 1001 */
- { 4, ST+SW }, /* 10 0 1010: stwbrx */
- INVALID, /* 10 0 1011 */
- { 2, LD+SW }, /* 10 0 1100: lhbrx */
- { 4, LD+SE }, /* 10 0 1101 lwa */
- { 2, ST+SW }, /* 10 0 1110: sthbrx */
- INVALID, /* 10 0 1111 */
- INVALID, /* 10 1 0000 */
- INVALID, /* 10 1 0001 */
- INVALID, /* 10 1 0010 */
- INVALID, /* 10 1 0011 */
- INVALID, /* 10 1 0100 */
- INVALID, /* 10 1 0101 */
- INVALID, /* 10 1 0110 */
- INVALID, /* 10 1 0111 */
- INVALID, /* 10 1 1000 */
- INVALID, /* 10 1 1001 */
- INVALID, /* 10 1 1010 */
- INVALID, /* 10 1 1011 */
- INVALID, /* 10 1 1100 */
- INVALID, /* 10 1 1101 */
- INVALID, /* 10 1 1110 */
- { L1_CACHE_BYTES, ST }, /* 10 1 1111: dcbz */
- { 4, LD }, /* 11 0 0000: lwzx */
- INVALID, /* 11 0 0001 */
- { 4, ST }, /* 11 0 0010: stwx */
- INVALID, /* 11 0 0011 */
- { 2, LD }, /* 11 0 0100: lhzx */
- { 2, LD+SE }, /* 11 0 0101: lhax */
- { 2, ST }, /* 11 0 0110: sthx */
- INVALID, /* 11 0 0111 */
- { 4, LD+F }, /* 11 0 1000: lfsx */
- { 8, LD+F }, /* 11 0 1001: lfdx */
- { 4, ST+F }, /* 11 0 1010: stfsx */
- { 8, ST+F }, /* 11 0 1011: stfdx */
- INVALID, /* 11 0 1100 */
- { 8, LD+M }, /* 11 0 1101: lmd */
- INVALID, /* 11 0 1110 */
- { 8, ST+M }, /* 11 0 1111: stmd */
- { 4, LD+U }, /* 11 1 0000: lwzux */
- INVALID, /* 11 1 0001 */
- { 4, ST+U }, /* 11 1 0010: stwux */
- INVALID, /* 11 1 0011 */
- { 2, LD+U }, /* 11 1 0100: lhzux */
- { 2, LD+SE+U }, /* 11 1 0101: lhaux */
- { 2, ST+U }, /* 11 1 0110: sthux */
- INVALID, /* 11 1 0111 */
- { 4, LD+F+U }, /* 11 1 1000: lfsux */
- { 8, LD+F+U }, /* 11 1 1001: lfdux */
- { 4, ST+F+U }, /* 11 1 1010: stfsux */
- { 8, ST+F+U }, /* 11 1 1011: stfdux */
- INVALID, /* 11 1 1100 */
- INVALID, /* 11 1 1101 */
- INVALID, /* 11 1 1110 */
- INVALID, /* 11 1 1111 */
-};
-
-#define SWAP(a, b) (t = (a), (a) = (b), (b) = t)
-
-static inline unsigned make_dsisr(unsigned instr)
-{
- unsigned dsisr;
-
- /* create a DSISR value from the instruction */
- dsisr = (instr & 0x03ff0000) >> 16; /* bits 6:15 --> 22:31 */
-
- if ( IS_XFORM(instr) ) {
- dsisr |= (instr & 0x00000006) << 14; /* bits 29:30 --> 15:16 */
- dsisr |= (instr & 0x00000040) << 8; /* bit 25 --> 17 */
- dsisr |= (instr & 0x00000780) << 3; /* bits 21:24 --> 18:21 */
- }
- else {
- dsisr |= (instr & 0x04000000) >> 12; /* bit 5 --> 17 */
- dsisr |= (instr & 0x78000000) >> 17; /* bits 1: 4 --> 18:21 */
- if ( IS_DSFORM(instr) ) {
- dsisr |= (instr & 0x00000003) << 18; /* bits 30:31 --> 12:13 */
- }
- }
-
- return dsisr;
-}
-
-int
-fix_alignment(struct pt_regs *regs)
-{
- unsigned int instr, nb, flags;
- int t;
- unsigned long reg, areg;
- unsigned long i;
- int ret;
- unsigned dsisr;
- unsigned char __user *addr;
- unsigned char __user *p;
- unsigned long __user *lp;
- union {
- long ll;
- double dd;
- unsigned char v[8];
- struct {
- unsigned hi32;
- int low32;
- } x32;
- struct {
- unsigned char hi48[6];
- short low16;
- } x16;
- } data;
-
- /*
- * Return 1 on success
- * Return 0 if unable to handle the interrupt
- * Return -EFAULT if data address is bad
- */
-
- dsisr = regs->dsisr;
-
- if (cpu_has_feature(CPU_FTR_NODSISRALIGN)) {
- unsigned int real_instr;
- if (__get_user(real_instr, (unsigned int __user *)regs->nip))
- return 0;
- dsisr = make_dsisr(real_instr);
- }
-
- /* extract the operation and registers from the dsisr */
- reg = (dsisr >> 5) & 0x1f; /* source/dest register */
- areg = dsisr & 0x1f; /* register to update */
- instr = (dsisr >> 10) & 0x7f;
- instr |= (dsisr >> 13) & 0x60;
-
- /* Lookup the operation in our table */
- nb = aligninfo[instr].len;
- flags = aligninfo[instr].flags;
-
- /* DAR has the operand effective address */
- addr = (unsigned char __user *)regs->dar;
-
- /* A size of 0 indicates an instruction we don't support */
- /* we also don't support the multiples (lmw, stmw, lmd, stmd) */
- if ((nb == 0) || (flags & M))
- return 0; /* too hard or invalid instruction */
-
- /*
- * Special handling for dcbz
- * dcbz may give an alignment exception for accesses to caching inhibited
- * storage
- */
- if (instr == DCBZ)
- addr = (unsigned char __user *) ((unsigned long)addr & -L1_CACHE_BYTES);
-
- /* Verify the address of the operand */
- if (user_mode(regs)) {
- if (!access_ok((flags & ST? VERIFY_WRITE: VERIFY_READ), addr, nb))
- return -EFAULT; /* bad address */
- }
-
- /* Force the fprs into the save area so we can reference them */
- if (flags & F) {
- if (!user_mode(regs))
- return 0;
- flush_fp_to_thread(current);
- }
-
- /* If we are loading, get the data from user space */
- if (flags & LD) {
- data.ll = 0;
- ret = 0;
- p = addr;
- switch (nb) {
- case 8:
- ret |= __get_user(data.v[0], p++);
- ret |= __get_user(data.v[1], p++);
- ret |= __get_user(data.v[2], p++);
- ret |= __get_user(data.v[3], p++);
- case 4:
- ret |= __get_user(data.v[4], p++);
- ret |= __get_user(data.v[5], p++);
- case 2:
- ret |= __get_user(data.v[6], p++);
- ret |= __get_user(data.v[7], p++);
- if (ret)
- return -EFAULT;
- }
- }
-
- /* If we are storing, get the data from the saved gpr or fpr */
- if (flags & ST) {
- if (flags & F) {
- if (nb == 4) {
- /* Doing stfs, have to convert to single */
- preempt_disable();
- enable_kernel_fp();
- cvt_df(¤t->thread.fpr[reg], (float *)&data.v[4], ¤t->thread);
- disable_kernel_fp();
- preempt_enable();
- }
- else
- data.dd = current->thread.fpr[reg];
- }
- else
- data.ll = regs->gpr[reg];
- }
-
- /* Swap bytes as needed */
- if (flags & SW) {
- if (nb == 2)
- SWAP(data.v[6], data.v[7]);
- else { /* nb must be 4 */
- SWAP(data.v[4], data.v[7]);
- SWAP(data.v[5], data.v[6]);
- }
- }
-
- /* Sign extend as needed */
- if (flags & SE) {
- if ( nb == 2 )
- data.ll = data.x16.low16;
- else /* nb must be 4 */
- data.ll = data.x32.low32;
- }
-
- /* If we are loading, move the data to the gpr or fpr */
- if (flags & LD) {
- if (flags & F) {
- if (nb == 4) {
- /* Doing lfs, have to convert to double */
- preempt_disable();
- enable_kernel_fp();
- cvt_fd((float *)&data.v[4], ¤t->thread.fpr[reg], ¤t->thread);
- disable_kernel_fp();
- preempt_enable();
- }
- else
- current->thread.fpr[reg] = data.dd;
- }
- else
- regs->gpr[reg] = data.ll;
- }
-
- /* If we are storing, copy the data to the user */
- if (flags & ST) {
- ret = 0;
- p = addr;
- switch (nb) {
- case 128: /* Special case - must be dcbz */
- lp = (unsigned long __user *)p;
- for (i = 0; i < L1_CACHE_BYTES / sizeof(long); ++i)
- ret |= __put_user(0, lp++);
- break;
- case 8:
- ret |= __put_user(data.v[0], p++);
- ret |= __put_user(data.v[1], p++);
- ret |= __put_user(data.v[2], p++);
- ret |= __put_user(data.v[3], p++);
- case 4:
- ret |= __put_user(data.v[4], p++);
- ret |= __put_user(data.v[5], p++);
- case 2:
- ret |= __put_user(data.v[6], p++);
- ret |= __put_user(data.v[7], p++);
- }
- if (ret)
- return -EFAULT;
- }
-
- /* Update RA as needed */
- if (flags & U) {
- regs->gpr[areg] = regs->dar;
- }
-
- return 1;
-}
-
^ permalink raw reply
* Re: [Edson.Seabra@cyclades.com: Re: BDI and 85xx]
From: Dan Malek @ 2005-11-15 0:27 UTC (permalink / raw)
To: Kumar Gala; +Cc: linux-ppc-embedded
In-Reply-To: <475D0B8F-FF5A-44DC-9D03-7156AFE2AAB0@kernel.crashing.org>
On Nov 14, 2005, at 5:50 PM, Kumar Gala wrote:
> I'm not 100% sure this is even possible on some of the book-e variants.
I suspect we could if we didn't just keep whacking
the MSR with some constant value :-) What
happens if we just leave DE set all of the time?
I know as part of ptrace, etc. it can get manipulated,
but if we are debugging through COP we shouldn't
get to these software functions.
-- Dan
^ permalink raw reply
* Re: [RFC] Attempt to clean up sigsuspend et al
From: David Woodhouse @ 2005-11-15 0:19 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
In-Reply-To: <17270.58406.370195.733887@cargo.ozlabs.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 772 bytes --]
On Sun, 2005-11-13 at 17:58 +1100, Paul Mackerras wrote:
> I'll be upset if you can shorten it by a lot - I thought I had it
> pretty tight already. :)
The patch appears to speed up a null syscall benchmark by about 3%.
With the old kernel I get an average of 5863600 cycles for 100000
getpid() calls; with the new kernel it's 5695256 cycles.
I still haven't done much testing for correctness, but it needs at least
this (d'oh)...
--- arch/powerpc/kernel/entry_64.S~ 2005-11-14 23:41:22.000000000 +0000
+++ arch/powerpc/kernel/entry_64.S 2005-11-14 23:45:35.000000000 +0000
@@ -295,7 +295,7 @@ save_user_nvgprs:
ori r10,r10,MSR_EE
mtmsrd r10,1
- ld r10,TI_SIGFRAME(r9)
+ ld r10,TI_SIGFRAME(r12)
andi. r0,r9,_TIF_32BIT
beq- save_user_nvgprs_64
--
dwmw2
[-- Attachment #2: newkernel.txt --]
[-- Type: text/plain, Size: 2040 bytes --]
Used 5687730 cycles
Used 5721828 cycles
Used 5686992 cycles
Used 5658466 cycles
Used 5630346 cycles
Used 5640494 cycles
Used 5709830 cycles
Used 5654279 cycles
Used 5659045 cycles
Used 5747328 cycles
Used 5635214 cycles
Used 5694711 cycles
Used 5646751 cycles
Used 5738407 cycles
Used 5898139 cycles
Used 5787047 cycles
Used 5670900 cycles
Used 5707616 cycles
Used 5694654 cycles
Used 5722101 cycles
Used 5666626 cycles
Used 5702401 cycles
Used 5723496 cycles
Used 5708662 cycles
Used 5675878 cycles
Used 5772019 cycles
Used 5653936 cycles
Used 5675029 cycles
Used 5657729 cycles
Used 5694485 cycles
Used 5781104 cycles
Used 5687276 cycles
Used 5668391 cycles
Used 5661477 cycles
Used 5729791 cycles
Used 5667902 cycles
Used 5669606 cycles
Used 5655594 cycles
Used 5703992 cycles
Used 5685671 cycles
Used 5659003 cycles
Used 5710373 cycles
Used 5754017 cycles
Used 5677565 cycles
Used 5699307 cycles
Used 5734777 cycles
Used 5647465 cycles
Used 5630120 cycles
Used 5688174 cycles
Used 5697787 cycles
Used 5735130 cycles
Used 5795555 cycles
Used 5657136 cycles
Used 5705851 cycles
Used 5708684 cycles
Used 5680934 cycles
Used 5666883 cycles
Used 5650389 cycles
Used 5702600 cycles
Used 5692186 cycles
Used 5667843 cycles
Used 5612066 cycles
Used 5675461 cycles
Used 5663601 cycles
Used 5667161 cycles
Used 5736776 cycles
Used 5727070 cycles
Used 5720203 cycles
Used 5824526 cycles
Used 5694799 cycles
Used 5600060 cycles
Used 5767003 cycles
Used 5691184 cycles
Used 5705613 cycles
Used 5670786 cycles
Used 5728827 cycles
Used 5685249 cycles
Used 5742188 cycles
Used 5699514 cycles
Used 5670884 cycles
Used 5758295 cycles
Used 5712180 cycles
Used 5697514 cycles
Used 5757201 cycles
Used 5694345 cycles
Used 5669453 cycles
Used 5674303 cycles
Used 5647565 cycles
Used 5663152 cycles
Used 5683005 cycles
Used 5666470 cycles
Used 5714193 cycles
Used 5689820 cycles
Used 5679402 cycles
Used 5672894 cycles
Used 5682461 cycles
Used 5701143 cycles
Used 5683074 cycles
Used 5760015 cycles
Used 5663922 cycles
Used 5677554 cycles
Used 5690482 cycles
[-- Attachment #3: oldkernel.txt --]
[-- Type: text/plain, Size: 1780 bytes --]
Used 5882164 cycles
Used 5850099 cycles
Used 5930877 cycles
Used 5841572 cycles
Used 5809251 cycles
Used 5845593 cycles
Used 5832703 cycles
Used 5819283 cycles
Used 5885083 cycles
Used 5888057 cycles
Used 5857240 cycles
Used 5838354 cycles
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Used 5826108 cycles
Used 5892050 cycles
Used 5907373 cycles
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Used 5885804 cycles
Used 5944564 cycles
Used 5837752 cycles
Used 5832153 cycles
Used 5883830 cycles
Used 5883603 cycles
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Used 5852603 cycles
Used 5826546 cycles
Used 5843635 cycles
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Used 5846276 cycles
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Used 5849252 cycles
Used 5857151 cycles
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Used 5924924 cycles
Used 5872509 cycles
Used 5805744 cycles
Used 5831126 cycles
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Used 5827185 cycles
Used 5848652 cycles
Used 5863982 cycles
Used 5873140 cycles
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Used 6000375 cycles
Used 5840141 cycles
Used 5906836 cycles
Used 5974467 cycles
Used 5811534 cycles
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Used 5850431 cycles
Used 5822444 cycles
Used 5817241 cycles
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Used 5912106 cycles
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Used 5861770 cycles
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Used 5801599 cycles
Used 5852515 cycles
Used 6151891 cycles
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Used 5878106 cycles
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Used 5905804 cycles
Used 5856291 cycles
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Used 5833760 cycles
Used 5806083 cycles
Used 5838144 cycles
Used 6102020 cycles
Used 5883813 cycles
Used 5853801 cycles
Used 5883441 cycles
Used 5827994 cycles
Used 5918981 cycles
Used 5788855 cycles
Used 5824117 cycles
Used 5890999 cycles
Used 5828463 cycles
Used 5870945 cycles
Used 5876589 cycles
Used 5789181 cycles
Used 5843746 cycles
[-- Attachment #4: syscalltest.S --]
[-- Type: text/plain, Size: 413 bytes --]
.globl main
main:
subi 1,1,12
stw 14,0(1)
stw 15,4(1)
stw 16,8(1)
li 14, 10000
mftb 15
1: li 0, 24
sc
li 0, 24
sc
li 0, 24
sc
li 0, 24
sc
li 0, 24
sc
li 0, 24
sc
li 0, 24
sc
li 0, 24
sc
li 0, 24
sc
li 0, 24
sc
addic. 14,14,-1
bne 1b
mftb 16
sub 4,16,15
lwz 14,0(1)
lwz 15,4(1)
lwz 16,8(1)
addi 1,1,12
lis 3,msg@ha
la 3,msg@l(3)
b printf
msg: .string "Used %d cycles\n"
^ permalink raw reply
* Re: asm-ppc/page.h vs asm-powerpc/page.h
From: Michael Ellerman @ 2005-11-14 23:47 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, linuxppc64
In-Reply-To: <Pine.LNX.4.44.0511141655560.8331-100000@gate.crashing.org>
[-- Attachment #1: Type: text/plain, Size: 807 bytes --]
My original patch removed it, so Paulus must have kept if for some good
reason.
asm-powerpc/page.h probably should have page_to_virt, I'm not sure why I took
it out :?
cheers
On Tue, 15 Nov 2005 10:01, Kumar Gala wrote:
> Guys, what's going on here.
>
> Why haven't we removed asm-ppc/page.h?
>
> When I build ARCH=powerpc I get asm-powerpc/page.h, which doesn't build on
> 85xx since page_to_virt is missing.
>
> Any reason we are keeping around asm-ppc/page.h and causing this
> confusion?
>
> - kumar
--
Michael Ellerman
IBM OzLabs
email: michael:ellerman.id.au
inmsg: mpe:jabber.org
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
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^ permalink raw reply
* Re: BDI2000 and Linux 2.6 kernel
From: Guillaume Autran @ 2005-11-14 23:42 UTC (permalink / raw)
To: Marcelo Tosatti; +Cc: support, linux-ppc-embedded
In-Reply-To: <20051107121101.GI15522@logos.cnet>
Hi Marcelo,
Despite your patch, I'm still having trouble getting my BDI2000 to translate
kernel virtual address to physical address on a 2.6.13 kernel.
What should I look for to make sure I set it up properly ?
Regards,
Guillaume.
Marcelo Tosatti wrote:
> Hi,
>
> Currently gdb over BDI (and I've seen other reports on this list) fails to
> translate virtual->physical addresses on PPC 8xx:
>
> *** MMU: address translation for 0xC000C66C failed
> *** MMU: address translation for 0xC000C66C failed
>
> Thats because the v2.6 kernel was changed to use physical addresses on the
> first level page.
>
> Dan informed me there might be a firmware update available to address
> this problem. Is this true?
>
> With the following the kernel stores the virtual address on the PMD
> getting the BDI "to work".
>
> A newer firmware would be much better though.
>
> --- linux-2.6.14-rc4.orig/arch/ppc/kernel/head_8xx.S 2005-10-18 16:59:34.000000000 -0500
> +++ linux-2.6.14-rc4/arch/ppc/kernel/head_8xx.S 2005-11-01 05:45:00.000000000 -0600
> @@ -320,11 +320,12 @@ InstructionTLBMiss:
> lwz r11, 0(r10) /* Get the level 1 entry */
> rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
> beq 2f /* If zero, don't try to find a pte */
> + tophys(r11,r11)
>
> /* We have a pte table, so load the MI_TWC with the attributes
> * for this "segment."
> */
> - ori r11,r11,1 /* Set valid bit */
> + /*ori r11,r11,1 Set valid bit */
> DO_8xx_CPU6(0x2b80, r3)
> mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
> DO_8xx_CPU6(0x3b80, r3)
> @@ -379,6 +380,7 @@ DataStoreTLBMiss:
> lwz r11, 0(r10) /* Get the level 1 entry */
> rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
> beq 2f /* If zero, don't try to find a pte */
> + tophys(r11,r11)
>
> /* We have a pte table, so load fetch the pte from the table.
> */
> @@ -493,6 +495,7 @@ DataTLBError:
> lwz r11, 0(r10) /* Get the level 1 entry */
> rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
> beq 2f /* If zero, bail */
> + tophys(r11,r11)
>
> /* We have a pte table, so fetch the pte from the table.
> */
> diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/include/asm-ppc/pgalloc.h linux-2.6.14-rc4/include/asm-ppc/pgalloc.h
> --- linux-2.6.14-rc4.orig/include/asm-ppc/pgalloc.h 2005-10-18 17:00:09.000000000 -0500
> +++ linux-2.6.14-rc4/include/asm-ppc/pgalloc.h 2005-11-01 08:02:08.000000000 -0600
> @@ -19,16 +19,16 @@ extern void pgd_free(pgd_t *pgd);
> #define __pmd_free_tlb(tlb,x) do { } while (0)
> #define pgd_populate(mm, pmd, pte) BUG()
>
> -#ifndef CONFIG_BOOKE
> +#if defined(CONFIG_BOOKE) || defined(CONFIG_8xx)
> #define pmd_populate_kernel(mm, pmd, pte) \
> - (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT)
> + (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT)
> #define pmd_populate(mm, pmd, pte) \
> - (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT)
> + (pmd_val(*(pmd)) = (unsigned long)page_to_virt(pte) | _PMD_PRESENT)
> #else
> #define pmd_populate_kernel(mm, pmd, pte) \
> - (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT)
> + (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT)
> #define pmd_populate(mm, pmd, pte) \
> - (pmd_val(*(pmd)) = (unsigned long)page_to_virt(pte) | _PMD_PRESENT)
> + (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT)
> #endif
>
> extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
> diff -Nur -p --exclude-from=linux-2.6.14-rc4/Documentation/dontdiff linux-2.6.14-rc4.orig/include/asm-ppc/pgtable.h linux-2.6.14-rc4/include/asm-ppc/pgtable.h
> --- linux-2.6.14-rc4.orig/include/asm-ppc/pgtable.h 2005-10-18 17:00:09.000000000 -0500
> +++ linux-2.6.14-rc4/include/asm-ppc/pgtable.h 2005-11-01 08:01:34.000000000 -0600
> @@ -719,16 +719,16 @@ extern pgprot_t phys_mem_access_prot(str
> * handler). On everything else the pmd contains the physical address
> * of the pte page. -- paulus
> */
> -#ifndef CONFIG_BOOKE
> +#if defined (CONFIG_BOOKE) || defined CONFIG_8xx
> #define pmd_page_kernel(pmd) \
> - ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
> + ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
> #define pmd_page(pmd) \
> - (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
> + (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
> #else
> #define pmd_page_kernel(pmd) \
> - ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
> + ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
> #define pmd_page(pmd) \
> - (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
> + (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
> #endif
>
> /* to find an entry in a kernel page-table-directory */
>
>
>
>
>
>
>
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
--
=======================================
Guillaume Autran
Senior Software Engineer
MRV Communications, Inc.
Tel: (978) 952-4932 office
=======================================
^ permalink raw reply
* [PATCH] powerpc: put page page_to_virt for Book-e processors
From: Kumar Gala @ 2005-11-14 23:21 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, linuxppc64-dev
Book-E processors use page_to_virt since we have to always translate.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
commit 62ac3a10f41d7d300cf82846348f65eab0dbfd40
tree 039f1c393bd77fb8c6daf1c8ebd883c9a72be6e2
parent ed24c128ba54329d142c4d4c7c5e05cec6065b08
author Kumar Gala <galak@kernel.crashing.org> Mon, 14 Nov 2005 17:22:35 -0600
committer Kumar Gala <galak@kernel.crashing.org> Mon, 14 Nov 2005 17:22:35 -0600
include/asm-powerpc/page.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/asm-powerpc/page.h b/include/asm-powerpc/page.h
index 18c1e5e..e34a2ba 100644
--- a/include/asm-powerpc/page.h
+++ b/include/asm-powerpc/page.h
@@ -53,6 +53,7 @@
#endif
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT)
#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
^ permalink raw reply related
* asm-ppc/page.h vs asm-powerpc/page.h
From: Kumar Gala @ 2005-11-14 23:01 UTC (permalink / raw)
To: Paul Mackerras; +Cc: michael, linuxppc-dev, linuxppc64
Guys, what's going on here.
Why haven't we removed asm-ppc/page.h?
When I build ARCH=powerpc I get asm-powerpc/page.h, which doesn't build on
85xx since page_to_virt is missing.
Any reason we are keeping around asm-ppc/page.h and causing this
confusion?
- kumar
^ permalink raw reply
* Re: [Edson.Seabra@cyclades.com: Re: BDI and 85xx]
From: Kumar Gala @ 2005-11-14 22:50 UTC (permalink / raw)
To: Dan Malek; +Cc: linux-ppc-embedded
In-Reply-To: <608ff4f57a546901e9193ebbbe368053@embeddededge.com>
On Nov 14, 2005, at 4:43 PM, Dan Malek wrote:
>
> On Nov 14, 2005, at 10:53 AM, Marcelo Tosatti wrote:
>
>> Doh my bad. Attached it is.
>>
>>
>> <8xx_gdb.diff>
>
> Well, this probably works for you but have you
> considered how it affects others?
>
> I'm not going to get into the -ggdb flags discussion,
> since I know we've had that in the past. Why is
> this needed and should it be done for everyone?
>
> Your update of MSR_KERNEL will work for you,
> but won't work on anything that isn't a Book E processor.
> You can't make this a generic update to all processors.
> It will fail on everything that really wants to use the
> BDI_SWITCH configuration option as it was intended.
> The DE in Book E conflicts with BE in traditional PPC.
We should but this in asm-ppc/reg_booke.h since book-e has its own
MSR_* defines.
> This also doesn't do anything to address my real concern,
> we shouldn't have to create a special kernel configuration
> just to attach a debugger .........
I'm not 100% sure this is even possible on some of the book-e variants.
- kumar
^ permalink raw reply
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