* [PATCH] powerpc: Fix compile problem in pci.c for ppc32
From: Kumar Gala @ 2005-12-19 21:49 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev
pci_address_to_pio is missing a closing curly brace
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
commit a86f866f7b31e01c729ee7498228c547a51d8514
tree 7cc7df7f28735a34618d450cc46bfd3c86d8725b
parent c211d7347a735eb5d5996433f3eef7159c3fe41a
author Kumar Gala <galak@kernel.crashing.org> Mon, 19 Dec 2005 15:52:42 -0600
committer Kumar Gala <galak@kernel.crashing.org> Mon, 19 Dec 2005 15:52:42 -0600
arch/ppc/kernel/pci.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/kernel/pci.c b/arch/ppc/kernel/pci.c
index 664af8b..7d4c0e3 100644
--- a/arch/ppc/kernel/pci.c
+++ b/arch/ppc/kernel/pci.c
@@ -1823,7 +1823,7 @@ unsigned long pci_address_to_pio(phys_ad
unsigned long base =
(unsigned long)hose->io_base_virt - _IO_BASE;
return base + (address - hose->io_base_phys);
-
+ }
}
return (unsigned int)-1;
}
^ permalink raw reply related
* Re: RFC: Rev 0.5 Booting the Linux/ppc kernel without Open Firmware
From: Kumar Gala @ 2005-12-19 20:49 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Arnd Bergmann, linuxppc64-dev
In-Reply-To: <1134856762.6102.54.camel@gaston>
On Sun, 18 Dec 2005, Benjamin Herrenschmidt wrote:
>
> > - Do we need a way to identify the type of soc bus? There are different
> > standards for this, e.g. PLB4 on PPC440 or the EIB on the Cell BE.
> > My initial idea was to have different device-type properties for these,
> > but I now think that device_type = "soc" makes sense for all of them.
> > Maybe we could add a model or compatible property for them.
>
> That would be a good idea.
>
> Also, it might be useful to ass a "clock-frequency" to it for processors
> where it makes sense. One of the things we are passing from uboot
> currently is the list of clock frequencies for PLB/OPB/PCI/... we need
> to replace this with appropriate nodes and their respective
> "clock-frequency" properties
>
> > - It does not really belong into this document, but is related anyway:
> > how do you want to represent this in Linux? Currently, most of these
> > would be of_platform_device, but I think it would be good to have
> > a new bus_type for it. The advantage would be that you can see the
> > devices in /sys/devices/soc@xxx/ even if the driver is not loaded
> > and the driver can even be autoloaded by udev.
> > Also, which properties should show up in sysfs? All of them or just
> > those specified in this document or a subset of them?
I'm still in favor of just leaving these devices as straight platform
devices. Unless there is something that is bus specific that each device
on the bus conforms to I dont see any reason to create a new bus type.
> If we go that way, we also need to have the SOC type take optionally
> part in the matching. That is, the driver matching infos should be based
> on model & compatible like OF does, thus we could recommend something
> like:
>
> - Define a unique SOC name per SOC bus type/family, for example,
> ppc4xxPLB, etc... This goes into /soc/model.
>
> - Optionally, use compatible for similar busses. For example, if you
> have a new rev of that PLB that is similar but has extensions called
> PLB2, you can have model be ppc4xxPLB2 and compatible containing
> ppc4xxPLB.
>
> - Define that the "model" property of a device under /soc is of the
> form "socname,devicename"... For example, EMAC would be ppc4xxPLB,emac",
> Same rule applies with compatible (this one could be compatible, among
> others, with "ppc4xxPLB,emac" and model "ppc4xxPLB2,emac".
>
> > - What do we do with pci root devices? They are often physically connected
> > to the internal CPU bus, so it would make sense to represent them
> > this way in the device tree. Should we add them to the specification
> > here? Would it even work the expected way in Linux?
- kumar
^ permalink raw reply
* Re: kernel 2.6.15-rc5-latest doesn't work anymore on mpc8540ads
From: Kumar Gala @ 2005-12-19 20:38 UTC (permalink / raw)
To: Clemens Koller; +Cc: linuxppc-embedded
In-Reply-To: <43A6ED1E.20506@anagramm.de>
On Mon, 19 Dec 2005, Clemens Koller wrote:
> Hello!
>
> Here is a little update:
>
> > I am just about to update my kernel from 2.6.13-rc7 which is working
> > fine to linus' 2.6.15-rc5-latest git on my mpc8540ads flavored board.
> > However, the kernel hangs pretty early after
> >
> > openpic: exit
>
> openpic_init() is called by mpc85xx_ads_init_IRQ in ppc/platforms/85xx
>
> ppc_md.init_IRQ=mpc85xx_ads_init_IRQ in ppc/platforms/85xx
>
> ppc_md.init_IRQ() is called from powerpc/kernel/irq.c
>
> init_IRQ() is called from init/main.c:start_kernel()
>
> and that seems to work fine. So, it crashes silently somewhere
> after that point. I try to build 2.6.15-rc6-latest with kgbd support,
> not knowing if it's supposed to work on this platform.
It was a guess :)
> Are there some open issues from the ppc->powerpc migration?
possible, can you use git bisect to find what commit may have caused the
issue?
- kumar
^ permalink raw reply
* Re: kernel 2.6.15-rc5-latest doesn't work anymore on mpc8540ads
From: Clemens Koller @ 2005-12-19 17:25 UTC (permalink / raw)
To: Clemens Koller; +Cc: linuxppc-embedded
In-Reply-To: <43A2E175.9050004@anagramm.de>
Hello!
Here is a little update:
> I am just about to update my kernel from 2.6.13-rc7 which is working
> fine to linus' 2.6.15-rc5-latest git on my mpc8540ads flavored board.
> However, the kernel hangs pretty early after
>
> openpic: exit
openpic_init() is called by mpc85xx_ads_init_IRQ in ppc/platforms/85xx
ppc_md.init_IRQ=mpc85xx_ads_init_IRQ in ppc/platforms/85xx
ppc_md.init_IRQ() is called from powerpc/kernel/irq.c
init_IRQ() is called from init/main.c:start_kernel()
and that seems to work fine. So, it crashes silently somewhere
after that point. I try to build 2.6.15-rc6-latest with kgbd support,
not knowing if it's supposed to work on this platform.
Are there some open issues from the ppc->powerpc migration?
Thanks,
--
Clemens Koller
_______________________________
R&D Imaging Devices
Anagramm GmbH
Rupert-Mayer-Str. 45/1
81379 Muenchen
Germany
http://www.anagramm.de
Phone: +49-89-741518-50
Fax: +49-89-741518-19
^ permalink raw reply
* Re: POSIX High Resolution Timers in LinuxPPC 2.4
From: Egan @ 2005-12-19 15:57 UTC (permalink / raw)
To: linuxppc-embedded, linuxppc-embedded
In-Reply-To: <200512191039.58149.david.jander@protonic.nl>
> Hi Tim,
>
> On Friday 16 December 2005 23:34, Martin, Tim wrote:
> > Could someone give me a brief history lesson on POSIX high resolution
> > timers (e.g. timer_create() function) implemented in the Linux kernel on
> > the PowerPC 405 architecture? Specifically:
> >
> > Confirm they are in the mainline 2.6 kernel now (e.g. kernel.org)?
> >
> > Were they ever a part of the "mainline" 2.4 linuxppc kernel (e.g
> > ppc.bkbits.net)?
> >
> > If no, were they ever available as a patch? The stuff at
> > sourceforge.net/projects/high-res-timers stops at 2.4.20 and looks like it
> > was only ever working for i386, not ppc.
>
> I asked a related question a while back, and got no answer (yet).
> I did find this though, which you might have overlooked:
> http://prdownloads.sourceforge.net/high-res-timers/ppc-hrt-2.6.10.patch?download
>
> I am equally puzzled about whether this has made it into mainstream, is about
> to, or never will. I don't even know if it actually works.
>
> Greetings,
>
> --
>
> David Jander
> Protonic Holland.
>
High resolution timer support has been rewritten for 2.6 by Thomas Gleixner
with help from Ingo Molnar and others and is available at:
http://tglx.de/hrtimers.html. It is also integrated into Ingo's
realtime-preempt patch at: http://people.redhat.com/mingo/realtime-preempt/.
It is not available in the mainline kernel yet. Currently only X86 is
supported, PPC and other architectures are reported to be in progress. If you
monitor the LKML you will see a lot of discussion/development in this area
right now.
Regards,
Tony
^ permalink raw reply
* WG: Problem loading modules
From: Achim Machura @ 2005-12-19 16:41 UTC (permalink / raw)
To: Linuxppc-Embedded (E-Mail)
-----Ursprüngliche Nachricht-----
Von: Achim Machura [mailto:achim.machura@berghof.com]
Gesendet: Montag, 19. Dezember 2005 17:41
An: 'Paula Saameño'
Betreff: AW: Problem loading modules
Hello,
> Yes, I tried with insmod and the error then was: "couldn't find the kernel
version the module was
make sure that the kernel was compiled with the same header as your
kernelmoduls.
best regards
achim
^ permalink raw reply
* Re: Problem loading modules
From: Paula Saameño @ 2005-12-19 16:22 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 624 bytes --]
>>Hi!
>>I'm working with a ml403 board, porting Linux 2.4.devel on it. I got the
OS
>>running, but I cannot load modules.
>>When I try "modprobe /lib/modules/<version>/kernel/net/<module.o>, I
obtain
>>the error messages:
>>Note: /etc/modules.conf is more recent than
>>/lib/modules/<version>/modules.dep
>>modprobe: Can't locate module lib/modules/<version>/kernel/net/<module.o>
>did you try with insmod ?
>then try running depmod.
Yes, I tried with insmod and the error then was: "couldn't find the kernel
version the module was compiled for"
In modules.dep, the references are ok.
Greetings!
[-- Attachment #2: Type: text/html, Size: 788 bytes --]
^ permalink raw reply
* [PATCH][UPDATE] powerpc: CPM2 interrupt handler failure after 100, 000 interrupts
From: Kumar Gala @ 2005-12-19 15:16 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-embedded
From: Edson Seabra <Edson.Seabra@cyclades.com>
The CPM2 interrupt handler does not return success to the IRQ subsystem, which
causes it to kill the IRQ line after 100,000 interrupts.
Signed-off-by: Edson Seabra <Edson.Seabra@cyclades.com>
Signed-off-by: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
Paul: We should put this in the merge tree for linus to pick up for
2.6.15. Fixed up return type to be irqreturn_t
commit c211d7347a735eb5d5996433f3eef7159c3fe41a
tree 1c14ca8d89ae7b7d989dac917f8bf87dba40b6c7
parent 1abf7e247b676a84fbfcd47442dc44788526f2f6
author Kumar Gala <galak@kernel.crashing.org> Mon, 19 Dec 2005 09:17:05 -0600
committer Kumar Gala <galak@kernel.crashing.org> Mon, 19 Dec 2005 09:17:05 -0600
arch/ppc/platforms/85xx/mpc85xx_cds_common.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
index d8991b8..5e8cc5e 100644
--- a/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
+++ b/arch/ppc/platforms/85xx/mpc85xx_cds_common.c
@@ -130,10 +130,11 @@ mpc85xx_cds_show_cpuinfo(struct seq_file
}
#ifdef CONFIG_CPM2
-static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
{
while((irq = cpm2_get_irq(regs)) >= 0)
__do_IRQ(irq, regs);
+ return IRQ_HANDLED;
}
static struct irqaction cpm2_irqaction = {
^ permalink raw reply related
* Re: [PATCH] powerpc: CPM2 interrupt handler failure after 100,000
From: Kumar Gala @ 2005-12-19 15:18 UTC (permalink / raw)
To: Nathael Pajani; +Cc: linuxppc-embedded
In-Reply-To: <20051219085747.5D79425C7AA@smtp-out.completel.net>
On Dec 19, 2005, at 3:00 AM, Nathael Pajani wrote:
> interrupts
> Message-Id: <20051219100059.5a95533f.nathael.pajani@cpe.fr>
> X-Mailer: Sylpheed version 2.0.4 (GTK+ 2.8.9; i486-pc-linux-gnu)
> Mime-Version: 1.0
> Content-Type: text/plain; charset=ISO-8859-1
> Content-Transfer-Encoding: quoted-printable
>
> Hi!
>
> Hum.. in the patch you moved from "void" to "int":
>> -static void cpm2_cascade(int irq, void *dev_id, struct pt_regs
>> *regs)
>> +static int cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
>
> But should'nt it be "irqreturn_t" ?
> static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct
> pt_regs *regs)
Yep, should be. I'll fixup the patch and resend.
- kumar
^ permalink raw reply
* mv643xx_eth, sleeping function called from invalid context at mm/slab.c:2472
From: Olaf Hering @ 2005-12-19 13:39 UTC (permalink / raw)
To: Manish_Lachwani, netdev; +Cc: linuxppc-dev
I get this with 2.6.15-rc6 on a pegasos2 board:
MV-643xx 10/100/1000 Ethernet Driver
eth1: port 1 with MAC address 00:2b:2f:de:ad:01
eth1: Scatter Gather Enabled
eth1: TX TCP/IP Checksumming Supported
eth1: RX TCP/UDP Checksum Offload ON
eth1: RX NAPI Enabled
eth1: Using SRAM
Debug: sleeping function called from invalid context at mm/slab.c:2472
in_atomic():0, irqs_disabled():1
Call Trace:
[CB32DCF0] [C000AFCC] show_stack+0x54/0x180 (unreliable)
[CB32DD10] [C0027CD4] __might_sleep+0xbc/0xd0
[CB32DD20] [C005E50C] kmem_cache_alloc+0x34/0x108
[CB32DD40] [C01C5F40] rand_initialize_irq+0x40/0x6c
[CB32DD60] [C0054104] setup_irq+0x5c/0x154
[CB32DD90] [C0054284] request_irq+0x88/0xb8
[CB32DDC0] [D22820A0] mv643xx_eth_open+0x44/0xb4 [mv643xx_eth]
[CB32DDE0] [C0257394] dev_open+0x70/0xd8
[CB32DE00] [C02554F0] dev_change_flags+0x6c/0x13c
[CB32DE20] [C02A2818] devinet_ioctl+0x280/0x708
[CB32DE80] [C02A319C] inet_ioctl+0xb4/0x100
[CB32DE90] [C02C0078] packet_ioctl+0x15c/0x188
[CB32DEB0] [C024B998] sock_ioctl+0x30c/0x334
[CB32DED0] [C00922F4] do_ioctl+0x3c/0x88
[CB32DEE0] [C0092728] vfs_ioctl+0x3e8/0x424
[CB32DF10] [C00927CC] sys_ioctl+0x68/0x98
[CB32DF40] [C000FAEC] ret_from_syscall+0x0/0x4c
--- Exception: c01 at 0x7f6be80
LR = 0x7fec9d0
eth1: no IPv6 routers present
00:00.0 Host bridge: Marvell Technology Group Ltd. MV64360/64361/64362 System Controller (rev 03)
00:01.0 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller (rev 46)
00:0c.0 ISA bridge: VIA Technologies, Inc. VT8231 [PCI-to-ISA Bridge] (rev 10)
00:0c.1 IDE interface: VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE (rev 06)
00:0c.2 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 1e)
00:0c.3 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 1e)
00:0c.4 Bridge: VIA Technologies, Inc. VT8235 ACPI (rev 10)
00:0c.5 Multimedia audio controller: VIA Technologies, Inc. VT82C686 AC97 Audio Controller (rev 40)
00:0c.6 Communication controller: VIA Technologies, Inc. AC'97 Modem Controller (rev 20)
00:0d.0 Ethernet controller: VIA Technologies, Inc. VT6102 [Rhine-II] (rev 51)
0001:01:00.0 Host bridge: Marvell Technology Group Ltd. MV64360/64361/64362 System Controller (rev 03)
0001:01:08.0 VGA compatible controller: ATI Technologies Inc RV280 [Radeon 9200 SE] (rev 01)
0001:01:08.1 Display controller: ATI Technologies Inc RV280 [Radeon 9200 SE] (Secondary) (rev 01)
--
short story of a lazy sysadmin:
alias appserv=wotan
^ permalink raw reply
* [PATCH 3/3] ppc32: Adds MPC885ADS, MPC866ADS and MPC8272ADS-specific platform stuff for fs_enet
From: Vitaly Bordug @ 2005-12-19 13:21 UTC (permalink / raw)
To: Kumar Gala, Marcelo Tosatti, Pantelis Antoniou,
linuxppc-embedded list
Added proper ppc_sys identification and fs_platform_info's for MPC 885ADS,
866ADS and 8272ADS, utilizing function assignment to remove/do not use
platform devices which conflict with PD-incompatible drivers.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
---
arch/ppc/Kconfig | 47 ++++
arch/ppc/platforms/Makefile | 4
arch/ppc/platforms/fads.h | 2
arch/ppc/platforms/mpc8272ads_setup.c | 235 ++++++++++++++++++++
arch/ppc/platforms/mpc866ads_setup.c | 269 +++++++++++++++++++++++
arch/ppc/platforms/mpc885ads_setup.c | 387 +++++++++++++++++++++++++++++++++
arch/ppc/platforms/pq2ads.h | 4
arch/ppc/platforms/pq2ads_pd.h | 114 ++++++++++
8 files changed, 1061 insertions(+), 1 deletions(-)
create mode 100644 arch/ppc/platforms/mpc8272ads_setup.c
create mode 100644 arch/ppc/platforms/mpc866ads_setup.c
create mode 100644 arch/ppc/platforms/mpc885ads_setup.c
create mode 100644 arch/ppc/platforms/pq2ads_pd.h
applies-to: f51b03be0daf16352ec61e3499f61c95adf115e7
5406392976524c1e504f2a612f49eac2b41dc16c
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig
index cc3f64c..ac32793 100644
--- a/arch/ppc/Kconfig
+++ b/arch/ppc/Kconfig
@@ -506,6 +506,53 @@ config WINCEPT
endchoice
+menu "Freescale Ethernet driver platform-specific options"
+ depends on FS_ENET
+
+ config MPC8xx_SECOND_ETH
+ bool "Second Ethernet channel"
+ depends on (MPC885ADS || MPC86XADS)
+ default y
+ help
+ This enables support for second Ethernet on MPC885ADS and MPC86xADS boards.
+ The latter will use SCC1, for 885ADS you can select it below.
+
+ choice
+ prompt "Second Ethernet channel"
+ depends on MPC8xx_SECOND_ETH
+ default MPC8xx_SECOND_ETH_FEC2
+
+ config MPC8xx_SECOND_ETH_FEC2
+ bool "FEC2"
+ depends on MPC885ADS
+ help
+ Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
+ (often 2-nd UART) will not work if this is enabled.
+
+ config MPC8xx_SECOND_ETH_SCC1
+ bool "SCC1"
+ depends on MPC86XADS
+ select MPC8xx_SCC_ENET_FIXED
+ help
+ Enable SCC1 to serve as 2-nd Ethernet channel. Note that SMC1
+ (often 1-nd UART) will not work if this is enabled.
+
+ config MPC8xx_SECOND_ETH_SCC3
+ bool "SCC3"
+ depends on MPC885ADS
+ help
+ Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
+ (often 1-nd UART) will not work if this is enabled.
+
+ endchoice
+
+ config MPC8xx_SCC_ENET_FIXED
+ depends on MPC8xx_SECOND_ETH_SCC
+ default n
+ bool "Use fixed MII-less mode for SCC Ethernet"
+
+endmenu
+
choice
prompt "Machine Type"
depends on 6xx || POWER3 || POWER4
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
index 7c5cdab..ee50b0d 100644
--- a/arch/ppc/platforms/Makefile
+++ b/arch/ppc/platforms/Makefile
@@ -22,6 +22,8 @@ ifeq ($(CONFIG_PPC_PMAC),y)
obj-$(CONFIG_NVRAM) += pmac_nvram.o
obj-$(CONFIG_CPU_FREQ_PMAC) += pmac_cpufreq.o
endif
+
+obj-$(CONFIG_ADS8272) += mpc8272ads_setup.o
obj-$(CONFIG_PMAC_BACKLIGHT) += pmac_backlight.o
obj-$(CONFIG_PREP_RESIDUAL) += residual.o
obj-$(CONFIG_PQ2ADS) += pq2ads.o
@@ -45,6 +47,8 @@ obj-$(CONFIG_SBC82xx) += sbc82xx.o
obj-$(CONFIG_SPRUCE) += spruce.o
obj-$(CONFIG_LITE5200) += lite5200.o
obj-$(CONFIG_EV64360) += ev64360.o
+obj-$(CONFIG_MPC86XADS) += mpc866ads_setup.o
+obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o
ifeq ($(CONFIG_SMP),y)
obj-$(CONFIG_PPC_PMAC) += pmac_smp.o
diff --git a/arch/ppc/platforms/fads.h b/arch/ppc/platforms/fads.h
index a48fb8d..e1c0b1b 100644
--- a/arch/ppc/platforms/fads.h
+++ b/arch/ppc/platforms/fads.h
@@ -112,7 +112,7 @@
/* CPM Ethernet through SCC1 or SCC2 */
-#ifdef CONFIG_SCC1_ENET /* Probably 860 variant */
+#if defined(CONFIG_SCC1_ENET) || defined(CONFIG_MPC8xx_SECOND_ETH_SCC1) /* Probably 860 variant */
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC1 use.
* TCLK - CLK1, RCLK - CLK2.
diff --git a/arch/ppc/platforms/mpc8272ads_setup.c b/arch/ppc/platforms/mpc8272ads_setup.c
new file mode 100644
index 0000000..0f228ad
--- /dev/null
+++ b/arch/ppc/platforms/mpc8272ads_setup.c
@@ -0,0 +1,235 @@
+/*
+ * arch/ppc/platforms/82xx/pq2ads_pd.c
+ *
+ * MPC82xx Board-specific PlatformDevice descriptions
+ *
+ * 2005 (c) MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/ioport.h>
+#include <linux/fs_enet_pd.h>
+
+#include <asm/io.h>
+#include <asm/mpc8260.h>
+#include <asm/cpm2.h>
+#include <asm/immap_cpm2.h>
+#include <asm/irq.h>
+#include <asm/ppc_sys.h>
+#include <asm/ppcboot.h>
+
+#include "pq2ads_pd.h"
+
+static void init_fcc1_ioports(void);
+static void init_fcc2_ioports(void);
+
+static struct fs_mii_bus_info mii_bus_info = {
+ .method = fsmii_bitbang,
+ .id = 0,
+ .i.bitbang = {
+ .mdio_port = fsiop_portc,
+ .mdio_bit = 18,
+ .mdc_port = fsiop_portc,
+ .mdc_bit = 19,
+ .delay = 1,
+ },
+};
+
+static struct fs_platform_info mpc82xx_fcc1_pdata = {
+ .fs_no = fsid_fcc1,
+ .cp_page = CPM_CR_FCC1_PAGE,
+ .cp_block = CPM_CR_FCC1_SBLOCK,
+ .clk_trx = (PC_F1RXCLK | PC_F1TXCLK),
+ .clk_route = CMX1_CLK_ROUTE,
+ .clk_mask = CMX1_CLK_MASK,
+ .init_ioports = init_fcc1_ioports,
+
+ .phy_addr = 0,
+#ifdef PHY_INTERRUPT
+ .phy_irq = PHY_INTERRUPT,
+#else
+ .phy_irq = -1;
+#endif
+ .mem_offset = FCC1_MEM_OFFSET,
+ .bus_info = &mii_bus_info,
+ .rx_ring = 32,
+ .tx_ring = 32,
+ .rx_copybreak = 240,
+ .use_napi = 0,
+ .napi_weight = 17,
+};
+
+static struct fs_platform_info mpc82xx_fcc2_pdata = {
+ .fs_no = fsid_fcc2,
+ .cp_page = CPM_CR_FCC2_PAGE,
+ .cp_block = CPM_CR_FCC2_SBLOCK,
+ .clk_trx = (PC_F2RXCLK | PC_F2TXCLK),
+ .clk_route = CMX2_CLK_ROUTE,
+ .clk_mask = CMX2_CLK_MASK,
+ .init_ioports = init_fcc2_ioports,
+
+ .phy_addr = 3,
+#ifdef PHY_INTERRUPT
+ .phy_irq = PHY_INTERRUPT,
+#else
+ .phy_irq = -1;
+#endif
+ .mem_offset = FCC2_MEM_OFFSET,
+ .bus_info = &mii_bus_info,
+ .rx_ring = 32,
+ .tx_ring = 32,
+ .rx_copybreak = 240,
+ .use_napi = 0,
+ .napi_weight = 17,
+};
+
+static void init_fcc1_ioports(void)
+{
+ struct io_port *io;
+ u32 tempval;
+ cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
+ u32 *bcsr = ioremap(BCSR_ADDR+4, sizeof(u32));
+
+ io = &immap->im_ioport;
+
+ /* Enable the PHY */
+ clrbits32(bcsr, BCSR1_FETHIEN);
+ setbits32(bcsr, BCSR1_FETH_RST);
+
+ /* FCC1 pins are on port A/C. */
+ /* Configure port A and C pins for FCC1 Ethernet. */
+
+ tempval = in_be32(&io->iop_pdira);
+ tempval &= ~PA1_DIRA0;
+ tempval |= PA1_DIRA1;
+ out_be32(&io->iop_pdira, tempval);
+
+ tempval = in_be32(&io->iop_psora);
+ tempval &= ~PA1_PSORA0;
+ tempval |= PA1_PSORA1;
+ out_be32(&io->iop_psora, tempval);
+
+ setbits32(&io->iop_ppara,PA1_DIRA0 | PA1_DIRA1);
+
+ /* Alter clocks */
+ tempval = PC_F1TXCLK|PC_F1RXCLK;
+
+ clrbits32(&io->iop_psorc, tempval);
+ clrbits32(&io->iop_pdirc, tempval);
+ setbits32(&io->iop_pparc, tempval);
+
+ clrbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_MASK);
+ setbits32(&immap->im_cpmux.cmx_fcr, CMX1_CLK_ROUTE);
+ iounmap(bcsr);
+ iounmap(immap);
+}
+
+static void init_fcc2_ioports(void)
+{
+ cpm2_map_t* immap = ioremap(CPM_MAP_ADDR, sizeof(cpm2_map_t));
+ u32 *bcsr = ioremap(BCSR_ADDR+12, sizeof(u32));
+
+ struct io_port *io;
+ u32 tempval;
+
+ immap = cpm2_immr;
+
+ io = &immap->im_ioport;
+
+ /* Enable the PHY */
+ clrbits32(bcsr, BCSR3_FETHIEN2);
+ setbits32(bcsr, BCSR3_FETH2_RST);
+
+ /* FCC2 are port B/C. */
+ /* Configure port A and C pins for FCC2 Ethernet. */
+
+ tempval = in_be32(&io->iop_pdirb);
+ tempval &= ~PB2_DIRB0;
+ tempval |= PB2_DIRB1;
+ out_be32(&io->iop_pdirb, tempval);
+
+ tempval = in_be32(&io->iop_psorb);
+ tempval &= ~PB2_PSORB0;
+ tempval |= PB2_PSORB1;
+ out_be32(&io->iop_psorb, tempval);
+
+ setbits32(&io->iop_pparb,PB2_DIRB0 | PB2_DIRB1);
+
+ tempval = PC_F2RXCLK|PC_F2TXCLK;
+
+ /* Alter clocks */
+ clrbits32(&io->iop_psorc,tempval);
+ clrbits32(&io->iop_pdirc,tempval);
+ setbits32(&io->iop_pparc,tempval);
+
+ clrbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_MASK);
+ setbits32(&immap->im_cpmux.cmx_fcr, CMX2_CLK_ROUTE);
+
+ iounmap(bcsr);
+ iounmap(immap);
+}
+
+
+static void __init mpc8272ads_fixup_enet_pdata(struct platform_device *pdev,
+ int idx)
+{
+ bd_t* bi = (void*)__res;
+ int fs_no = fsid_fcc1+pdev->id-1;
+
+ mpc82xx_fcc1_pdata.dpram_offset = mpc82xx_fcc2_pdata.dpram_offset = (u32)cpm2_immr->im_dprambase;
+ mpc82xx_fcc1_pdata.fcc_regs_c = mpc82xx_fcc2_pdata.fcc_regs_c = (u32)cpm2_immr->im_fcc_c;
+
+ switch(fs_no) {
+ case fsid_fcc1:
+ memcpy(&mpc82xx_fcc1_pdata.macaddr,bi->bi_enetaddr,6);
+ pdev->dev.platform_data = &mpc82xx_fcc1_pdata;
+ break;
+ case fsid_fcc2:
+ memcpy(&mpc82xx_fcc2_pdata.macaddr,bi->bi_enetaddr,6);
+ mpc82xx_fcc2_pdata.macaddr[5] ^= 1;
+ pdev->dev.platform_data = &mpc82xx_fcc2_pdata;
+ break;
+ }
+ printk("all\n");
+}
+
+static int mpc8272ads_platform_notify(struct device *dev)
+{
+ static const struct platform_notify_dev_map dev_map[] = {
+ {
+ .bus_id = "fsl-cpm-fcc",
+ .rtn = mpc8272ads_fixup_enet_pdata
+ },
+ {
+ .bus_id = NULL
+ }
+ };
+ platform_notify_map(dev_map,dev);
+
+ return 0;
+
+}
+
+int __init mpc8272ads_init(void)
+{
+ printk(KERN_NOTICE "mpc8272ads: Init\n");
+
+ platform_notify = mpc8272ads_platform_notify;
+
+ ppc_sys_device_initfunc();
+ ppc_sys_device_set_func_all(FUNC_DISABLED);
+ ppc_sys_device_setfunc(MPC82xx_CPM_FCC1, FUNC_ENABLED);
+ ppc_sys_device_setfunc(MPC82xx_CPM_FCC2, FUNC_ENABLED);
+
+ return 0;
+}
+
+arch_initcall(mpc8272ads_init);
diff --git a/arch/ppc/platforms/mpc866ads_setup.c b/arch/ppc/platforms/mpc866ads_setup.c
new file mode 100644
index 0000000..ed1b050
--- /dev/null
+++ b/arch/ppc/platforms/mpc866ads_setup.c
@@ -0,0 +1,269 @@
+/*arch/ppc/platforms/mpc885ads-setup.c
+ *
+ * Platform setup for the Freescale mpc885ads board
+ *
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * Copyright 2005 MontaVista Software Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+
+#include <linux/fs_enet_pd.h>
+#include <linux/mii.h>
+
+#include <asm/delay.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/ppcboot.h>
+#include <asm/8xx_immap.h>
+#include <asm/commproc.h>
+#include <asm/ppc_sys.h>
+#include <asm/mpc8xx.h>
+
+extern unsigned char __res[];
+
+static struct fs_mii_bus_info fec_mii_bus_info = {
+ .method = fsmii_fec,
+ .id = 0,
+};
+
+static struct fs_mii_bus_info scc_mii_bus_info = {
+ .method = fsmii_fixed,
+ .id = 0,
+ .i.fixed.speed = 10,
+ .i.fixed.duplex = 0,
+};
+
+static struct fs_platform_info mpc8xx_fec_pdata[] = {
+ {
+ .rx_ring = 128,
+ .tx_ring = 16,
+ .rx_copybreak = 240,
+
+ .use_napi = 1,
+ .napi_weight = 17,
+
+ .phy_addr = 15,
+ .phy_irq = -1,
+
+ .use_rmii = 0,
+
+ .bus_info = &fec_mii_bus_info,
+ }
+};
+
+static struct fs_platform_info mpc8xx_scc_pdata = {
+ .rx_ring = 64,
+ .tx_ring = 8,
+ .rx_copybreak = 240,
+
+ .use_napi = 1,
+ .napi_weight = 17,
+
+ .phy_addr = -1,
+ .phy_irq = -1,
+
+ .bus_info = &scc_mii_bus_info,
+};
+
+void __init board_init(void)
+{
+ volatile cpm8xx_t *cp = cpmp;
+ unsigned *bcsr_io;
+
+ bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
+
+ if (bcsr_io == NULL) {
+ printk(KERN_CRIT "Could not remap BCSR1\n");
+ return;
+ }
+#ifdef CONFIG_SERIAL_CPM_SMC1
+ cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */
+ clrbits32(bcsr_io,(0x80000000 >> 7));
+#else
+ setbits32(bcsr_io,(0x80000000 >> 7));
+
+ cp->cp_pbpar &= ~(0x000000c0);
+ cp->cp_pbdir |= 0x000000c0;
+ cp->cp_smc[0].smc_smcmr = 0;
+ cp->cp_smc[0].smc_smce = 0;
+#endif
+
+#ifdef CONFIG_SERIAL_CPM_SMC2
+ cp->cp_simode &= ~(0xe0000000 >> 1);
+ cp->cp_simode |= (0x20000000 >> 1); /* brg2 */
+ clrbits32(bcsr_io,(0x80000000 >> 13));
+#else
+ clrbits32(bcsr_io,(0x80000000 >> 13));
+ cp->cp_pbpar &= ~(0x00000c00);
+ cp->cp_pbdir |= 0x00000c00;
+ cp->cp_smc[1].smc_smcmr = 0;
+ cp->cp_smc[1].smc_smce = 0;
+#endif
+ iounmap(bcsr_io);
+}
+
+static void setup_fec1_ioports(void)
+{
+ immap_t *immap = (immap_t *) IMAP_ADDR;
+
+ setbits16(&immap->im_ioport.iop_pdpar, 0x1fff);
+ setbits16(&immap->im_ioport.iop_pddir, 0x1fff);
+}
+
+static void setup_scc1_ioports(void)
+{
+ immap_t *immap = (immap_t *) IMAP_ADDR;
+ unsigned *bcsr_io;
+
+ bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
+
+ if (bcsr_io == NULL) {
+ printk(KERN_CRIT "Could not remap BCSR1\n");
+ return;
+ }
+
+ /* Enable the PHY.
+ */
+ clrbits32(bcsr_io,BCSR1_ETHEN);
+
+ /* Configure port A pins for Txd and Rxd.
+ */
+ /* Disable receive and transmit in case EPPC-Bug started it.
+ */
+ setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
+ clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
+ clrbits16(&immap->im_ioport.iop_paodr, PA_ENET_TXD);
+
+ /* Configure port C pins to enable CLSN and RENA.
+ */
+ clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
+ clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
+ setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
+ /* Configure port A for TCLK and RCLK.
+ */
+ setbits16(&immap->im_ioport.iop_papar, PA_ENET_TCLK | PA_ENET_RCLK);
+ clrbits16(&immap->im_ioport.iop_padir, PA_ENET_TCLK | PA_ENET_RCLK);
+ clrbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA);
+ clrbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA);
+
+ /* Configure Serial Interface clock routing.
+ * First, clear all SCC bits to zero, then set the ones we want.
+ */
+ clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK);
+ setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
+
+ /* In the original SCC enet driver the following code is placed at
+ the end of the initialization */
+ setbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA);
+ setbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA);
+
+}
+
+static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
+{
+ struct fs_platform_info *fpi = pdev->dev.platform_data;
+
+ volatile cpm8xx_t *cp;
+ bd_t *bd = (bd_t *) __res;
+ char *e;
+ int i;
+
+ /* Get pointer to Communication Processor */
+ cp = cpmp;
+ switch (fs_no) {
+ case fsid_fec1:
+ fpi = &mpc8xx_fec_pdata[0];
+ fpi->init_ioports = &setup_fec1_ioports;
+
+ break;
+ case fsid_scc1:
+ fpi = &mpc8xx_scc_pdata;
+ fpi->init_ioports = &setup_scc1_ioports;
+
+ break;
+ default:
+ break;
+ }
+
+ pdev->dev.platform_data = fpi;
+ fpi->fs_no = fs_no;
+
+ e = (unsigned char *)&bd->bi_enetaddr;
+ for (i = 0; i < 6; i++)
+ fpi->macaddr[i] = *e++;
+
+ fpi->macaddr[5 - pdev->id]++;
+
+}
+
+static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
+ int idx)
+{
+ /* This is for FEC devices only */
+ if (strcmp(pdev->name, "fsl-cpm-fec"))
+ return;
+ mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
+}
+
+static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
+ int idx)
+{
+ /* This is for SCC devices only */
+ if (strcmp(pdev->name, "fsl-cpm-scc"))
+ return;
+
+ mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
+}
+
+static int mpc866ads_platform_notify(struct device *dev)
+{
+ static const struct platform_notify_dev_map dev_map[] = {
+ {
+ .bus_id = "fsl-cpm-fec",
+ .rtn = mpc866ads_fixup_fec_enet_pdata,
+ },
+ {
+ .bus_id = "fsl-cpm-scc",
+ .rtn = mpc866ads_fixup_scc_enet_pdata,
+ },
+ {
+ .bus_id = NULL
+ }
+ };
+
+ platform_notify_map(dev_map,dev);
+
+ return 0;
+}
+
+int __init mpc866ads_init(void)
+{
+ printk(KERN_NOTICE "mpc866ads: Init\n");
+
+ platform_notify = mpc866ads_platform_notify;
+
+ ppc_sys_device_initfunc();
+ ppc_sys_device_set_func_all(FUNC_DISABLED);
+ ppc_sys_device_setfunc(MPC8xx_CPM_SCC1, FUNC_ENABLED);
+ ppc_sys_device_setfunc(MPC8xx_CPM_FEC1, FUNC_ENABLED);
+
+ return 0;
+}
+
+arch_initcall(mpc866ads_init);
diff --git a/arch/ppc/platforms/mpc885ads_setup.c b/arch/ppc/platforms/mpc885ads_setup.c
new file mode 100644
index 0000000..feefa91
--- /dev/null
+++ b/arch/ppc/platforms/mpc885ads_setup.c
@@ -0,0 +1,387 @@
+/*arch/ppc/platforms/mpc885ads-setup.c
+ *
+ * Platform setup for the Freescale mpc885ads board
+ *
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * Copyright 2005 MontaVista Software Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/device.h>
+
+#include <linux/fs_enet_pd.h>
+#include <linux/mii.h>
+
+#include <asm/delay.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/ppcboot.h>
+#include <asm/8xx_immap.h>
+#include <asm/commproc.h>
+#include <asm/ppc_sys.h>
+
+extern unsigned char __res[];
+
+static void __init mpc885ads_scc_phy_init(char);
+
+static struct fs_mii_bus_info fec_mii_bus_info = {
+ .method = fsmii_fec,
+ .id = 0,
+};
+
+static struct fs_mii_bus_info scc_mii_bus_info = {
+#ifdef CONFIG_SCC_ENET_8xx_FIXED
+ .method = fsmii_fixed,
+#else
+ .method = fsmii_fec,
+#endif
+
+ .id = 0,
+};
+
+static struct fs_platform_info mpc8xx_fec_pdata[] = {
+ {
+ .rx_ring = 128,
+ .tx_ring = 16,
+ .rx_copybreak = 240,
+
+ .use_napi = 1,
+ .napi_weight = 17,
+
+ .phy_addr = 0,
+ .phy_irq = SIU_IRQ7,
+
+ .bus_info = &fec_mii_bus_info,
+ }, {
+ .rx_ring = 128,
+ .tx_ring = 16,
+ .rx_copybreak = 240,
+
+ .use_napi = 1,
+ .napi_weight = 17,
+
+ .phy_addr = 1,
+ .phy_irq = SIU_IRQ7,
+
+ .bus_info = &fec_mii_bus_info,
+ }
+};
+
+static struct fs_platform_info mpc8xx_scc_pdata = {
+ .rx_ring = 64,
+ .tx_ring = 8,
+ .rx_copybreak = 240,
+
+ .use_napi = 1,
+ .napi_weight = 17,
+
+ .phy_addr = 2,
+#ifdef CONFIG_MPC8xx_SCC_ENET_FIXED
+ .phy_irq = -1,
+#else
+ .phy_irq = SIU_IRQ7,
+#endif
+
+ .bus_info = &scc_mii_bus_info,
+};
+
+void __init board_init(void)
+{
+ volatile cpm8xx_t *cp = cpmp;
+ unsigned int *bcsr_io;
+
+#ifdef CONFIG_FS_ENET
+ immap_t *immap = (immap_t *) IMAP_ADDR;
+#endif
+ bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
+
+ if (bcsr_io == NULL) {
+ printk(KERN_CRIT "Could not remap BCSR\n");
+ return;
+ }
+#ifdef CONFIG_SERIAL_CPM_SMC1
+ cp->cp_simode &= ~(0xe0000000 >> 17); /* brg1 */
+ clrbits32(bcsr_io, BCSR1_RS232EN_1);
+#else
+ setbits32(bcsr_io,BCSR1_RS232EN_1);
+ cp->cp_smc[0].smc_smcmr = 0;
+ cp->cp_smc[0].smc_smce = 0;
+#endif
+
+#ifdef CONFIG_SERIAL_CPM_SMC2
+ cp->cp_simode &= ~(0xe0000000 >> 1);
+ cp->cp_simode |= (0x20000000 >> 1); /* brg2 */
+ clrbits32(bcsr_io,BCSR1_RS232EN_2);
+#else
+ setbits32(bcsr_io,BCSR1_RS232EN_2);
+ cp->cp_smc[1].smc_smcmr = 0;
+ cp->cp_smc[1].smc_smce = 0;
+#endif
+ iounmap(bcsr_io);
+
+#ifdef CONFIG_FS_ENET
+ /* use MDC for MII (common) */
+ setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
+ clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
+#endif
+}
+
+static void setup_fec1_ioports(void)
+{
+ immap_t *immap = (immap_t *) IMAP_ADDR;
+
+ /* configure FEC1 pins */
+ setbits16(&immap->im_ioport.iop_papar, 0xf830);
+ setbits16(&immap->im_ioport.iop_padir, 0x0830);
+ clrbits16(&immap->im_ioport.iop_padir, 0xf000);
+ setbits32(&immap->im_cpm.cp_pbpar, 0x00001001);
+
+ clrbits32(&immap->im_cpm.cp_pbdir, 0x00001001);
+ setbits16(&immap->im_ioport.iop_pcpar, 0x000c);
+ clrbits16(&immap->im_ioport.iop_pcdir, 0x000c);
+ setbits32(&immap->im_cpm.cp_pepar, 0x00000003);
+
+ setbits32(&immap->im_cpm.cp_pedir, 0x00000003);
+ clrbits32(&immap->im_cpm.cp_peso, 0x00000003);
+ clrbits32(&immap->im_cpm.cp_cptr, 0x00000100);
+}
+
+static void setup_fec2_ioports(void)
+{
+ immap_t *immap = (immap_t *) IMAP_ADDR;
+
+ /* configure FEC2 pins */
+ setbits32(&immap->im_cpm.cp_pepar, 0x0003fffc);
+ setbits32(&immap->im_cpm.cp_pedir, 0x0003fffc);
+ setbits32(&immap->im_cpm.cp_peso, 0x00037800);
+ clrbits32(&immap->im_cpm.cp_peso, 0x000087fc);
+ clrbits32(&immap->im_cpm.cp_cptr, 0x00000080);
+}
+
+static void setup_scc3_ioports(void)
+{
+ immap_t *immap = (immap_t *) IMAP_ADDR;
+ unsigned *bcsr_io;
+
+ bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
+
+ if (bcsr_io == NULL) {
+ printk(KERN_CRIT "Could not remap BCSR\n");
+ return;
+ }
+
+ /* Enable the PHY.
+ */
+ setbits32(bcsr_io+4, BCSR4_ETH10_RST);
+ /* Configure port A pins for Txd and Rxd.
+ */
+ setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
+ clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
+
+ /* Configure port C pins to enable CLSN and RENA.
+ */
+ clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
+ clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
+ setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
+
+ /* Configure port E for TCLK and RCLK.
+ */
+ setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
+ clrbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA);
+ clrbits32(&immap->im_cpm.cp_pedir,
+ PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
+ clrbits32(&immap->im_cpm.cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
+ setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
+
+ /* Configure Serial Interface clock routing.
+ * First, clear all SCC bits to zero, then set the ones we want.
+ */
+ clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK);
+ setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
+
+ /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
+ */
+ immap->im_cpm.cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
+ /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
+ * by H/W setting after reset. SCC ethernet controller support only half duplex.
+ * This discrepancy of modes causes a lot of carrier lost errors.
+ */
+
+ /* In the original SCC enet driver the following code is placed at
+ the end of the initialization */
+ setbits32(&immap->im_cpm.cp_pepar, PE_ENET_TENA);
+ clrbits32(&immap->im_cpm.cp_pedir, PE_ENET_TENA);
+ setbits32(&immap->im_cpm.cp_peso, PE_ENET_TENA);
+
+ setbits32(bcsr_io+1, BCSR1_ETHEN);
+ iounmap(bcsr_io);
+}
+
+static void mpc885ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
+{
+ struct fs_platform_info *fpi = pdev->dev.platform_data;
+
+ volatile cpm8xx_t *cp;
+ bd_t *bd = (bd_t *) __res;
+ char *e;
+ int i;
+
+ /* Get pointer to Communication Processor */
+ cp = cpmp;
+ switch (fs_no) {
+ case fsid_fec1:
+ fpi = &mpc8xx_fec_pdata[0];
+ fpi->init_ioports = &setup_fec1_ioports;
+ break;
+ case fsid_fec2:
+ fpi = &mpc8xx_fec_pdata[1];
+ fpi->init_ioports = &setup_fec2_ioports;
+ break;
+ case fsid_scc3:
+ fpi = &mpc8xx_scc_pdata;
+ fpi->init_ioports = &setup_scc3_ioports;
+ mpc885ads_scc_phy_init(fpi->phy_addr);
+ break;
+ default:
+ break;
+ }
+
+ pdev->dev.platform_data = fpi;
+ fpi->fs_no = fs_no;
+
+ e = (unsigned char *)&bd->bi_enetaddr;
+ for (i = 0; i < 6; i++)
+ fpi->macaddr[i] = *e++;
+
+ fpi->macaddr[5 - pdev->id]++;
+
+}
+
+static void mpc885ads_fixup_fec_enet_pdata(struct platform_device *pdev,
+ int idx)
+{
+ /* This is for FEC devices only */
+ if (!strstr(pdev->name, "fsl-cpm-fec"))
+ return;
+ mpc885ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
+}
+
+static void __init mpc885ads_fixup_scc_enet_pdata(struct platform_device *pdev,
+ int idx)
+{
+ /* This is for SCC devices only */
+ if (!strstr(pdev->name, "fsl-cpm-scc"))
+ return;
+
+ mpc885ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
+}
+
+/* SCC ethernet controller does not have MII management channel. FEC1 MII
+ * channel is used to communicate with the 10Mbit PHY.
+ */
+
+#define MII_ECNTRL_PINMUX 0x4
+#define FEC_ECNTRL_PINMUX 0x00000004
+#define FEC_RCNTRL_MII_MODE 0x00000004
+
+/* Make MII read/write commands.
+ */
+#define mk_mii_write(REG, VAL, PHY_ADDR) (0x50020000 | (((REG) & 0x1f) << 18) | \
+ ((VAL) & 0xffff) | ((PHY_ADDR) << 23))
+
+static void mpc885ads_scc_phy_init(char phy_addr)
+{
+ volatile immap_t *immap;
+ volatile fec_t *fecp;
+ bd_t *bd;
+
+ bd = (bd_t *) __res;
+ immap = (immap_t *) IMAP_ADDR; /* pointer to internal registers */
+ fecp = &(immap->im_cpm.cp_fec);
+
+ /* Enable MII pins of the FEC1
+ */
+ setbits16(&immap->im_ioport.iop_pdpar, 0x0080);
+ clrbits16(&immap->im_ioport.iop_pddir, 0x0080);
+ /* Set MII speed to 2.5 MHz
+ */
+ out_be32(&fecp->fec_mii_speed,
+ ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1);
+
+ /* Enable FEC pin MUX
+ */
+ setbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);
+ setbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
+
+ out_be32(&fecp->fec_mii_data,
+ mk_mii_write(MII_BMCR, BMCR_ISOLATE, phy_addr));
+ udelay(100);
+ out_be32(&fecp->fec_mii_data,
+ mk_mii_write(MII_ADVERTISE,
+ ADVERTISE_10HALF | ADVERTISE_CSMA, phy_addr));
+ udelay(100);
+
+ /* Disable FEC MII settings
+ */
+ clrbits32(&fecp->fec_ecntrl, MII_ECNTRL_PINMUX);
+ clrbits32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE);
+ out_be32(&fecp->fec_mii_speed, 0);
+}
+
+static int mpc885ads_platform_notify(struct device *dev)
+{
+
+ static const struct platform_notify_dev_map dev_map[] = {
+ {
+ .bus_id = "fsl-cpm-fec",
+ .rtn = mpc885ads_fixup_fec_enet_pdata,
+ },
+ {
+ .bus_id = "fsl-cpm-scc",
+ .rtn = mpc885ads_fixup_scc_enet_pdata,
+ },
+ {
+ .bus_id = NULL
+ }
+ };
+
+ platform_notify_map(dev_map,dev);
+
+}
+
+int __init mpc885ads_init(void)
+{
+ printk(KERN_NOTICE "mpc885ads: Init\n");
+
+ platform_notify = mpc885ads_platform_notify;
+
+ ppc_sys_device_initfunc();
+ ppc_sys_device_set_func_all(FUNC_DISABLED);
+ ppc_sys_device_setfunc(MPC8xx_CPM_FEC1, FUNC_ENABLED);
+
+#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
+ ppc_sys_device_setfunc(MPC8xx_CPM_SCC1, FUNC_ENABLED);
+
+#endif
+#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
+ ppc_sys_device_setfunc(MPC8xx_CPM_FEC2, FUNC_ENABLED);
+#endif
+
+ return 0;
+}
+
+arch_initcall(mpc885ads_init);
diff --git a/arch/ppc/platforms/pq2ads.h b/arch/ppc/platforms/pq2ads.h
index 067d9a5..6b26dd3 100644
--- a/arch/ppc/platforms/pq2ads.h
+++ b/arch/ppc/platforms/pq2ads.h
@@ -13,6 +13,10 @@
#include <asm/ppcboot.h>
+#if defined(CONFIG_ADS8272)
+#define BOARD_CHIP_NAME "8272"
+#endif
+
/* Memory map is configured by the PROM startup.
* We just map a few things we need. The CSR is actually 4 byte-wide
* registers that can be accessed as 8-, 16-, or 32-bit values.
diff --git a/arch/ppc/platforms/pq2ads_pd.h b/arch/ppc/platforms/pq2ads_pd.h
new file mode 100644
index 0000000..8f14a43
--- /dev/null
+++ b/arch/ppc/platforms/pq2ads_pd.h
@@ -0,0 +1,114 @@
+#ifndef __PQ2ADS_PD_H
+#define __PQ2ADS_PD_H
+/*
+ * arch/ppc/platforms/82xx/pq2ads_pd.h
+ *
+ * Some defines for MPC82xx board-specific PlatformDevice descriptions
+ *
+ * 2005 (c) MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/* FCC1 Clock Source Configuration. These can be redefined in the board specific file.
+ Can only choose from CLK9-12 */
+
+#define F1_RXCLK 11
+#define F1_TXCLK 10
+
+/* FCC2 Clock Source Configuration. These can be redefined in the board specific file.
+ Can only choose from CLK13-16 */
+#define F2_RXCLK 15
+#define F2_TXCLK 16
+
+/* FCC3 Clock Source Configuration. These can be redefined in the board specific file.
+ Can only choose from CLK13-16 */
+#define F3_RXCLK 13
+#define F3_TXCLK 14
+
+/* Automatically generates register configurations */
+#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
+
+#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
+#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
+#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
+#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
+#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
+#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
+
+#define PC_F1RXCLK PC_CLK(F1_RXCLK)
+#define PC_F1TXCLK PC_CLK(F1_TXCLK)
+#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
+#define CMX1_CLK_MASK ((uint)0xff000000)
+
+#define PC_F2RXCLK PC_CLK(F2_RXCLK)
+#define PC_F2TXCLK PC_CLK(F2_TXCLK)
+#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
+#define CMX2_CLK_MASK ((uint)0x00ff0000)
+
+#define PC_F3RXCLK PC_CLK(F3_RXCLK)
+#define PC_F3TXCLK PC_CLK(F3_TXCLK)
+#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
+#define CMX3_CLK_MASK ((uint)0x0000ff00)
+
+/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
+ * but there is little variation among the choices.
+ */
+#define PA1_COL 0x00000001U
+#define PA1_CRS 0x00000002U
+#define PA1_TXER 0x00000004U
+#define PA1_TXEN 0x00000008U
+#define PA1_RXDV 0x00000010U
+#define PA1_RXER 0x00000020U
+#define PA1_TXDAT 0x00003c00U
+#define PA1_RXDAT 0x0003c000U
+#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
+#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
+ PA1_RXDV | PA1_RXER)
+#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
+#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
+
+
+/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
+ * but there is little variation among the choices.
+ */
+#define PB2_TXER 0x00000001U
+#define PB2_RXDV 0x00000002U
+#define PB2_TXEN 0x00000004U
+#define PB2_RXER 0x00000008U
+#define PB2_COL 0x00000010U
+#define PB2_CRS 0x00000020U
+#define PB2_TXDAT 0x000003c0U
+#define PB2_RXDAT 0x00003c00U
+#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
+ PB2_RXER | PB2_RXDV | PB2_TXER)
+#define PB2_PSORB1 (PB2_TXEN)
+#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
+#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
+
+
+/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
+ * but there is little variation among the choices.
+ */
+#define PB3_RXDV 0x00004000U
+#define PB3_RXER 0x00008000U
+#define PB3_TXER 0x00010000U
+#define PB3_TXEN 0x00020000U
+#define PB3_COL 0x00040000U
+#define PB3_CRS 0x00080000U
+#define PB3_TXDAT 0x0f000000U
+#define PB3_RXDAT 0x00f00000U
+#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
+ PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
+#define PB3_PSORB1 0
+#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
+#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
+
+#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
+#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
+#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
+
+#endif
---
Sincerely,
Vitaly
^ permalink raw reply related
* [PATCH 2/3] ppc32 8xx: Added setbitsXX/clrbitsXX macro for read-modify-write operations
From: Vitaly Bordug @ 2005-12-19 13:21 UTC (permalink / raw)
To: Kumar Gala, Marcelo Tosatti, Pantelis Antoniou,
linuxppc-embedded list
This adds setbitsXX/clrbitsXX macro for read-modify-write operations
and converts the 8xx core and drivers to use them.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
---
arch/ppc/8xx_io/commproc.c | 6 +++---
arch/ppc/syslib/m8xx_setup.c | 12 +++++-------
arch/ppc/syslib/m8xx_wdt.c | 3 +--
include/asm-ppc/io.h | 7 +++++++
4 files changed, 16 insertions(+), 12 deletions(-)
applies-to: 35d67fb06e89218629ae613633a01c7532f45ac0
3420ec0002cc78ecce97921ca4bb9488be6bbdf5
diff --git a/arch/ppc/8xx_io/commproc.c b/arch/ppc/8xx_io/commproc.c
index 579cd40..12b84ca 100644
--- a/arch/ppc/8xx_io/commproc.c
+++ b/arch/ppc/8xx_io/commproc.c
@@ -73,7 +73,7 @@ cpm_mask_irq(unsigned int irq)
{
int cpm_vec = irq - CPM_IRQ_OFFSET;
- out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr) & ~(1 << cpm_vec));
+ clrbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, (1 << cpm_vec));
}
static void
@@ -81,7 +81,7 @@ cpm_unmask_irq(unsigned int irq)
{
int cpm_vec = irq - CPM_IRQ_OFFSET;
- out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr) | (1 << cpm_vec));
+ setbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, (1 << cpm_vec));
}
static void
@@ -198,7 +198,7 @@ cpm_interrupt_init(void)
if (setup_irq(CPM_IRQ_OFFSET + CPMVEC_ERROR, &cpm_error_irqaction))
panic("Could not allocate CPM error IRQ!");
- out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr) | CICR_IEN);
+ setbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr, CICR_IEN);
}
/*
diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c
index 1cc3abe..ad7db45 100644
--- a/arch/ppc/syslib/m8xx_setup.c
+++ b/arch/ppc/syslib/m8xx_setup.c
@@ -149,8 +149,7 @@ void __init m8xx_calibrate_decr(void)
out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, KAPWR_KEY);
/* Force all 8xx processors to use divide by 16 processor clock. */
- out_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr,
- in_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr)|0x02000000);
+ setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr, 0x02000000);
/* Processor frequency is MHz.
* The value 'fp' is the number of decrementer ticks per second.
*/
@@ -184,10 +183,9 @@ void __init m8xx_calibrate_decr(void)
out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, KAPWR_KEY);
/* Disable the RTC one second and alarm interrupts. */
- out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) & ~(RTCSC_SIE | RTCSC_ALE));
+ clrbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
/* Enable the RTC */
- out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) | (RTCSC_RTF | RTCSC_RTE));
-
+ setbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
/* Enabling the decrementer also enables the timebase interrupts
* (or from the other point of view, to get decrementer interrupts
* we have to enable the timebase). The decrementer interrupt
@@ -232,8 +230,8 @@ m8xx_restart(char *cmd)
__volatile__ unsigned char dummy;
local_irq_disable();
- out_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, in_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr) | 0x00000080);
+ setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, 0x00000080);
/* Clear the ME bit in MSR to cause checkstop on machine check
*/
mtmsr(mfmsr() & ~0x1000);
@@ -303,8 +301,8 @@ m8xx_init_IRQ(void)
i8259_init(0);
/* The i8259 cascade interrupt must be level sensitive. */
- out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, in_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel & ~(0x80000000 >> ISA_BRIDGE_INT)));
+ clrbits32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, (0x80000000 >> ISA_BRIDGE_INT));
if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction))
enable_irq(ISA_BRIDGE_INT);
#endif /* CONFIG_PCI */
diff --git a/arch/ppc/syslib/m8xx_wdt.c b/arch/ppc/syslib/m8xx_wdt.c
index a21632d..57f8b9f 100644
--- a/arch/ppc/syslib/m8xx_wdt.c
+++ b/arch/ppc/syslib/m8xx_wdt.c
@@ -40,8 +40,7 @@ static irqreturn_t m8xx_wdt_interrupt(in
m8xx_wdt_reset();
- out_be16(&imap->im_sit.sit_piscr, in_be16(&imap->im_sit.sit_piscr) | PISCR_PS); /* clear irq */
-
+ setbits16(&imap->im_sit.sit_piscr, PISCR_PS);
return IRQ_HANDLED;
}
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 84ac6e2..9c2e3db 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -573,4 +573,11 @@ extern void pci_iounmap(struct pci_dev *
*/
#define xlate_dev_kmem_ptr(p) p
+/* access ports */
+#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
+#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
+
+#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
+#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
+
#endif /* __KERNEL__ */
---
Sincerely,
Vitaly
^ permalink raw reply related
* [PATCH 1/3] ppc32: Make platform devices being able to assign functions
From: Vitaly Bordug @ 2005-12-19 13:21 UTC (permalink / raw)
To: Kumar Gala, Marcelo Tosatti; +Cc: linuxppc-embedded list
Implemented by modification of the .name field of the platform device,
when PDs with the
same names are to be used within different drivers, as
<device_name> -> <device_name>:<function>
Corresponding drivers should change the .name in struct device_driver to
reflect upper of course.
Also helper platform_notify_map function added, making assignment of
board-specific platform_info more consistent and generic.
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
---
arch/ppc/syslib/ppc_sys.c | 136 ++++++++++++++++++++++++++++++++++++++++++++-
include/asm-ppc/mpc10x.h | 1
include/asm-ppc/mpc52xx.h | 1
include/asm-ppc/mpc8260.h | 1
include/asm-ppc/mpc83xx.h | 1
include/asm-ppc/mpc85xx.h | 1
include/asm-ppc/mpc8xx.h | 1
include/asm-ppc/ppc_sys.h | 24 ++++++++
8 files changed, 164 insertions(+), 2 deletions(-)
applies-to: 4ce1b1890dc687cb1cf77f98e7a95b94c7ef3a93
a8450a334dc930d7284800c457d91ed55a1a3dd7
diff --git a/arch/ppc/syslib/ppc_sys.c b/arch/ppc/syslib/ppc_sys.c
index c0b93c4..26d2658 100644
--- a/arch/ppc/syslib/ppc_sys.c
+++ b/arch/ppc/syslib/ppc_sys.c
@@ -15,11 +15,23 @@
*/
#include <linux/string.h>
+#include <linux/bootmem.h>
#include <asm/ppc_sys.h>
int (*ppc_sys_device_fixup) (struct platform_device * pdev);
static int ppc_sys_inited;
+static int ppc_sys_func_inited;
+
+static const char *ppc_sys_func_names[] = {
+ [FUNC_ENABLED] = "dummy",
+ [FUNC_ETH] = "eth",
+ [FUNC_UART] = "uart",
+ [FUNC_HLDC] = "hldc",
+ [FUNC_USB] = "usb",
+ [FUNC_IRDA] = "irda",
+ [FUNC_DISABLED] = "off",
+};
void __init identify_ppc_sys_by_id(u32 id)
{
@@ -38,13 +50,13 @@ void __init identify_ppc_sys_by_id(u32 i
void __init identify_ppc_sys_by_name(char *name)
{
unsigned int i = 0;
- while (ppc_sys_specs[i].ppc_sys_name[0])
- {
+ while (ppc_sys_specs[i].ppc_sys_name[0]) {
if (!strcmp(ppc_sys_specs[i].ppc_sys_name, name))
break;
i++;
}
cur_ppc_sys_spec = &ppc_sys_specs[i];
+
return;
}
@@ -128,6 +140,126 @@ void ppc_sys_device_remove(enum ppc_sys_
}
}
+/* Platform-notify mapping
+ * Helper function for BSP code to assign board-specific platfom-divice bits
+ */
+
+void platform_notify_map(const struct platform_notify_dev_map *map,
+ struct device *dev)
+{
+ struct platform_device *pdev;
+ int len, idx;
+ const char *s;
+
+ /* do nothing if no device or no bus_id */
+ if (!dev || !dev->bus_id)
+ return;
+
+ /* call per device map */
+ while (map->bus_id != NULL) {
+ idx = -1;
+ s = strrchr(dev->bus_id, '.');
+ if (s != NULL)
+ idx = (int)simple_strtol(s + 1, NULL, 10);
+ else
+ s = dev->bus_id + strlen(s);
+
+ len = s - dev->bus_id;
+
+ if (!strncmp(dev->bus_id, map->bus_id, len)) {
+ pdev = container_of(dev, struct platform_device, dev);
+ map->rtn(pdev, idx);
+ }
+ map++;
+ }
+}
+
+/*
+ Function assignment stuff.
+ Intended to work as follows:
+ the device name defined in foo_devices.c will be concatenated with :"func",
+ where func is string map of respective function from platfom_device_func enum
+
+ The FUNC_ENABLED function is intended to remove all assignments, making the device to appear
+ in platform bus with unmodified name.
+ */
+
+/*
+ Here we'll replace .name pointers with fixed-lenght strings
+ Hereby, this should be called *before* any func stuff triggeded.
+ */
+void ppc_sys_device_initfunc(void)
+{
+ int i;
+ const char *name;
+ static char new_names[NUM_PPC_SYS_DEVS][BUS_ID_SIZE];
+ enum ppc_sys_devices cur_dev;
+
+ /* If inited yet, do nothing */
+ if (ppc_sys_func_inited)
+ return;
+
+ for (i = 0; i < cur_ppc_sys_spec->num_devices; i++) {
+ if ((cur_dev = cur_ppc_sys_spec->device_list[i]) < 0)
+ continue;
+
+ if (ppc_sys_platform_devices[cur_dev].name) {
+ /*backup name */
+ name = ppc_sys_platform_devices[cur_dev].name;
+ strlcpy(new_names[i], name, BUS_ID_SIZE);
+ ppc_sys_platform_devices[cur_dev].name = new_names[i];
+ }
+ }
+
+ ppc_sys_func_inited = 1;
+}
+
+/*The "engine" of the func stuff. Here we either concat specified function string description
+ to the name, or remove it if FUNC_ENABLED parameter is passed here*/
+void ppc_sys_device_setfunc(enum ppc_sys_devices dev,
+ enum platform_device_func func)
+{
+ char *s;
+ char *name = (char *)ppc_sys_platform_devices[dev].name;
+ char tmp[BUS_ID_SIZE];
+
+ if (!ppc_sys_func_inited) {
+ printk(KERN_ERR "Unable to alter function - not inited!\n");
+ return;
+ }
+
+ if (ppc_sys_inited) {
+ platform_device_unregister(&ppc_sys_platform_devices[dev]);
+ }
+
+ if ((s = (char *)strchr(name, ':')) != NULL) { /* reassign */
+ /* Either change the name after ':' or remove func modifications */
+ if (func != FUNC_ENABLED)
+ strlcpy(s + 1, ppc_sys_func_names[func], BUS_ID_SIZE);
+ else
+ *s = 0;
+ } else if (func != FUNC_ENABLED) {
+ /* do assignment if it is not just "enable" request */
+ sprintf(tmp, "%s:%s", name, ppc_sys_func_names[func]);
+ strlcpy(name, tmp, BUS_ID_SIZE);
+ }
+
+ if (ppc_sys_inited) {
+ platform_device_register(&ppc_sys_platform_devices[dev]);
+ }
+}
+
+void ppc_sys_device_set_func_all(enum platform_device_func func)
+{
+ enum ppc_sys_devices cur_dev;
+ int i;
+
+ for (i = 0; i < cur_ppc_sys_spec->num_devices; i++) {
+ cur_dev = cur_ppc_sys_spec->device_list[i];
+ ppc_sys_device_setfunc(cur_dev, func);
+ }
+}
+
static int __init ppc_sys_init(void)
{
unsigned int i, dev_id, ret = 0;
diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h
index 77b1e09..976ad3d 100644
--- a/include/asm-ppc/mpc10x.h
+++ b/include/asm-ppc/mpc10x.h
@@ -165,6 +165,7 @@ enum ppc_sys_devices {
MPC10X_DMA1,
MPC10X_UART0,
MPC10X_UART1,
+ NUM_PPC_SYS_DEVS,
};
int mpc10x_bridge_init(struct pci_controller *hose,
diff --git a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
index e5f80c2..b2cb44f 100644
--- a/include/asm-ppc/mpc52xx.h
+++ b/include/asm-ppc/mpc52xx.h
@@ -49,6 +49,7 @@ enum ppc_sys_devices {
MPC52xx_ATA,
MPC52xx_I2C1,
MPC52xx_I2C2,
+ NUM_PPC_SYS_DEVS,
};
diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
index 3214526..6ba69a8 100644
--- a/include/asm-ppc/mpc8260.h
+++ b/include/asm-ppc/mpc8260.h
@@ -83,6 +83,7 @@ enum ppc_sys_devices {
MPC82xx_CPM_SMC2,
MPC82xx_CPM_USB,
MPC82xx_SEC1,
+ NUM_PPC_SYS_DEVS,
};
#ifndef __ASSEMBLY__
diff --git a/include/asm-ppc/mpc83xx.h b/include/asm-ppc/mpc83xx.h
index 7cdf60f..3c23fc4 100644
--- a/include/asm-ppc/mpc83xx.h
+++ b/include/asm-ppc/mpc83xx.h
@@ -108,6 +108,7 @@ enum ppc_sys_devices {
MPC83xx_USB2_DR,
MPC83xx_USB2_MPH,
MPC83xx_MDIO,
+ NUM_PPC_SYS_DEVS,
};
#endif /* CONFIG_83xx */
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
index 9d14bae..2a77884 100644
--- a/include/asm-ppc/mpc85xx.h
+++ b/include/asm-ppc/mpc85xx.h
@@ -135,6 +135,7 @@ enum ppc_sys_devices {
MPC85xx_eTSEC4,
MPC85xx_IIC2,
MPC85xx_MDIO,
+ NUM_PPC_SYS_DEVS,
};
/* Internal interrupts are all Level Sensitive, and Positive Polarity */
diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h
index 46f159c..90e3d59 100644
--- a/include/asm-ppc/mpc8xx.h
+++ b/include/asm-ppc/mpc8xx.h
@@ -111,6 +111,7 @@ enum ppc_sys_devices {
MPC8xx_CPM_SMC1,
MPC8xx_CPM_SMC2,
MPC8xx_CPM_USB,
+ NUM_PPC_SYS_DEVS,
};
#ifndef BOARD_CHIP_NAME
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
index 83d8c77..76f259f 100644
--- a/include/asm-ppc/ppc_sys.h
+++ b/include/asm-ppc/ppc_sys.h
@@ -47,6 +47,21 @@ struct ppc_sys_spec {
enum ppc_sys_devices *device_list;
};
+struct platform_notify_dev_map {
+ const char *bus_id;
+ void (*rtn)(struct platform_device * pdev, int idx);
+};
+
+enum platform_device_func {
+ FUNC_ENABLED = 0,
+ FUNC_ETH = 1,
+ FUNC_UART = 2,
+ FUNC_HLDC = 3,
+ FUNC_USB = 4,
+ FUNC_IRDA = 5,
+ FUNC_DISABLED = 6,
+};
+
/* describes all specific chips and which devices they have on them */
extern struct ppc_sys_spec ppc_sys_specs[];
extern struct ppc_sys_spec *cur_ppc_sys_spec;
@@ -72,5 +87,14 @@ extern void *ppc_sys_get_pdata(enum ppc_
/* remove a device from the system */
extern void ppc_sys_device_remove(enum ppc_sys_devices dev);
+/*Function assignment stuff*/
+void ppc_sys_device_initfunc(void);
+void ppc_sys_device_setfunc(enum ppc_sys_devices dev,
+ enum platform_device_func func);
+void ppc_sys_device_set_func_all(enum platform_device_func func);
+
+void platform_notify_map(const struct platform_notify_dev_map *map,
+ struct device *dev);
+
#endif /* __ASM_PPC_SYS_H */
#endif /* __KERNEL__ */
---
Sincerely,
Vitaly
^ permalink raw reply related
* Re: Howto submit drivers/patches ?
From: John Carlson @ 2005-12-19 13:10 UTC (permalink / raw)
To: David H. Lynch Jr., linuxppc-embedded
In-Reply-To: <43A64446.8080109@comcast.net>
--- "David H. Lynch Jr." <dhlii@comcast.net> wrote:
>
> I am just polishing off bringup a Xilinx Virtex
> IV/ppc405 system with
> minimal hardware under 2.6.14.4.
> I have a collection of patches that I can submit
> for the specific,
> board, for the Virtex IV, for board specific
> hardware, ...
> Additionally I have 2 complete boot loader through
> full serial driver
> implementations of a pseudo serial console driver
> for this board when it
> is in a HOST development system - it is a compact
> flash card normally
> plugged into a PC during development and using the
> PC as the console,
> and a complete serial driver chain for the Xilinx
> UartLite as a console
> when not in a Host, or as a general serial driver.
> The Xilinx Driver is
> based heavily on other 2.6 driver/serial drivers and
> not the 2.4
> implementation from Xilinx.
>
> Is this list the right place to submit this ?
> Is there a HOWTO addressing the rules/procedures to
> do so.
Look in the Documentation directory, specificly the
two files
SubmittingDrivers and SubmittingPatches where the
correct
procedure is explained.
>
> I have not looked at the kernel style guides, but
> the style of this
> code is pretty much identical to other Kernel code.
> The UartLite driver
> is virtually indistinguishable from other
> driver/serial drivers except
> the few places where hardware differences require
> changes, and that
> there is a full tree of end-end support similar to
> what exists for the
> 8250's.
>
> David H. Lynch Jr.
> DLA Systems
> 354 Rudy Dam Rd.
> Lititz, PA 17543
> 717.627.3770
>
>
>
>
>
>
>
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
>
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
John Carlson
<carlsj@yahoo.com>
__________________________________________________
Do You Yahoo!?
Tired of spam? Yahoo! Mail has the best spam protection around
http://mail.yahoo.com
^ permalink raw reply
* Re: [PATCH] CPM initial console on ttyS instead of ttyCPM
From: Pantelis Antoniou @ 2005-12-19 13:08 UTC (permalink / raw)
To: Nathael Pajani; +Cc: linuxppc-embedded
In-Reply-To: <20051219140927.55259cea.nathael.pajani@cpe.fr>
Nathael Pajani wrote:
> Hi!
>
> here is a patch to have the CPM consoles on /dev/ttyS* instead of /dev/ttyCPM*
> Of course, it depends on not already having a 8250 like uart configured, in which case it falls back to ttyCPM.
>
> Signed-off-by: Nathael Pajani <nathael.pajani at cpe.fr>
>
[snip]
>
>
>
WTF is that? There was a reason why both the device number & name changed.
And misusing the 8250 config option, that's nice.
Try to come up with something less intrusive please.
Pantelis
^ permalink raw reply
* [PATCH] CPM initial console on ttyS instead of ttyCPM
From: Nathael Pajani @ 2005-12-19 13:09 UTC (permalink / raw)
To: linuxppc-embedded
Hi!
here is a patch to have the CPM consoles on /dev/ttyS* instead of /dev/ttyC=
PM*
Of course, it depends on not already having a 8250 like uart configured, in=
which case it falls back to ttyCPM.
Signed-off-by: Nathael Pajani <nathael.pajani at cpe.fr>
diff -urpN linux-2.6.13.2_light/drivers/serial/cpm_uart/cpm_uart_core.c ecr=
in-2.6.13.2_light/drivers/serial/cpm_uart/cpm_uart_core.c
--- linux-2.6.13.2_light/drivers/serial/cpm_uart/cpm_uart_core.c 2005-12-16=
12:08:48.867092000 +0100
+++ ecrin-2.6.13.2_light/drivers/serial/cpm_uart/cpm_uart_core.c 2005-12-16=
11:53:13.140613000 +0100
@@ -70,10 +70,11 @@ static void cpm_uart_init_scc(struct uar
static void cpm_uart_initbd(struct uart_cpm_port *pinfo);
=20
/**************************************************************/
+/*cpm2_immr =3D (cpm2_map_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE)*/
=20
static inline unsigned long cpu2cpm_addr(void *addr)
{
- if ((unsigned long)addr >=3D CPM_ADDR)
+ if( (unsigned long)addr >=3D CPM_ADDR )
return (unsigned long)addr;
return virt_to_bus(addr);
}
@@ -1072,13 +1073,13 @@ static void cpm_uart_console_write(struc
}
=20
/*
- * Setup console. Be careful is called early !
+ * Setup console. Be careful this is called early !
*/
static int __init cpm_uart_console_setup(struct console *co, char *options)
{
struct uart_port *port;
struct uart_cpm_port *pinfo;
- int baud =3D 38400;
+ int baud =3D 9600; /* NATH: was 38400 */
int bits =3D 8;
int parity =3D 'n';
int flow =3D 'n';
@@ -1136,7 +1137,11 @@ static int __init cpm_uart_console_setup
=20
static struct uart_driver cpm_reg;
static struct console cpm_scc_uart_console =3D {
+#ifndef CONFIG_SERIAL_8250
+ .name =3D "ttyS",
+#else
.name =3D "ttyCPM",
+#endif
.write =3D cpm_uart_console_write,
.device =3D uart_console_device,
.setup =3D cpm_uart_console_setup,
@@ -1163,8 +1168,14 @@ console_initcall(cpm_uart_console_init);
=20
static struct uart_driver cpm_reg =3D {
.owner =3D THIS_MODULE,
+#ifndef CONFIG_SERIAL_8250
+ .driver_name =3D "serial",
+/* .devfs_name =3D "tts/", */
+ .dev_name =3D "ttyS",
+#else
.driver_name =3D "ttyCPM",
.dev_name =3D "ttyCPM",
+#endif
.major =3D SERIAL_CPM_MAJOR,
.minor =3D SERIAL_CPM_MINOR,
.cons =3D CPM_UART_CONSOLE,
@@ -1174,7 +1185,7 @@ static int __init cpm_uart_init(void)
{
int ret, i;
=20
- printk(KERN_INFO "Serial: CPM driver $Revision: 0.01 $\n");
+ printk(KERN_INFO "Serial: CPM driver $Revision: 0.01b $\n");
=20
#ifndef CONFIG_SERIAL_CPM_CONSOLE
ret =3D cpm_uart_init_portdesc();
diff -urpN linux-2.6.13.2_light/drivers/serial/cpm_uart/cpm_uart_cpm2.h ecr=
in-2.6.13.2_light/drivers/serial/cpm_uart/cpm_uart_cpm2.h
--- linux-2.6.13.2_light/drivers/serial/cpm_uart/cpm_uart_cpm2.h 2005-12-16=
12:08:48.883093000 +0100
+++ ecrin-2.6.13.2_light/drivers/serial/cpm_uart/cpm_uart_cpm2.h 2005-12-16=
11:53:13.144613000 +0100
@@ -20,9 +20,6 @@
#define SCC3_IRQ SIU_INT_SCC3
#define SCC4_IRQ SIU_INT_SCC4
=20
-/* the CPM address */
-#define CPM_ADDR CPM_MAP_ADDR
-
static inline void cpm_set_brg(int brg, int baud)
{
cpm_setbrg(brg, baud);
diff -urpN linux-2.6.13.2_light/drivers/serial/cpm_uart/cpm_uart.h ecrin-2.=
6.13.2_light/drivers/serial/cpm_uart/cpm_uart.h
--- linux-2.6.13.2_light/drivers/serial/cpm_uart/cpm_uart.h 2005-12-16 12:0=
8:48.863092000 +0100
+++ ecrin-2.6.13.2_light/drivers/serial/cpm_uart/cpm_uart.h 2005-12-16 11:5=
3:13.140613000 +0100
@@ -17,8 +17,13 @@
#include "cpm_uart_cpm1.h"
#endif
=20
-#define SERIAL_CPM_MAJOR 204
-#define SERIAL_CPM_MINOR 46
+#ifndef CONFIG_SERIAL_8250
+#define SERIAL_CPM_MAJOR TTY_MAJOR
+#define SERIAL_CPM_MINOR 64
+#else
+#define SERIAL_CPM_MAJOR 204
+#define SERIAL_CPM_MINOR 46
+#endif
=20
#define IS_SMC(pinfo) (pinfo->flags & FLAG_SMC)
#define IS_DISCARDING(pinfo) (pinfo->flags & FLAG_DISCARDING)
diff -urpN linux-2.6.13.2_light/drivers/serial/cpm_uart/Makefile ecrin-2.6.=
13.2_light/drivers/serial/cpm_uart/Makefile
--- linux-2.6.13.2_light/drivers/serial/cpm_uart/Makefile 2005-12-16 12:08:=
48.859091000 +0100
+++ ecrin-2.6.13.2_light/drivers/serial/cpm_uart/Makefile 2005-12-16 11:53:=
13.140613000 +0100
@@ -1,5 +1,5 @@
#
-# Makefile for the Motorola 8xx FEC ethernet controller
+# Makefile for the CPM ethernet controllers
#
=20
obj-$(CONFIG_SERIAL_CPM) +=3D cpm_uart.o
----=20
Nathael PAJANI
Ing=E9nieur CPE Lyon
nathael.pajani@cpe.fr
^ permalink raw reply
* Problem loading modules
From: Nathael Pajani @ 2005-12-19 13:09 UTC (permalink / raw)
To: linuxppc-embedded
Hi!=20
>I'm working with a ml403 board, porting Linux 2.4.devel on it. I got the OS
>running, but I cannot load modules.
>When I try "modprobe /lib/modules/<version>/kernel/net/<module.o>, I obtain
>the error messages:
>Note: /etc/modules.conf is more recent than
>/lib/modules/<version>/modules.dep
>modprobe: Can't locate module lib/modules/<version>/kernel/net/<module.o>
did you try with insmod ?
then try running depmod.
----=20
Nathael PAJANI
Ing=E9nieur CPE Lyon
nathael.pajani@cpe.fr
^ permalink raw reply
* Re: Ramdisk images for test
From: Wolfgang Denk @ 2005-12-19 12:39 UTC (permalink / raw)
To: HappyPhot; +Cc: linuxppc-embedded
In-Reply-To: <000501c6046b$f1abd5a0$0760120a@photon>
In message <000501c6046b$f1abd5a0$0760120a@photon> you wrote:
>
> I followed setion 7.6 of DULG and found got two Ramdisk images
> for test for ppc_82xx. One is pRamdisk, another is ramdisk_image.gz.
> Who can tell what the difference is between them ?
The former is a U-Boot/PPCBoot image, the later one a raw compressed
ramdisk image. They contain the same data, just packaged differently.
Best regards,
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
I'm a programmer: I don't buy software, I write it.
-- Tom Christiansen
^ permalink raw reply
* Re: Unable to open an initial console
From: Addison Baldwin @ 2005-12-19 12:17 UTC (permalink / raw)
To: Vitaly Bordug; +Cc: linuxppc-embedded
In-Reply-To: <43A31EE1.3030101@ru.mvista.com>
Thank you!
I had to create the /dev/ttyCPM0 and had to point /dev/console to it.
Now the console is working fine!
Best Regards,
Addison Baldwin
On 12/16/05, Vitaly Bordug <vbordug@ru.mvista.com> wrote:
> Addison Baldwin wrote:
> > I was sucessful to port U-Boot to our 8272 board. Now I'm experiencing
> > a problem:
> >
> > Our Kernel hangs with the message that says it was trasnferring
> > control to linux. A post morten analyzes indicated that it stopped at
> > "Unable to open an initial console" in the memory sapce where console
> > output should be out (in the sdram, like I had found somewhere in this
> > list, how to do it).
> >
> > I have checked the bootargs values, it is ok:
> > bootargs root=3D/dev/ram console=3DttyS0,115200
> >
> Only for 2.4, 2.6 is different for this.
> console=3DttyCPM0 should be there, and that device does have different ma=
jor/minor comparing to ttyS0.
> Note that the UART has to be enabled explicitly in kernel config, for mor=
e info, search this list archives.
>
> > We also checked our "/dev" and there was a link to console, pointing
> > ttyS0. Also, ttyS0 was there too.
> >
> > Does anyone have any idea how to fix it?
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> >
> >
>
>
> --
> Sincerely,
> Vitaly
>
^ permalink raw reply
* Re: Howto submit drivers/patches ?
From: Vitaly Bordug @ 2005-12-19 10:09 UTC (permalink / raw)
To: David H. Lynch Jr.; +Cc: Andrei Konovalov, linuxppc-embedded
In-Reply-To: <43A64446.8080109@comcast.net>
David H. Lynch Jr. wrote:
> I am just polishing off bringup a Xilinx Virtex IV/ppc405 system with
> minimal hardware under 2.6.14.4.
> I have a collection of patches that I can submit for the specific,
> board, for the Virtex IV, for board specific hardware, ...
> Additionally I have 2 complete boot loader through full serial driver
> implementations of a pseudo serial console driver for this board when it
> is in a HOST development system - it is a compact flash card normally
> plugged into a PC during development and using the PC as the console,
> and a complete serial driver chain for the Xilinx UartLite as a console
> when not in a Host, or as a general serial driver. The Xilinx Driver is
> based heavily on other 2.6 driver/serial drivers and not the 2.4
> implementation from Xilinx.
>
> Is this list the right place to submit this ?
Yes, this is the right place.
> Is there a HOWTO addressing the rules/procedures to do so.
>
Dunno actually, but that is not that tricky. Just send patches here, splitted if
possible to understand better what each one does, don't forget detailed description of a change
and the Signed-off-by: line.
> I have not looked at the kernel style guides, but the style of this
> code is pretty much identical to other Kernel code. The UartLite driver
> is virtually indistinguishable from other driver/serial drivers except
> the few places where hardware differences require changes, and that
> there is a full tree of end-end support similar to what exists for the
> 8250's.
>
> David H. Lynch Jr.
> DLA Systems
> 354 Rudy Dam Rd.
> Lititz, PA 17543
> 717.627.3770
>
>
>
>
>
>
>
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
--
Sincerely,
Vitaly
^ permalink raw reply
* Re: POSIX High Resolution Timers in LinuxPPC 2.4
From: David Jander @ 2005-12-19 9:39 UTC (permalink / raw)
To: linuxppc-embedded; +Cc: Martin, Tim
In-Reply-To: <821B2170E9E7F04FA38DF7EC21DE4871022BB9A9@VCAEXCH01.hq.corp.viasat.com>
Hi Tim,
On Friday 16 December 2005 23:34, Martin, Tim wrote:
> Could someone give me a brief history lesson on POSIX high resolution
> timers (e.g. timer_create() function) implemented in the Linux kernel on
> the PowerPC 405 architecture? Specifically:
>
> Confirm they are in the mainline 2.6 kernel now (e.g. kernel.org)?
>
> Were they ever a part of the "mainline" 2.4 linuxppc kernel (e.g
> ppc.bkbits.net)?
>
> If no, were they ever available as a patch? The stuff at
> sourceforge.net/projects/high-res-timers stops at 2.4.20 and looks like it
> was only ever working for i386, not ppc.
I asked a related question a while back, and got no answer (yet).
I did find this though, which you might have overlooked:
http://prdownloads.sourceforge.net/high-res-timers/ppc-hrt-2.6.10.patch?download
I am equally puzzled about whether this has made it into mainstream, is about
to, or never will. I don't even know if it actually works.
Greetings,
--
David Jander
Protonic Holland.
^ permalink raw reply
* Problem loading modules
From: Paula Saameño @ 2005-12-19 9:25 UTC (permalink / raw)
To: linuxppc-embedded
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Hi all,
First of all, Merry Xmas!!
I'm working with a ml403 board, porting Linux 2.4.devel on it. I got the OS
running, but I cannot load modules.
When I try "modprobe /lib/modules/<version>/kernel/net/<module.o>, I obtain
the error messages:
Note: /etc/modules.conf is more recent than
/lib/modules/<version>/modules.dep
modprobe: Can't locate module lib/modules/<version>/kernel/net/<module.o>
Do you know what is going on?
Thanks!!
Paula Saameno
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^ permalink raw reply
* [PATCH] powerpc: CPM2 interrupt handler failure after 100,000
From: Nathael Pajani @ 2005-12-19 9:00 UTC (permalink / raw)
To: linuxppc-embedded
interrupts
Message-Id: <20051219100059.5a95533f.nathael.pajani@cpe.fr>
X-Mailer: Sylpheed version 2.0.4 (GTK+ 2.8.9; i486-pc-linux-gnu)
Mime-Version: 1.0
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Content-Transfer-Encoding: quoted-printable
Hi!
Hum.. in the patch you moved from "void" to "int":
>-static void cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
>+static int cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
But should'nt it be "irqreturn_t" ?
static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
+++
Have fun :)
----=20
Nathael PAJANI
Ing=E9nieur CPE Lyon
nathael.pajani@cpe.fr
^ permalink raw reply
* RE: SMP on MV64460
From: Sam Song @ 2005-12-19 7:27 UTC (permalink / raw)
To: wilhardt; +Cc: 'Lance Ware', linuxppc-embedded
In-Reply-To: <200512190413.jBJ4D9nd031244@ylpvm01.prodigy.net>
wilhardt@wilhardts.com wrote:
>
> There are a few of examples of SMP using the
> MV64460 from Curtiss Wright,
> but I don't know of a 7447A SMP (you really
> need a backside external cache
> to take advantage of SMP). The CWCEC boards
> support 2.4 or 2.6.
>
>
http://www.cwembedded.com/products/0/2/151.html/
The above linkage is broken to me. With google,
I got some other info as well. I will report
back if some improvement.
Thanks,
Sam
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^ permalink raw reply
* Ramdisk images for test
From: HappyPhot @ 2005-12-19 7:15 UTC (permalink / raw)
To: linuxppc-embedded
Hello,
I am trying to use ramdisk for my board. (not success yet)
I followed setion 7.6 of DULG and found got two Ramdisk images
for test for ppc_82xx. One is pRamdisk, another is ramdisk_image.gz.
Who can tell what the difference is between them ?
thank you,
/HappyPhot
^ permalink raw reply
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