* Re: [PATCH] Document Linux's memory barriers [try #5]
From: Paul E. McKenney @ 2006-03-23 22:26 UTC (permalink / raw)
To: David Howells
Cc: akpm, linux-arch, linux-kernel, torvalds, davem, linuxppc64-dev
In-Reply-To: <895.1143138867@warthog.cambridge.redhat.com>
On Thu, Mar 23, 2006 at 06:34:27PM +0000, David Howells wrote:
> Paul E. McKenney <paulmck@us.ibm.com> wrote:
>
> > smp_mb__before_atomic_dec() and friends as well?
>
> These seem to be something Sparc64 related; or, at least, Sparc64 seems to do
> something weird with them.
>
> What are these meant to achieve anyway? They seems to just be barrier() on a
> lot of systems, even SMP ones.
On architectures such as x86 where atomic_dec() implies an smp_mb(),
they do nothing. On other architectures, they supply whatever memory
barrier is required.
So, on x86:
smp_mb();
atomic_dec(&my_atomic_counter);
would result in -two- atomic instructions, but the smp_mb() would be
absolutely required on CPUs with weaker memory-consistency models.
So your choice is to (1) be inefficient on x86 or (2) be unsafe on
weak-memory-consistency systems. What we can do instead is:
smp_mb__before_atomic_dec();
atomic_dec(&my_atomic_counter);
This allows x86 to generate efficient code -and- allows weak-memory
machines (e.g., Alpha, MIPS, PA-RISC(!), ppc, s390, SPARC64) to generate
safe code.
Thanx, Paul
^ permalink raw reply
* Re: [patch 06/13] powerpc: cell interrupt controller updates
From: Benjamin Herrenschmidt @ 2006-03-23 22:15 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Arnd Bergmann, stk, linux-kernel, Milton Miller, linuxppc-dev,
Paul Mackerras, hpenner, cbe-oss-dev
In-Reply-To: <20060323203521.862355000@dyn-9-152-242-103.boeblingen.de.ibm.com>
On Thu, 2006-03-23 at 00:00 +0100, Arnd Bergmann wrote:
> plain text document attachment (cell-pic-updates-3.diff)
> The current interrupt controller setup on Cell is done
> in a rather ad-hoc way with device tree properties
> that are not standardized at all.
>
> In an attempt to do something that follows the OF standard
> (or at least the IBM extensions to it) more closely,
> we have now come up with this patch. It still provides
> a fallback to the old behaviour when we find older firmware,
> that hack can not be removed until the existing customer
> installations have upgraded.
BTW... You still use __ioremap(...,PAGE_NO_CACHE); which I think won't
give you guarded... I wouldn'd do that if I were you... The accessors
should have barriers but still...
Ben.
^ permalink raw reply
* Re: [PATCH] Add support for 85xx CDS systems in arch/powerpc
From: Kumar Gala @ 2006-03-23 21:49 UTC (permalink / raw)
To: Andy Fleming; +Cc: linuxppc-embedded
In-Reply-To: <Pine.LNX.4.61.0603231523410.17021@ld0175-tx32.am.freescale.net>
On Mar 23, 2006, at 3:26 PM, Andy Fleming wrote:
> * This patch adds code to work on 85xx CDS using the flat device
> tree in
> arch/powerpc
>
> Signed-off-by: Andy Fleming <afleming@freescale.com>
>
> diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/
> platforms/85xx/Kconfig
> index d3d0ff7..6796164 100644
> --- a/arch/powerpc/platforms/85xx/Kconfig
> +++ b/arch/powerpc/platforms/85xx/Kconfig
> @@ -10,13 +10,19 @@ config MPC8540_ADS
> help
> This option enables support for the MPC 8540 ADS board
>
> +config MPC85xx_CDS
> + bool "Freescale MPC85xx CDS"
> + select PPC_I8259
> + help
> + This option enables support for the MPC85xx CDS board
> +
> endchoice
>
> config MPC8540
> bool
> select PPC_UDBG_16550
> select PPC_INDIRECT_PCI
> - default y if MPC8540_ADS
> + default y if MPC8540_ADS || MPC85xx_CDS
>
> config PPC_INDIRECT_PCI_BE
> bool
> @@ -27,4 +33,9 @@ config MPIC
> bool
> default y
>
> +config 85xx_PCI2
> + bool "Support for 2nd PCI"
> + depends on MPC85xx_CDS
> + default y
> +
Remove this. You shouldn't need a kernel config option for PCI2,
look at what 83xx does for 2nd PCI controller.
> endmenu
> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/
> powerpc/platforms/85xx/mpc85xx_cds.c
> new file mode 100644
> index 0000000..b625e8c
> --- /dev/null
> +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
> @@ -0,0 +1,375 @@
> +/*
> + * MPC85xx setup and early boot code plus other random bits.
> + *
> + * Maintained by Kumar Gala (see MAINTAINERS for contact information)
> + *
> + * Copyright 2005 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + */
> +
> +#include <linux/config.h>
> +#include <linux/stddef.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/errno.h>
> +#include <linux/reboot.h>
> +#include <linux/pci.h>
> +#include <linux/kdev_t.h>
> +#include <linux/major.h>
> +#include <linux/console.h>
> +#include <linux/delay.h>
> +#include <linux/seq_file.h>
> +#include <linux/root_dev.h>
> +#include <linux/initrd.h>
> +#include <linux/module.h>
> +#include <linux/fsl_devices.h>
> +
> +#include <asm/system.h>
> +#include <asm/pgtable.h>
> +#include <asm/page.h>
> +#include <asm/atomic.h>
> +#include <asm/time.h>
> +#include <asm/io.h>
> +#include <asm/machdep.h>
> +#include <asm/ipic.h>
> +#include <asm/bootinfo.h>
> +#include <asm/pci-bridge.h>
> +#include <asm/mpc85xx.h>
> +#include <asm/irq.h>
> +#include <mm/mmu_decl.h>
> +#include <asm/prom.h>
> +#include <asm/udbg.h>
> +#include <asm/mpic.h>
> +#include <asm/i8259.h>
> +
> +#include <sysdev/fsl_soc.h>
> +#include "mpc85xx.h"
> +
> +#ifndef CONFIG_PCI
> +unsigned long isa_io_base = 0;
> +unsigned long isa_mem_base = 0;
> +#endif
> +
> +static int cds_pci_slot = 2;
> +static volatile u8 *cadmus;
> +
> +/*
> + * Internal interrupts are all Level Sensitive, and Positive Polarity
> + *
> + * Note: Likely, this table and the following function should be
> + * obtained and derived from the OF Device Tree.
> + */
> +static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
> + MPC85XX_INTERNAL_IRQ_SENSES,
> +#if defined(CONFIG_PCI)
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Ext 0: PCI slot 0 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 1: PCI slot 1 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 2: PCI slot 2 */
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 3: PCI slot 3 */
> +#else
> + 0x0, /* External 0: */
> + 0x0, /* External 1: */
> + 0x0, /* External 2: */
> + 0x0, /* External 3: */
> +#endif
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
> + 0x0, /* External 6: */
> + 0x0, /* External 7: */
> + 0x0, /* External 8: */
> + 0x0, /* External 9: */
> + 0x0, /* External 10: */
> +#if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
> + (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 11: PCI2
> slot 0 */
> +#else
> + 0x0, /* External 11: */
> +#endif
> +};
> +
> +
> +#ifdef CONFIG_PCI
> +/*
> + * interrupt routing
> + */
> +int
> +mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned
> char pin)
> +{
> + struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
> +
> + if (!hose->index)
> + {
> + /* Handle PCI1 interrupts */
> + char pci_irq_table[][4] =
> + /*
> + * PCI IDSEL/INTPIN->INTLINE
> + * A B C D
> + */
> +
> + /* Note IRQ assignment for slots is based on which slot the
> elysium is
> + * in -- in this setup elysium is in slot #2 (this PIRQA as first
> + * interrupt on slot */
> + {
> + { 0, 1, 2, 3 }, /* 16 - PMC */
> + { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
> + { 0, 1, 2, 3 }, /* 18 - Slot 1 */
> + { 1, 2, 3, 0 }, /* 19 - Slot 2 */
> + { 2, 3, 0, 1 }, /* 20 - Slot 3 */
> + { 3, 0, 1, 2 }, /* 21 - Slot 4 */
> + };
> +
> + const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
> + int i, j;
> +
> + for (i = 0; i < 6; i++)
> + for (j = 0; j < 4; j++)
> + pci_irq_table[i][j] =
> + ((pci_irq_table[i][j] + 5 -
> + cds_pci_slot) & 0x3) + PIRQ0A;
> +
> + return PCI_IRQ_TABLE_LOOKUP;
> + } else {
> + /* Handle PCI2 interrupts (if we have one) */
> + char pci_irq_table[][4] =
> + {
> + /*
> + * We only have one slot and one interrupt
> + * going to PIRQA - PIRQD */
> + { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
> + };
> +
> + const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
> +
> + return PCI_IRQ_TABLE_LOOKUP;
> + }
> +}
> +
> +#define ARCADIA_HOST_BRIDGE_IDSEL 17
> +#define ARCADIA_2ND_BRIDGE_IDSEL 3
> +
> +extern int mpc85xx_pci2_busno;
> +
> +int
> +mpc85xx_exclude_device(u_char bus, u_char devfn)
> +{
> + if (bus == 0 && PCI_SLOT(devfn) == 0)
> + return PCIBIOS_DEVICE_NOT_FOUND;
> +#ifdef CONFIG_85xx_PCI2
> + if (mpc85xx_pci2_busno)
> + if (bus == (mpc85xx_pci2_busno) && PCI_SLOT(devfn) == 0)
> + return PCIBIOS_DEVICE_NOT_FOUND;
> +#endif
> + /* We explicitly do not go past the Tundra 320 Bridge */
> + if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
> + return PCIBIOS_DEVICE_NOT_FOUND;
> + if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
> + return PCIBIOS_DEVICE_NOT_FOUND;
> + else
> + return PCIBIOS_SUCCESSFUL;
> +}
> +
> +void __init
> +mpc85xx_cds_pcibios_fixup(void)
> +{
> + struct pci_dev *dev;
> + u_char c;
> +
> + if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
> +
> PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
> + /*
> + * U-Boot does not set the enable bits
> + * for the IDE device. Force them on here.
> + */
> + pci_read_config_byte(dev, 0x40, &c);
> + c |= 0x03; /* IDE: Chip Enable Bits */
> + pci_write_config_byte(dev, 0x40, c);
> +
> + /*
> + * Since only primary interface works, force the
> + * IDE function to standard primary IDE interrupt
> + * w/ 8259 offset
> + */
> + dev->irq = 14;
> + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev-
> >irq);
> + pci_dev_put(dev);
> + }
> +
> + /*
> + * Force legacy USB interrupt routing
> + */
> + if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
> +
> PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
> + dev->irq = 10;
> + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
> + pci_dev_put(dev);
> + }
> +
> + if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
> +
> PCI_DEVICE_ID_VIA_82C586_2, dev))) {
> + dev->irq = 11;
> + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
> + pci_dev_put(dev);
> + }
> +}
> +#endif /* CONFIG_PCI */
Don't we do the fixup in u-boot now?
> +
> +void __init mpc85xx_cds_pic_init(void)
> +{
> + struct mpic *mpic1;
> + phys_addr_t OpenPIC_PAddr;
> +
> + /* Determine the Physical Address of the OpenPIC regs */
> + OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET;
> +
> + mpic1 = mpic_alloc(OpenPIC_PAddr,
> + MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
> + 4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250,
> + mpc85xx_cds_openpic_initsenses,
> + sizeof(mpc85xx_cds_openpic_initsenses), " OpenPIC ");
> + BUG_ON(mpic1 == NULL);
> + mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200);
> + mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280);
> + mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300);
> + mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380);
> + mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400);
> + mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480);
> + mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500);
> + mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580);
> +
> + /* dummy mappings to get to 48 */
> + mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600);
> + mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680);
> + mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700);
> + mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780);
> +
> + /* External ints */
> + mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000);
> + mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080);
> + mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100);
> +
> + mpic_init(mpic1);
> +
> +#ifdef CONFIG_PCI
> + mpic_setup_cascade(PIRQ0A, i8259_irq_cascade, NULL);
> +
> + i8259_init(0,0);
> +#endif
> +}
> +
> +
> +/*
> + * Setup the architecture
> + */
> +static void __init
> +mpc85xx_cds_setup_arch(void)
> +{
> + struct device_node *cpu;
> +#ifdef CONFIG_PCI
> + struct device_node *np;
> +#endif
> +
> + if (ppc_md.progress)
> + ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
> +
> + cpu = of_find_node_by_type(NULL, "cpu");
> + if (cpu != 0) {
> + unsigned int *fp;
> +
> + fp = (int *)get_property(cpu, "clock-frequency", NULL);
> + if (fp != 0)
> + loops_per_jiffy = *fp / HZ;
> + else
> + loops_per_jiffy = 50000000 / HZ;
> + of_node_put(cpu);
> + }
> +
> + cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
> + cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
> +
> + if (ppc_md.progress) {
> + char buf[40];
> + snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
> + cadmus[CM_VER], cds_pci_slot);
> + ppc_md.progress(buf, 0);
> + }
> +
> +#ifdef CONFIG_PCI
> + for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
> + add_bridge(np);
> +
> + ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
I feel like there is a white space issue
> + ppc_md.pci_swizzle = common_swizzle;
> + ppc_md.pci_map_irq = mpc85xx_map_irq;
> + ppc_md.pci_exclude_device = mpc85xx_exclude_device;
> +#endif
> +
> +#ifdef CONFIG_ROOT_NFS
> + ROOT_DEV = Root_NFS;
> +#else
> + ROOT_DEV = Root_HDA1;
> +#endif
> +}
> +
> +
> +void
> +mpc85xx_cds_show_cpuinfo(struct seq_file *m)
> +{
> + uint pvid, svid, phid1;
> + struct device_node *cpu;
> + unsigned int *freq = NULL;
> + uint memsize = total_memory;
> + struct device_node *root = find_path_device("/");
> + char *machine = get_property(root, "model", NULL);
> +
> + cpu = of_find_node_by_type(NULL, "cpu");
> + if (cpu != 0) {
> + freq = (int *)get_property(cpu, "clock-frequency", NULL);
> + of_node_put(cpu);
> + }
> +
> + pvid = mfspr(SPRN_PVR);
> + svid = mfspr(SPRN_SVR);
> +
> + seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
> + seq_printf(m, "Machine\t\t: %s (%x)\n",
> + machine, cadmus[CM_VER]);
> + seq_printf(m, "clock\t\t: %dMHz\n", (freq ? *freq:5000000) /
> 1000000);
> + seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
> + seq_printf(m, "SVR\t\t: 0x%x\n", svid);
> +
> + /* Display cpu Pll setting */
> + phid1 = mfspr(SPRN_HID1);
> + seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
> +
> + /* Display the amount of memory */
> + seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
> +}
What does cat /proc/cpuinfo show now?
> +
> +
> +void __init
> +platform_init(void)
> +{
> + ppc_md.setup_arch = mpc85xx_cds_setup_arch;
> + ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
> +
> + ppc_md.init_IRQ = mpc85xx_cds_pic_init;
> + ppc_md.get_irq = mpic_get_irq;
> +
> + ppc_md.restart = mpc85xx_restart;
> + ppc_md.power_off = NULL;
> + ppc_md.halt = NULL;
> +
> + ppc_md.time_init = NULL;
> + ppc_md.set_rtc_time = NULL;
> + ppc_md.get_rtc_time = NULL;
> + ppc_md.calibrate_decr = generic_calibrate_decr;
> +
> + ppc_md.progress = udbg_progress;
> +
> + if (ppc_md.progress)
> + ppc_md.progress("mpc85xx_cds platform_init(): exit", 0);
> +}
> +
> +
> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.h b/arch/
> powerpc/platforms/85xx/mpc85xx_cds.h
> new file mode 100644
> index 0000000..68d8913
> --- /dev/null
> +++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.h
> @@ -0,0 +1,43 @@
> +/*
> + * arch/ppc/platforms/85xx/mpc85xx_cds_common.h
> + *
> + * MPC85xx CDS board definitions
> + *
> + * Maintainer: Kumar Gala <galak@kernel.crashing.org>
> + *
> + * Copyright 2004 Freescale Semiconductor, Inc
> + *
> + * This program is free software; you can redistribute it and/or
> modify it
> + * under the terms of the GNU General Public License as
> published by the
> + * Free Software Foundation; either version 2 of the License, or
> (at your
> + * option) any later version.
> + *
> + */
> +
> +#ifndef __MACH_MPC85XX_CDS_H__
> +#define __MACH_MPC85XX_CDS_H__
> +
> +/* CADMUS info */
> +#define CADMUS_BASE (0xf8004000)
> +#define CADMUS_SIZE (256)
> +#define CM_VER (0)
> +#define CM_CSR (1)
> +#define CM_RST (2)
> +
> +/* CDS NVRAM/RTC */
> +#define CDS_RTC_ADDR (0xf8000000)
> +#define CDS_RTC_SIZE (8 * 1024)
> +
> +/* PCI interrupt controller */
> +#define PIRQ0A MPC85xx_IRQ_EXT0
> +#define PIRQ0B MPC85xx_IRQ_EXT1
> +#define PIRQ0C MPC85xx_IRQ_EXT2
> +#define PIRQ0D MPC85xx_IRQ_EXT3
> +#define PIRQ1A MPC85xx_IRQ_EXT11
> +
> +#define NR_8259_INTS 80
Uugh, why is NR_8259_INTS set to 80?
> +#define CPM_IRQ_OFFSET NR_8259_INTS
> +
> +#define MPC85xx_OPENPIC_IRQ_OFFSET NR_8259_INTS
> +
> +#endif /* __MACH_MPC85XX_CDS_H__ */
> diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
> index c8a96aa..93c889a 100644
> --- a/include/asm-ppc/mpc85xx.h
> +++ b/include/asm-ppc/mpc85xx.h
> @@ -28,6 +28,9 @@
> #if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
> #include <platforms/85xx/mpc8555_cds.h>
> #endif
> +#ifdef CONFIG_MPC85xx_CDS
> +#include <platforms/85xx/mpc85xx_cds.h>
> +#endif
> #ifdef CONFIG_MPC8560_ADS
> #include <platforms/85xx/mpc8560_ads.h>
> #endif
^ permalink raw reply
* Re: [patch 02/13] powerpc: add hvc backend for rtas
From: Olof Johansson @ 2006-03-23 21:32 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Arnd Bergmann, linuxppc-dev, Paul Mackerras, cbe-oss-dev,
linux-kernel
In-Reply-To: <20060323203521.100452000@dyn-9-152-242-103.boeblingen.de.ibm.com>
Hi,
I have a couple of nitpicks below, nothing major.
Since it's such a simple driver, it's easy to use as a base for similar
ones, and as such it'd be nice to have it as clean as possible to avoid
others to inherit strangeness.
-Olof
On Thu, Mar 23, 2006 at 12:00:02AM +0100, Arnd Bergmann wrote:
> +static inline int hvc_rtas_write_console(uint32_t vtermno, const char *buf, int count)
> +{
> + int done;
> +
> + /* if there is more than one character to be displayed, wait a bit */
> + for (done = 0; done < count; done++) {
> + int result;
> + result = rtas_call(rtascons_put_char_token, 1, 1, NULL, buf[done]);
> + if (result)
> + break;
Why introduce a scope-local variable just to check it?
if(rtas_call(...)) would be cleaner.
> + }
> + /* the calling routine expects to receive the number of bytes sent */
> + return done;
> +}
> +
> +static int hvc_rtas_read_console(uint32_t vtermno, char *buf, int count)
> +{
> + int i;
> +
> + for (i = 0; i < count; i++) {
> + int c, err;
> +
> + err = rtas_call(rtascons_get_char_token, 0, 2, &c);
> + if (err)
> + break;
Same here
> +
> + buf[i] = c;
> + }
> +
> + return i;
> +}
> +
> +static struct hv_ops hvc_rtas_get_put_ops = {
> + .get_chars = hvc_rtas_read_console,
> + .put_chars = hvc_rtas_write_console,
> +};
> +
> +static int hvc_rtas_init(void)
> +{
> + struct hvc_struct *hp;
> +
> + if (rtascons_put_char_token == RTAS_UNKNOWN_SERVICE)
> + rtascons_put_char_token = rtas_token("put-term-char");
> + if (rtascons_put_char_token == RTAS_UNKNOWN_SERVICE)
> + return -EIO;
> +
> + if (rtascons_get_char_token == RTAS_UNKNOWN_SERVICE)
> + rtascons_get_char_token = rtas_token("get-term-char");
> + if (rtascons_get_char_token == RTAS_UNKNOWN_SERVICE)
> + return -EIO;
> +
> + BUG_ON(hvc_rtas_dev);
> +
> + /* Allocate an hvc_struct for the console device we instantiated
> + * earlier. Save off hp so that we can return it on exit */
> + hp = hvc_alloc(hvc_rtas_cookie, NO_IRQ, &hvc_rtas_get_put_ops);
> + if (IS_ERR(hp))
> + return PTR_ERR(hp);
> + hvc_rtas_dev = hp;
> + return 0;
> +}
> +module_init(hvc_rtas_init);
> +
> +/* This will tear down the tty portion of the driver */
> +static void __exit hvc_rtas_exit(void)
> +{
> + /* Really the fun isn't over until the worker thread breaks down and the
> + * tty cleans up */
> + if (hvc_rtas_dev)
> + hvc_remove(hvc_rtas_dev);
> +}
> +module_exit(hvc_rtas_exit); /* before drivers/char/hvc_console.c */
Cryptic comment?
> +/* This will happen prior to module init. There is no tty at this time? */
> +static int hvc_rtas_console_init(void)
> +{
> + rtascons_put_char_token = rtas_token("put-term-char");
> + if (rtascons_put_char_token == RTAS_UNKNOWN_SERVICE)
> + return -EIO;
> + rtascons_get_char_token = rtas_token("get-term-char");
> + if (rtascons_get_char_token == RTAS_UNKNOWN_SERVICE)
> + return -EIO;
> +
> + hvc_instantiate(hvc_rtas_cookie, 0, &hvc_rtas_get_put_ops );
> + add_preferred_console("hvc", 0, NULL);
> + return 0;
> +}
> +console_initcall(hvc_rtas_console_init);
> Index: linus-2.6/drivers/char/Makefile
> ===================================================================
> --- linus-2.6.orig/drivers/char/Makefile
> +++ linus-2.6/drivers/char/Makefile
> @@ -43,6 +43,7 @@ obj-$(CONFIG_SX) += sx.o generic_serial
> obj-$(CONFIG_RIO) += rio/ generic_serial.o
> obj-$(CONFIG_HVC_DRIVER) += hvc_console.o
> obj-$(CONFIG_HVC_CONSOLE) += hvc_vio.o hvsi.o
> +obj-$(CONFIG_HVC_RTAS) += hvc_rtas.o
> obj-$(CONFIG_RAW_DRIVER) += raw.o
> obj-$(CONFIG_SGI_SNSC) += snsc.o snsc_event.o
> obj-$(CONFIG_MMTIMER) += mmtimer.o
> Index: linus-2.6/drivers/char/Kconfig
> ===================================================================
> --- linus-2.6.orig/drivers/char/Kconfig
> +++ linus-2.6/drivers/char/Kconfig
> @@ -578,6 +578,13 @@ config HVC_CONSOLE
> console. This driver allows each pSeries partition to have a console
> which is accessed via the HMC.
>
> +config HVC_RTAS
> + bool "IBM RTAS Console support"
> + depends on PPC_RTAS
> + select HVC_DRIVER
> + help
> + IBM Console device driver which makes use of RTAS
> +
> config HVCS
> tristate "IBM Hypervisor Virtual Console Server support"
> depends on PPC_PSERIES
>
> --
>
> -
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
^ permalink raw reply
* [PATCH] Add support for 85xx CDS systems in arch/powerpc
From: Andy Fleming @ 2006-03-23 21:26 UTC (permalink / raw)
To: linuxppc-embedded
* This patch adds code to work on 85xx CDS using the flat device tree in
arch/powerpc
Signed-off-by: Andy Fleming <afleming@freescale.com>
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index d3d0ff7..6796164 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -10,13 +10,19 @@ config MPC8540_ADS
help
This option enables support for the MPC 8540 ADS board
+config MPC85xx_CDS
+ bool "Freescale MPC85xx CDS"
+ select PPC_I8259
+ help
+ This option enables support for the MPC85xx CDS board
+
endchoice
config MPC8540
bool
select PPC_UDBG_16550
select PPC_INDIRECT_PCI
- default y if MPC8540_ADS
+ default y if MPC8540_ADS || MPC85xx_CDS
config PPC_INDIRECT_PCI_BE
bool
@@ -27,4 +33,9 @@ config MPIC
bool
default y
+config 85xx_PCI2
+ bool "Support for 2nd PCI"
+ depends on MPC85xx_CDS
+ default y
+
endmenu
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
new file mode 100644
index 0000000..b625e8c
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -0,0 +1,375 @@
+/*
+ * MPC85xx setup and early boot code plus other random bits.
+ *
+ * Maintained by Kumar Gala (see MAINTAINERS for contact information)
+ *
+ * Copyright 2005 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/initrd.h>
+#include <linux/module.h>
+#include <linux/fsl_devices.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/atomic.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ipic.h>
+#include <asm/bootinfo.h>
+#include <asm/pci-bridge.h>
+#include <asm/mpc85xx.h>
+#include <asm/irq.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+#include <asm/i8259.h>
+
+#include <sysdev/fsl_soc.h>
+#include "mpc85xx.h"
+
+#ifndef CONFIG_PCI
+unsigned long isa_io_base = 0;
+unsigned long isa_mem_base = 0;
+#endif
+
+static int cds_pci_slot = 2;
+static volatile u8 *cadmus;
+
+/*
+ * Internal interrupts are all Level Sensitive, and Positive Polarity
+ *
+ * Note: Likely, this table and the following function should be
+ * obtained and derived from the OF Device Tree.
+ */
+static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
+ MPC85XX_INTERNAL_IRQ_SENSES,
+#if defined(CONFIG_PCI)
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Ext 0: PCI slot 0 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 1: PCI slot 1 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 2: PCI slot 2 */
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 3: PCI slot 3 */
+#else
+ 0x0, /* External 0: */
+ 0x0, /* External 1: */
+ 0x0, /* External 2: */
+ 0x0, /* External 3: */
+#endif
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
+ 0x0, /* External 6: */
+ 0x0, /* External 7: */
+ 0x0, /* External 8: */
+ 0x0, /* External 9: */
+ 0x0, /* External 10: */
+#if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
+ (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 11: PCI2 slot 0 */
+#else
+ 0x0, /* External 11: */
+#endif
+};
+
+
+#ifdef CONFIG_PCI
+/*
+ * interrupt routing
+ */
+int
+mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
+{
+ struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
+
+ if (!hose->index)
+ {
+ /* Handle PCI1 interrupts */
+ char pci_irq_table[][4] =
+ /*
+ * PCI IDSEL/INTPIN->INTLINE
+ * A B C D
+ */
+
+ /* Note IRQ assignment for slots is based on which slot the elysium is
+ * in -- in this setup elysium is in slot #2 (this PIRQA as first
+ * interrupt on slot */
+ {
+ { 0, 1, 2, 3 }, /* 16 - PMC */
+ { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
+ { 0, 1, 2, 3 }, /* 18 - Slot 1 */
+ { 1, 2, 3, 0 }, /* 19 - Slot 2 */
+ { 2, 3, 0, 1 }, /* 20 - Slot 3 */
+ { 3, 0, 1, 2 }, /* 21 - Slot 4 */
+ };
+
+ const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
+ int i, j;
+
+ for (i = 0; i < 6; i++)
+ for (j = 0; j < 4; j++)
+ pci_irq_table[i][j] =
+ ((pci_irq_table[i][j] + 5 -
+ cds_pci_slot) & 0x3) + PIRQ0A;
+
+ return PCI_IRQ_TABLE_LOOKUP;
+ } else {
+ /* Handle PCI2 interrupts (if we have one) */
+ char pci_irq_table[][4] =
+ {
+ /*
+ * We only have one slot and one interrupt
+ * going to PIRQA - PIRQD */
+ { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
+ };
+
+ const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
+
+ return PCI_IRQ_TABLE_LOOKUP;
+ }
+}
+
+#define ARCADIA_HOST_BRIDGE_IDSEL 17
+#define ARCADIA_2ND_BRIDGE_IDSEL 3
+
+extern int mpc85xx_pci2_busno;
+
+int
+mpc85xx_exclude_device(u_char bus, u_char devfn)
+{
+ if (bus == 0 && PCI_SLOT(devfn) == 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+#ifdef CONFIG_85xx_PCI2
+ if (mpc85xx_pci2_busno)
+ if (bus == (mpc85xx_pci2_busno) && PCI_SLOT(devfn) == 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+#endif
+ /* We explicitly do not go past the Tundra 320 Bridge */
+ if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ else
+ return PCIBIOS_SUCCESSFUL;
+}
+
+void __init
+mpc85xx_cds_pcibios_fixup(void)
+{
+ struct pci_dev *dev;
+ u_char c;
+
+ if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
+ /*
+ * U-Boot does not set the enable bits
+ * for the IDE device. Force them on here.
+ */
+ pci_read_config_byte(dev, 0x40, &c);
+ c |= 0x03; /* IDE: Chip Enable Bits */
+ pci_write_config_byte(dev, 0x40, c);
+
+ /*
+ * Since only primary interface works, force the
+ * IDE function to standard primary IDE interrupt
+ * w/ 8259 offset
+ */
+ dev->irq = 14;
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+ pci_dev_put(dev);
+ }
+
+ /*
+ * Force legacy USB interrupt routing
+ */
+ if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
+ dev->irq = 10;
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
+ pci_dev_put(dev);
+ }
+
+ if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_82C586_2, dev))) {
+ dev->irq = 11;
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
+ pci_dev_put(dev);
+ }
+}
+#endif /* CONFIG_PCI */
+
+void __init mpc85xx_cds_pic_init(void)
+{
+ struct mpic *mpic1;
+ phys_addr_t OpenPIC_PAddr;
+
+ /* Determine the Physical Address of the OpenPIC regs */
+ OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET;
+
+ mpic1 = mpic_alloc(OpenPIC_PAddr,
+ MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+ 4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250,
+ mpc85xx_cds_openpic_initsenses,
+ sizeof(mpc85xx_cds_openpic_initsenses), " OpenPIC ");
+ BUG_ON(mpic1 == NULL);
+ mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200);
+ mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280);
+ mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300);
+ mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380);
+ mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400);
+ mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480);
+ mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500);
+ mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580);
+
+ /* dummy mappings to get to 48 */
+ mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600);
+ mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680);
+ mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700);
+ mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780);
+
+ /* External ints */
+ mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000);
+ mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080);
+ mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100);
+
+ mpic_init(mpic1);
+
+#ifdef CONFIG_PCI
+ mpic_setup_cascade(PIRQ0A, i8259_irq_cascade, NULL);
+
+ i8259_init(0,0);
+#endif
+}
+
+
+/*
+ * Setup the architecture
+ */
+static void __init
+mpc85xx_cds_setup_arch(void)
+{
+ struct device_node *cpu;
+#ifdef CONFIG_PCI
+ struct device_node *np;
+#endif
+
+ if (ppc_md.progress)
+ ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
+
+ cpu = of_find_node_by_type(NULL, "cpu");
+ if (cpu != 0) {
+ unsigned int *fp;
+
+ fp = (int *)get_property(cpu, "clock-frequency", NULL);
+ if (fp != 0)
+ loops_per_jiffy = *fp / HZ;
+ else
+ loops_per_jiffy = 50000000 / HZ;
+ of_node_put(cpu);
+ }
+
+ cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
+ cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
+
+ if (ppc_md.progress) {
+ char buf[40];
+ snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
+ cadmus[CM_VER], cds_pci_slot);
+ ppc_md.progress(buf, 0);
+ }
+
+#ifdef CONFIG_PCI
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+ add_bridge(np);
+
+ ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_map_irq = mpc85xx_map_irq;
+ ppc_md.pci_exclude_device = mpc85xx_exclude_device;
+#endif
+
+#ifdef CONFIG_ROOT_NFS
+ ROOT_DEV = Root_NFS;
+#else
+ ROOT_DEV = Root_HDA1;
+#endif
+}
+
+
+void
+mpc85xx_cds_show_cpuinfo(struct seq_file *m)
+{
+ uint pvid, svid, phid1;
+ struct device_node *cpu;
+ unsigned int *freq = NULL;
+ uint memsize = total_memory;
+ struct device_node *root = find_path_device("/");
+ char *machine = get_property(root, "model", NULL);
+
+ cpu = of_find_node_by_type(NULL, "cpu");
+ if (cpu != 0) {
+ freq = (int *)get_property(cpu, "clock-frequency", NULL);
+ of_node_put(cpu);
+ }
+
+ pvid = mfspr(SPRN_PVR);
+ svid = mfspr(SPRN_SVR);
+
+ seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
+ seq_printf(m, "Machine\t\t: %s (%x)\n",
+ machine, cadmus[CM_VER]);
+ seq_printf(m, "clock\t\t: %dMHz\n", (freq ? *freq:5000000) / 1000000);
+ seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
+ seq_printf(m, "SVR\t\t: 0x%x\n", svid);
+
+ /* Display cpu Pll setting */
+ phid1 = mfspr(SPRN_HID1);
+ seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
+
+ /* Display the amount of memory */
+ seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
+}
+
+
+void __init
+platform_init(void)
+{
+ ppc_md.setup_arch = mpc85xx_cds_setup_arch;
+ ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
+
+ ppc_md.init_IRQ = mpc85xx_cds_pic_init;
+ ppc_md.get_irq = mpic_get_irq;
+
+ ppc_md.restart = mpc85xx_restart;
+ ppc_md.power_off = NULL;
+ ppc_md.halt = NULL;
+
+ ppc_md.time_init = NULL;
+ ppc_md.set_rtc_time = NULL;
+ ppc_md.get_rtc_time = NULL;
+ ppc_md.calibrate_decr = generic_calibrate_decr;
+
+ ppc_md.progress = udbg_progress;
+
+ if (ppc_md.progress)
+ ppc_md.progress("mpc85xx_cds platform_init(): exit", 0);
+}
+
+
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.h b/arch/powerpc/platforms/85xx/mpc85xx_cds.h
new file mode 100644
index 0000000..68d8913
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.h
@@ -0,0 +1,43 @@
+/*
+ * arch/ppc/platforms/85xx/mpc85xx_cds_common.h
+ *
+ * MPC85xx CDS board definitions
+ *
+ * Maintainer: Kumar Gala <galak@kernel.crashing.org>
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MACH_MPC85XX_CDS_H__
+#define __MACH_MPC85XX_CDS_H__
+
+/* CADMUS info */
+#define CADMUS_BASE (0xf8004000)
+#define CADMUS_SIZE (256)
+#define CM_VER (0)
+#define CM_CSR (1)
+#define CM_RST (2)
+
+/* CDS NVRAM/RTC */
+#define CDS_RTC_ADDR (0xf8000000)
+#define CDS_RTC_SIZE (8 * 1024)
+
+/* PCI interrupt controller */
+#define PIRQ0A MPC85xx_IRQ_EXT0
+#define PIRQ0B MPC85xx_IRQ_EXT1
+#define PIRQ0C MPC85xx_IRQ_EXT2
+#define PIRQ0D MPC85xx_IRQ_EXT3
+#define PIRQ1A MPC85xx_IRQ_EXT11
+
+#define NR_8259_INTS 80
+#define CPM_IRQ_OFFSET NR_8259_INTS
+
+#define MPC85xx_OPENPIC_IRQ_OFFSET NR_8259_INTS
+
+#endif /* __MACH_MPC85XX_CDS_H__ */
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
index c8a96aa..93c889a 100644
--- a/include/asm-ppc/mpc85xx.h
+++ b/include/asm-ppc/mpc85xx.h
@@ -28,6 +28,9 @@
#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
#include <platforms/85xx/mpc8555_cds.h>
#endif
+#ifdef CONFIG_MPC85xx_CDS
+#include <platforms/85xx/mpc85xx_cds.h>
+#endif
#ifdef CONFIG_MPC8560_ADS
#include <platforms/85xx/mpc8560_ads.h>
#endif
^ permalink raw reply related
* Re: new sound driver
From: Benjamin Herrenschmidt @ 2006-03-23 21:09 UTC (permalink / raw)
To: Johannes Berg; +Cc: linuxppc-dev, Alastair Poole
In-Reply-To: <1143134017.8395.19.camel@localhost>
> What I'm currently thinking of is creating one PCM per codec, and then
> if you can't use them at the same time just forbid access to it.
No, it should really be one PCM per bus... I don't see why you would
prevent somebody from outputing on both digital and analog outputs at
the same time for example (the same data of course). One PCM = one
stream = one bus carrying the samples. All codecs on that bus whould be
set to the same settings of course. If one can't but the other can, just
mute the one that can't I suppose...
Also, Alsa does have some means of asynchronous notifyication of a state
change on a control (and calls you back later with some locking) though
I'm not too familiar with the details. You should ask on the list once
you have the basic dbdma stuff there :)
> > Just sleep on it for now :) We definitely need a "core" module that
> > handles all of the gpio mess. ..
>
> Yeah. Haven't even opened that can of worms yet...
>
> johannes
^ permalink raw reply
* Re: [PATCH] return to OF via trap, not exit
From: Olaf Hering @ 2006-03-23 21:03 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: Michael Ellerman, linuxppc-dev
In-Reply-To: <EA07A673-A993-490A-ADEC-29CFDF1DDAC1@kernel.crashing.org>
On Mon, Mar 06, Segher Boessenkool wrote:
> That's better than always calling trap, sure. Is there any reason
> you can't just do it on Macs though? Because the problem you're trying
> to work around only happens there.
Maybe something like this? Only compile tested
Do not call prom exit prom_panic. It clears the screen and the exit message is lost.
On some (or all?) pmacs it causes another crash when OF tries to print the
date and time in its banner.
Set of_platform earlier to catch more prom_panic() calls.
Signed-off-by: Olaf Hering <olh@suse.de>
arch/powerpc/kernel/prom_init.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
Index: linux-2.6.16-olh/arch/powerpc/kernel/prom_init.c
===================================================================
--- linux-2.6.16-olh.orig/arch/powerpc/kernel/prom_init.c
+++ linux-2.6.16-olh/arch/powerpc/kernel/prom_init.c
@@ -397,6 +397,11 @@ static void __init __attribute__((noretu
reason = PTRRELOC(reason);
#endif
prom_print(reason);
+ /* Do not call exit because it clears the screen on pmac
+ * it also causes some sort of double-fault on early pmacs */
+ if (RELOC(of_platform) == PLATFORM_POWERMAC)
+ asm("trap\n");
+
/* ToDo: should put up an SRC here on p/iSeries */
call_prom("exit", 0, 0);
@@ -2060,15 +2065,6 @@ unsigned long __init prom_init(unsigned
*/
prom_init_stdout();
- /* Bail if this is a kdump kernel. */
- if (PHYSICAL_START > 0)
- prom_panic("Error: You can't boot a kdump kernel from OF!\n");
-
- /*
- * Check for an initrd
- */
- prom_check_initrd(r3, r4);
-
/*
* Get default machine type. At this point, we do not differentiate
* between pSeries SMP and pSeries LPAR
@@ -2078,6 +2074,15 @@ unsigned long __init prom_init(unsigned
prom_setprop(_prom->chosen, "/chosen", "linux,platform",
&getprop_rval, sizeof(getprop_rval));
+ /* Bail if this is a kdump kernel. */
+ if (PHYSICAL_START > 0)
+ prom_panic("Error: You can't boot a kdump kernel from OF!\n");
+
+ /*
+ * Check for an initrd
+ */
+ prom_check_initrd(r3, r4);
+
#ifdef CONFIG_PPC_PSERIES
/*
* On pSeries, inform the firmware about our capabilities
^ permalink raw reply
* [patch 00/13] Cell kernel updates
From: Arnd Bergmann @ 2006-03-23 20:34 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, cbe-oss-dev, linux-kernel
Sorry for having delayed these patches so long. This should
bring the mainline kernel up-to-date with the experimental
stuff that is hosted on bsc.es. It should apply on today's
git tree and with trivial modifications also works on 2.6.16,
for those that are interested.
Apart from a number of bug fixes, the important parts in here
are:
- the hvc console driver for rtas
- spufs support for doing syscalls from an spu
- host-initiated DMA though spufs
- option to map SPU control registers into user space
Paulus, please apply and forward as appropriate.
Arnd <><
--
^ permalink raw reply
* Re: Memory mapping PCI memory region to user space
From: David Hawkins @ 2006-03-23 20:26 UTC (permalink / raw)
To: Mark Chambers; +Cc: Linuxppc-Embedded ((E-Mail))
In-Reply-To: <00c701c64eb3$c23b0c40$6401a8c0@CHUCK2>
Hi Mark,
> Ok, I should be a little more specific.
Ok :)
> Yes, I/O space is little endian, and any configuration
> registers and such are little endian. But memory space
> is strictly 32 bit as far as PCI is concerned.
> (forgetting 64 bit PCI for the moment) The two lower
> bits of address are not used, and there is no required
> correlation of byte enables to those missing address bits.
>
> So, the point is, Freescale swaps bytes between its internal
> bus and PCI. Other processors (like TI DSPs) do not. I
> don't know that one method is necessarily right, but the fact
> that we have this discussion periodically suggests that Freescale's
> method is not the best.
Hmm, I'd have to look on the PCI bus with the analyzer to
confirm this ... but I do recall seeing a mapping of
the 128-bit PLB to PCI bus in the 440EP manual, so
you're probably right.
The PLX PCI-9054 has an 'endianness' option like this too.
I believe its so you can use a PPC on the local bus, and
swap bytes when the are written onto the PCI bus.
Sounds like the Freescale SoC bridges have just hardcoded
that type of implementation.
> This might be an academic point, but I think it does help to
> see the distinction. To talk to a device over PCI you must
> know how both ends map their internal buss(es) to PCI,
> and it's not directly a big/little endian issue.
Its nice to be aware of these subtle differences.
Thanks for the discussion.
Dave
^ permalink raw reply
* Re: [PATCH] kdump: Fix for machine checkstop on DMA fault
From: Olof Johansson @ 2006-03-23 20:12 UTC (permalink / raw)
To: Olof Johansson
Cc: Milton Miller, Michael Ellerman, linuxppc-dev, Paul Mackerras,
Olaf Hering, ellerman
In-Reply-To: <20060323061904.GA22439@pb15.lixom.net>
On Thu, Mar 23, 2006 at 12:19:04AM -0600, Olof Johansson wrote:
> The crash kernel needs to be even more careful, and instead read out
> the entries that are mapped and reserve them. This would require a bit
> more plumbing since there's no way to read an entry right now, but it'd
> remove that hole.
Actually, what's probably easier is to allocate some entries when the
purgatory is set up, and make the crash kernel only use those by modifying
the device tree accordingly. Sort of how regular memory is handled right
now. That'd be a cleaner solution with less changes needed.
The trick will be to get a decent size contiguous allocation, but the
same applies for the memory reserve.
-Olof
^ permalink raw reply
* [PATCH] Document Linux's memory barriers [try #6]
From: David Howells @ 2006-03-23 20:01 UTC (permalink / raw)
To: torvalds, akpm; +Cc: linux-arch, linuxppc64-dev, linux-kernel
The attached patch documents the Linux kernel's memory barriers.
I've updated it from the comments I've been given.
The per-arch notes sections are gone because it's clear that there are so many
exceptions, that it's not worth having them.
I've added a list of references to other documents.
I've tried to get rid of the concept of memory accesses appearing on the bus;
what matters is apparent behaviour with respect to other observers in the
system.
Interrupts barrier effects are now considered to be non-existent. They may be
there, but you may not rely on them.
I've added a couple of definition sections at the top of the document: one to
specify the minimum execution model that may be assumed, the other to specify
what this document refers to by the term "memory".
I've made greater mention of the use of mmiowb().
I've adjusted the way in which caches are described, and described the fun
that can be had with cache coherence maintenance being unordered and data
dependency not being necessarily implicit.
I've described (smp_)read_barrier_depends().
I've rearranged the order of the sections, so that memory barriers are
discussed in abstract first, and then described the memory barrier facilities
available on Linux, before going on to more real-world discussions and examples.
I've added information about the lack of memory barriering effects with atomic
ops and bitops.
I've added information about control dependencies.
Signed-Off-By: David Howells <dhowells@redhat.com>
---
warthog>diffstat -p1 /tmp/mb.diff
Documentation/memory-barriers.txt | 1639 ++++++++++++++++++++++++++++++++++++++
1 files changed, 1639 insertions(+)
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
new file mode 100644
index 0000000..caa2781
--- /dev/null
+++ b/Documentation/memory-barriers.txt
@@ -0,0 +1,1639 @@
+ ============================
+ LINUX KERNEL MEMORY BARRIERS
+ ============================
+
+Contents:
+
+ (*) Abstract memory access model.
+
+ - Device operations.
+ - Guarantees.
+
+ (*) What are memory barriers?
+
+ - Varieties of memory barrier.
+ - What can't be assumed about memory barriers?
+ - Data dependency barriers.
+ - Control dependencies.
+ - SMP barrier pairing.
+
+ (*) Explicit kernel barriers.
+
+ - Compiler barrier.
+ - The CPU memory barriers.
+ - MMIO write barrier.
+
+ (*) Implicit kernel memory barriers.
+
+ - Locking functions.
+ - Interrupt disabling functions.
+ - Miscellaneous functions.
+
+ (*) Inter-CPU locking barrier effects.
+
+ - Locks vs memory accesses.
+ - Locks vs I/O accesses.
+
+ (*) Where are memory barriers needed?
+
+ - Interprocessor interaction.
+ - Atomic operations.
+ - Accessing devices.
+ - Interrupts.
+
+ (*) Kernel I/O barrier effects.
+
+ (*) Assumed minimum execution ordering model.
+
+ (*) The effects of the cpu cache.
+
+ - Cache coherency.
+ - Cache coherency vs DMA.
+ - Cache coherency vs MMIO.
+
+ (*) The things CPUs get up to.
+
+ - And then there's the Alpha.
+
+ (*) References.
+
+
+============================
+ABSTRACT MEMORY ACCESS MODEL
+============================
+
+Consider the following abstract model of the system:
+
+ : :
+ : :
+ : :
+ +-------+ : +--------+ : +-------+
+ | | : | | : | |
+ | | : | | : | |
+ | CPU 1 |<----->| Memory |<----->| CPU 2 |
+ | | : | | : | |
+ | | : | | : | |
+ +-------+ : +--------+ : +-------+
+ ^ : ^ : ^
+ | : | : |
+ | : | : |
+ | : v : |
+ | : +--------+ : |
+ | : | | : |
+ | : | | : |
+ +---------->| Device |<----------+
+ : | | :
+ : | | :
+ : +--------+ :
+ : :
+
+Each CPU executes a program that generates memory access operations. In the
+abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
+perform the memory operations in any order it likes, provided program causality
+appears to be maintained. Similarly, the compiler may also arrange the
+instructions it emits in any order it likes, provided it doesn't affect the
+apparent operation of the program.
+
+So in the above diagram, the effects of the memory operations performed by a
+CPU are perceived by the rest of the system as the operations cross the
+interface between the CPU and rest of the system (the dotted lines).
+
+
+For example, consider the following sequence of events:
+
+ CPU 1 CPU 2
+ =============== ===============
+ { A == 1; B == 2 }
+ A = 3; x = A;
+ B = 4; y = B;
+
+The set of accesses as seen by the memory system in the middle can be arranged
+in 24 different combinations:
+
+ STORE A=3, STORE B=4, x=LOAD A->3, y=LOAD B->4
+ STORE A=3, STORE B=4, y=LOAD B->4, x=LOAD A->3
+ STORE A=3, x=LOAD A->3, STORE B=4, y=LOAD B->4
+ STORE A=3, x=LOAD A->3, y=LOAD B->2, STORE B=4
+ STORE A=3, y=LOAD B->2, STORE B=4, x=LOAD A->3
+ STORE A=3, y=LOAD B->2, x=LOAD A->3, STORE B=4
+ STORE B=4, STORE A=3, x=LOAD A->3, y=LOAD B->4
+ STORE B=4, ...
+ ...
+
+and can thus result in four different combinations of values:
+
+ x == 1, y == 2
+ x == 1, y == 4
+ x == 3, y == 2
+ x == 3, y == 4
+
+
+Furthermore, the stores committed by a CPU to the memory system may not be
+perceived by the loads made by another CPU in the same order as the stores were
+committed.
+
+
+As a further example, consider this sequence of events:
+
+ CPU 1 CPU 2
+ =============== ===============
+ { A == 1, B == 2, C = 3, P == &A, Q == &C }
+ B = 4; Q = P;
+ P = &B D = *Q;
+
+There is an obvious data dependency here, as the value loaded into D depends on
+the address retrieved from P by CPU 2. At the end of the sequence, any of the
+following results are possible:
+
+ (Q == &A) and (D == 1)
+ (Q == &B) and (D == 2)
+ (Q == &B) and (D == 4)
+
+Note that CPU 2 will never try and load C into D because the CPU will load P
+into Q before issuing the load of *Q.
+
+
+DEVICE OPERATIONS
+-----------------
+
+Some devices present their control interfaces as collections of memory
+locations, but the order in which the control registers are accessed is very
+important. For instance, imagine an ethernet card with a set of internal
+registers that are accessed through an address port register (A) and a data
+port register (D). To read internal register 5, the following code might then
+be used:
+
+ *A = 5;
+ x = *D;
+
+but this might show up as either of the following two sequences:
+
+ STORE *A = 5, x = LOAD *D
+ x = LOAD *D, STORE *A = 5
+
+the second of which will almost certainly result in a malfunction, since it set
+the address _after_ attempting to read the register.
+
+
+GUARANTEES
+----------
+
+There are some minimal guarantees that may be expected of a CPU:
+
+ (*) On any given CPU, dependent memory accesses will be issued in order, with
+ respect to itself. This means that for:
+
+ Q = P; D = *Q;
+
+ the CPU will issue the following memory operations:
+
+ Q = LOAD P, D = LOAD *Q
+
+ and always in that order.
+
+ (*) Overlapping loads and stores within a particular CPU will appear to be
+ ordered within that CPU. This means that for:
+
+ a = *X; *X = b;
+
+ the CPU will only issue the following sequence of memory operations:
+
+ a = LOAD *X, STORE *X = b
+
+ And for:
+
+ *X = c; d = *X;
+
+ the CPU will only issue:
+
+ STORE *X = c, d = LOAD *X
+
+ (Loads and stores overlap if they are targetted at overlapping pieces of
+ memory).
+
+And there are a number of things that _must_ or _must_not_ be assumed:
+
+ (*) It must not be assumed that independent loads and stores will be issued in
+ the order given. This means that for:
+
+ X = *A; Y = *B; *D = Z;
+
+ we may get any of the following sequences:
+
+ X = LOAD *A, Y = LOAD *B, STORE *D = Z
+ X = LOAD *A, STORE *D = Z, Y = LOAD *B
+ Y = LOAD *B, X = LOAD *A, STORE *D = Z
+ Y = LOAD *B, STORE *D = Z, X = LOAD *A
+ STORE *D = Z, X = LOAD *A, Y = LOAD *B
+ STORE *D = Z, Y = LOAD *B, X = LOAD *A
+
+ (*) It must be assumed that overlapping memory accesses may be merged or
+ discarded. This means that for:
+
+ X = *A; Y = *(A + 4);
+
+ we may get any one of the following sequences:
+
+ X = LOAD *A; Y = LOAD *(A + 4);
+ Y = LOAD *(A + 4); X = LOAD *A;
+ {X, Y} = LOAD {*A, *(A + 4) };
+
+ And for:
+
+ *A = X; Y = *A;
+
+ we may get either of:
+
+ STORE *A = X; Y = LOAD *A;
+ STORE *A = Y;
+
+
+=========================
+WHAT ARE MEMORY BARRIERS?
+=========================
+
+As can be seen above, independent memory operations are effectively performed
+in random order, but this can be a problem for CPU-CPU interaction and for I/O.
+What is required is some way of intervening to instruct the compiler and the
+CPU to restrict the order.
+
+Memory barriers are such interventions. They impose a perceived partial
+ordering between the memory operations specified either side of the barrier.
+They request that the sequence of memory events generated appears to other
+parts of the system as if the barrier is effective on that CPU.
+
+
+VARIETIES OF MEMORY BARRIER
+---------------------------
+
+Memory barriers come in four basic varieties:
+
+ (1) Read (or load) memory barriers.
+
+ A read memory barrier gives a guarantee that all the LOAD operations
+ specified before the barrier will appear to happen before all the LOAD
+ operations specified after the barrier with respect to the other
+ components of the system.
+
+ A read barrier is a partial ordering on loads only; it is not required to
+ have any effect on stores.
+
+ A read barrier guarantees that the issuing CPU's perception of all the
+ other stores in that system is up to date by the time the next load goes
+ from that CPU to the rest of the system.
+
+ Read memory barriers imply data dependency barriers, and so can substitute
+ for them.
+
+ (2) Write (or store) memory barriers.
+
+ A write memory barrier gives a guarantee that all the STORE operations
+ specified before the barrier will appear to happen before all the STORE
+ operations specified after the barrier with respect to the other
+ components of the system.
+
+ A write barrier is a partial ordering on stores only; it is not required
+ to have any effect on loads.
+
+ (3) General memory barriers.
+
+ A general memory barrier is a combination of both a read memory barrier
+ and a write memory barrier. It is a partial ordering over both loads and
+ stores.
+
+ General memory barriers imply both read and write memory barriers, and so
+ can substitute for either.
+
+ (4) Data dependency barriers.
+
+ A data dependency barrier is a weaker form of read barrier. In the case
+ where two loads are performed such that the second depends on the result
+ of the first (eg: the first load retrieves the address to which the second
+ load will be directed), a data dependency barrier would be required to
+ make sure that the target of the second load is updated before the address
+ obtained by the first load is accessed.
+
+ A data dependency barrier is a partial ordering on interdependent loads
+ only; it is not required to have any effect on stores, independent loads
+ or overlapping loads.
+
+ A data dependency barrier guarantees that the issuing CPU's perception of
+ all the other stores in that system is up to date by the time the next
+ load goes from that CPU to the rest of the system.
+
+ [!] Note that the first load really has to have a _data_ dependency, not a
+ control dependency. If the address for the second load is dependent on
+ the first load, but the dependency is through a conditional rather than
+ actually loading the address itself, then it's a _control_ dependency and
+ a full read barrier or better is required. See the "Control dependencies"
+ subsection for more information.
+
+Plus two common implicit varieties:
+
+ (5) LOCK operations.
+
+ This acts as a one-way permeable barrier. It guarantees that all memory
+ operations after the LOCK operation will appear to happen after the LOCK
+ operation with respect to the other components of the system.
+
+ Memory operations that occur before a LOCK operation may appear to happen
+ after it completes.
+
+ (6) UNLOCK operations.
+
+ This also acts as a one-way permeable barrier. It guarantees that all
+ memory operations before the UNLOCK operation will appear to happen before
+ the UNLOCK operation with respect to the other components of the system.
+
+ Memory operations that occur after an UNLOCK operation may appear to
+ happen before it completes.
+
+ LOCK and UNLOCK operations are guaranteed to appear with respect to each
+ other strictly in the order specified.
+
+
+Memory barriers are only required where there's a possibility of interaction
+between two CPUs or between a CPU and a device. If it can be guaranteed that
+there won't be any such interaction in any particular piece of code, then
+memory barriers are unnecessary in that piece of code.
+
+
+Note that these are the _minimum_ guarantees. Different architectures may give
+more substantial guarantees, but they may _not_ be relied upon outside of arch
+specific code.
+
+
+WHAT CAN'T BE ASSUMED ABOUT MEMORY BARRIERS?
+--------------------------------------------
+
+There are certain things that the Linux kernel memory barriers do not guarantee:
+
+ (*) There is no guarantee that any of the memory accesses specified before a
+ memory barrier will be _complete_ by the completion of a memory barrier
+ instruction; the barrier can be considered to draw a line in that CPU's
+ access queue that accesses of the appropriate type may not cross.
+
+ (*) There is no guarantee that issuing a memory barrier on one CPU will have
+ any direct effect on another CPU or any other hardware in the system. The
+ indirect effect will be the order in which the second CPU sees the effects
+ of the first CPU's accesses occur.
+
+ (*) There is no guarantee that the a CPU will see the correct order of effects
+ from a second CPU's accesses, even _if_ the second CPU uses a memory
+ barrier, unless the first CPU _also_ uses a matching memory barrier (see
+ the subsection on "SMP Barrier Pairing").
+
+ (*) There is no guarantee that some intervening piece of off-the-CPU
+ hardware[*] will not reorder the memory accesses. CPU cache coherency
+ mechanisms should propagate the indirect effects of a memory barrier
+ between CPUs, but may not do so in order.
+
+ [*] For information on bus mastering DMA and coherency please read:
+
+ Documentation/pci.txt
+ Documentation/DMA-mapping.txt
+ Documentation/DMA-API.txt
+
+
+DATA DEPENDENCY BARRIERS
+------------------------
+
+The usage requirements of data dependency barriers are a little subtle, and
+it's not always obvious that they're needed. To illustrate, consider the
+following sequence of events:
+
+ CPU 1 CPU 2
+ =============== ===============
+ { A == 1, B == 2, C = 3, P == &A, Q == &C }
+ B = 4;
+ <write barrier>
+ P = &B
+ Q = P;
+ D = *Q;
+
+There's a clear data dependency here, and it would seem that by the end of the
+sequence, Q must be either &A or &B, and that:
+
+ (Q == &A) implies (D == 1)
+ (Q == &B) implies (D == 4)
+
+But! CPU 2's perception of P may be updated _before_ its perception of B, thus
+leading to the following situation:
+
+ (Q == &B) and (D == 2) ????
+
+Whilst this may seem like a failure of coherency or causality maintenance, it
+isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
+Alpha).
+
+To deal with this, a data dependency barrier must be inserted between the
+address load and the data load:
+
+ CPU 1 CPU 2
+ =============== ===============
+ { A == 1, B == 2, C = 3, P == &A, Q == &C }
+ B = 4;
+ <write barrier>
+ P = &B
+ Q = P;
+ <data dependency barrier>
+ D = *Q;
+
+This enforces the occurrence of one of the two implications, and prevents the
+third possibility from arising.
+
+
+Another example of where data dependency barriers might by required is where a
+number is read from memory and then used to calculate the index for an array
+access:
+
+ CPU 1 CPU 2
+ =============== ===============
+ { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
+ M[1] = 4;
+ <write barrier>
+ P = 1
+ Q = P;
+ <data dependency barrier>
+ D = M[Q];
+
+
+The data dependency barrier is very important to the RCU system, for example.
+See rcu_dereference() in include/linux/rcupdate.h. This permits the current
+target of an RCU'd pointer to be replaced with a new modified target, without
+the replacement target appearing to be incompletely initialised.
+
+Note that this extremely counterintuitive situation arises most easily on
+machines with split caches, so that, for example, one cache bank processes
+even-numbered cache lines and the other bank processes odd-numbered cache
+lines. The pointer P might be stored in an odd-numbered cache line, and the
+variable B might be stored in an even-numbered cache line. Then, if the
+even-numbered bank of the reading CPU's cache is extremely busy while the
+odd-numbered bank is idle, one can see the new value of the pointer (&b), but
+the old value of the variable (1).
+
+See also the subsection on "Cache Coherency" for a more thorough example.
+
+
+CONTROL DEPENDENCIES
+--------------------
+
+A control dependency requires a full read memory barrier, not simply a data
+dependency barrier to make it work correctly. Consider the following bit of
+code:
+
+ q = &a;
+ if (p)
+ q = &b;
+ <data dependency barrier>
+ x = *q;
+
+This will not have the desired effect because there is no actual data
+dependency, but rather a control dependency that the CPU may short-circuit by
+attempting to predict the outcome in advance. In such a case what's actually
+required is:
+
+ q = &a;
+ if (p)
+ q = &b;
+ <read barrier>
+ x = *q;
+
+
+SMP BARRIER PAIRING
+-------------------
+
+When dealing with CPU-CPU interactions, certain types of memory barrier should
+always be paired. A lack of appropriate pairing is almost certainly an error.
+
+A write barrier should always be paired with a data dependency barrier or read
+barrier, though a general barrier would also be viable. Similarly a read
+barrier or a data dependency barrier should always be paired with at least an
+write barrier, though, again, a general barrier is viable:
+
+ CPU 1 CPU 2
+ =============== ===============
+ a = 1;
+ <write barrier>
+ b = 2; x = a;
+ <read barrier>
+ y = b;
+
+Or:
+
+ CPU 1 CPU 2
+ =============== ===============================
+ a = 1;
+ <write barrier>
+ b = &a; x = b;
+ <data dependency barrier>
+ y = *x;
+
+Basically, the read barrier always has to be there, even though it can be of
+the "weaker" type.
+
+
+========================
+EXPLICIT KERNEL BARRIERS
+========================
+
+The Linux kernel has a variety of different barriers that act at different
+levels:
+
+ (*) Compiler barrier.
+
+ (*) CPU memory barriers.
+
+ (*) MMIO write barrier.
+
+
+COMPILER BARRIER
+----------------
+
+The Linux kernel has an explicit compiler barrier function that prevents the
+compiler from moving the memory accesses either side of it to the other side:
+
+ barrier();
+
+This a general barrier - lesser varieties of compiler barrier do not exist.
+
+The compiler barrier has no direct effect on the CPU, which may then reorder
+things however it wishes.
+
+
+CPU MEMORY BARRIERS
+-------------------
+
+The Linux kernel has eight basic CPU memory barriers:
+
+ TYPE MANDATORY SMP CONDITIONAL
+ =============== ======================= ===========================
+ GENERAL mb() smp_mb()
+ WRITE wmb() smp_wmb()
+ READ rmb() smp_rmb()
+ DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
+
+
+All CPU memory barriers unconditionally imply compiler barriers.
+
+SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
+systems because it is assumed that a CPU will be appear to be self-consistent,
+and will order overlapping accesses correctly with respect to itself.
+
+[!] Note that SMP memory barriers _must_ be used if they look like they might
+be needed on an SMP system.
+
+Mandatory barriers should not be used to control SMP effects; but may be used
+to control MMIO effects on accesses through relaxed memory I/O windows.
+
+
+There are some more advanced barrier functions:
+
+ (*) set_mb(var, value)
+ (*) set_wmb(var, value)
+
+ These assign the value to the variable and then insert at least a write
+ barrier after it, depending on the function. They aren't guaranteed to
+ insert anything more than a compiler barrier in a UP compilation.
+
+
+ (*) smp_mb__before_atomic_dec();
+ (*) smp_mb__after_atomic_dec();
+ (*) smp_mb__before_atomic_inc();
+ (*) smp_mb__after_atomic_inc();
+
+ These are for use with atomic add, subtract, increment and decrement
+ functions, especially when used for reference counting. These functions
+ do not imply memory barriers.
+
+ As an example, consider a piece of code that marks an object as being dead
+ and then decrements the object's reference count:
+
+ obj->dead = 1;
+ smp_mb__before_atomic_dec();
+ atomic_dec(&obj->ref_count);
+
+ This makes sure that the death mark on the object is perceived to be set
+ *before* the reference counter is decremented.
+
+ See Documentation/atomic_ops.txt for more information.
+
+
+ (*) smp_mb__before_clear_bit(void);
+ (*) smp_mb__after_clear_bit(void);
+
+ These are for use similar to the atomic inc/dec barriers. These are
+ typically used for bitwise unlocking operations, so care must be taken as
+ there are no implicit memory barriers here either.
+
+ Consider implementing an unlock operation of some nature by clearing a
+ locking bit. The clear_bit() would then need to be barriered like this:
+
+ smp_mb__before_clear_bit();
+ clear_bit( ... );
+
+ This prevents memory operations before the clear leaking to after it. See
+ the subsection on "Locking Functions" with reference to UNLOCK operation
+ implications.
+
+ See Documentation/atomic_ops.txt for more information.
+
+
+MMIO WRITE BARRIER
+------------------
+
+The Linux kernel also has a special barrier for use with memory-mapped I/O
+writes:
+
+ mmiowb();
+
+This is a variation on the mandatory write barrier that causes writes to weakly
+ordered I/O regions to be partially ordered. Its effects may go beyond the
+CPU->Hardware interface and actually affect the hardware at some level.
+
+See the subsection "Locks vs I/O accesses" for more information.
+
+
+===============================
+IMPLICIT KERNEL MEMORY BARRIERS
+===============================
+
+Some of the other functions in the linux kernel imply memory barriers, amongst
+which are locking, scheduling and memory allocation functions.
+
+This specification is a _minimum_ guarantee; any particular architecture may
+provide more substantial guarantees, but these may not be relied upon outside
+of arch specific code.
+
+
+LOCKING FUNCTIONS
+-----------------
+
+The Linux kernel has a number of locking constructs:
+
+ (*) spin locks
+ (*) R/W spin locks
+ (*) mutexes
+ (*) semaphores
+ (*) R/W semaphores
+
+In all cases there are variants on "LOCK" operations and "UNLOCK" operations
+for each construct. These operations all imply certain barriers:
+
+ (1) LOCK operation implication:
+
+ Memory operations issued after the LOCK will be completed after the LOCK
+ operation has completed.
+
+ Memory operations issued before the LOCK may be completed after the LOCK
+ operation has completed.
+
+ (2) UNLOCK operation implication:
+
+ Memory operations issued before the UNLOCK will be completed before the
+ UNLOCK operation has completed.
+
+ Memory operations issued after the UNLOCK may be completed before the
+ UNLOCK operation has completed.
+
+ (3) LOCK vs LOCK implication:
+
+ All LOCK operations issued before another LOCK operation will be completed
+ before that LOCK operation.
+
+ (4) LOCK vs UNLOCK implication:
+
+ All LOCK operations issued before an UNLOCK operation will be completed
+ before the UNLOCK operation.
+
+ All UNLOCK operations issued before a LOCK operation will be completed
+ before the LOCK operation.
+
+ (5) Failed conditional LOCK implication:
+
+ Certain variants of the LOCK operation may fail, either due to being
+ unable to get the lock immediately, or due to receiving an unblocked
+ signal whilst asleep waiting for the lock to become available. Failed
+ locks do not imply any sort of barrier.
+
+Therefore, from (1), (2) and (4) an UNLOCK followed by an unconditional LOCK is
+equivalent to a full barrier, but a LOCK followed by an UNLOCK is not.
+
+[!] Note: one of the consequence of LOCKs and UNLOCKs being only one-way
+ barriers is that the effects instructions outside of a critical section may
+ seep into the inside of the critical section.
+
+Locks and semaphores may not provide any guarantee of ordering on UP compiled
+systems, and so cannot be counted on in such a situation to actually achieve
+anything at all - especially with respect to I/O accesses - unless combined
+with interrupt disabling operations.
+
+See also the section on "Inter-CPU locking barrier effects".
+
+
+As an example, consider the following:
+
+ *A = a;
+ *B = b;
+ LOCK
+ *C = c;
+ *D = d;
+ UNLOCK
+ *E = e;
+ *F = f;
+
+The following sequence of events is acceptable:
+
+ LOCK, {*F,*A}, *E, {*C,*D}, *B, UNLOCK
+
+ [+] Note that {*F,*A} indicates a combined access.
+
+But none of the following are:
+
+ {*F,*A}, *B, LOCK, *C, *D, UNLOCK, *E
+ *A, *B, *C, LOCK, *D, UNLOCK, *E, *F
+ *A, *B, LOCK, *C, UNLOCK, *D, *E, *F
+ *B, LOCK, *C, *D, UNLOCK, {*F,*A}, *E
+
+
+INTERRUPT DISABLING FUNCTIONS
+-----------------------------
+
+Functions that disable interrupts (LOCK equivalent) and enable interrupts
+(UNLOCK equivalent) will act as compiler barriers only. So if memory or I/O
+barriers are required in such a situation, they must be provided from some
+other means.
+
+
+MISCELLANEOUS FUNCTIONS
+-----------------------
+
+Other functions that imply barriers:
+
+ (*) schedule() and similar imply full memory barriers.
+
+ (*) Memory allocation and release functions imply full memory barriers.
+
+
+=================================
+INTER-CPU LOCKING BARRIER EFFECTS
+=================================
+
+On SMP systems locking primitives give a more substantial form of barrier: one
+that does affect memory access ordering on other CPUs, within the context of
+conflict on any particular lock.
+
+
+LOCKS VS MEMORY ACCESSES
+------------------------
+
+Consider the following: the system has a pair of spinlocks (N) and (Q), and
+three CPUs; then should the following sequence of events occur:
+
+ CPU 1 CPU 2
+ =============================== ===============================
+ *A = a; *E = e;
+ LOCK M LOCK Q
+ *B = b; *F = f;
+ *C = c; *G = g;
+ UNLOCK M UNLOCK Q
+ *D = d; *H = h;
+
+Then there is no guarantee as to what order CPU #3 will see the accesses to *A
+through *H occur in, other than the constraints imposed by the separate locks
+on the separate CPUs. It might, for example, see:
+
+ *E, LOCK M, LOCK Q, *G, *C, *F, *A, *B, UNLOCK Q, *D, *H, UNLOCK M
+
+But it won't see any of:
+
+ *B, *C or *D preceding LOCK M
+ *A, *B or *C following UNLOCK M
+ *F, *G or *H preceding LOCK Q
+ *E, *F or *G following UNLOCK Q
+
+
+However, if the following occurs:
+
+ CPU 1 CPU 2
+ =============================== ===============================
+ *A = a;
+ LOCK M [1]
+ *B = b;
+ *C = c;
+ UNLOCK M [1]
+ *D = d; *E = e;
+ LOCK M [2]
+ *F = f;
+ *G = g;
+ UNLOCK M [2]
+ *H = h;
+
+CPU #3 might see:
+
+ *E, LOCK M [1], *C, *B, *A, UNLOCK M [1],
+ LOCK M [2], *H, *F, *G, UNLOCK M [2], *D
+
+But assuming CPU #1 gets the lock first, it won't see any of:
+
+ *B, *C, *D, *F, *G or *H preceding LOCK M [1]
+ *A, *B or *C following UNLOCK M [1]
+ *F, *G or *H preceding LOCK M [2]
+ *A, *B, *C, *E, *F or *G following UNLOCK M [2]
+
+
+LOCKS VS I/O ACCESSES
+---------------------
+
+Under certain circumstances (especially involving NUMA), I/O accesses within
+two spinlocked sections on two different CPUs may be seen as interleaved by the
+PCI bridge, because the PCI bridge does not necessarily participate in the
+cache-coherence protocol, and is therefore incapable of issuing the required
+read memory barriers.
+
+For example:
+
+ CPU 1 CPU 2
+ =============================== ===============================
+ spin_lock(Q)
+ writel(0, ADDR)
+ writel(1, DATA);
+ spin_unlock(Q);
+ spin_lock(Q);
+ writel(4, ADDR);
+ writel(5, DATA);
+ spin_unlock(Q);
+
+may be seen by the PCI bridge as follows:
+
+ STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
+
+which would probably cause the hardware to malfunction.
+
+
+What is necessary here is to intervene with an mmiowb() before dropping the
+spinlock, for example:
+
+ CPU 1 CPU 2
+ =============================== ===============================
+ spin_lock(Q)
+ writel(0, ADDR)
+ writel(1, DATA);
+ mmiowb();
+ spin_unlock(Q);
+ spin_lock(Q);
+ writel(4, ADDR);
+ writel(5, DATA);
+ mmiowb();
+ spin_unlock(Q);
+
+this will ensure that the two stores issued on CPU #1 appear at the PCI bridge
+before either of the stores issued on CPU #2.
+
+
+Furthermore, following a store by a load to the same device obviates the need
+for an mmiowb(), because the load forces the store to complete before the load
+is performed:
+
+ CPU 1 CPU 2
+ =============================== ===============================
+ spin_lock(Q)
+ writel(0, ADDR)
+ a = readl(DATA);
+ spin_unlock(Q);
+ spin_lock(Q);
+ writel(4, ADDR);
+ b = readl(DATA);
+ spin_unlock(Q);
+
+
+See Documentation/DocBook/deviceiobook.tmpl for more information.
+
+
+=================================
+WHERE ARE MEMORY BARRIERS NEEDED?
+=================================
+
+Under normal operation, memory operation reordering is generally not going to
+be a problem as a single-threaded linear piece of code will still appear to
+work correctly, even if it's in an SMP kernel. There are, however, three
+circumstances in which reordering definitely _could_ be a problem:
+
+ (*) Interprocessor interaction.
+
+ (*) Atomic operations.
+
+ (*) Accessing devices (I/O).
+
+ (*) Interrupts.
+
+
+INTERPROCESSOR INTERACTION
+--------------------------
+
+When there's a system with more than one processor, more than one CPU in the
+system may be working on the same data set at the same time. This can cause
+synchronisation problems, and the usual way of dealing with them is to use
+locks. Locks, however, are quite expensive, and so it may be preferable to
+operate without the use of a lock if at all possible. In such a case
+operations that affect both CPUs may have to be carefully ordered to prevent
+a malfunction.
+
+Consider, for example, the R/W semaphore slow path. Here a waiting process is
+queued on the semaphore, by virtue of it having a piece of its stack linked to
+the semaphore's list of waiting processes:
+
+ struct rw_semaphore {
+ ...
+ spinlock_t lock;
+ struct list_head waiters;
+ };
+
+ struct rwsem_waiter {
+ struct list_head list;
+ struct task_struct *task;
+ };
+
+To wake up a particular waiter, the up_read() or up_write() functions have to:
+
+ (1) read the next pointer from this waiter's record to know as to where the
+ next waiter record is;
+
+ (4) read the pointer to the waiter's task structure;
+
+ (3) clear the task pointer to tell the waiter it has been given the semaphore;
+
+ (4) call wake_up_process() on the task; and
+
+ (5) release the reference held on the waiter's task struct.
+
+In otherwords, it has to perform this sequence of events:
+
+ LOAD waiter->list.next;
+ LOAD waiter->task;
+ STORE waiter->task;
+ CALL wakeup
+ RELEASE task
+
+and if any of these steps occur out of order, then the whole thing may
+malfunction.
+
+Once it has queued itself and dropped the semaphore lock, the waiter does not
+get the lock again; it instead just waits for its task pointer to be cleared
+before proceeding. Since the record is on the waiter's stack, this means that
+if the task pointer is cleared _before_ the next pointer in the list is read,
+another CPU might start processing the waiter and might clobber the waiter's
+stack before the up*() function has a chance to read the next pointer.
+
+Consider then what might happen to the above sequence of events:
+
+ CPU 1 CPU 2
+ =============================== ===============================
+ down_xxx()
+ Queue waiter
+ Sleep
+ up_yyy()
+ LOAD waiter->task;
+ STORE waiter->task;
+ Woken up by other event
+ <preempt>
+ Resume processing
+ down_xxx() returns
+ call foo()
+ foo() clobbers *waiter
+ </preempt>
+ LOAD waiter->list.next;
+ --- OOPS ---
+
+This could be dealt with using the semaphore lock, but then the down_xxx()
+function has to needlessly get the spinlock again after being woken up.
+
+The way to deal with this is to insert a general SMP memory barrier:
+
+ LOAD waiter->list.next;
+ LOAD waiter->task;
+ smp_mb();
+ STORE waiter->task;
+ CALL wakeup
+ RELEASE task
+
+In this case, the barrier makes a guarantee that all memory accesses before the
+barrier will appear to happen before all the memory accesses after the barrier
+with respect to the other CPUs on the system. It does _not_ guarantee that all
+the memory accesses before the barrier will be complete by the time the barrier
+instruction itself is complete.
+
+On a UP system - where this wouldn't be a problem - the smp_mb() is just a
+compiler barrier, thus making sure the compiler emits the instructions in the
+right order without actually intervening in the CPU. Since there there's only
+one CPU, that CPU's dependency ordering logic will take care of everything
+else.
+
+
+ATOMIC OPERATIONS
+-----------------
+
+Though they are technically interprocessor interaction considerations, atomic
+operations are noted specially as they do _not_ generally imply memory
+barriers. The possible offenders include:
+
+ xchg();
+ cmpxchg();
+ test_and_set_bit();
+ test_and_clear_bit();
+ test_and_change_bit();
+ atomic_cmpxchg();
+ atomic_inc_return();
+ atomic_dec_return();
+ atomic_add_return();
+ atomic_sub_return();
+ atomic_inc_and_test();
+ atomic_dec_and_test();
+ atomic_sub_and_test();
+ atomic_add_negative();
+ atomic_add_unless();
+
+These may be used for such things as implementing LOCK operations or controlling
+the lifetime of objects by decreasing their reference counts.
+
+The following may also be possible offenders as they may be used as UNLOCK
+operations.
+
+ set_bit();
+ clear_bit();
+ change_bit();
+ atomic_set();
+
+But the following should be safe as they can't be used for conditional
+processing since they don't return a result.
+
+ atomic_add();
+ atomic_sub();
+ atomic_inc();
+ atomic_dec();
+
+See Documentation/atomic_ops.txt for more information.
+
+
+ACCESSING DEVICES
+-----------------
+
+Many devices can be memory mapped, and so appear to the CPU as if they're just
+as set of memory locations. However, to control the device, the driver
+usually has to make the right accesses in exactly the right order.
+
+Consider, for example, an ethernet chipset such as the AMD PCnet32. It
+presents to the CPU an "address register" and a bunch of "data registers". The
+way it's accessed is to write the index of the internal register to be accessed
+to the address register, and then read or write the appropriate data register
+to access the chip's internal register. This could theoretically be done by:
+
+ *ADDR = 3;
+ reg = *DATA;
+
+Or:
+
+ *ADDR = 3;
+ *DATA = value;
+
+The problem with a clever CPU or a clever compiler is that the store to the
+address register is not guaranteed to happen before the operation on the data
+register, if the CPU or the compiler thinks it is more efficient to defer the
+address store:
+
+ LOAD *DATA, STORE *ADDR
+
+or:
+
+ STORE *DATA, STORE *ADDR
+
+which will cause the device or the driver to malfunction.
+
+
+In the Linux kernel, however, I/O should be done through the appropriate
+accessor routines - such as inb() or writel() - which know how to make such
+accesses appropriately sequential.
+
+On some systems, I/O stores are not strongly ordered across all CPUs, and so
+locking should be used and mmiowb() must be issued prior to unlocking the
+critical section.
+
+See Documentation/DocBook/deviceiobook.tmpl for more information.
+
+
+INTERRUPTS
+----------
+
+A driver may be interrupted by its own interrupt service routine, and thus the
+two parts of the driver may interfere with each other's attempts to control or
+access the device.
+
+This may be alleviated - at least in part - by disabling local interrupts (a
+form of locking), such that the critical operations are all contained within
+the interrupt-disabled section in the driver. Whilst the driver's interrupt
+routine is executing, the driver's core may not run on the same CPU, and its
+interrupt is not permitted to happen again until the current interrupt has been
+handled, thus the interrupt handler does not need to lock against that.
+
+However, consider a driver that was talking to an ethernet card that sports an
+address register and a data register. If that driver's core talks to the card
+under interrupt-disablement and then the driver's interrupt handler is invoked:
+
+ LOCAL IRQ DISABLE
+ writew(ADDR, 3);
+ writew(DATA, y);
+ LOCAL IRQ ENABLE
+ <interrupt>
+ writew(ADDR, 4);
+ q = readw(DATA);
+ </interrupt>
+
+The store to the data register might happen after the second store to the
+address register if ordering rules are sufficiently relaxed:
+
+ STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
+
+
+If ordering rules are relaxed, it must be assumed that accesses done inside an
+interrupt disabled section may leak outside of it and may interleave with
+accesses performed in an interrupt - and vice versa - unless implicit or
+explicit barriers are used.
+
+Normally this won't be a problem because the I/O accesses done inside such
+sections will include synchronous load operations on strictly ordered I/O
+registers that form implicit I/O barriers. If this isn't sufficient then an
+mmiowb() may need to be used explicitly.
+
+
+A similar situation may occur between an interrupt routine and two routines
+running on separate CPUs that communicate with each other. If such a case is
+likely, then interrupt-disabling locks should be used to guarantee ordering.
+
+
+==========================
+KERNEL I/O BARRIER EFFECTS
+==========================
+
+When accessing I/O memory, drivers should use the appropriate accessor
+functions:
+
+ (*) inX(), outX():
+
+ These are intended to talk to I/O space rather than memory space, but
+ that's primarily a CPU-specific concept. The i386 and x86_64 processors do
+ indeed have special I/O space access cycles and instructions, but many
+ CPUs don't have such a concept.
+
+ The PCI bus, amongst others, defines an I/O space concept - which on such
+ CPUs as i386 and x86_64 cpus readily maps to the CPU's concept of I/O
+ space. However, it may also mapped as a virtual I/O space in the CPU's
+ memory map, particularly on those CPUs that don't support alternate
+ I/O spaces.
+
+ Accesses to this space may be fully synchronous (as on i386), but
+ intermediary bridges (such as the PCI host bridge) may not fully honour
+ that.
+
+ They are guaranteed to be fully ordered with respect to each other.
+
+ They are not guaranteed to be fully ordered with respect to other types of
+ memory and I/O operation.
+
+ (*) readX(), writeX():
+
+ Whether these are guaranteed to be fully ordered and uncombined with
+ respect to each other on the issuing CPU depends on the characteristics
+ defined for the memory window through which they're accessing. On later
+ i386 architecture machines, for example, this is controlled by way of the
+ MTRR registers.
+
+ Ordinarily, these will be guaranteed to be fully ordered and uncombined,,
+ provided they're not accessing a prefetchable device.
+
+ However, intermediary hardware (such as a PCI bridge) may indulge in
+ deferral if it so wishes; to flush a store, a load from the same location
+ is preferred[*], but a load from the same device or from configuration
+ space should suffice for PCI.
+
+ [*] NOTE! attempting to load from the same location as was written to may
+ cause a malfunction - consider the 16550 Rx/Tx serial registers for
+ example.
+
+ Used with prefetchable I/O memory, an mmiowb() barrier may be required to
+ force stores to be ordered.
+
+ Please refer to the PCI specification for more information on interactions
+ between PCI transactions.
+
+ (*) readX_relaxed()
+
+ These are similar to readX(), but are not guaranteed to be ordered in any
+ way. Be aware that there is no I/O read barrier available.
+
+ (*) ioreadX(), iowriteX()
+
+ These will perform as appropriate for the type of access they're actually
+ doing, be it inX()/outX() or readX()/writeX().
+
+
+========================================
+ASSUMED MINIMUM EXECUTION ORDERING MODEL
+========================================
+
+It has to be assumed that the conceptual CPU is weakly-ordered but that it will
+maintain the appearance of program causality with respect to itself. Some CPUs
+(such as i386 or x86_64) are more constrained than others (such as powerpc or
+frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
+of arch-specific code.
+
+This means that it must be considered that the CPU will execute its instruction
+stream in any order it feels like - or even in parallel - provided that if an
+instruction in the stream depends on the an earlier instruction, then that
+earlier instruction must be sufficiently complete[*] before the later
+instruction may proceed; in other words: provided that the appearance of
+causality is maintained.
+
+ [*] Some instructions have more than one effect - such as changing the
+ condition codes, changing registers or changing memory - and different
+ instructions may depend on different effects.
+
+A CPU may also discard any instruction sequence that winds up having no
+ultimate effect. For example, if two adjacent instructions both load an
+immediate value into the same register, the first may be discarded.
+
+
+Similarly, it has to be assumed that compiler might reorder the instruction
+stream in any way it sees fit, again provided the appearance of causality is
+maintained.
+
+
+============================
+THE EFFECTS OF THE CPU CACHE
+============================
+
+The way cached memory operations are perceived across the system is affected to
+a certain extent by the caches that lie between CPUs and memory, and by the
+memory coherence system that maintains the consistency of state in the system.
+
+As far as the way a CPU interacts with another part of the system through the
+caches goes, the memory system has to include the CPU's caches, and memory
+barriers for the most part act at the interface between the CPU and its cache
+(memory barriers logically act on the dotted line in the following diagram):
+
+ <--- CPU ---> : <----------- Memory ----------->
+ :
+ +--------+ +--------+ : +--------+ +-----------+
+ | | | | : | | | | +--------+
+ | CPU | | Memory | : | CPU | | | | |
+ | Core |--->| Access |----->| Cache |<-->| | | |
+ | | | Queue | : | | | |--->| Memory |
+ | | | | : | | | | | |
+ +--------+ +--------+ : +--------+ | | | |
+ : | Cache | +--------+
+ : | Coherency |
+ : | Mechanism | +--------+
+ +--------+ +--------+ : +--------+ | | | |
+ | | | | : | | | | | |
+ | CPU | | Memory | : | CPU | | |--->| Device |
+ | Core |--->| Access |----->| Cache |<-->| | | |
+ | | | Queue | : | | | | | |
+ | | | | : | | | | +--------+
+ +--------+ +--------+ : +--------+ +-----------+
+ :
+ :
+
+Although any particular load or store may not actually appear outside of the
+CPU that issued it since it may have been satisfied within the CPU's own cache,
+it will still appear as if the full memory access had taken place as far as the
+other CPUs are concerned since the cache coherency mechanisms will migrate the
+cacheline over to the accessing CPU and propagate the effects upon conflict.
+
+The CPU core may execute instructions in any order it deems fit, provided the
+expected program causality appears to be maintained. Some of the instructions
+generate load and store operations which then go into the queue of memory
+accesses to be performed. The core may place these in the queue in any order
+it wishes, and continue execution until it is forced to wait for an instruction
+to complete.
+
+What memory barriers are concerned with is controlling the order in which
+accesses cross from the CPU side of things to the memory side of things, and
+the order in which the effects are perceived to happen by the other observers
+in the system.
+
+[!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
+their own loads and stores as if they had happened in program order.
+
+
+CACHE COHERENCY
+---------------
+
+Life isn't quite as simple as it may appear above, however: for while the
+caches are expected to be coherent, there's no guarantee that that coherency
+will be ordered. This means that whilst changes made on one CPU will
+eventually become visible on all CPUs, there's no guarantee that they will
+become apparent in the same order on those other CPUs.
+
+
+Consider dealing with a system that has pair of CPUs (1 & 2), each of which has
+a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
+
+ :
+ : +--------+
+ : +---------+ | |
+ +--------+ : +--->| Cache A |<------->| |
+ | | : | +---------+ | |
+ | CPU 1 |<---+ | |
+ | | : | +---------+ | |
+ +--------+ : +--->| Cache B |<------->| |
+ : +---------+ | |
+ : | Memory |
+ : +---------+ | System |
+ +--------+ : +--->| Cache C |<------->| |
+ | | : | +---------+ | |
+ | CPU 2 |<---+ | |
+ | | : | +---------+ | |
+ +--------+ : +--->| Cache D |<------->| |
+ : +---------+ | |
+ : +--------+
+ :
+
+Imagine the system has the following properties:
+
+ (*) an odd-numbered cache line may be in cache A, cache C or it may still be
+ resident in memory;
+
+ (*) an even-numbered cache line may be in cache B, cache D or it may still be
+ resident in memory;
+
+ (*) whilst the CPU core is interrogating one cache, the other cache may be
+ making use of the bus to access the rest of the system - perhaps to
+ displace a dirty cacheline or to do a speculative load;
+
+ (*) each cache has a queue of operations that need to be applied to that cache
+ to maintain coherency with the rest of the system;
+
+ (*) the coherency queue is not flushed by normal loads to lines already
+ present in the cache, even though the contents of the queue may
+ potentially effect those loads.
+
+Imagine, then, that two writes are made on the first CPU, with a write barrier
+between them to guarantee that they will appear to reach that CPU's caches in
+the requisite order:
+
+ CPU 1 CPU 2 COMMENT
+ =============== =============== =======================================
+ u == 0, v == 1 and p == &u, q == &u
+ v = 2;
+ smp_wmb(); Make sure change to v visible before
+ change to p
+ <A:modify v=2> v is now in cache A exclusively
+ p = &v;
+ <B:modify p=&v> p is now in cache B exclusively
+
+The write memory barrier forces the other CPUs in the system to perceive that
+the local CPU's caches have apparently been updated in the correct order. But
+now imagine that the second CPU that wants to read those values:
+
+ CPU 1 CPU 2 COMMENT
+ =============== =============== =======================================
+ ...
+ q = p;
+ x = *q;
+
+The above pair of reads may then fail to happen in expected order, as the
+cacheline holding p may get updated in one of the second CPU's caches whilst
+the update to the cacheline holding v is delayed in the other of the second
+CPU's caches by some other cache event:
+
+ CPU 1 CPU 2 COMMENT
+ =============== =============== =======================================
+ u == 0, v == 1 and p == &u, q == &u
+ v = 2;
+ smp_wmb();
+ <A:modify v=2> <C:busy>
+ <C:queue v=2>
+ p = &b; q = p;
+ <D:request p>
+ <B:modify p=&v> <D:commit p=&v>
+ <D:read p>
+ x = *q;
+ <C:read *q> Reads from v before v updated in cache
+ <C:unbusy>
+ <C:commit v=2>
+
+Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
+no guarantee that, without intervention, the order of update will be the same
+as that committed on CPU 1.
+
+
+To intervene, we need to interpolate a data dependency barrier or a read
+barrier between the loads. This will force the cache to commit its coherency
+queue before processing any further requests:
+
+ CPU 1 CPU 2 COMMENT
+ =============== =============== =======================================
+ u == 0, v == 1 and p == &u, q == &u
+ v = 2;
+ smp_wmb();
+ <A:modify v=2> <C:busy>
+ <C:queue v=2>
+ p = &b; q = p;
+ <D:request p>
+ <B:modify p=&v> <D:commit p=&v>
+ <D:read p>
+ smp_read_barrier_depends()
+ <C:unbusy>
+ <C:commit v=2>
+ x = *q;
+ <C:read *q> Reads from v after v updated in cache
+
+
+This sort of problem can be encountered on DEC Alpha processors as they have a
+split cache that improves performance by making better use of the data bus.
+Whilst most CPUs do imply a data dependency barrier on the read when a memory
+access depends on a read, not all do, so it may not be relied on.
+
+
+CACHE COHERENCY VS DMA
+----------------------
+
+Not all systems maintain cache coherency with respect to devices doing DMA. In
+such cases, a device attempting DMA may obtain stale data from RAM because
+dirty cache lines may be resident in the caches of various CPUs, and may not
+have been written back to RAM yet. To deal with this, the appropriate part of
+the kernel must flush the overlapping bits of cache on each CPU (and maybe
+invalidate them as well).
+
+In addition, the data DMA'd to RAM by a device may be overwritten by dirty
+cache lines being written back to RAM from a CPU's cache after the device has
+installed its own data, or cache lines simply present in a CPUs cache may
+simply obscure the fact that RAM has been updated, until at such time as the
+cacheline is discarded from the CPU's cache and reloaded. To deal with this,
+the appropriate part of the kernel must invalidate the overlapping bits of the
+cache on each CPU.
+
+See Documentation/cachetlb.txt for more information on cache management.
+
+
+CACHE COHERENCY VS MMIO
+-----------------------
+
+Memory mapped I/O usually takes place through memory locations that are part of
+a window in the CPU's memory space that have different properties assigned than
+the usual RAM directed window.
+
+Amongst these properties is usually the fact that such accesses bypass the
+caching entirely and go directly to the device buses. This means MMIO accesses
+may, in effect, overtake accesses to cached memory that were emitted earlier.
+A memory barrier isn't sufficient in such a case, but rather the cache must be
+flushed between the cached memory write and the MMIO access if the two are in
+any way dependent.
+
+
+=========================
+THE THINGS CPUS GET UP TO
+=========================
+
+A programmer might take it for granted that the CPU will perform memory
+operations in exactly the order specified, so that if a CPU is, for example,
+given the following piece of code to execute:
+
+ a = *A;
+ *B = b;
+ c = *C;
+ d = *D;
+ *E = e;
+
+They would then expect that the CPU will complete the memory operation for each
+instruction before moving on to the next one, leading to a definite sequence of
+operations as seen by external observers in the system:
+
+ LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
+
+
+Reality is, of course, much messier. With many CPUs and compilers, the above
+assumption doesn't hold because:
+
+ (*) loads are more likely to need to be completed immediately to permit
+ execution progress, whereas stores can often be deferred without a
+ problem;
+
+ (*) loads may be done speculatively, and the result discarded should it prove
+ to have been unnecessary;
+
+ (*) loads may be done speculatively, leading to the result having being
+ fetched at the wrong time in the expected sequence of events;
+
+ (*) the order of the memory accesses may be rearranged to promote better use
+ of the CPU buses and caches;
+
+ (*) loads and stores may be combined to improve performance when talking to
+ memory or I/O hardware that can do batched accesses of adjacent locations,
+ thus cutting down on transaction setup costs (memory and PCI devices may
+ both be able to do this); and
+
+ (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
+ mechanisms may alleviate this - once the store has actually hit the cache
+ - there's no guarantee that the coherency management will be propagated in
+ order to other CPUs.
+
+So what another CPU, say, might actually observe from the above piece of code
+is:
+
+ LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
+
+ (Where "LOAD {*C,*D}" is a combined load)
+
+
+However, it is guaranteed that a CPU will be self-consistent: it will see its
+_own_ accesses appear to be correctly ordered, without the need for a memory
+barrier. For instance with the following code:
+
+ X = *A;
+ *A = Y;
+ Z = *A;
+
+and assuming no intervention by an external influence, it can be taken that:
+
+ (*) X will hold the old value of *A, and will never happen after the store and
+ thus end up being given the value that was assigned to *A from Y instead;
+ and
+
+ (*) Z will always be given the value in *A that was assigned there from Y, and
+ will never happen before the store, and thus end up with the same value
+ that was in *A initially.
+
+(This is ignoring the fact that the value initially in *A may appear to be the
+same as the value assigned to *A from Y).
+
+
+AND THEN THERE'S THE ALPHA
+--------------------------
+
+The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
+some versions of the Alpha CPU have a split data cache, permitting them to have
+two semantically related cache lines updating at separate times. This is where
+the data dependency barrier really becomes necessary as this synchronises both
+caches with the memory coherence system, thus making it seem like pointer
+changes vs new data occur in the right order.
+
+The Alpha defines the Linux's kernel's memory barrier model.
+
+See the subsection on "Cache Coherency" above.
+
+
+==========
+REFERENCES
+==========
+
+Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
+Digital Press)
+ Chapter 5.2: Physical Address Space Characteristics
+ Chapter 5.4: Caches and Write Buffers
+ Chapter 5.5: Data Sharing
+ Chapter 5.6: Read/Write Ordering
+
+AMD64 Architecture Programmer's Manual Volume 2: System Programming
+ Chapter 7.1: Memory-Access Ordering
+ Chapter 7.4: Buffering and Combining Memory Writes
+
+IA-32 Intel Architecture Software Developer's Manual, Volume 3:
+System Programming Guide
+ Chapter 7.1: Locked Atomic Operations
+ Chapter 7.2: Memory Ordering
+ Chapter 7.4: Serializing Instructions
+
+The SPARC Architecture Manual, Version 9
+ Chapter 8: Memory Models
+ Appendix D: Formal Specification of the Memory Models
+ Appendix J: Programming with the Memory Models
+
+UltraSPARC Programmer Reference Manual
+ Chapter 5: Memory Accesses and Cacheability
+ Chapter 15: Sparc-V9 Memory Models
+
+UltraSPARC III Cu User's Manual
+ Chapter 9: Memory Models
+
+UltraSPARC IIIi Processor User's Manual
+ Chapter 8: Memory Models
+
+UltraSPARC Architecture 2005
+ Chapter 9: Memory
+ Appendix D: Formal Specifications of the Memory Models
+
+UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
+ Chapter 8: Memory Models
+ Appendix F: Caches and Cache Coherency
+
+Solaris Internals, Core Kernel Architecture, p63-68:
+ Chapter 3.3: Hardware Considerations for Locks and
+ Synchronization
+
+Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
+for Kernel Programmers:
+ Chapter 13: Other Memory Models
+
+Intel Itanium Architecture Software Developer's Manual: Volume 1:
+ Section 2.6: Speculation
+ Section 4.4: Memory Access
^ permalink raw reply related
* Re: Memory mapping PCI memory region to user space
From: Kumar Gala @ 2006-03-23 20:01 UTC (permalink / raw)
To: Wyse, Chris; +Cc: Linuxppc-Embedded ((E-Mail))
In-Reply-To: <B1E46DE837A394458BB1A58F74A66A78059878@ala-mail02.corp.ad.wrs.com>
On Mar 23, 2006, at 1:52 PM, Wyse, Chris wrote:
> Hi,
>
> Thanks for all the help.
>
> My ideal solution would have been to use sysfs, but I didn't want to
> upgrade the kernel. Therefore, I used Dave's program as a guide for
> setting the protect bits appropriately, and was able to get the driver
> working. The driver required the pfn_pte macro change specified in my
> original post. It appears to be a kernel bug on PPC processors with a
> greater than 32 bit address space.
The issue with greater than 32 bit address spaces goes away in newer
kernels with the use of io_remap_pfn_range() instead of
io_remap_page_range().
- kumar
> -----Original Message-----
> From: David Hawkins [mailto:dwh@ovro.caltech.edu]
> Sent: Thursday, March 23, 2006 12:47 PM
> To: Kumar Gala
> Cc: Wyse, Chris; Linuxppc-Embedded ((E-Mail))
> Subject: Re: Memory mapping PCI memory region to user space
>
> Hi Kumar,
>
>>> When I was testing the Yosemite board as the host, I found that I
>>> could set the endian flag on the mmapped page, which then made the
>>> PCI device registers read as 32-bit quantities read back with the
>>> same layout under both x86 and PPC hosts.
>>
>> Hmm, I guess I would handle this like how the reset of the kernel
>> handle is with the io routines handling the swapping. Not sure if
>> there is any advantage to using the endian flag. I guess if you have
>> something you are treating as just memory there would be.
>
> I haven't used the feature, I just tested it to see what it did.
>
> The application case I thought of was this; the PCI boards I built
> (that
> I am revising, and replacing the DSP with a PPC) have an 8MB PCI
> region
> that I can mmap from the host. I have a test suite that runs from the
> host that manipulates registers on the boards to download FPGAs etc.
> When the boards are used in a real system, the onboard DSP is
> generally
> used, and the host just talks to the DSP.
>
> However, for the test suite, if I have a header with definitions
> like:
>
> #define CONTROL_FPGA_ENABLE (1 << 0)
> #define CONTROL_FPGA_DONE_BIT (1 << 1)
>
> that correspond to bits in a 32-bit PCI mmapped register. Then code in
> the user-space test suite that did something like
>
> pci_addr[CONTROL_OFFSET] |= CONTROL_FPGA_ENABLE;
>
> would instead need to be re-written, eg.,
>
> write_le32(&pci_addr[CONTROL_OFFSET], CONTROL_FPGA_ENABLE);
>
> to be portable.
>
> I definitely agree that this is how kernel-level code should be
> written,
> but user-space code ... well, if I want to reuse code already written,
> setting the page endian flag and reusing the code would seem like the
> way to go. (This isn't what I need to do, since my host will still
> be an
> x86, the PPC will be a target device, but I still need to think about
> the endian issues).
>
> Now of course that I have seen the consequences of my coding, I'll be
> more careful to deal with endianness more appropriately.
>
> Its a tricky trade-off though. I could define control ioctl's that
> hide
> all the endianness issues ... but then the driver just gets bigger. I
> think the appropriate solution for the user-space test code would
> be to
> use CPU-to-little-endian routines, and wrap the lot in a re-usable
> library that the test suite links against.
>
>> There isn't a sysfs flag for the endianness page attribute since
>> thats a PPC book-e specific feature. We could possible expand things
>
>> to support it but, I've been trying to actively avoid using the 'E'
> bit.
>
> Ok, I haven't received the 8349E board that I am waiting on, so I
> hadn't
> spotted that the PAGE_ENDIAN flag was Book E specific.
>
> Thanks for your insight.
>
> Cheers
> Dave
>
>
>
^ permalink raw reply
* Re: Memory mapping PCI memory region to user space
From: Mark Chambers @ 2006-03-23 19:55 UTC (permalink / raw)
To: David Hawkins; +Cc: Linuxppc-Embedded ((E-Mail))
In-Reply-To: <4422E0CB.8080701@ovro.caltech.edu>
>
>>
>> PCI is actually endian-agnostic, so we're really 'fixing' the
>> Freescale PCI implementation with endian swapping.
>>
>
> Hi Mark,
>
> Its not agnostic, its little-endian.
>
Ok, I should be a little more specific. Yes, I/O space is
little endian, and any configuration registers and such are
little endian. But memory space is strictly 32 bit as far
as PCI is concerned. (forgetting 64 bit PCI for the moment)
The two lower bits of address are not used, and there
is no required correlation of byte enables to those missing
address bits.
So, the point is, Freescale swaps bytes between its internal
bus and PCI. Other processors (like TI DSPs) do not. I
don't know that one method is necessarily right, but the fact
that we have this discussion periodically suggests that
Freescale's method is not the best.
This might be an academic point, but I think it does help to
see the distinction. To talk to a device over PCI you must
know how both ends map their internal buss(es) to PCI,
and it's not directly a big/little endian issue.
Mark
^ permalink raw reply
* RE: Memory mapping PCI memory region to user space
From: Wyse, Chris @ 2006-03-23 19:52 UTC (permalink / raw)
To: David Hawkins, Kumar Gala; +Cc: Linuxppc-Embedded ((E-Mail))
Hi,
Thanks for all the help.
My ideal solution would have been to use sysfs, but I didn't want to
upgrade the kernel. Therefore, I used Dave's program as a guide for
setting the protect bits appropriately, and was able to get the driver
working. The driver required the pfn_pte macro change specified in my
original post. It appears to be a kernel bug on PPC processors with a
greater than 32 bit address space.
Chris Wyse
Member of Technical Staff
Embedded Technologies
860-749-1556 office
860-978-0849 cell
413-778-9101 fax
http://www.windriver.com
=20
-----Original Message-----
From: David Hawkins [mailto:dwh@ovro.caltech.edu]=20
Sent: Thursday, March 23, 2006 12:47 PM
To: Kumar Gala
Cc: Wyse, Chris; Linuxppc-Embedded ((E-Mail))
Subject: Re: Memory mapping PCI memory region to user space
Hi Kumar,
>> When I was testing the Yosemite board as the host, I found that I=20
>> could set the endian flag on the mmapped page, which then made the=20
>> PCI device registers read as 32-bit quantities read back with the=20
>> same layout under both x86 and PPC hosts.
>=20
> Hmm, I guess I would handle this like how the reset of the kernel=20
> handle is with the io routines handling the swapping. Not sure if=20
> there is any advantage to using the endian flag. I guess if you have=20
> something you are treating as just memory there would be.
I haven't used the feature, I just tested it to see what it did.
The application case I thought of was this; the PCI boards I built (that
I am revising, and replacing the DSP with a PPC) have an 8MB PCI region
that I can mmap from the host. I have a test suite that runs from the
host that manipulates registers on the boards to download FPGAs etc.
When the boards are used in a real system, the onboard DSP is generally
used, and the host just talks to the DSP.
However, for the test suite, if I have a header with definitions
like:
#define CONTROL_FPGA_ENABLE (1 << 0)
#define CONTROL_FPGA_DONE_BIT (1 << 1)
that correspond to bits in a 32-bit PCI mmapped register. Then code in
the user-space test suite that did something like
pci_addr[CONTROL_OFFSET] |=3D CONTROL_FPGA_ENABLE;
would instead need to be re-written, eg.,
write_le32(&pci_addr[CONTROL_OFFSET], CONTROL_FPGA_ENABLE);
to be portable.
I definitely agree that this is how kernel-level code should be written,
but user-space code ... well, if I want to reuse code already written,
setting the page endian flag and reusing the code would seem like the
way to go. (This isn't what I need to do, since my host will still be an
x86, the PPC will be a target device, but I still need to think about
the endian issues).
Now of course that I have seen the consequences of my coding, I'll be
more careful to deal with endianness more appropriately.
Its a tricky trade-off though. I could define control ioctl's that hide
all the endianness issues ... but then the driver just gets bigger. I
think the appropriate solution for the user-space test code would be to
use CPU-to-little-endian routines, and wrap the lot in a re-usable
library that the test suite links against.
> There isn't a sysfs flag for the endianness page attribute since =20
> thats a PPC book-e specific feature. We could possible expand things
> to support it but, I've been trying to actively avoid using the 'E'
bit.
Ok, I haven't received the 8349E board that I am waiting on, so I hadn't
spotted that the PAGE_ENDIAN flag was Book E specific.
Thanks for your insight.
Cheers
Dave
^ permalink raw reply
* Re: [PATCH] Document Linux's memory barriers [try #5]
From: Linus Torvalds @ 2006-03-23 19:28 UTC (permalink / raw)
To: David Howells
Cc: akpm, linux-arch, linux-kernel, paulmck, davem, linuxppc64-dev
In-Reply-To: <895.1143138867@warthog.cambridge.redhat.com>
On Thu, 23 Mar 2006, David Howells wrote:
>
> > Some architectures have more expansive definition of data dependency,
> > including then- and else-clauses being data-dependent on the if-condition,
> > but this is probably too much detail.
>
> Linus calls that a "control dependency" and doesn't seem to think that's a
> problem as it's sorted out by branch prediction. What you said makes me
> wonder about conditional instructions (such as conditional move).
I'd put it the other way: a control dependency is not "sorted out" by
branch prediction, it is effectively _nullified_ by branch prediction.
Basically, control dependencies aren't dependencies at all. There is
absolutely _zero_ dependency between the following two loads:
if (load a)
load b;
because the "load b" can happen before the "load a" because of control
prediction.
So if you need a read barrier where there is a _control_ dependency in
between loading a and loading b, you need to make it a full "smp_rmb()".
It is _not_ sufficient to make this a "read_barrier_depends", because the
load of b really doesn't depend on the load of a at all.
So data dependencies that result in control dependencies aren't
dependencies at all. Not even if the address depends on the control
dependency.
So
int *address_of_b;
address_of_b = load(&a);
smp_read_barrier_depends();
b = load(address_of_b);
is correct, but
int *address_of_b = default_address_of_b;
if (load(&a))
address_of_b = another_address_of_b;
smp_read_barrier_depends();
b = load(address_of_b);
is NOT correct, because there is no data dependency on the load of b, just
a control dependency that the CPU may short-circuit with prediction, and
that second case thus needs a real smp_rmb().
And yes, if we ever hit a CPU that does actual data prediction, not just
control prediction, that will force smp_read_barrier_depends() to be the
same as smp_rmb() on such an architecture.
Linus
^ permalink raw reply
* Re: [PATCH] Document Linux's memory barriers [try #5]
From: David Howells @ 2006-03-23 18:34 UTC (permalink / raw)
To: paulmck, davem; +Cc: akpm, linux-arch, linux-kernel, torvalds, linuxppc64-dev
In-Reply-To: <20060316231723.GB1323@us.ibm.com>
Paul E. McKenney <paulmck@us.ibm.com> wrote:
> smp_mb__before_atomic_dec() and friends as well?
These seem to be something Sparc64 related; or, at least, Sparc64 seems to do
something weird with them.
What are these meant to achieve anyway? They seems to just be barrier() on a
lot of systems, even SMP ones.
> Some architectures have more expansive definition of data dependency,
> including then- and else-clauses being data-dependent on the if-condition,
> but this is probably too much detail.
Linus calls that a "control dependency" and doesn't seem to think that's a
problem as it's sorted out by branch prediction. What you said makes me
wonder about conditional instructions (such as conditional move).
Anyway, I've incorporated your comments as well as reworking the document,
which I'll shortly push upstream once again.
David
^ permalink raw reply
* Re: Memory mapping PCI memory region to user space
From: David Hawkins @ 2006-03-23 17:54 UTC (permalink / raw)
To: Mark Chambers; +Cc: Linuxppc-Embedded ((E-Mail))
In-Reply-To: <00be01c64ea1$4c6e0e20$6401a8c0@CHUCK2>
>
> PCI is actually endian-agnostic, so we're really 'fixing' the
> Freescale PCI implementation with endian swapping.
>
Hi Mark,
Its not agnostic, its little-endian.
The configuration space layout of parameters larger than a
byte are defined in little endian format.
The wiring on the PCI bus is little-endian, and 32-bit
quantities on the bus are represented by a logic analyzer
in little endian format.
But once you start talking about BAR regions, then yeah,
they're your bytes, do with them what you will. My hardware
uses a little-endian TI DSP, and an x86 host, so I
had been using compatible machines.
But the PLX PCI-9054 PCI chipset exposes BAR[0] and BAR[1]
as control registers that are little-endian format.
Conversely, we also use some Janz CAN cards, and their
messaging protocol over PCI uses big-endian format
structures in their protocol.
Dave
^ permalink raw reply
* Re: Memory mapping PCI memory region to user space
From: David Hawkins @ 2006-03-23 17:46 UTC (permalink / raw)
To: Kumar Gala; +Cc: Chris Wyse, Linuxppc-Embedded ((E-Mail))
In-Reply-To: <CCA437BF-E204-4652-9E6D-25388225EFE8@kernel.crashing.org>
Hi Kumar,
>> When I was testing the Yosemite board as the host, I found
>> that I could set the endian flag on the mmapped page, which
>> then made the PCI device registers read as 32-bit quantities
>> read back with the same layout under both x86 and PPC
>> hosts.
>
> Hmm, I guess I would handle this like how the reset of the kernel
> handle is with the io routines handling the swapping. Not sure if
> there is any advantage to using the endian flag. I guess if you have
> something you are treating as just memory there would be.
I haven't used the feature, I just tested it to see what it did.
The application case I thought of was this; the PCI boards I built
(that I am revising, and replacing the DSP with a PPC) have an
8MB PCI region that I can mmap from the host. I have a test
suite that runs from the host that manipulates registers on the boards
to download FPGAs etc. When the boards are used in a real system,
the onboard DSP is generally used, and the host just talks to
the DSP.
However, for the test suite, if I have a header with definitions
like:
#define CONTROL_FPGA_ENABLE (1 << 0)
#define CONTROL_FPGA_DONE_BIT (1 << 1)
that correspond to bits in a 32-bit PCI mmapped register. Then
code in the user-space test suite that did something like
pci_addr[CONTROL_OFFSET] |= CONTROL_FPGA_ENABLE;
would instead need to be re-written, eg.,
write_le32(&pci_addr[CONTROL_OFFSET], CONTROL_FPGA_ENABLE);
to be portable.
I definitely agree that this is how kernel-level code should be
written, but user-space code ... well, if I want to reuse code
already written, setting the page endian flag and reusing the
code would seem like the way to go. (This isn't what I need
to do, since my host will still be an x86, the PPC will
be a target device, but I still need to think about the
endian issues).
Now of course that I have seen the consequences of my coding,
I'll be more careful to deal with endianness more appropriately.
Its a tricky trade-off though. I could define control ioctl's
that hide all the endianness issues ... but then the driver just
gets bigger. I think the appropriate solution for the user-space
test code would be to use CPU-to-little-endian routines, and
wrap the lot in a re-usable library that the test suite
links against.
> There isn't a sysfs flag for the endianness page attribute since thats
> a PPC book-e specific feature. We could possible expand things to
> support it but, I've been trying to actively avoid using the 'E' bit.
Ok, I haven't received the 8349E board that I am waiting
on, so I hadn't spotted that the PAGE_ENDIAN flag was
Book E specific.
Thanks for your insight.
Cheers
Dave
^ permalink raw reply
* Re: Memory mapping PCI memory region to user space
From: Mark Chambers @ 2006-03-23 17:43 UTC (permalink / raw)
To: Linuxppc-Embedded ((E-Mail))
In-Reply-To: <CCA437BF-E204-4652-9E6D-25388225EFE8@kernel.crashing.org>
>>
>> When I was testing the Yosemite board as the host, I found
>> that I could set the endian flag on the mmapped page, which
>> then made the PCI device registers read as 32-bit quantities
>> read back with the same layout under both x86 and PPC
>> hosts.
>
> Hmm, I guess I would handle this like how the reset of the kernel
> handle is with the io routines handling the swapping. Not sure if
> there is any advantage to using the endian flag. I guess if you have
> something you are treating as just memory there would be.
>
>> So, if someone planned on using that 'feature', that would
>> be a reason for writing your own mmap() implementation.
>> I didn't see any option in the sysfs file for setting that
>> page flag (but, I didn't look around in other sysfs files).
>
> There isn't a sysfs flag for the endianness page attribute since
> thats a PPC book-e specific feature. We could possible expand things
> to support it but, I've been trying to actively avoid using the 'E' bit.
>
Framebuffer applications could care about this. Also, on the MPC8247
(maybe others, but I know about this one) you can make the PCI space
big- or little-endian.
Seems to me this is really not an endian issue but a PCI implementation
issue. PCI is actually endian-agnostic, so we're really 'fixing' the
Freescale
PCI implementation with endian swapping.
Mark Chambers
^ permalink raw reply
* Re: Memory mapping PCI memory region to user space
From: Kumar Gala @ 2006-03-23 17:19 UTC (permalink / raw)
To: David Hawkins; +Cc: Chris Wyse, Linuxppc-Embedded ((E-Mail))
In-Reply-To: <4422D6E3.1010407@ovro.caltech.edu>
On Mar 23, 2006, at 11:12 AM, David Hawkins wrote:
>
>
>> Why don't use the mmap file exposed by sysfs so you dont have to
>> write your own code?
>> See Documentation/filesystems/sysfs-pci.txt. But effectively
>> down under /sys/bus/pci/devices/[domain:bus:dev:func]/ you will
>> get resource[0..N-1] that corresponds to each BAR on the device.
>> This is a mmap file to access that region.
>
> Hi Kumar,
>
> Most likely he didn't know about it, I didn't :)
>
> When I was testing the Yosemite board as the host, I found
> that I could set the endian flag on the mmapped page, which
> then made the PCI device registers read as 32-bit quantities
> read back with the same layout under both x86 and PPC
> hosts.
Hmm, I guess I would handle this like how the reset of the kernel
handle is with the io routines handling the swapping. Not sure if
there is any advantage to using the endian flag. I guess if you have
something you are treating as just memory there would be.
> So, if someone planned on using that 'feature', that would
> be a reason for writing your own mmap() implementation.
> I didn't see any option in the sysfs file for setting that
> page flag (but, I didn't look around in other sysfs files).
There isn't a sysfs flag for the endianness page attribute since
thats a PPC book-e specific feature. We could possible expand things
to support it but, I've been trying to actively avoid using the 'E' bit.
> Thanks for the pointer to the sysfs node!
No problem, its what we're here for :)
- kumar
^ permalink raw reply
* Re: swizzling pci irqs
From: Kumar Gala @ 2006-03-23 17:15 UTC (permalink / raw)
To: David Updegraff; +Cc: linuxppc-embedded
In-Reply-To: <dvuj1k$318$1@sea.gmane.org>
On Mar 23, 2006, at 10:40 AM, David Updegraff wrote:
> Kumar Gala wrote:
>> On Mar 22, 2006, at 2:59 PM, David Updegraff wrote:
>>
>>
>>> Hi.
>>>
>>> If there were a noswizzle option to the kernel command line that
>>> resulted in pci scan simply trusting that the bootrom/u-boot had
>>> already
>>> correctly assigned the PCI irqs.... every tom,dick,harry, and
>>> yours-truly wouldn't have to make a new platform to define the
>>> swizzle-o-the-day. Or have I already missed this argument?
>>
>>
>> Sure, I do this now. Just don't build pci_auto into your pci support
>> and don't explicitly rescan in your pci setup. The 83xx pci code
>> under arch/powerpc should effective do this.
>>
>> - kumar
>
> Hmm; I must be missing something... cuz to me it looks like pci_32.c
> will allways call pcibios_init, which will will scan the bus, which
> will
> swizzle irqs if the platform has non-null swizzle and map_irq function
> pointers defined.. Perhaps a setting I've missed somewhere re.
> 'pci_auto', which I thought was a 'ppc' thing, not a 'powerpc'
> thing..??
Ahh, why do you have swizzle and map_irq functions? I guess I forgot
that part. In my setup I have u-boot do all IRQ assignment (via PCI
IRQ line register) as well as all BAR config. I just leave swizzle
and map_irq null.
- kumar
^ permalink raw reply
* Re: new sound driver
From: Johannes Berg @ 2006-03-23 17:13 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, Alastair Poole
In-Reply-To: <1143064237.3823.29.camel@localhost.localdomain>
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On Thu, 2006-03-23 at 08:50 +1100, Benjamin Herrenschmidt wrote:
> that would make soundbus totally pmac specific, in which case you should
> call it aoa-bus or something like that.
Yeah, well, I just did it differently now with the dbdma stuff done by
the i2sbus objects.
> Regarding your previous question well... I think the soundbus can create
> the pcm streams. Alsa has 2 levels: PCM objects and PCM substreams. We
> need the former. Substreams are used when the harware has several
> streams that are hw mixed to the same mixers which isn't the case with
> apple layout. When we have multiple i2s busses, they are really
> independant with separate codecs, frame rates & formats etc.. thus
> separate PCM objects.
>
> I think the sound bus should create the PCMs. Now I don't remember from
> Alsa API but do we need to know the available rates in advance ? In that
> case, we may want to have the bitmask provided by the fabric (from the
> layout array for example).
Right. I was still confused on the notion of PCM streams vs. objects.
Got that sorted out, and yes, it is creating pcm objects.
> I'm also not sure how Alsa handle changes there. For example, if you
> plug a digital input, the entire bus where this input is has to be
> clocked from that, thus limiting dynamically what rates/formats are
> available. I'm not sure Alsa API can cope with that yet.
Well, if we're unlucky the Alsa API must just return -EINVAL to users
trying to use other bitrates, if we're lucky then it copes better ;)
> > Actually, this isn't quite possible. On the newer machines where you
> > have two codecs on the same i2s bus, we need to have the layout fabric
> > create the one pcm stream and have it ask the codecs what it should
> > advertise. Then it needs to advertise the lowest common denominator of
> > the multiple codecs... (Or can alsa handle pcms that change their
> > supported rates/formats?) Then it refers to the soundbus functions for
> > actual data transmission.
>
> The problem is that codec objects have to be created asynchronously
> since they use asynchronous i2c discovery. Unless you instanciate them
> all but simply mark them "offline" and then mark them "online" later
> when the hardware actually shows up. That is fine except for .. topaz
> where you need to access the hw to know the chip type, thus you can't
> really know everything you need early enough (or maybe you can ...)
What I'm currently thinking of is creating one PCM per codec, and then
if you can't use them at the same time just forbid access to it.
> Just sleep on it for now :) We definitely need a "core" module that
> handles all of the gpio mess. ..
Yeah. Haven't even opened that can of worms yet...
johannes
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^ permalink raw reply
* Re: Memory mapping PCI memory region to user space
From: David Hawkins @ 2006-03-23 17:12 UTC (permalink / raw)
To: Kumar Gala; +Cc: Wyse, Chris, +linux-embedded, linuxppc-embedded
In-Reply-To: <204E7000-3E88-4497-86C0-5AF786D72F75@kernel.crashing.org>
> Why don't use the mmap file exposed by sysfs so you dont have to
> write your own code?
>
> See Documentation/filesystems/sysfs-pci.txt. But effectively down
> under /sys/bus/pci/devices/[domain:bus:dev:func]/ you will get
> resource[0..N-1] that corresponds to each BAR on the device. This is
> a mmap file to access that region.
Hi Kumar,
Most likely he didn't know about it, I didn't :)
When I was testing the Yosemite board as the host, I found
that I could set the endian flag on the mmapped page, which
then made the PCI device registers read as 32-bit quantities
read back with the same layout under both x86 and PPC
hosts.
So, if someone planned on using that 'feature', that would
be a reason for writing your own mmap() implementation.
I didn't see any option in the sysfs file for setting that
page flag (but, I didn't look around in other sysfs files).
Thanks for the pointer to the sysfs node!
Cheers
Dave
^ permalink raw reply
* Re: Memory mapping PCI memory region to user space
From: David Hawkins @ 2006-03-23 17:04 UTC (permalink / raw)
To: Wyse, Chris; +Cc: +linux-embedded, linuxppc-embedded
In-Reply-To: <B1E46DE837A394458BB1A58F74A66A780596CB@ala-mail02.corp.ad.wrs.com>
> I'm trying to map a PCI memory region 1 into user space from my driver
> (PPC440GX, Linux 2.6.10). Here's the mmap routine of the driver that
> I'm using:
Hi Chris,
I wrote a generic PCI IO driver when testing the
Yosemite 440EP, take a look at the code, its fairly
well commented. You probably just need to add the
PCI vendor ID for your target board:
(or you can echo the deviceID:vendorID to the
sysfs node for the driver)
http://www.ovro.caltech.edu/~dwh/pci_io.tar.gz
There's some comments in here on it:
http://www.ovro.caltech.edu/~dwh/correlator/pdf/LNX-723-Hawkins.pdf
For example, on an x86 system, I was looking for
a PLX PCI9054 10b5:9054, and then on the yosemite
board I was looking for the same hardware.
In your case, its not clear from your email whether you
are on a 440GX looking for another device, or on a host
looking for a 440GX. Either way, the driver should work.
Cheers
Dave
^ permalink raw reply
* Re: new sound driver
From: Johannes Berg @ 2006-03-23 17:00 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Alastair Poole
In-Reply-To: <1143020119.11724.41.camel@localhost>
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Obviously, I'm still collecting information. For future reference and
archiving, here's the contents of a file I just added to my code
describing how apple derives i2s clocks. Well, as far as I can see from
their code.
Short description of the i2s clock derivation system Apple uses.
The i2s chip Apple uses has three available clocks: 18432000, 45158400 and
49152000 Hz. These are used to drive the codec's system clock as well as the
i2s transfer bus.
The clocks for these are derived as follows:
First, you need to know the sampling frequency you want to use, and the
system clock the codec requires. The pcm3052 (onyx) for example requires a
system clock of 256*sampling frequency.
Thus, you divide the clock source speed by the sampling frequency and then
the factor the codec chip requires. This is the 'mclk divisor'.
Now you can derive the system clock from the clock source by taking only
every 'mclk divisor' transition of the clock, and thus you get a system
clock of the required speed.
Next, you need to know the i2s bus speed wrt. the sampling frequency. For
Sony and I2S 32x serial formats, this is 32*sampling frequency, for the I2S
64x format it is 64*sampling frequency. Since the i2s wire clock is derived
from the system clock we have already derived from the clock source, you
need to put as 'sclk divisor' the factor between the system clock of the
codec and the bus clock, for example 256/32 (=8) if the codec is driven in
Sony mode.
For the 'sclk divisor' you have to take care that it is an even number or 1
or 3, other values cannot be represented to the i2s chip (see logic in
i2sbus.h).
With a codec system clock (MClk) of 256*sampling frequency, you can have the
following frequencies (in the range from 8KHz to 96KHz) depending on the
clock source you use:
18432000: 9000 12000 14400 18000 24000 36000 72000
45158400: 8820 9800 11025 12600 14700 17640 22050 29400 35280 44100 58800 88200
49152000: 8000 9600 12000 16000 19200 24000 32000 38400 48000 64000 96000
(this is exactly what we can do with the onyx chip)
to create this table use calc (debian package apcalc):
min=8000
max=96000
clock=49152000
factor=256
for (f=min;f<=max;f++) {
if ((clock%f==0) && ((clock/f)%factor == 0)) {
div = clock/f/factor ;
n = ceil(div/2-1) ;
if ((div==1||div==3||div==5||div==14||(2*(n+1)==div && n<0x1f))
&& (1))
print f,
}
}
print ''
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^ permalink raw reply
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