* [PATCH] powerpc: fix idr locking in init_new_context
From: Sonny Rao @ 2006-06-27 12:46 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, linux-kernel, anton
We always need to serialize accesses to mmu_context_idr.
I hit this bug when testing with a small number of mmu contexts.
Signed-off-by: Sonny Rao <sonny@burdell.org>
--- a/arch/powerpc/mm/mmu_context_64.c
+++ b/arch/powerpc/mm/mmu_context_64.c
@@ -44,7 +44,9 @@ again:
return err;
if (index > MAX_CONTEXT) {
+ spin_lock(&mmu_context_lock);
idr_remove(&mmu_context_idr, index);
+ spin_unlock(&mmu_context_lock);
return -ENOMEM;
}
^ permalink raw reply
* How to search in this mailing-list?
From: Stephen Cheng @ 2006-06-27 13:23 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <mailman.1133.1151372366.11183.linuxppc-embedded@ozlabs.org>
[-- Attachment #1: Type: text/plain, Size: 151 bytes --]
hi ALL,
This is maybe a bit silly, but I really don't know:
How to search using some key words in this mailing-list?
Thanks & Best Regards,
Steven C.
[-- Attachment #2: Type: text/html, Size: 336 bytes --]
^ permalink raw reply
* Re: How to search in this mailing-list?
From: Florian Boelstler @ 2006-06-27 13:44 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <OF10AE4861.E394E791-ON4825719A.004971D0-4825719A.004991C4@celestica.com>
Stephen Cheng schrieb:
> This is maybe a bit silly, but I really don't know:
> How to search using some key words in this mailing-list?
You may use one of the options found here:
http://dir.gmane.org/gmane.linux.ports.ppc.embedded
Florian
^ permalink raw reply
* RE: How to search in this mailing-list?
From: Derycke, Johan @ 2006-06-27 13:40 UTC (permalink / raw)
To: Stephen Cheng, linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 1366 bytes --]
hi,
put this google, replace searchstring with whatever you are searching for:
searchstring site:ozlabs.org/pipermail
br,
Johan
_____
From: linuxppc-embedded-bounces+johan.derycke=barco.com@ozlabs.org
[mailto:linuxppc-embedded-bounces+johan.derycke=barco.com@ozlabs.org] On
Behalf Of Stephen Cheng
Sent: dinsdag 27 juni 2006 15:24
To: linuxppc-embedded@ozlabs.org
Subject: How to search in this mailing-list?
hi ALL,
This is maybe a bit silly, but I really don't know:
How to search using some key words in this mailing-list?
Thanks & Best Regards,
Steven C.
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^ permalink raw reply
* RE: How to search in this mailing-list?
From: Steven Blakeslee @ 2006-06-27 13:34 UTC (permalink / raw)
To: Stephen Cheng, linuxppc-embedded
=20
=09
> This is maybe a bit silly, but I really don't know:=20
> How to search using some key words in this mailing-list?=20
Go to google and do a site search
example
site:ozlabs.org/pipermail/linuxppc-embedded/ 440EP
=09
=09
^ permalink raw reply
* Re: [Alsa-devel] [RFC 01/12] snd-powermac: no longer handle anything with a layout-id property
From: Takashi Iwai @ 2006-06-27 14:29 UTC (permalink / raw)
To: Andreas Schwab; +Cc: linuxppc-dev, Johannes Berg, alsa-devel, netstar
In-Reply-To: <jey7vjiqwv.fsf@sykes.suse.de>
At Mon, 26 Jun 2006 22:49:04 +0200,
Andreas Schwab wrote:
>
> Johannes Berg <johannes@sipsolutions.net> writes:
>
> > This patch removes from snd-powermac the code that check for the layout-id
> > and instead adds code that makes it refuse loading when a layout-id property
> > is present, nothing that snd-aoa should be used.
>
> Can we get snd-powermac back as long as snd-aoa is lacking all those
> features from snd-powermac?
What functions are missing?
Takashi
^ permalink raw reply
* Re: [PATCH] Remove extra local_bh_disable/enable from arch do_softirq
From: Martin Schwidefsky @ 2006-06-27 11:43 UTC (permalink / raw)
To: Paul Mackerras; +Cc: akpm, linuxppc-dev, mingo, linux-kernel
In-Reply-To: <17566.32236.368906.227113@cargo.ozlabs.ibm.com>
On Sun, 2006-06-25 at 22:13 +1000, Paul Mackerras wrote:
> At the moment, powerpc and s390 have their own versions of do_softirq
> which include local_bh_disable() and __local_bh_enable() calls. They
> end up calling __do_softirq (in kernel/softirq.c) which also does
> local_bh_disable/enable.
>
> Apparently the two levels of disable/enable trigger a warning from
> some validation code that Ingo is working on, and he would like to see
> the outer level removed. But to do that, we have to move the
> account_system_vtime calls that are currently in the arch do_softirq()
> implementations for powerpc and s390 into the generic __do_softirq()
> (this is a no-op for other archs because account_system_vtime is
> defined to be an empty inline function on all other archs). This
> patch does that.
Nod, Heiko stumbled over that one as well as he ported the lock
validator patch. Moving the account_system_vtime call is the correct
solution.
--
blue skies,
Martin.
Martin Schwidefsky
Linux for zSeries Development & Services
IBM Deutschland Entwicklung GmbH
"Reality continues to ruin my life." - Calvin.
^ permalink raw reply
* Re: [Alsa-devel] [RFC 01/12] snd-powermac: no longer handle anything with a layout-id property
From: Andreas Schwab @ 2006-06-27 15:32 UTC (permalink / raw)
To: Takashi Iwai; +Cc: linuxppc-dev, Johannes Berg, alsa-devel, netstar
In-Reply-To: <s5hac7yvfhe.wl%tiwai@suse.de>
Takashi Iwai <tiwai@suse.de> writes:
> At Mon, 26 Jun 2006 22:49:04 +0200,
> Andreas Schwab wrote:
>>
>> Johannes Berg <johannes@sipsolutions.net> writes:
>>
>> > This patch removes from snd-powermac the code that check for the layout-id
>> > and instead adds code that makes it refuse loading when a layout-id property
>> > is present, nothing that snd-aoa should be used.
>>
>> Can we get snd-powermac back as long as snd-aoa is lacking all those
>> features from snd-powermac?
>
> What functions are missing?
Sound on PowerMac7,2, DRC on TAS, probably more.
Andreas.
--
Andreas Schwab, SuSE Labs, schwab@suse.de
SuSE Linux Products GmbH, Maxfeldstraße 5, 90409 Nürnberg, Germany
PGP key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5
"And now for something completely different."
^ permalink raw reply
* Re: 2.6.17-mm2
From: Martin J. Bligh @ 2006-06-27 15:37 UTC (permalink / raw)
To: Martin J. Bligh
Cc: Andrew Morton, linuxppc64-dev, Linux Kernel Mailing List,
Martin J. Bligh
In-Reply-To: <449FF3A2.8010907@mbligh.org>
Martin J. Bligh wrote:
> Martin J. Bligh wrote:
>
>> Panic on PPC64. I'm guessing it's the same as the i386 panics I sent
>> you yesterday, just more cryptic ;-) But for the record ...
>>
>> http://test.kernel.org/abat/37737/debug/console.log
>>
>> cpu 0x2: Vector: 300 (Data Access) at [c0000000f99f78c0]
>> pc: c0000000000c6a34: .s_show+0x178/0x364
>> lr: c0000000000c696c: .s_show+0xb0/0x364
>> sp: c0000000f99f7b40
>> msr: 8000000000001032
>> dar: fd528000
>> dsisr: 40000000
>> current = 0xc0000000f23e0000
>> paca = 0xc00000000046e300
>> pid = 17653, comm = cp
>> enter ? for help
>>
>
> Eeek, this is definitely an intermittent thing. I was trawling older
> results, and it shows up (on PPC only) in 2.6.17-git10, so it's not
> just an -mm thing ;-(
OK, still happens in -mm3, though in a different workload now. I also
get a new panic, that's maybe related but more informative
cpu 0x0: Vector: 700 (Program Check) at [c0000000024938b0]
pc: c0000000000c3218: .free_block+0xe4/0x240
lr: c0000000000c3514: .drain_array+0xf4/0x170
sp: c000000002493b30
msr: 8000000000021032
current = 0xc0000000025457f0
paca = 0xc0000000004f9f00
pid = 14, comm = events/0
kernel BUG in list_del at include/linux/list.h:160!
Plus one with an actual backtrace from PPC64 that looks more like the
i386 ones
SMP NR_CPUS=32 NUMA
Modules linked in:
NIP: C0000000000A311C LR: C0000000000A30D4 CTR: C0000000000A3024
REGS: c0000007725b38d0 TRAP: 0300 Not tainted (2.6.17-mm3-autokern1)
MSR: 8000000000001032 <ME,IR,DR> CR: 28224424 XER: 00000000
DAR: 000000077BCC6180, DSISR: 0000000040000000
TASK = c00000002fc74670[29812] 'cp' THREAD: c0000007725b0000 CPU: 2
GPR00: 0000000000000000 C0000007725B3B50 C00000000063B828 C00000001E303EC0
GPR04: 0000000000000010 0000000000000000 0000000000000000 FFFFFFFFFFFFFFFD
GPR08: 0000000000000001 0000000000000000 000000077BCC6180 0000000000000000
GPR12: 0000000000000000 C00000000051FF80 0000000000000000 0000000000000001
GPR16: 0000000000000000 0000000000000004 0000000000020000 0000000000000000
GPR20: 0000000000000000 0000000000000000 C0000007759F9D00 0000000000000000
GPR24: 0000000000000E42 0000000000000000 000000000000474A C00000001E30F300
GPR28: 0000000000000000 0000000000000000 C000000000537288 C00000001E303E80
NIP [C0000000000A311C] .s_show+0xf8/0x364
LR [C0000000000A30D4] .s_show+0xb0/0x364
Call Trace:
[C0000007725B3B50] [C0000000000A3334] .s_show+0x310/0x364 (unreliable)
[C0000007725B3C20] [C0000000000D5E84] .seq_read+0x2f4/0x450
[C0000007725B3D00] [C0000000000AADF8] .vfs_read+0xe0/0x1b4
[C0000007725B3D90] [C0000000000AAFD4] .sys_read+0x54/0x98
[C0000007725B3E30] [C00000000000871C] syscall_exit+0x0/0x40
Instruction dump:
3b180001 7c004a78 79290020 7c0bfe70 7f5a4a14 7d600278 7c005850 54000ffe
7c094038 2c090000 41820008 ebbe80b0 <e96a0000> 2fab0000 419e0008 7c005a2c
^ permalink raw reply
* Re: MPC8548 PCIe / PCI support with BSP MPC8548CDS 02/24/2006
From: Florian Boelstler @ 2006-06-27 16:06 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <9FCDBA58F226D911B202000BDBAD467306D93192@zch01exm40.ap.freescale.net>
Hi,
Zhang Wei-r63237 schrieb:
> It's an add-on PCIe patch. We have tested it on MPC8641, but we have no PCIe-PCI bridge on MPC8548 platform to do more test. So if you verify it, I'll commit it. :)
We did the hardware fix described in the BSP user's manual to make PCIe
work (according to the manual section 2.1, step 3).
I.e.
1) removed R193 and R194 on the carrier card (rev 1.2)
2) removed RN1 on the CPU daughter card
2a) connected pad3 of RN1 to pin3 of U12 (IRQ0)
2b) connected pad2 of RN1 to pin4 of U12 (IRQ1)
Does this fix the interrupt polarity problem (as well)?
We applied the provided kernel patch as well.
IMHO that patch just moves the local PCIe root-complex "out-of-space" so
no detection of that one occurs any more.
This is what actually happens when "lspci" is run.
However we still don't see any devices behind the PCIe switch (e.g. a
transparent PLX8516). It seems that the enumeration process (traversing
through the bus hierarchy) in the kernel is somehow disabled.
Bottom line: Only one device accessible at all on the PCIe port.
Any further ideas?
Thanks,
Florian
^ permalink raw reply
* Re: [RFC 01/12] snd-powermac: no longer handle anything with a layout-id property
From: Johannes Berg @ 2006-06-27 17:30 UTC (permalink / raw)
To: Andreas Schwab; +Cc: linuxppc-dev, alsa-devel, netstar
In-Reply-To: <jey7vjiqwv.fsf@sykes.suse.de>
[-- Attachment #1: Type: text/plain, Size: 374 bytes --]
On Mon, 2006-06-26 at 22:49 +0200, Andreas Schwab wrote:
> Can we get snd-powermac back as long as snd-aoa is lacking all those
> features from snd-powermac?
I'll be fixing it next week after an exam on Friday, or if I don't go to
Nuremburg next week (4h hacking on train :) ) then the week after.
Until then, you can just revert that patch locally.
johannes
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^ permalink raw reply
* Re: [PATCH] convert powermac ide blink to new led infrastructure
From: Johannes Berg @ 2006-06-27 17:31 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list, Richard Purdie
In-Reply-To: <1151394629.2350.64.camel@localhost.localdomain>
[-- Attachment #1: Type: text/plain, Size: 317 bytes --]
> Looks good. Only one nit: in pmu_led_set(), you should be able to test
> if the requested state is identical to the current one and do nothing
> without taking the lock no ?
>
> Or does the upper level LED infrastructure takes care of it ?
I don't know, Richard? But yeah, I can do that too.
johannes
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^ permalink raw reply
* Re: [Alsa-devel] [RFC 01/12] snd-powermac: no longer handle anything with a layout-id property
From: Johannes Berg @ 2006-06-27 17:40 UTC (permalink / raw)
To: Takashi Iwai; +Cc: alsa-devel, netstar, linuxppc-dev
In-Reply-To: <s5hac7yvfhe.wl%tiwai@suse.de>
[-- Attachment #1: Type: text/plain, Size: 251 bytes --]
On Tue, 2006-06-27 at 16:29 +0200, Takashi Iwai wrote:
> What functions are missing?
I think Andreas is referring to the fact that the device-trees on
PowerMac7,2 and 7,3 are broken and hence snd-aoa-i2sbus doesn't work
properly.
johannes
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^ permalink raw reply
* [PATCH] powerpc: remove kconfig warning
From: Olof Johansson @ 2006-06-27 18:14 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, arnd
scripts/kconfig/conf -s arch/powerpc/Kconfig
arch/powerpc/Kconfig:416:warning: leading whitespace ignored
Signed-off-by: Olof Johansson <olof@lixom.net>
Index: linux-2.6/arch/powerpc/Kconfig
===================================================================
--- linux-2.6.orig/arch/powerpc/Kconfig
+++ linux-2.6/arch/powerpc/Kconfig
@@ -413,7 +413,7 @@ config PPC_CELL_NATIVE
default n
config PPC_IBM_CELL_BLADE
- bool " IBM Cell Blade"
+ bool "IBM Cell Blade"
depends on PPC_MULTIPLATFORM && PPC64
select PPC_CELL_NATIVE
select PPC_RTAS
^ permalink raw reply
* [PATCH] fix windfarm core thread wrt. signal handling
From: Johannes Berg @ 2006-06-27 18:17 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Rafael J. Wysocki, linuxppc-dev list, linux-pm
In-Reply-To: <1151394268.2350.61.camel@localhost.localdomain>
This patch removes the signal_pending() from the windfarm core thread
loop as it isn't necessary and messes up when there actually *is* a
signal pending because we should enter the freezer.
Signed-off-by: Johannes Berg <johannes@sipsolutions.net>
diff --git a/drivers/macintosh/windfarm_core.c b/drivers/macintosh/windfarm_core.c
index ab3faa7..c05a838 100644
--- a/drivers/macintosh/windfarm_core.c
+++ b/drivers/macintosh/windfarm_core.c
@@ -116,12 +116,6 @@ static int wf_thread_func(void *data)
delay = next - jiffies;
if (delay <= HZ)
schedule_timeout_interruptible(delay);
-
- /* there should be no signal, but oh well */
- if (signal_pending(current)) {
- printk(KERN_WARNING "windfarm: thread got sigl !\n");
- break;
- }
}
DBG("wf: thread stopped\n");
^ permalink raw reply related
* Lite5200 MTD partitions in 2.6 build
From: Rowan, Chad @ 2006-06-27 18:38 UTC (permalink / raw)
To: linuxppc-embedded
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In the 2.4 build I had to modify icecube.c in /linux/drivers/mtd/maps/ to
specify the u-boot, kernel image, and root fs partitions. Icecube.c doesn't
exist in the 2.6 drop. I got the top of the tree from the denx git
yesterday. How do you config the partitions for the 2.6 kernel?
Thanks,
Chad
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^ permalink raw reply
* [PATCH] powerpc: Do a bit more cpu init cleanups
From: Olof Johansson @ 2006-06-27 19:22 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
Cleanup CPU inits a bit more, Geoff Levand already did some earlier.
* Rename cpu_setup_power4.S to cpu_setup_ppc970.S
* Move CPU state save to cpu_setup, since cpu_setup is only ever done
on cpu 0 on 64-bit.
* Rename __restore_cpu_setup to __restore_cpu_setup_ppc970 since it's
only actually doing anything there, and check before calling instead
of in the function (no check needed on powermac).
* Same for __970_cpu_preinit
* Rename pSeries_secondary_smp_init to generic_secondary_smp_init since
everyone but powermac and iSeries use it.
Build tested with all 64-bit defconfigs, boot tested on power5 and
powermac.
Signed-off-by: Olof Johansson <olof@lixom.net>
Index: linux-2.6/arch/powerpc/kernel/Makefile
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/Makefile
+++ linux-2.6/arch/powerpc/kernel/Makefile
@@ -16,7 +16,7 @@ obj-y := semaphore.o cputable.o ptrac
obj-y += vdso32/
obj-$(CONFIG_PPC64) += setup_64.o binfmt_elf32.o sys_ppc32.o \
signal_64.o ptrace32.o \
- paca.o cpu_setup_power4.o \
+ paca.o cpu_setup_ppc970.o \
firmware.o sysfs.o
obj-$(CONFIG_PPC64) += vdso64/
obj-$(CONFIG_ALTIVEC) += vecemu.o vector.o
Index: linux-2.6/arch/powerpc/kernel/cpu_setup_power4.S
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/cpu_setup_power4.S
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * This file contains low level CPU setup functions.
- * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-
-#include <linux/config.h>
-#include <asm/processor.h>
-#include <asm/page.h>
-#include <asm/cputable.h>
-#include <asm/ppc_asm.h>
-#include <asm/asm-offsets.h>
-#include <asm/cache.h>
-
-_GLOBAL(__970_cpu_preinit)
- /*
- * Do nothing if not running in HV mode
- */
- mfmsr r0
- rldicl. r0,r0,4,63
- beqlr
-
- /*
- * Deal only with PPC970 and PPC970FX.
- */
- mfspr r0,SPRN_PVR
- srwi r0,r0,16
- cmpwi r0,0x39
- beq 1f
- cmpwi r0,0x3c
- beq 1f
- cmpwi r0,0x44
- bnelr
-1:
-
- /* Make sure HID4:rm_ci is off before MMU is turned off, that large
- * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
- * HID5:DCBZ32_ill
- */
- li r0,0
- mfspr r3,SPRN_HID4
- rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
- rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
- sync
- mtspr SPRN_HID4,r3
- isync
- sync
- mfspr r3,SPRN_HID5
- rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
- sync
- mtspr SPRN_HID5,r3
- isync
- sync
-
- /* Setup some basic HID1 features */
- mfspr r0,SPRN_HID1
- li r3,0x1200 /* enable i-fetch cacheability */
- sldi r3,r3,44 /* and prefetch */
- or r0,r0,r3
- mtspr SPRN_HID1,r0
- mtspr SPRN_HID1,r0
- isync
-
- /* Clear HIOR */
- li r0,0
- sync
- mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
- isync
- blr
-
-_GLOBAL(__setup_cpu_ppc970)
- mfspr r0,SPRN_HID0
- li r11,5 /* clear DOZE and SLEEP */
- rldimi r0,r11,52,8 /* set NAP and DPM */
- mtspr SPRN_HID0,r0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- sync
- isync
- blr
-
-/* Definitions for the table use to save CPU states */
-#define CS_HID0 0
-#define CS_HID1 8
-#define CS_HID4 16
-#define CS_HID5 24
-#define CS_SIZE 32
-
- .data
- .balign L1_CACHE_BYTES,0
-cpu_state_storage:
- .space CS_SIZE
- .balign L1_CACHE_BYTES,0
- .text
-
-/* Called in normal context to backup CPU 0 state. This
- * does not include cache settings. This function is also
- * called for machine sleep. This does not include the MMU
- * setup, BATs, etc... but rather the "special" registers
- * like HID0, HID1, HID4, etc...
- */
-_GLOBAL(__save_cpu_setup)
- /* Some CR fields are volatile, we back it up all */
- mfcr r7
-
- /* Get storage ptr */
- LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
-
- /* We only deal with 970 for now */
- mfspr r0,SPRN_PVR
- srwi r0,r0,16
- cmpwi r0,0x39
- beq 1f
- cmpwi r0,0x3c
- beq 1f
- cmpwi r0,0x44
- bne 2f
-
-1: /* Save HID0,1,4 and 5 */
- mfspr r3,SPRN_HID0
- std r3,CS_HID0(r5)
- mfspr r3,SPRN_HID1
- std r3,CS_HID1(r5)
- mfspr r3,SPRN_HID4
- std r3,CS_HID4(r5)
- mfspr r3,SPRN_HID5
- std r3,CS_HID5(r5)
-
-2:
- mtcr r7
- blr
-
-/* Called with no MMU context (typically MSR:IR/DR off) to
- * restore CPU state as backed up by the previous
- * function. This does not include cache setting
- */
-_GLOBAL(__restore_cpu_setup)
- /* Get storage ptr (FIXME when using anton reloc as we
- * are running with translation disabled here
- */
- LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
-
- /* We only deal with 970 for now */
- mfspr r0,SPRN_PVR
- srwi r0,r0,16
- cmpwi r0,0x39
- beq 1f
- cmpwi r0,0x3c
- beq 1f
- cmpwi r0,0x44
- bnelr
-
-1: /* Before accessing memory, we make sure rm_ci is clear */
- li r0,0
- mfspr r3,SPRN_HID4
- rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
- sync
- mtspr SPRN_HID4,r3
- isync
- sync
-
- /* Clear interrupt prefix */
- li r0,0
- sync
- mtspr SPRN_HIOR,0
- isync
-
- /* Restore HID0 */
- ld r3,CS_HID0(r5)
- sync
- isync
- mtspr SPRN_HID0,r3
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- sync
- isync
-
- /* Restore HID1 */
- ld r3,CS_HID1(r5)
- sync
- isync
- mtspr SPRN_HID1,r3
- mtspr SPRN_HID1,r3
- sync
- isync
-
- /* Restore HID4 */
- ld r3,CS_HID4(r5)
- sync
- isync
- mtspr SPRN_HID4,r3
- sync
- isync
-
- /* Restore HID5 */
- ld r3,CS_HID5(r5)
- sync
- isync
- mtspr SPRN_HID5,r3
- sync
- isync
- blr
-
Index: linux-2.6/arch/powerpc/kernel/cpu_setup_ppc970.S
===================================================================
--- /dev/null
+++ linux-2.6/arch/powerpc/kernel/cpu_setup_ppc970.S
@@ -0,0 +1,175 @@
+/*
+ * This file contains low level CPU setup functions.
+ * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/config.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+#include <asm/cputable.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/cache.h>
+
+_GLOBAL(__cpu_preinit_ppc970)
+ /* Do nothing if not running in HV mode */
+ mfmsr r0
+ rldicl. r0,r0,4,63
+ beqlr
+
+ /* Make sure HID4:rm_ci is off before MMU is turned off, that large
+ * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
+ * HID5:DCBZ32_ill
+ */
+ li r0,0
+ mfspr r3,SPRN_HID4
+ rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
+ rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
+ sync
+ mtspr SPRN_HID4,r3
+ isync
+ sync
+ mfspr r3,SPRN_HID5
+ rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
+ sync
+ mtspr SPRN_HID5,r3
+ isync
+ sync
+
+ /* Setup some basic HID1 features */
+ mfspr r0,SPRN_HID1
+ li r3,0x1200 /* enable i-fetch cacheability */
+ sldi r3,r3,44 /* and prefetch */
+ or r0,r0,r3
+ mtspr SPRN_HID1,r0
+ mtspr SPRN_HID1,r0
+ isync
+
+ /* Clear HIOR */
+ li r0,0
+ sync
+ mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
+ isync
+ blr
+
+/* Definitions for the table use to save CPU states */
+#define CS_HID0 0
+#define CS_HID1 8
+#define CS_HID4 16
+#define CS_HID5 24
+#define CS_SIZE 32
+
+ .data
+ .balign L1_CACHE_BYTES,0
+cpu_state_storage:
+ .space CS_SIZE
+ .balign L1_CACHE_BYTES,0
+ .text
+
+
+_GLOBAL(__setup_cpu_ppc970)
+ /* Do nothing if not running in HV mode */
+ mfmsr r0
+ rldicl. r0,r0,4,63
+ beqlr
+
+ mfspr r0,SPRN_HID0
+ li r11,5 /* clear DOZE and SLEEP */
+ rldimi r0,r11,52,8 /* set NAP and DPM */
+ mtspr SPRN_HID0,r0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ sync
+ isync
+
+ /* Save away cpu state */
+ LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
+
+ /* Save HID0,1,4 and 5 */
+ mfspr r3,SPRN_HID0
+ std r3,CS_HID0(r5)
+ mfspr r3,SPRN_HID1
+ std r3,CS_HID1(r5)
+ mfspr r3,SPRN_HID4
+ std r3,CS_HID4(r5)
+ mfspr r3,SPRN_HID5
+ std r3,CS_HID5(r5)
+
+ blr
+
+/* Called with no MMU context (typically MSR:IR/DR off) to
+ * restore CPU state as backed up by the previous
+ * function. This does not include cache setting
+ */
+_GLOBAL(__restore_cpu_setup_ppc970)
+ /* Do nothing if not running in HV mode */
+ mfmsr r0
+ rldicl. r0,r0,4,63
+ beqlr
+
+ LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
+ /* Before accessing memory, we make sure rm_ci is clear */
+ li r0,0
+ mfspr r3,SPRN_HID4
+ rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
+ sync
+ mtspr SPRN_HID4,r3
+ isync
+ sync
+
+ /* Clear interrupt prefix */
+ li r0,0
+ sync
+ mtspr SPRN_HIOR,0
+ isync
+
+ /* Restore HID0 */
+ ld r3,CS_HID0(r5)
+ sync
+ isync
+ mtspr SPRN_HID0,r3
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ sync
+ isync
+
+ /* Restore HID1 */
+ ld r3,CS_HID1(r5)
+ sync
+ isync
+ mtspr SPRN_HID1,r3
+ mtspr SPRN_HID1,r3
+ sync
+ isync
+
+ /* Restore HID4 */
+ ld r3,CS_HID4(r5)
+ sync
+ isync
+ mtspr SPRN_HID4,r3
+ sync
+ isync
+
+ /* Restore HID5 */
+ ld r3,CS_HID5(r5)
+ sync
+ isync
+ mtspr SPRN_HID5,r3
+ sync
+ isync
+ blr
+
Index: linux-2.6/arch/powerpc/kernel/head_64.S
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/head_64.S
+++ linux-2.6/arch/powerpc/kernel/head_64.S
@@ -152,7 +152,7 @@ _GLOBAL(__secondary_hold)
bne 100b
#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
- LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init)
+ LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
mtctr r4
mr r3,r24
bctr
@@ -1473,18 +1473,28 @@ fwnmi_data_area:
. = 0x8000
/*
- * On pSeries, secondary processors spin in the following code.
+ * On pSeries and most other platforms, secondary processors spin
+ * in the following code.
* At entry, r3 = this processor's number (physical cpu id)
*/
-_GLOBAL(pSeries_secondary_smp_init)
+_GLOBAL(generic_secondary_smp_init)
mr r24,r3
/* turn on 64-bit mode */
bl .enable_64b_mode
isync
- /* Copy some CPU settings from CPU 0 */
- bl .__restore_cpu_setup
+ /* Copy some CPU settings from CPU 0, only needed on PPC970{,FX,MP} */
+ mfspr r0,SPRN_PVR
+ srwi r0,r0,16
+ cmpwi r0,0x39 /* 970 */
+ beq 1f
+ cmpwi r0,0x3c /* 970FX */
+ beq 1f
+ cmpwi r0,0x44 /* 970MP */
+ bne 2f
+1: bl .__restore_cpu_setup_ppc970
+2:
/* Set up a paca value for this processor. Since we have the
* physical cpu id in r24, we need to search the pacas to find
@@ -1600,7 +1610,16 @@ _GLOBAL(__start_initialization_multiplat
bl .enable_64b_mode
/* Setup some critical 970 SPRs before switching MMU off */
- bl .__970_cpu_preinit
+ mfspr r0,SPRN_PVR
+ srwi r0,r0,16
+ cmpwi r0,0x39 /* 970 */
+ beq 1f
+ cmpwi r0,0x3c /* 970FX */
+ beq 1f
+ cmpwi r0,0x44 /* 970MP */
+ bne 2f
+1: bl .__cpu_preinit_ppc970
+2:
/* cpu # */
li r24,0
@@ -1771,7 +1790,7 @@ _GLOBAL(pmac_secondary_start)
isync
/* Copy some CPU settings from CPU 0 */
- bl .__restore_cpu_setup
+ bl .__restore_cpu_setup_ppc970
/* pSeries do that early though I don't think we really need it */
mfmsr r3
@@ -1921,12 +1940,6 @@ _STATIC(start_here_multiplatform)
mr r5,r26
bl .identify_cpu
- /* Save some low level config HIDs of CPU0 to be copied to
- * other CPUs later on, or used for suspend/resume
- */
- bl .__save_cpu_setup
- sync
-
/* Do very early kernel initializations, including initial hash table,
* stab and slb setup before we turn on relocation. */
Index: linux-2.6/arch/powerpc/platforms/cell/smp.c
===================================================================
--- linux-2.6.orig/arch/powerpc/platforms/cell/smp.c
+++ linux-2.6/arch/powerpc/platforms/cell/smp.c
@@ -58,7 +58,7 @@
*/
static cpumask_t of_spin_map;
-extern void pSeries_secondary_smp_init(unsigned long);
+extern void generic_secondary_smp_init(unsigned long);
/**
* smp_startup_cpu() - start the given cpu
@@ -75,7 +75,7 @@ static inline int __devinit smp_startup_
{
int status;
unsigned long start_here = __pa((u32)*((unsigned long *)
- pSeries_secondary_smp_init));
+ generic_secondary_smp_init));
unsigned int pcpu;
int start_cpu;
Index: linux-2.6/arch/powerpc/platforms/pseries/smp.c
===================================================================
--- linux-2.6.orig/arch/powerpc/platforms/pseries/smp.c
+++ linux-2.6/arch/powerpc/platforms/pseries/smp.c
@@ -63,7 +63,7 @@
*/
static cpumask_t of_spin_map;
-extern void pSeries_secondary_smp_init(unsigned long);
+extern void generic_secondary_smp_init(unsigned long);
#ifdef CONFIG_HOTPLUG_CPU
@@ -271,7 +271,7 @@ static inline int __devinit smp_startup_
{
int status;
unsigned long start_here = __pa((u32)*((unsigned long *)
- pSeries_secondary_smp_init));
+ generic_secondary_smp_init));
unsigned int pcpu;
int start_cpu;
^ permalink raw reply
* Re: Lite5200 MTD partitions in 2.6 build
From: White @ 2006-06-27 19:24 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <86EC6E02268B3D4BA41C1B0C61FB14E60AFCD219@mdcexc01.na.ops.local>
Am Tue, 27 Jun 2006 13:38:25 -0500 schrieb "Rowan, Chad"
<Chad.Rowan@thyssenkrupp.com> :
> In the 2.4 build I had to modify icecube.c in /linux/drivers/mtd/maps/ to
> specify the u-boot, kernel image, and root fs partitions. Icecube.c doesn't
> exist in the 2.6 drop. I got the top of the tree from the denx git
> yesterday. How do you config the partitions for the 2.6 kernel?
>
>
>
> Thanks,
> Chad
>
Please throw a look to the Platform Devices MTD memory Mapper.
(drivers/mtd/maps/plat-ram.c)
With this Info you can add the Info to the Plattform Device List. f.e.
in the Board Support File. (lite5200.c ?)
Good Luck,
Gabor
^ permalink raw reply
* Re: [PATCH] fix windfarm core thread wrt. signal handling
From: Benjamin Herrenschmidt @ 2006-06-27 22:07 UTC (permalink / raw)
To: Johannes Berg; +Cc: Rafael J. Wysocki, linuxppc-dev list, linux-pm
In-Reply-To: <1151432266.4289.6.camel@localhost>
On Tue, 2006-06-27 at 20:17 +0200, Johannes Berg wrote:
> This patch removes the signal_pending() from the windfarm core thread
> loop as it isn't necessary and messes up when there actually *is* a
> signal pending because we should enter the freezer.
>
> Signed-off-by: Johannes Berg <johannes@sipsolutions.net>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> diff --git a/drivers/macintosh/windfarm_core.c b/drivers/macintosh/windfarm_core.c
> index ab3faa7..c05a838 100644
> --- a/drivers/macintosh/windfarm_core.c
> +++ b/drivers/macintosh/windfarm_core.c
> @@ -116,12 +116,6 @@ static int wf_thread_func(void *data)
> delay = next - jiffies;
> if (delay <= HZ)
> schedule_timeout_interruptible(delay);
> -
> - /* there should be no signal, but oh well */
> - if (signal_pending(current)) {
> - printk(KERN_WARNING "windfarm: thread got sigl !\n");
> - break;
> - }
> }
>
> DBG("wf: thread stopped\n");
>
^ permalink raw reply
* Re: [PATCH] powerpc: Do a bit more cpu init cleanups
From: Benjamin Herrenschmidt @ 2006-06-27 22:20 UTC (permalink / raw)
To: Olof Johansson; +Cc: linuxppc-dev, paulus
In-Reply-To: <20060627192206.GB5130@pb15.lixom.net>
On Tue, 2006-06-27 at 12:22 -0700, Olof Johansson wrote:
> Cleanup CPU inits a bit more, Geoff Levand already did some earlier.
>
> * Rename cpu_setup_power4.S to cpu_setup_ppc970.S
> * Move CPU state save to cpu_setup, since cpu_setup is only ever done
> on cpu 0 on 64-bit.
Nah, keep that one separate, will be needed as soon as we start doing
some sleep/wake stuff for ppc64
> * Rename __restore_cpu_setup to __restore_cpu_setup_ppc970 since it's
> only actually doing anything there, and check before calling instead
> of in the function (no check needed on powermac).
I'd like to keep a generic save/restore.. that or we put then in
cputable.
> * Same for __970_cpu_preinit
> * Rename pSeries_secondary_smp_init to generic_secondary_smp_init since
> everyone but powermac and iSeries use it.
Ok.
> Build tested with all 64-bit defconfigs, boot tested on power5 and
> powermac.
>
> Signed-off-by: Olof Johansson <olof@lixom.net>
>
>
> Index: linux-2.6/arch/powerpc/kernel/Makefile
> ===================================================================
> --- linux-2.6.orig/arch/powerpc/kernel/Makefile
> +++ linux-2.6/arch/powerpc/kernel/Makefile
> @@ -16,7 +16,7 @@ obj-y := semaphore.o cputable.o ptrac
> obj-y += vdso32/
> obj-$(CONFIG_PPC64) += setup_64.o binfmt_elf32.o sys_ppc32.o \
> signal_64.o ptrace32.o \
> - paca.o cpu_setup_power4.o \
> + paca.o cpu_setup_ppc970.o \
> firmware.o sysfs.o
> obj-$(CONFIG_PPC64) += vdso64/
> obj-$(CONFIG_ALTIVEC) += vecemu.o vector.o
> Index: linux-2.6/arch/powerpc/kernel/cpu_setup_power4.S
> ===================================================================
> --- linux-2.6.orig/arch/powerpc/kernel/cpu_setup_power4.S
> +++ /dev/null
> @@ -1,216 +0,0 @@
> -/*
> - * This file contains low level CPU setup functions.
> - * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License
> - * as published by the Free Software Foundation; either version
> - * 2 of the License, or (at your option) any later version.
> - *
> - */
> -
> -#include <linux/config.h>
> -#include <asm/processor.h>
> -#include <asm/page.h>
> -#include <asm/cputable.h>
> -#include <asm/ppc_asm.h>
> -#include <asm/asm-offsets.h>
> -#include <asm/cache.h>
> -
> -_GLOBAL(__970_cpu_preinit)
> - /*
> - * Do nothing if not running in HV mode
> - */
> - mfmsr r0
> - rldicl. r0,r0,4,63
> - beqlr
> -
> - /*
> - * Deal only with PPC970 and PPC970FX.
> - */
> - mfspr r0,SPRN_PVR
> - srwi r0,r0,16
> - cmpwi r0,0x39
> - beq 1f
> - cmpwi r0,0x3c
> - beq 1f
> - cmpwi r0,0x44
> - bnelr
> -1:
> -
> - /* Make sure HID4:rm_ci is off before MMU is turned off, that large
> - * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
> - * HID5:DCBZ32_ill
> - */
> - li r0,0
> - mfspr r3,SPRN_HID4
> - rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
> - rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
> - sync
> - mtspr SPRN_HID4,r3
> - isync
> - sync
> - mfspr r3,SPRN_HID5
> - rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
> - sync
> - mtspr SPRN_HID5,r3
> - isync
> - sync
> -
> - /* Setup some basic HID1 features */
> - mfspr r0,SPRN_HID1
> - li r3,0x1200 /* enable i-fetch cacheability */
> - sldi r3,r3,44 /* and prefetch */
> - or r0,r0,r3
> - mtspr SPRN_HID1,r0
> - mtspr SPRN_HID1,r0
> - isync
> -
> - /* Clear HIOR */
> - li r0,0
> - sync
> - mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
> - isync
> - blr
> -
> -_GLOBAL(__setup_cpu_ppc970)
> - mfspr r0,SPRN_HID0
> - li r11,5 /* clear DOZE and SLEEP */
> - rldimi r0,r11,52,8 /* set NAP and DPM */
> - mtspr SPRN_HID0,r0
> - mfspr r0,SPRN_HID0
> - mfspr r0,SPRN_HID0
> - mfspr r0,SPRN_HID0
> - mfspr r0,SPRN_HID0
> - mfspr r0,SPRN_HID0
> - mfspr r0,SPRN_HID0
> - sync
> - isync
> - blr
> -
> -/* Definitions for the table use to save CPU states */
> -#define CS_HID0 0
> -#define CS_HID1 8
> -#define CS_HID4 16
> -#define CS_HID5 24
> -#define CS_SIZE 32
> -
> - .data
> - .balign L1_CACHE_BYTES,0
> -cpu_state_storage:
> - .space CS_SIZE
> - .balign L1_CACHE_BYTES,0
> - .text
> -
> -/* Called in normal context to backup CPU 0 state. This
> - * does not include cache settings. This function is also
> - * called for machine sleep. This does not include the MMU
> - * setup, BATs, etc... but rather the "special" registers
> - * like HID0, HID1, HID4, etc...
> - */
> -_GLOBAL(__save_cpu_setup)
> - /* Some CR fields are volatile, we back it up all */
> - mfcr r7
> -
> - /* Get storage ptr */
> - LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
> -
> - /* We only deal with 970 for now */
> - mfspr r0,SPRN_PVR
> - srwi r0,r0,16
> - cmpwi r0,0x39
> - beq 1f
> - cmpwi r0,0x3c
> - beq 1f
> - cmpwi r0,0x44
> - bne 2f
> -
> -1: /* Save HID0,1,4 and 5 */
> - mfspr r3,SPRN_HID0
> - std r3,CS_HID0(r5)
> - mfspr r3,SPRN_HID1
> - std r3,CS_HID1(r5)
> - mfspr r3,SPRN_HID4
> - std r3,CS_HID4(r5)
> - mfspr r3,SPRN_HID5
> - std r3,CS_HID5(r5)
> -
> -2:
> - mtcr r7
> - blr
> -
> -/* Called with no MMU context (typically MSR:IR/DR off) to
> - * restore CPU state as backed up by the previous
> - * function. This does not include cache setting
> - */
> -_GLOBAL(__restore_cpu_setup)
> - /* Get storage ptr (FIXME when using anton reloc as we
> - * are running with translation disabled here
> - */
> - LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
> -
> - /* We only deal with 970 for now */
> - mfspr r0,SPRN_PVR
> - srwi r0,r0,16
> - cmpwi r0,0x39
> - beq 1f
> - cmpwi r0,0x3c
> - beq 1f
> - cmpwi r0,0x44
> - bnelr
> -
> -1: /* Before accessing memory, we make sure rm_ci is clear */
> - li r0,0
> - mfspr r3,SPRN_HID4
> - rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
> - sync
> - mtspr SPRN_HID4,r3
> - isync
> - sync
> -
> - /* Clear interrupt prefix */
> - li r0,0
> - sync
> - mtspr SPRN_HIOR,0
> - isync
> -
> - /* Restore HID0 */
> - ld r3,CS_HID0(r5)
> - sync
> - isync
> - mtspr SPRN_HID0,r3
> - mfspr r3,SPRN_HID0
> - mfspr r3,SPRN_HID0
> - mfspr r3,SPRN_HID0
> - mfspr r3,SPRN_HID0
> - mfspr r3,SPRN_HID0
> - mfspr r3,SPRN_HID0
> - sync
> - isync
> -
> - /* Restore HID1 */
> - ld r3,CS_HID1(r5)
> - sync
> - isync
> - mtspr SPRN_HID1,r3
> - mtspr SPRN_HID1,r3
> - sync
> - isync
> -
> - /* Restore HID4 */
> - ld r3,CS_HID4(r5)
> - sync
> - isync
> - mtspr SPRN_HID4,r3
> - sync
> - isync
> -
> - /* Restore HID5 */
> - ld r3,CS_HID5(r5)
> - sync
> - isync
> - mtspr SPRN_HID5,r3
> - sync
> - isync
> - blr
> -
> Index: linux-2.6/arch/powerpc/kernel/cpu_setup_ppc970.S
> ===================================================================
> --- /dev/null
> +++ linux-2.6/arch/powerpc/kernel/cpu_setup_ppc970.S
> @@ -0,0 +1,175 @@
> +/*
> + * This file contains low level CPU setup functions.
> + * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + *
> + */
> +
> +#include <linux/config.h>
> +#include <asm/processor.h>
> +#include <asm/page.h>
> +#include <asm/cputable.h>
> +#include <asm/ppc_asm.h>
> +#include <asm/asm-offsets.h>
> +#include <asm/cache.h>
> +
> +_GLOBAL(__cpu_preinit_ppc970)
> + /* Do nothing if not running in HV mode */
> + mfmsr r0
> + rldicl. r0,r0,4,63
> + beqlr
> +
> + /* Make sure HID4:rm_ci is off before MMU is turned off, that large
> + * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
> + * HID5:DCBZ32_ill
> + */
> + li r0,0
> + mfspr r3,SPRN_HID4
> + rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
> + rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
> + sync
> + mtspr SPRN_HID4,r3
> + isync
> + sync
> + mfspr r3,SPRN_HID5
> + rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
> + sync
> + mtspr SPRN_HID5,r3
> + isync
> + sync
> +
> + /* Setup some basic HID1 features */
> + mfspr r0,SPRN_HID1
> + li r3,0x1200 /* enable i-fetch cacheability */
> + sldi r3,r3,44 /* and prefetch */
> + or r0,r0,r3
> + mtspr SPRN_HID1,r0
> + mtspr SPRN_HID1,r0
> + isync
> +
> + /* Clear HIOR */
> + li r0,0
> + sync
> + mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
> + isync
> + blr
> +
> +/* Definitions for the table use to save CPU states */
> +#define CS_HID0 0
> +#define CS_HID1 8
> +#define CS_HID4 16
> +#define CS_HID5 24
> +#define CS_SIZE 32
> +
> + .data
> + .balign L1_CACHE_BYTES,0
> +cpu_state_storage:
> + .space CS_SIZE
> + .balign L1_CACHE_BYTES,0
> + .text
> +
> +
> +_GLOBAL(__setup_cpu_ppc970)
> + /* Do nothing if not running in HV mode */
> + mfmsr r0
> + rldicl. r0,r0,4,63
> + beqlr
> +
> + mfspr r0,SPRN_HID0
> + li r11,5 /* clear DOZE and SLEEP */
> + rldimi r0,r11,52,8 /* set NAP and DPM */
> + mtspr SPRN_HID0,r0
> + mfspr r0,SPRN_HID0
> + mfspr r0,SPRN_HID0
> + mfspr r0,SPRN_HID0
> + mfspr r0,SPRN_HID0
> + mfspr r0,SPRN_HID0
> + mfspr r0,SPRN_HID0
> + sync
> + isync
> +
> + /* Save away cpu state */
> + LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
> +
> + /* Save HID0,1,4 and 5 */
> + mfspr r3,SPRN_HID0
> + std r3,CS_HID0(r5)
> + mfspr r3,SPRN_HID1
> + std r3,CS_HID1(r5)
> + mfspr r3,SPRN_HID4
> + std r3,CS_HID4(r5)
> + mfspr r3,SPRN_HID5
> + std r3,CS_HID5(r5)
> +
> + blr
> +
> +/* Called with no MMU context (typically MSR:IR/DR off) to
> + * restore CPU state as backed up by the previous
> + * function. This does not include cache setting
> + */
> +_GLOBAL(__restore_cpu_setup_ppc970)
> + /* Do nothing if not running in HV mode */
> + mfmsr r0
> + rldicl. r0,r0,4,63
> + beqlr
> +
> + LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
> + /* Before accessing memory, we make sure rm_ci is clear */
> + li r0,0
> + mfspr r3,SPRN_HID4
> + rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
> + sync
> + mtspr SPRN_HID4,r3
> + isync
> + sync
> +
> + /* Clear interrupt prefix */
> + li r0,0
> + sync
> + mtspr SPRN_HIOR,0
> + isync
> +
> + /* Restore HID0 */
> + ld r3,CS_HID0(r5)
> + sync
> + isync
> + mtspr SPRN_HID0,r3
> + mfspr r3,SPRN_HID0
> + mfspr r3,SPRN_HID0
> + mfspr r3,SPRN_HID0
> + mfspr r3,SPRN_HID0
> + mfspr r3,SPRN_HID0
> + mfspr r3,SPRN_HID0
> + sync
> + isync
> +
> + /* Restore HID1 */
> + ld r3,CS_HID1(r5)
> + sync
> + isync
> + mtspr SPRN_HID1,r3
> + mtspr SPRN_HID1,r3
> + sync
> + isync
> +
> + /* Restore HID4 */
> + ld r3,CS_HID4(r5)
> + sync
> + isync
> + mtspr SPRN_HID4,r3
> + sync
> + isync
> +
> + /* Restore HID5 */
> + ld r3,CS_HID5(r5)
> + sync
> + isync
> + mtspr SPRN_HID5,r3
> + sync
> + isync
> + blr
> +
> Index: linux-2.6/arch/powerpc/kernel/head_64.S
> ===================================================================
> --- linux-2.6.orig/arch/powerpc/kernel/head_64.S
> +++ linux-2.6/arch/powerpc/kernel/head_64.S
> @@ -152,7 +152,7 @@ _GLOBAL(__secondary_hold)
> bne 100b
>
> #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
> - LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init)
> + LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
> mtctr r4
> mr r3,r24
> bctr
> @@ -1473,18 +1473,28 @@ fwnmi_data_area:
> . = 0x8000
>
> /*
> - * On pSeries, secondary processors spin in the following code.
> + * On pSeries and most other platforms, secondary processors spin
> + * in the following code.
> * At entry, r3 = this processor's number (physical cpu id)
> */
> -_GLOBAL(pSeries_secondary_smp_init)
> +_GLOBAL(generic_secondary_smp_init)
> mr r24,r3
>
> /* turn on 64-bit mode */
> bl .enable_64b_mode
> isync
>
> - /* Copy some CPU settings from CPU 0 */
> - bl .__restore_cpu_setup
> + /* Copy some CPU settings from CPU 0, only needed on PPC970{,FX,MP} */
> + mfspr r0,SPRN_PVR
> + srwi r0,r0,16
> + cmpwi r0,0x39 /* 970 */
> + beq 1f
> + cmpwi r0,0x3c /* 970FX */
> + beq 1f
> + cmpwi r0,0x44 /* 970MP */
> + bne 2f
> +1: bl .__restore_cpu_setup_ppc970
> +2:
>
> /* Set up a paca value for this processor. Since we have the
> * physical cpu id in r24, we need to search the pacas to find
> @@ -1600,7 +1610,16 @@ _GLOBAL(__start_initialization_multiplat
> bl .enable_64b_mode
>
> /* Setup some critical 970 SPRs before switching MMU off */
> - bl .__970_cpu_preinit
> + mfspr r0,SPRN_PVR
> + srwi r0,r0,16
> + cmpwi r0,0x39 /* 970 */
> + beq 1f
> + cmpwi r0,0x3c /* 970FX */
> + beq 1f
> + cmpwi r0,0x44 /* 970MP */
> + bne 2f
> +1: bl .__cpu_preinit_ppc970
> +2:
>
> /* cpu # */
> li r24,0
> @@ -1771,7 +1790,7 @@ _GLOBAL(pmac_secondary_start)
> isync
>
> /* Copy some CPU settings from CPU 0 */
> - bl .__restore_cpu_setup
> + bl .__restore_cpu_setup_ppc970
>
> /* pSeries do that early though I don't think we really need it */
> mfmsr r3
> @@ -1921,12 +1940,6 @@ _STATIC(start_here_multiplatform)
> mr r5,r26
> bl .identify_cpu
>
> - /* Save some low level config HIDs of CPU0 to be copied to
> - * other CPUs later on, or used for suspend/resume
> - */
> - bl .__save_cpu_setup
> - sync
> -
> /* Do very early kernel initializations, including initial hash table,
> * stab and slb setup before we turn on relocation. */
>
> Index: linux-2.6/arch/powerpc/platforms/cell/smp.c
> ===================================================================
> --- linux-2.6.orig/arch/powerpc/platforms/cell/smp.c
> +++ linux-2.6/arch/powerpc/platforms/cell/smp.c
> @@ -58,7 +58,7 @@
> */
> static cpumask_t of_spin_map;
>
> -extern void pSeries_secondary_smp_init(unsigned long);
> +extern void generic_secondary_smp_init(unsigned long);
>
> /**
> * smp_startup_cpu() - start the given cpu
> @@ -75,7 +75,7 @@ static inline int __devinit smp_startup_
> {
> int status;
> unsigned long start_here = __pa((u32)*((unsigned long *)
> - pSeries_secondary_smp_init));
> + generic_secondary_smp_init));
> unsigned int pcpu;
> int start_cpu;
>
> Index: linux-2.6/arch/powerpc/platforms/pseries/smp.c
> ===================================================================
> --- linux-2.6.orig/arch/powerpc/platforms/pseries/smp.c
> +++ linux-2.6/arch/powerpc/platforms/pseries/smp.c
> @@ -63,7 +63,7 @@
> */
> static cpumask_t of_spin_map;
>
> -extern void pSeries_secondary_smp_init(unsigned long);
> +extern void generic_secondary_smp_init(unsigned long);
>
> #ifdef CONFIG_HOTPLUG_CPU
>
> @@ -271,7 +271,7 @@ static inline int __devinit smp_startup_
> {
> int status;
> unsigned long start_here = __pa((u32)*((unsigned long *)
> - pSeries_secondary_smp_init));
> + generic_secondary_smp_init));
> unsigned int pcpu;
> int start_cpu;
>
^ permalink raw reply
* Re: cpu power "management" for non-dfs chips with no pmu (for instance, 750cxe and mpc7447 in pegasos)
From: Benjamin Herrenschmidt @ 2006-06-27 22:43 UTC (permalink / raw)
To: matt; +Cc: linuxppc-dev
In-Reply-To: <018201c696b1$e942ba40$99dfdfdf@bakuhatsu.net>
> I am basically trying to evaluate if we can do ANYTHING to reduce
> power consumption of systems which are idle, as I have noticed that
> for running firmware (sitting at a Forth prompt) and booting a
> Linux kernel and doing some work (for instance a simple benchmark),
> power consumption barely changes at all. The difference between an
> idle G4 and a running G4 is negligible. RC5 makes a big difference
> but it is heavily tuned. Most people won't run RC5 all the time to
> stress the CPU to the level that it wants to draw a couple extra
> watts, I think.
Well, I would expect the Idle G4 to have a fairly good PM in the first
place due to the NAP mode... though we may not enable that on Pegasos.
It depends if the bridge supports the proper protocol to handle
snooping. The Discovery II is bad enough as it is, I wouldn't expect it
to support that in a non-buggy way unfortunately.
Ben.
^ permalink raw reply
* Re: cpu power "management" for non-dfs chips with no pmu (for instance, 750cxe and mpc7447 in pegasos)
From: Benjamin Herrenschmidt @ 2006-06-27 22:47 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
In-Reply-To: <E1Ftmcb-0007rG-QS@jdl.com>
> > ICTC is such a simple thing to support and you can slow down the CPU
> > pretty comprehensively (from halving to 255x in theory) with an on and
> > off flag. I am surprised nobody implemented a cpufreq governer even if
> > it is totally useless and gives no perceivable benefits..
>
> See? You _are_ contributing already. I encourage
> you to hit the linux-pm@lists.osdl.org list for a spell!
His question is very powerpc specific... I don't see the point of
bringing ICTC related discussions to linux-pm...
Now, we _did_ some experiemnts in the past and didn't see that much
improvements. That might have changed though, since those 744x/745x CPUs
cannot DOZE and we cannot use their NAP mode neither when idle on
Pegasdos, in which case ICTC might have some use there...
It's easy to tweak it, just test and tell us. I'm not sure if cpufreq is
the right interface though as the cpu frequency isn't actually changing.
Ben.
^ permalink raw reply
* Re: Fixed PPC SHA1
From: Benjamin Herrenschmidt @ 2006-06-27 22:50 UTC (permalink / raw)
To: linux; +Cc: linuxppc-dev, git
In-Reply-To: <20060623005456.21460.qmail@science.horizon.com>
On Thu, 2006-06-22 at 20:54 -0400, linux@horizon.com wrote:
> Here's the lwsi-based version that's slightly faster on a G5, but slightly
> slower on a G4.
I wouldn't bother with 2 versions... use the non-string version (string
operations will cause performance problems on other processors)
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Do a bit more cpu init cleanups
From: Olof Johansson @ 2006-06-27 22:54 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Olof Johansson, linuxppc-dev, paulus
In-Reply-To: <1151446849.2350.95.camel@localhost.localdomain>
On Wed, Jun 28, 2006 at 08:20:48AM +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2006-06-27 at 12:22 -0700, Olof Johansson wrote:
> > Cleanup CPU inits a bit more, Geoff Levand already did some earlier.
> >
> > * Rename cpu_setup_power4.S to cpu_setup_ppc970.S
>
> > * Move CPU state save to cpu_setup, since cpu_setup is only ever done
> > on cpu 0 on 64-bit.
>
> Nah, keep that one separate, will be needed as soon as we start doing
> some sleep/wake stuff for ppc64
Why? I can see having to restore the settings on wake, but not doing a
brand new cpu_setup.
> > * Rename __restore_cpu_setup to __restore_cpu_setup_ppc970 since it's
> > only actually doing anything there, and check before calling instead
> > of in the function (no check needed on powermac).
>
> I'd like to keep a generic save/restore.. that or we put then in
> cputable.
Keep? There never was one. :)
Since restore is called very first thing in smp secondary init, we don't
have cputable available.
> > * Same for __970_cpu_preinit
> > * Rename pSeries_secondary_smp_init to generic_secondary_smp_init since
> > everyone but powermac and iSeries use it.
>
> Ok.
-Olof
^ permalink raw reply
* Re: [PATCH] powerpc: Do a bit more cpu init cleanups
From: Benjamin Herrenschmidt @ 2006-06-27 23:07 UTC (permalink / raw)
To: Olof Johansson; +Cc: linuxppc-dev, paulus
In-Reply-To: <20060627225401.GC5130@pb15.lixom.net>
On Tue, 2006-06-27 at 15:54 -0700, Olof Johansson wrote:
> On Wed, Jun 28, 2006 at 08:20:48AM +1000, Benjamin Herrenschmidt wrote:
> > On Tue, 2006-06-27 at 12:22 -0700, Olof Johansson wrote:
> > > Cleanup CPU inits a bit more, Geoff Levand already did some earlier.
> > >
> > > * Rename cpu_setup_power4.S to cpu_setup_ppc970.S
> >
> > > * Move CPU state save to cpu_setup, since cpu_setup is only ever done
> > > on cpu 0 on 64-bit.
> >
> > Nah, keep that one separate, will be needed as soon as we start doing
> > some sleep/wake stuff for ppc64
>
> Why? I can see having to restore the settings on wake, but not doing a
> brand new cpu_setup.
No, a new save, not setup.
> > > * Rename __restore_cpu_setup to __restore_cpu_setup_ppc970 since it's
> > > only actually doing anything there, and check before calling instead
> > > of in the function (no check needed on powermac).
> >
> > I'd like to keep a generic save/restore.. that or we put then in
> > cputable.
>
> Keep? There never was one. :)
There is one for 32 bits :)
> Since restore is called very first thing in smp secondary init, we don't
> have cputable available.
We could easily
Ben.
^ permalink raw reply
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