* Re: [PATCH] convert powermac ide blink to new led infrastructure
From: Johannes Berg @ 2006-06-27 17:31 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev list, Richard Purdie
In-Reply-To: <1151394629.2350.64.camel@localhost.localdomain>
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> Looks good. Only one nit: in pmu_led_set(), you should be able to test
> if the requested state is identical to the current one and do nothing
> without taking the lock no ?
>
> Or does the upper level LED infrastructure takes care of it ?
I don't know, Richard? But yeah, I can do that too.
johannes
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* Re: [Alsa-devel] [RFC 01/12] snd-powermac: no longer handle anything with a layout-id property
From: Johannes Berg @ 2006-06-27 17:40 UTC (permalink / raw)
To: Takashi Iwai; +Cc: alsa-devel, netstar, linuxppc-dev
In-Reply-To: <s5hac7yvfhe.wl%tiwai@suse.de>
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On Tue, 2006-06-27 at 16:29 +0200, Takashi Iwai wrote:
> What functions are missing?
I think Andreas is referring to the fact that the device-trees on
PowerMac7,2 and 7,3 are broken and hence snd-aoa-i2sbus doesn't work
properly.
johannes
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* [PATCH] powerpc: remove kconfig warning
From: Olof Johansson @ 2006-06-27 18:14 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev, arnd
scripts/kconfig/conf -s arch/powerpc/Kconfig
arch/powerpc/Kconfig:416:warning: leading whitespace ignored
Signed-off-by: Olof Johansson <olof@lixom.net>
Index: linux-2.6/arch/powerpc/Kconfig
===================================================================
--- linux-2.6.orig/arch/powerpc/Kconfig
+++ linux-2.6/arch/powerpc/Kconfig
@@ -413,7 +413,7 @@ config PPC_CELL_NATIVE
default n
config PPC_IBM_CELL_BLADE
- bool " IBM Cell Blade"
+ bool "IBM Cell Blade"
depends on PPC_MULTIPLATFORM && PPC64
select PPC_CELL_NATIVE
select PPC_RTAS
^ permalink raw reply
* [PATCH] fix windfarm core thread wrt. signal handling
From: Johannes Berg @ 2006-06-27 18:17 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Rafael J. Wysocki, linuxppc-dev list, linux-pm
In-Reply-To: <1151394268.2350.61.camel@localhost.localdomain>
This patch removes the signal_pending() from the windfarm core thread
loop as it isn't necessary and messes up when there actually *is* a
signal pending because we should enter the freezer.
Signed-off-by: Johannes Berg <johannes@sipsolutions.net>
diff --git a/drivers/macintosh/windfarm_core.c b/drivers/macintosh/windfarm_core.c
index ab3faa7..c05a838 100644
--- a/drivers/macintosh/windfarm_core.c
+++ b/drivers/macintosh/windfarm_core.c
@@ -116,12 +116,6 @@ static int wf_thread_func(void *data)
delay = next - jiffies;
if (delay <= HZ)
schedule_timeout_interruptible(delay);
-
- /* there should be no signal, but oh well */
- if (signal_pending(current)) {
- printk(KERN_WARNING "windfarm: thread got sigl !\n");
- break;
- }
}
DBG("wf: thread stopped\n");
^ permalink raw reply related
* Lite5200 MTD partitions in 2.6 build
From: Rowan, Chad @ 2006-06-27 18:38 UTC (permalink / raw)
To: linuxppc-embedded
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In the 2.4 build I had to modify icecube.c in /linux/drivers/mtd/maps/ to
specify the u-boot, kernel image, and root fs partitions. Icecube.c doesn't
exist in the 2.6 drop. I got the top of the tree from the denx git
yesterday. How do you config the partitions for the 2.6 kernel?
Thanks,
Chad
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^ permalink raw reply
* [PATCH] powerpc: Do a bit more cpu init cleanups
From: Olof Johansson @ 2006-06-27 19:22 UTC (permalink / raw)
To: paulus; +Cc: linuxppc-dev
Cleanup CPU inits a bit more, Geoff Levand already did some earlier.
* Rename cpu_setup_power4.S to cpu_setup_ppc970.S
* Move CPU state save to cpu_setup, since cpu_setup is only ever done
on cpu 0 on 64-bit.
* Rename __restore_cpu_setup to __restore_cpu_setup_ppc970 since it's
only actually doing anything there, and check before calling instead
of in the function (no check needed on powermac).
* Same for __970_cpu_preinit
* Rename pSeries_secondary_smp_init to generic_secondary_smp_init since
everyone but powermac and iSeries use it.
Build tested with all 64-bit defconfigs, boot tested on power5 and
powermac.
Signed-off-by: Olof Johansson <olof@lixom.net>
Index: linux-2.6/arch/powerpc/kernel/Makefile
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/Makefile
+++ linux-2.6/arch/powerpc/kernel/Makefile
@@ -16,7 +16,7 @@ obj-y := semaphore.o cputable.o ptrac
obj-y += vdso32/
obj-$(CONFIG_PPC64) += setup_64.o binfmt_elf32.o sys_ppc32.o \
signal_64.o ptrace32.o \
- paca.o cpu_setup_power4.o \
+ paca.o cpu_setup_ppc970.o \
firmware.o sysfs.o
obj-$(CONFIG_PPC64) += vdso64/
obj-$(CONFIG_ALTIVEC) += vecemu.o vector.o
Index: linux-2.6/arch/powerpc/kernel/cpu_setup_power4.S
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/cpu_setup_power4.S
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- * This file contains low level CPU setup functions.
- * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- */
-
-#include <linux/config.h>
-#include <asm/processor.h>
-#include <asm/page.h>
-#include <asm/cputable.h>
-#include <asm/ppc_asm.h>
-#include <asm/asm-offsets.h>
-#include <asm/cache.h>
-
-_GLOBAL(__970_cpu_preinit)
- /*
- * Do nothing if not running in HV mode
- */
- mfmsr r0
- rldicl. r0,r0,4,63
- beqlr
-
- /*
- * Deal only with PPC970 and PPC970FX.
- */
- mfspr r0,SPRN_PVR
- srwi r0,r0,16
- cmpwi r0,0x39
- beq 1f
- cmpwi r0,0x3c
- beq 1f
- cmpwi r0,0x44
- bnelr
-1:
-
- /* Make sure HID4:rm_ci is off before MMU is turned off, that large
- * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
- * HID5:DCBZ32_ill
- */
- li r0,0
- mfspr r3,SPRN_HID4
- rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
- rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
- sync
- mtspr SPRN_HID4,r3
- isync
- sync
- mfspr r3,SPRN_HID5
- rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
- sync
- mtspr SPRN_HID5,r3
- isync
- sync
-
- /* Setup some basic HID1 features */
- mfspr r0,SPRN_HID1
- li r3,0x1200 /* enable i-fetch cacheability */
- sldi r3,r3,44 /* and prefetch */
- or r0,r0,r3
- mtspr SPRN_HID1,r0
- mtspr SPRN_HID1,r0
- isync
-
- /* Clear HIOR */
- li r0,0
- sync
- mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
- isync
- blr
-
-_GLOBAL(__setup_cpu_ppc970)
- mfspr r0,SPRN_HID0
- li r11,5 /* clear DOZE and SLEEP */
- rldimi r0,r11,52,8 /* set NAP and DPM */
- mtspr SPRN_HID0,r0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- mfspr r0,SPRN_HID0
- sync
- isync
- blr
-
-/* Definitions for the table use to save CPU states */
-#define CS_HID0 0
-#define CS_HID1 8
-#define CS_HID4 16
-#define CS_HID5 24
-#define CS_SIZE 32
-
- .data
- .balign L1_CACHE_BYTES,0
-cpu_state_storage:
- .space CS_SIZE
- .balign L1_CACHE_BYTES,0
- .text
-
-/* Called in normal context to backup CPU 0 state. This
- * does not include cache settings. This function is also
- * called for machine sleep. This does not include the MMU
- * setup, BATs, etc... but rather the "special" registers
- * like HID0, HID1, HID4, etc...
- */
-_GLOBAL(__save_cpu_setup)
- /* Some CR fields are volatile, we back it up all */
- mfcr r7
-
- /* Get storage ptr */
- LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
-
- /* We only deal with 970 for now */
- mfspr r0,SPRN_PVR
- srwi r0,r0,16
- cmpwi r0,0x39
- beq 1f
- cmpwi r0,0x3c
- beq 1f
- cmpwi r0,0x44
- bne 2f
-
-1: /* Save HID0,1,4 and 5 */
- mfspr r3,SPRN_HID0
- std r3,CS_HID0(r5)
- mfspr r3,SPRN_HID1
- std r3,CS_HID1(r5)
- mfspr r3,SPRN_HID4
- std r3,CS_HID4(r5)
- mfspr r3,SPRN_HID5
- std r3,CS_HID5(r5)
-
-2:
- mtcr r7
- blr
-
-/* Called with no MMU context (typically MSR:IR/DR off) to
- * restore CPU state as backed up by the previous
- * function. This does not include cache setting
- */
-_GLOBAL(__restore_cpu_setup)
- /* Get storage ptr (FIXME when using anton reloc as we
- * are running with translation disabled here
- */
- LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
-
- /* We only deal with 970 for now */
- mfspr r0,SPRN_PVR
- srwi r0,r0,16
- cmpwi r0,0x39
- beq 1f
- cmpwi r0,0x3c
- beq 1f
- cmpwi r0,0x44
- bnelr
-
-1: /* Before accessing memory, we make sure rm_ci is clear */
- li r0,0
- mfspr r3,SPRN_HID4
- rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
- sync
- mtspr SPRN_HID4,r3
- isync
- sync
-
- /* Clear interrupt prefix */
- li r0,0
- sync
- mtspr SPRN_HIOR,0
- isync
-
- /* Restore HID0 */
- ld r3,CS_HID0(r5)
- sync
- isync
- mtspr SPRN_HID0,r3
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- mfspr r3,SPRN_HID0
- sync
- isync
-
- /* Restore HID1 */
- ld r3,CS_HID1(r5)
- sync
- isync
- mtspr SPRN_HID1,r3
- mtspr SPRN_HID1,r3
- sync
- isync
-
- /* Restore HID4 */
- ld r3,CS_HID4(r5)
- sync
- isync
- mtspr SPRN_HID4,r3
- sync
- isync
-
- /* Restore HID5 */
- ld r3,CS_HID5(r5)
- sync
- isync
- mtspr SPRN_HID5,r3
- sync
- isync
- blr
-
Index: linux-2.6/arch/powerpc/kernel/cpu_setup_ppc970.S
===================================================================
--- /dev/null
+++ linux-2.6/arch/powerpc/kernel/cpu_setup_ppc970.S
@@ -0,0 +1,175 @@
+/*
+ * This file contains low level CPU setup functions.
+ * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/config.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+#include <asm/cputable.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/cache.h>
+
+_GLOBAL(__cpu_preinit_ppc970)
+ /* Do nothing if not running in HV mode */
+ mfmsr r0
+ rldicl. r0,r0,4,63
+ beqlr
+
+ /* Make sure HID4:rm_ci is off before MMU is turned off, that large
+ * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
+ * HID5:DCBZ32_ill
+ */
+ li r0,0
+ mfspr r3,SPRN_HID4
+ rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
+ rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
+ sync
+ mtspr SPRN_HID4,r3
+ isync
+ sync
+ mfspr r3,SPRN_HID5
+ rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
+ sync
+ mtspr SPRN_HID5,r3
+ isync
+ sync
+
+ /* Setup some basic HID1 features */
+ mfspr r0,SPRN_HID1
+ li r3,0x1200 /* enable i-fetch cacheability */
+ sldi r3,r3,44 /* and prefetch */
+ or r0,r0,r3
+ mtspr SPRN_HID1,r0
+ mtspr SPRN_HID1,r0
+ isync
+
+ /* Clear HIOR */
+ li r0,0
+ sync
+ mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
+ isync
+ blr
+
+/* Definitions for the table use to save CPU states */
+#define CS_HID0 0
+#define CS_HID1 8
+#define CS_HID4 16
+#define CS_HID5 24
+#define CS_SIZE 32
+
+ .data
+ .balign L1_CACHE_BYTES,0
+cpu_state_storage:
+ .space CS_SIZE
+ .balign L1_CACHE_BYTES,0
+ .text
+
+
+_GLOBAL(__setup_cpu_ppc970)
+ /* Do nothing if not running in HV mode */
+ mfmsr r0
+ rldicl. r0,r0,4,63
+ beqlr
+
+ mfspr r0,SPRN_HID0
+ li r11,5 /* clear DOZE and SLEEP */
+ rldimi r0,r11,52,8 /* set NAP and DPM */
+ mtspr SPRN_HID0,r0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ mfspr r0,SPRN_HID0
+ sync
+ isync
+
+ /* Save away cpu state */
+ LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
+
+ /* Save HID0,1,4 and 5 */
+ mfspr r3,SPRN_HID0
+ std r3,CS_HID0(r5)
+ mfspr r3,SPRN_HID1
+ std r3,CS_HID1(r5)
+ mfspr r3,SPRN_HID4
+ std r3,CS_HID4(r5)
+ mfspr r3,SPRN_HID5
+ std r3,CS_HID5(r5)
+
+ blr
+
+/* Called with no MMU context (typically MSR:IR/DR off) to
+ * restore CPU state as backed up by the previous
+ * function. This does not include cache setting
+ */
+_GLOBAL(__restore_cpu_setup_ppc970)
+ /* Do nothing if not running in HV mode */
+ mfmsr r0
+ rldicl. r0,r0,4,63
+ beqlr
+
+ LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
+ /* Before accessing memory, we make sure rm_ci is clear */
+ li r0,0
+ mfspr r3,SPRN_HID4
+ rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
+ sync
+ mtspr SPRN_HID4,r3
+ isync
+ sync
+
+ /* Clear interrupt prefix */
+ li r0,0
+ sync
+ mtspr SPRN_HIOR,0
+ isync
+
+ /* Restore HID0 */
+ ld r3,CS_HID0(r5)
+ sync
+ isync
+ mtspr SPRN_HID0,r3
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ mfspr r3,SPRN_HID0
+ sync
+ isync
+
+ /* Restore HID1 */
+ ld r3,CS_HID1(r5)
+ sync
+ isync
+ mtspr SPRN_HID1,r3
+ mtspr SPRN_HID1,r3
+ sync
+ isync
+
+ /* Restore HID4 */
+ ld r3,CS_HID4(r5)
+ sync
+ isync
+ mtspr SPRN_HID4,r3
+ sync
+ isync
+
+ /* Restore HID5 */
+ ld r3,CS_HID5(r5)
+ sync
+ isync
+ mtspr SPRN_HID5,r3
+ sync
+ isync
+ blr
+
Index: linux-2.6/arch/powerpc/kernel/head_64.S
===================================================================
--- linux-2.6.orig/arch/powerpc/kernel/head_64.S
+++ linux-2.6/arch/powerpc/kernel/head_64.S
@@ -152,7 +152,7 @@ _GLOBAL(__secondary_hold)
bne 100b
#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
- LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init)
+ LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
mtctr r4
mr r3,r24
bctr
@@ -1473,18 +1473,28 @@ fwnmi_data_area:
. = 0x8000
/*
- * On pSeries, secondary processors spin in the following code.
+ * On pSeries and most other platforms, secondary processors spin
+ * in the following code.
* At entry, r3 = this processor's number (physical cpu id)
*/
-_GLOBAL(pSeries_secondary_smp_init)
+_GLOBAL(generic_secondary_smp_init)
mr r24,r3
/* turn on 64-bit mode */
bl .enable_64b_mode
isync
- /* Copy some CPU settings from CPU 0 */
- bl .__restore_cpu_setup
+ /* Copy some CPU settings from CPU 0, only needed on PPC970{,FX,MP} */
+ mfspr r0,SPRN_PVR
+ srwi r0,r0,16
+ cmpwi r0,0x39 /* 970 */
+ beq 1f
+ cmpwi r0,0x3c /* 970FX */
+ beq 1f
+ cmpwi r0,0x44 /* 970MP */
+ bne 2f
+1: bl .__restore_cpu_setup_ppc970
+2:
/* Set up a paca value for this processor. Since we have the
* physical cpu id in r24, we need to search the pacas to find
@@ -1600,7 +1610,16 @@ _GLOBAL(__start_initialization_multiplat
bl .enable_64b_mode
/* Setup some critical 970 SPRs before switching MMU off */
- bl .__970_cpu_preinit
+ mfspr r0,SPRN_PVR
+ srwi r0,r0,16
+ cmpwi r0,0x39 /* 970 */
+ beq 1f
+ cmpwi r0,0x3c /* 970FX */
+ beq 1f
+ cmpwi r0,0x44 /* 970MP */
+ bne 2f
+1: bl .__cpu_preinit_ppc970
+2:
/* cpu # */
li r24,0
@@ -1771,7 +1790,7 @@ _GLOBAL(pmac_secondary_start)
isync
/* Copy some CPU settings from CPU 0 */
- bl .__restore_cpu_setup
+ bl .__restore_cpu_setup_ppc970
/* pSeries do that early though I don't think we really need it */
mfmsr r3
@@ -1921,12 +1940,6 @@ _STATIC(start_here_multiplatform)
mr r5,r26
bl .identify_cpu
- /* Save some low level config HIDs of CPU0 to be copied to
- * other CPUs later on, or used for suspend/resume
- */
- bl .__save_cpu_setup
- sync
-
/* Do very early kernel initializations, including initial hash table,
* stab and slb setup before we turn on relocation. */
Index: linux-2.6/arch/powerpc/platforms/cell/smp.c
===================================================================
--- linux-2.6.orig/arch/powerpc/platforms/cell/smp.c
+++ linux-2.6/arch/powerpc/platforms/cell/smp.c
@@ -58,7 +58,7 @@
*/
static cpumask_t of_spin_map;
-extern void pSeries_secondary_smp_init(unsigned long);
+extern void generic_secondary_smp_init(unsigned long);
/**
* smp_startup_cpu() - start the given cpu
@@ -75,7 +75,7 @@ static inline int __devinit smp_startup_
{
int status;
unsigned long start_here = __pa((u32)*((unsigned long *)
- pSeries_secondary_smp_init));
+ generic_secondary_smp_init));
unsigned int pcpu;
int start_cpu;
Index: linux-2.6/arch/powerpc/platforms/pseries/smp.c
===================================================================
--- linux-2.6.orig/arch/powerpc/platforms/pseries/smp.c
+++ linux-2.6/arch/powerpc/platforms/pseries/smp.c
@@ -63,7 +63,7 @@
*/
static cpumask_t of_spin_map;
-extern void pSeries_secondary_smp_init(unsigned long);
+extern void generic_secondary_smp_init(unsigned long);
#ifdef CONFIG_HOTPLUG_CPU
@@ -271,7 +271,7 @@ static inline int __devinit smp_startup_
{
int status;
unsigned long start_here = __pa((u32)*((unsigned long *)
- pSeries_secondary_smp_init));
+ generic_secondary_smp_init));
unsigned int pcpu;
int start_cpu;
^ permalink raw reply
* Re: Lite5200 MTD partitions in 2.6 build
From: White @ 2006-06-27 19:24 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <86EC6E02268B3D4BA41C1B0C61FB14E60AFCD219@mdcexc01.na.ops.local>
Am Tue, 27 Jun 2006 13:38:25 -0500 schrieb "Rowan, Chad"
<Chad.Rowan@thyssenkrupp.com> :
> In the 2.4 build I had to modify icecube.c in /linux/drivers/mtd/maps/ to
> specify the u-boot, kernel image, and root fs partitions. Icecube.c doesn't
> exist in the 2.6 drop. I got the top of the tree from the denx git
> yesterday. How do you config the partitions for the 2.6 kernel?
>
>
>
> Thanks,
> Chad
>
Please throw a look to the Platform Devices MTD memory Mapper.
(drivers/mtd/maps/plat-ram.c)
With this Info you can add the Info to the Plattform Device List. f.e.
in the Board Support File. (lite5200.c ?)
Good Luck,
Gabor
^ permalink raw reply
* Re: [PATCH] fix windfarm core thread wrt. signal handling
From: Benjamin Herrenschmidt @ 2006-06-27 22:07 UTC (permalink / raw)
To: Johannes Berg; +Cc: Rafael J. Wysocki, linuxppc-dev list, linux-pm
In-Reply-To: <1151432266.4289.6.camel@localhost>
On Tue, 2006-06-27 at 20:17 +0200, Johannes Berg wrote:
> This patch removes the signal_pending() from the windfarm core thread
> loop as it isn't necessary and messes up when there actually *is* a
> signal pending because we should enter the freezer.
>
> Signed-off-by: Johannes Berg <johannes@sipsolutions.net>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> diff --git a/drivers/macintosh/windfarm_core.c b/drivers/macintosh/windfarm_core.c
> index ab3faa7..c05a838 100644
> --- a/drivers/macintosh/windfarm_core.c
> +++ b/drivers/macintosh/windfarm_core.c
> @@ -116,12 +116,6 @@ static int wf_thread_func(void *data)
> delay = next - jiffies;
> if (delay <= HZ)
> schedule_timeout_interruptible(delay);
> -
> - /* there should be no signal, but oh well */
> - if (signal_pending(current)) {
> - printk(KERN_WARNING "windfarm: thread got sigl !\n");
> - break;
> - }
> }
>
> DBG("wf: thread stopped\n");
>
^ permalink raw reply
* Re: [PATCH] powerpc: Do a bit more cpu init cleanups
From: Benjamin Herrenschmidt @ 2006-06-27 22:20 UTC (permalink / raw)
To: Olof Johansson; +Cc: linuxppc-dev, paulus
In-Reply-To: <20060627192206.GB5130@pb15.lixom.net>
On Tue, 2006-06-27 at 12:22 -0700, Olof Johansson wrote:
> Cleanup CPU inits a bit more, Geoff Levand already did some earlier.
>
> * Rename cpu_setup_power4.S to cpu_setup_ppc970.S
> * Move CPU state save to cpu_setup, since cpu_setup is only ever done
> on cpu 0 on 64-bit.
Nah, keep that one separate, will be needed as soon as we start doing
some sleep/wake stuff for ppc64
> * Rename __restore_cpu_setup to __restore_cpu_setup_ppc970 since it's
> only actually doing anything there, and check before calling instead
> of in the function (no check needed on powermac).
I'd like to keep a generic save/restore.. that or we put then in
cputable.
> * Same for __970_cpu_preinit
> * Rename pSeries_secondary_smp_init to generic_secondary_smp_init since
> everyone but powermac and iSeries use it.
Ok.
> Build tested with all 64-bit defconfigs, boot tested on power5 and
> powermac.
>
> Signed-off-by: Olof Johansson <olof@lixom.net>
>
>
> Index: linux-2.6/arch/powerpc/kernel/Makefile
> ===================================================================
> --- linux-2.6.orig/arch/powerpc/kernel/Makefile
> +++ linux-2.6/arch/powerpc/kernel/Makefile
> @@ -16,7 +16,7 @@ obj-y := semaphore.o cputable.o ptrac
> obj-y += vdso32/
> obj-$(CONFIG_PPC64) += setup_64.o binfmt_elf32.o sys_ppc32.o \
> signal_64.o ptrace32.o \
> - paca.o cpu_setup_power4.o \
> + paca.o cpu_setup_ppc970.o \
> firmware.o sysfs.o
> obj-$(CONFIG_PPC64) += vdso64/
> obj-$(CONFIG_ALTIVEC) += vecemu.o vector.o
> Index: linux-2.6/arch/powerpc/kernel/cpu_setup_power4.S
> ===================================================================
> --- linux-2.6.orig/arch/powerpc/kernel/cpu_setup_power4.S
> +++ /dev/null
> @@ -1,216 +0,0 @@
> -/*
> - * This file contains low level CPU setup functions.
> - * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License
> - * as published by the Free Software Foundation; either version
> - * 2 of the License, or (at your option) any later version.
> - *
> - */
> -
> -#include <linux/config.h>
> -#include <asm/processor.h>
> -#include <asm/page.h>
> -#include <asm/cputable.h>
> -#include <asm/ppc_asm.h>
> -#include <asm/asm-offsets.h>
> -#include <asm/cache.h>
> -
> -_GLOBAL(__970_cpu_preinit)
> - /*
> - * Do nothing if not running in HV mode
> - */
> - mfmsr r0
> - rldicl. r0,r0,4,63
> - beqlr
> -
> - /*
> - * Deal only with PPC970 and PPC970FX.
> - */
> - mfspr r0,SPRN_PVR
> - srwi r0,r0,16
> - cmpwi r0,0x39
> - beq 1f
> - cmpwi r0,0x3c
> - beq 1f
> - cmpwi r0,0x44
> - bnelr
> -1:
> -
> - /* Make sure HID4:rm_ci is off before MMU is turned off, that large
> - * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
> - * HID5:DCBZ32_ill
> - */
> - li r0,0
> - mfspr r3,SPRN_HID4
> - rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
> - rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
> - sync
> - mtspr SPRN_HID4,r3
> - isync
> - sync
> - mfspr r3,SPRN_HID5
> - rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
> - sync
> - mtspr SPRN_HID5,r3
> - isync
> - sync
> -
> - /* Setup some basic HID1 features */
> - mfspr r0,SPRN_HID1
> - li r3,0x1200 /* enable i-fetch cacheability */
> - sldi r3,r3,44 /* and prefetch */
> - or r0,r0,r3
> - mtspr SPRN_HID1,r0
> - mtspr SPRN_HID1,r0
> - isync
> -
> - /* Clear HIOR */
> - li r0,0
> - sync
> - mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
> - isync
> - blr
> -
> -_GLOBAL(__setup_cpu_ppc970)
> - mfspr r0,SPRN_HID0
> - li r11,5 /* clear DOZE and SLEEP */
> - rldimi r0,r11,52,8 /* set NAP and DPM */
> - mtspr SPRN_HID0,r0
> - mfspr r0,SPRN_HID0
> - mfspr r0,SPRN_HID0
> - mfspr r0,SPRN_HID0
> - mfspr r0,SPRN_HID0
> - mfspr r0,SPRN_HID0
> - mfspr r0,SPRN_HID0
> - sync
> - isync
> - blr
> -
> -/* Definitions for the table use to save CPU states */
> -#define CS_HID0 0
> -#define CS_HID1 8
> -#define CS_HID4 16
> -#define CS_HID5 24
> -#define CS_SIZE 32
> -
> - .data
> - .balign L1_CACHE_BYTES,0
> -cpu_state_storage:
> - .space CS_SIZE
> - .balign L1_CACHE_BYTES,0
> - .text
> -
> -/* Called in normal context to backup CPU 0 state. This
> - * does not include cache settings. This function is also
> - * called for machine sleep. This does not include the MMU
> - * setup, BATs, etc... but rather the "special" registers
> - * like HID0, HID1, HID4, etc...
> - */
> -_GLOBAL(__save_cpu_setup)
> - /* Some CR fields are volatile, we back it up all */
> - mfcr r7
> -
> - /* Get storage ptr */
> - LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
> -
> - /* We only deal with 970 for now */
> - mfspr r0,SPRN_PVR
> - srwi r0,r0,16
> - cmpwi r0,0x39
> - beq 1f
> - cmpwi r0,0x3c
> - beq 1f
> - cmpwi r0,0x44
> - bne 2f
> -
> -1: /* Save HID0,1,4 and 5 */
> - mfspr r3,SPRN_HID0
> - std r3,CS_HID0(r5)
> - mfspr r3,SPRN_HID1
> - std r3,CS_HID1(r5)
> - mfspr r3,SPRN_HID4
> - std r3,CS_HID4(r5)
> - mfspr r3,SPRN_HID5
> - std r3,CS_HID5(r5)
> -
> -2:
> - mtcr r7
> - blr
> -
> -/* Called with no MMU context (typically MSR:IR/DR off) to
> - * restore CPU state as backed up by the previous
> - * function. This does not include cache setting
> - */
> -_GLOBAL(__restore_cpu_setup)
> - /* Get storage ptr (FIXME when using anton reloc as we
> - * are running with translation disabled here
> - */
> - LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
> -
> - /* We only deal with 970 for now */
> - mfspr r0,SPRN_PVR
> - srwi r0,r0,16
> - cmpwi r0,0x39
> - beq 1f
> - cmpwi r0,0x3c
> - beq 1f
> - cmpwi r0,0x44
> - bnelr
> -
> -1: /* Before accessing memory, we make sure rm_ci is clear */
> - li r0,0
> - mfspr r3,SPRN_HID4
> - rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
> - sync
> - mtspr SPRN_HID4,r3
> - isync
> - sync
> -
> - /* Clear interrupt prefix */
> - li r0,0
> - sync
> - mtspr SPRN_HIOR,0
> - isync
> -
> - /* Restore HID0 */
> - ld r3,CS_HID0(r5)
> - sync
> - isync
> - mtspr SPRN_HID0,r3
> - mfspr r3,SPRN_HID0
> - mfspr r3,SPRN_HID0
> - mfspr r3,SPRN_HID0
> - mfspr r3,SPRN_HID0
> - mfspr r3,SPRN_HID0
> - mfspr r3,SPRN_HID0
> - sync
> - isync
> -
> - /* Restore HID1 */
> - ld r3,CS_HID1(r5)
> - sync
> - isync
> - mtspr SPRN_HID1,r3
> - mtspr SPRN_HID1,r3
> - sync
> - isync
> -
> - /* Restore HID4 */
> - ld r3,CS_HID4(r5)
> - sync
> - isync
> - mtspr SPRN_HID4,r3
> - sync
> - isync
> -
> - /* Restore HID5 */
> - ld r3,CS_HID5(r5)
> - sync
> - isync
> - mtspr SPRN_HID5,r3
> - sync
> - isync
> - blr
> -
> Index: linux-2.6/arch/powerpc/kernel/cpu_setup_ppc970.S
> ===================================================================
> --- /dev/null
> +++ linux-2.6/arch/powerpc/kernel/cpu_setup_ppc970.S
> @@ -0,0 +1,175 @@
> +/*
> + * This file contains low level CPU setup functions.
> + * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + *
> + */
> +
> +#include <linux/config.h>
> +#include <asm/processor.h>
> +#include <asm/page.h>
> +#include <asm/cputable.h>
> +#include <asm/ppc_asm.h>
> +#include <asm/asm-offsets.h>
> +#include <asm/cache.h>
> +
> +_GLOBAL(__cpu_preinit_ppc970)
> + /* Do nothing if not running in HV mode */
> + mfmsr r0
> + rldicl. r0,r0,4,63
> + beqlr
> +
> + /* Make sure HID4:rm_ci is off before MMU is turned off, that large
> + * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
> + * HID5:DCBZ32_ill
> + */
> + li r0,0
> + mfspr r3,SPRN_HID4
> + rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
> + rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
> + sync
> + mtspr SPRN_HID4,r3
> + isync
> + sync
> + mfspr r3,SPRN_HID5
> + rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
> + sync
> + mtspr SPRN_HID5,r3
> + isync
> + sync
> +
> + /* Setup some basic HID1 features */
> + mfspr r0,SPRN_HID1
> + li r3,0x1200 /* enable i-fetch cacheability */
> + sldi r3,r3,44 /* and prefetch */
> + or r0,r0,r3
> + mtspr SPRN_HID1,r0
> + mtspr SPRN_HID1,r0
> + isync
> +
> + /* Clear HIOR */
> + li r0,0
> + sync
> + mtspr SPRN_HIOR,0 /* Clear interrupt prefix */
> + isync
> + blr
> +
> +/* Definitions for the table use to save CPU states */
> +#define CS_HID0 0
> +#define CS_HID1 8
> +#define CS_HID4 16
> +#define CS_HID5 24
> +#define CS_SIZE 32
> +
> + .data
> + .balign L1_CACHE_BYTES,0
> +cpu_state_storage:
> + .space CS_SIZE
> + .balign L1_CACHE_BYTES,0
> + .text
> +
> +
> +_GLOBAL(__setup_cpu_ppc970)
> + /* Do nothing if not running in HV mode */
> + mfmsr r0
> + rldicl. r0,r0,4,63
> + beqlr
> +
> + mfspr r0,SPRN_HID0
> + li r11,5 /* clear DOZE and SLEEP */
> + rldimi r0,r11,52,8 /* set NAP and DPM */
> + mtspr SPRN_HID0,r0
> + mfspr r0,SPRN_HID0
> + mfspr r0,SPRN_HID0
> + mfspr r0,SPRN_HID0
> + mfspr r0,SPRN_HID0
> + mfspr r0,SPRN_HID0
> + mfspr r0,SPRN_HID0
> + sync
> + isync
> +
> + /* Save away cpu state */
> + LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
> +
> + /* Save HID0,1,4 and 5 */
> + mfspr r3,SPRN_HID0
> + std r3,CS_HID0(r5)
> + mfspr r3,SPRN_HID1
> + std r3,CS_HID1(r5)
> + mfspr r3,SPRN_HID4
> + std r3,CS_HID4(r5)
> + mfspr r3,SPRN_HID5
> + std r3,CS_HID5(r5)
> +
> + blr
> +
> +/* Called with no MMU context (typically MSR:IR/DR off) to
> + * restore CPU state as backed up by the previous
> + * function. This does not include cache setting
> + */
> +_GLOBAL(__restore_cpu_setup_ppc970)
> + /* Do nothing if not running in HV mode */
> + mfmsr r0
> + rldicl. r0,r0,4,63
> + beqlr
> +
> + LOAD_REG_IMMEDIATE(r5,cpu_state_storage)
> + /* Before accessing memory, we make sure rm_ci is clear */
> + li r0,0
> + mfspr r3,SPRN_HID4
> + rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
> + sync
> + mtspr SPRN_HID4,r3
> + isync
> + sync
> +
> + /* Clear interrupt prefix */
> + li r0,0
> + sync
> + mtspr SPRN_HIOR,0
> + isync
> +
> + /* Restore HID0 */
> + ld r3,CS_HID0(r5)
> + sync
> + isync
> + mtspr SPRN_HID0,r3
> + mfspr r3,SPRN_HID0
> + mfspr r3,SPRN_HID0
> + mfspr r3,SPRN_HID0
> + mfspr r3,SPRN_HID0
> + mfspr r3,SPRN_HID0
> + mfspr r3,SPRN_HID0
> + sync
> + isync
> +
> + /* Restore HID1 */
> + ld r3,CS_HID1(r5)
> + sync
> + isync
> + mtspr SPRN_HID1,r3
> + mtspr SPRN_HID1,r3
> + sync
> + isync
> +
> + /* Restore HID4 */
> + ld r3,CS_HID4(r5)
> + sync
> + isync
> + mtspr SPRN_HID4,r3
> + sync
> + isync
> +
> + /* Restore HID5 */
> + ld r3,CS_HID5(r5)
> + sync
> + isync
> + mtspr SPRN_HID5,r3
> + sync
> + isync
> + blr
> +
> Index: linux-2.6/arch/powerpc/kernel/head_64.S
> ===================================================================
> --- linux-2.6.orig/arch/powerpc/kernel/head_64.S
> +++ linux-2.6/arch/powerpc/kernel/head_64.S
> @@ -152,7 +152,7 @@ _GLOBAL(__secondary_hold)
> bne 100b
>
> #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
> - LOAD_REG_IMMEDIATE(r4, .pSeries_secondary_smp_init)
> + LOAD_REG_IMMEDIATE(r4, .generic_secondary_smp_init)
> mtctr r4
> mr r3,r24
> bctr
> @@ -1473,18 +1473,28 @@ fwnmi_data_area:
> . = 0x8000
>
> /*
> - * On pSeries, secondary processors spin in the following code.
> + * On pSeries and most other platforms, secondary processors spin
> + * in the following code.
> * At entry, r3 = this processor's number (physical cpu id)
> */
> -_GLOBAL(pSeries_secondary_smp_init)
> +_GLOBAL(generic_secondary_smp_init)
> mr r24,r3
>
> /* turn on 64-bit mode */
> bl .enable_64b_mode
> isync
>
> - /* Copy some CPU settings from CPU 0 */
> - bl .__restore_cpu_setup
> + /* Copy some CPU settings from CPU 0, only needed on PPC970{,FX,MP} */
> + mfspr r0,SPRN_PVR
> + srwi r0,r0,16
> + cmpwi r0,0x39 /* 970 */
> + beq 1f
> + cmpwi r0,0x3c /* 970FX */
> + beq 1f
> + cmpwi r0,0x44 /* 970MP */
> + bne 2f
> +1: bl .__restore_cpu_setup_ppc970
> +2:
>
> /* Set up a paca value for this processor. Since we have the
> * physical cpu id in r24, we need to search the pacas to find
> @@ -1600,7 +1610,16 @@ _GLOBAL(__start_initialization_multiplat
> bl .enable_64b_mode
>
> /* Setup some critical 970 SPRs before switching MMU off */
> - bl .__970_cpu_preinit
> + mfspr r0,SPRN_PVR
> + srwi r0,r0,16
> + cmpwi r0,0x39 /* 970 */
> + beq 1f
> + cmpwi r0,0x3c /* 970FX */
> + beq 1f
> + cmpwi r0,0x44 /* 970MP */
> + bne 2f
> +1: bl .__cpu_preinit_ppc970
> +2:
>
> /* cpu # */
> li r24,0
> @@ -1771,7 +1790,7 @@ _GLOBAL(pmac_secondary_start)
> isync
>
> /* Copy some CPU settings from CPU 0 */
> - bl .__restore_cpu_setup
> + bl .__restore_cpu_setup_ppc970
>
> /* pSeries do that early though I don't think we really need it */
> mfmsr r3
> @@ -1921,12 +1940,6 @@ _STATIC(start_here_multiplatform)
> mr r5,r26
> bl .identify_cpu
>
> - /* Save some low level config HIDs of CPU0 to be copied to
> - * other CPUs later on, or used for suspend/resume
> - */
> - bl .__save_cpu_setup
> - sync
> -
> /* Do very early kernel initializations, including initial hash table,
> * stab and slb setup before we turn on relocation. */
>
> Index: linux-2.6/arch/powerpc/platforms/cell/smp.c
> ===================================================================
> --- linux-2.6.orig/arch/powerpc/platforms/cell/smp.c
> +++ linux-2.6/arch/powerpc/platforms/cell/smp.c
> @@ -58,7 +58,7 @@
> */
> static cpumask_t of_spin_map;
>
> -extern void pSeries_secondary_smp_init(unsigned long);
> +extern void generic_secondary_smp_init(unsigned long);
>
> /**
> * smp_startup_cpu() - start the given cpu
> @@ -75,7 +75,7 @@ static inline int __devinit smp_startup_
> {
> int status;
> unsigned long start_here = __pa((u32)*((unsigned long *)
> - pSeries_secondary_smp_init));
> + generic_secondary_smp_init));
> unsigned int pcpu;
> int start_cpu;
>
> Index: linux-2.6/arch/powerpc/platforms/pseries/smp.c
> ===================================================================
> --- linux-2.6.orig/arch/powerpc/platforms/pseries/smp.c
> +++ linux-2.6/arch/powerpc/platforms/pseries/smp.c
> @@ -63,7 +63,7 @@
> */
> static cpumask_t of_spin_map;
>
> -extern void pSeries_secondary_smp_init(unsigned long);
> +extern void generic_secondary_smp_init(unsigned long);
>
> #ifdef CONFIG_HOTPLUG_CPU
>
> @@ -271,7 +271,7 @@ static inline int __devinit smp_startup_
> {
> int status;
> unsigned long start_here = __pa((u32)*((unsigned long *)
> - pSeries_secondary_smp_init));
> + generic_secondary_smp_init));
> unsigned int pcpu;
> int start_cpu;
>
^ permalink raw reply
* Re: cpu power "management" for non-dfs chips with no pmu (for instance, 750cxe and mpc7447 in pegasos)
From: Benjamin Herrenschmidt @ 2006-06-27 22:43 UTC (permalink / raw)
To: matt; +Cc: linuxppc-dev
In-Reply-To: <018201c696b1$e942ba40$99dfdfdf@bakuhatsu.net>
> I am basically trying to evaluate if we can do ANYTHING to reduce
> power consumption of systems which are idle, as I have noticed that
> for running firmware (sitting at a Forth prompt) and booting a
> Linux kernel and doing some work (for instance a simple benchmark),
> power consumption barely changes at all. The difference between an
> idle G4 and a running G4 is negligible. RC5 makes a big difference
> but it is heavily tuned. Most people won't run RC5 all the time to
> stress the CPU to the level that it wants to draw a couple extra
> watts, I think.
Well, I would expect the Idle G4 to have a fairly good PM in the first
place due to the NAP mode... though we may not enable that on Pegasos.
It depends if the bridge supports the proper protocol to handle
snooping. The Discovery II is bad enough as it is, I wouldn't expect it
to support that in a non-buggy way unfortunately.
Ben.
^ permalink raw reply
* Re: cpu power "management" for non-dfs chips with no pmu (for instance, 750cxe and mpc7447 in pegasos)
From: Benjamin Herrenschmidt @ 2006-06-27 22:47 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
In-Reply-To: <E1Ftmcb-0007rG-QS@jdl.com>
> > ICTC is such a simple thing to support and you can slow down the CPU
> > pretty comprehensively (from halving to 255x in theory) with an on and
> > off flag. I am surprised nobody implemented a cpufreq governer even if
> > it is totally useless and gives no perceivable benefits..
>
> See? You _are_ contributing already. I encourage
> you to hit the linux-pm@lists.osdl.org list for a spell!
His question is very powerpc specific... I don't see the point of
bringing ICTC related discussions to linux-pm...
Now, we _did_ some experiemnts in the past and didn't see that much
improvements. That might have changed though, since those 744x/745x CPUs
cannot DOZE and we cannot use their NAP mode neither when idle on
Pegasdos, in which case ICTC might have some use there...
It's easy to tweak it, just test and tell us. I'm not sure if cpufreq is
the right interface though as the cpu frequency isn't actually changing.
Ben.
^ permalink raw reply
* Re: Fixed PPC SHA1
From: Benjamin Herrenschmidt @ 2006-06-27 22:50 UTC (permalink / raw)
To: linux; +Cc: linuxppc-dev, git
In-Reply-To: <20060623005456.21460.qmail@science.horizon.com>
On Thu, 2006-06-22 at 20:54 -0400, linux@horizon.com wrote:
> Here's the lwsi-based version that's slightly faster on a G5, but slightly
> slower on a G4.
I wouldn't bother with 2 versions... use the non-string version (string
operations will cause performance problems on other processors)
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Do a bit more cpu init cleanups
From: Olof Johansson @ 2006-06-27 22:54 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Olof Johansson, linuxppc-dev, paulus
In-Reply-To: <1151446849.2350.95.camel@localhost.localdomain>
On Wed, Jun 28, 2006 at 08:20:48AM +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2006-06-27 at 12:22 -0700, Olof Johansson wrote:
> > Cleanup CPU inits a bit more, Geoff Levand already did some earlier.
> >
> > * Rename cpu_setup_power4.S to cpu_setup_ppc970.S
>
> > * Move CPU state save to cpu_setup, since cpu_setup is only ever done
> > on cpu 0 on 64-bit.
>
> Nah, keep that one separate, will be needed as soon as we start doing
> some sleep/wake stuff for ppc64
Why? I can see having to restore the settings on wake, but not doing a
brand new cpu_setup.
> > * Rename __restore_cpu_setup to __restore_cpu_setup_ppc970 since it's
> > only actually doing anything there, and check before calling instead
> > of in the function (no check needed on powermac).
>
> I'd like to keep a generic save/restore.. that or we put then in
> cputable.
Keep? There never was one. :)
Since restore is called very first thing in smp secondary init, we don't
have cputable available.
> > * Same for __970_cpu_preinit
> > * Rename pSeries_secondary_smp_init to generic_secondary_smp_init since
> > everyone but powermac and iSeries use it.
>
> Ok.
-Olof
^ permalink raw reply
* Re: [PATCH] powerpc: Do a bit more cpu init cleanups
From: Benjamin Herrenschmidt @ 2006-06-27 23:07 UTC (permalink / raw)
To: Olof Johansson; +Cc: linuxppc-dev, paulus
In-Reply-To: <20060627225401.GC5130@pb15.lixom.net>
On Tue, 2006-06-27 at 15:54 -0700, Olof Johansson wrote:
> On Wed, Jun 28, 2006 at 08:20:48AM +1000, Benjamin Herrenschmidt wrote:
> > On Tue, 2006-06-27 at 12:22 -0700, Olof Johansson wrote:
> > > Cleanup CPU inits a bit more, Geoff Levand already did some earlier.
> > >
> > > * Rename cpu_setup_power4.S to cpu_setup_ppc970.S
> >
> > > * Move CPU state save to cpu_setup, since cpu_setup is only ever done
> > > on cpu 0 on 64-bit.
> >
> > Nah, keep that one separate, will be needed as soon as we start doing
> > some sleep/wake stuff for ppc64
>
> Why? I can see having to restore the settings on wake, but not doing a
> brand new cpu_setup.
No, a new save, not setup.
> > > * Rename __restore_cpu_setup to __restore_cpu_setup_ppc970 since it's
> > > only actually doing anything there, and check before calling instead
> > > of in the function (no check needed on powermac).
> >
> > I'd like to keep a generic save/restore.. that or we put then in
> > cputable.
>
> Keep? There never was one. :)
There is one for 32 bits :)
> Since restore is called very first thing in smp secondary init, we don't
> have cputable available.
We could easily
Ben.
^ permalink raw reply
* Re: [PATCH] powerpc: Do a bit more cpu init cleanups
From: Olof Johansson @ 2006-06-27 23:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev, paulus
In-Reply-To: <1151449661.2350.106.camel@localhost.localdomain>
On Wed, Jun 28, 2006 at 09:07:41AM +1000, Benjamin Herrenschmidt wrote:
> On Tue, 2006-06-27 at 15:54 -0700, Olof Johansson wrote:
> > On Wed, Jun 28, 2006 at 08:20:48AM +1000, Benjamin Herrenschmidt wrote:
> > > On Tue, 2006-06-27 at 12:22 -0700, Olof Johansson wrote:
> > > > Cleanup CPU inits a bit more, Geoff Levand already did some earlier.
> > > >
> > > > * Rename cpu_setup_power4.S to cpu_setup_ppc970.S
> > >
> > > > * Move CPU state save to cpu_setup, since cpu_setup is only ever done
> > > > on cpu 0 on 64-bit.
> > >
> > > Nah, keep that one separate, will be needed as soon as we start doing
> > > some sleep/wake stuff for ppc64
> >
> > Why? I can see having to restore the settings on wake, but not doing a
> > brand new cpu_setup.
>
> No, a new save, not setup.
I prefer to join them for now. I'm not convinced resaving is the best way
to go for sleep/wake, HID defaults are saved during boot. If other bits
have been flipped, chances are there's higher-level code that needs to
be aware and do things on resume anyway, and they can just set the bit
again there (i.e. platform suspend/resume handlers).
So, I prefer to keep the change as-is until there's code that shows the
neccessity of having it the other way.
> > > > * Rename __restore_cpu_setup to __restore_cpu_setup_ppc970 since it's
> > > > only actually doing anything there, and check before calling instead
> > > > of in the function (no check needed on powermac).
> > >
> > > I'd like to keep a generic save/restore.. that or we put then in
> > > cputable.
> >
> > Keep? There never was one. :)
>
> There is one for 32 bits :)
I didn't change any 32-bit code, so it's still there! :) (see below)
> > Since restore is called very first thing in smp secondary init, we don't
> > have cputable available.
>
> We could easily
Yeah, on second look it wouldn't be hard. I'll add it to the cputable
and use those pointers. It'll get rid of one of the PVR checks too.
-Olof
^ permalink raw reply
* Re: [PATCH] Assume we're on cpu 0 in early boot
From: Paul Mackerras @ 2006-06-28 1:42 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, Arnd Bergmann
In-Reply-To: <20060627040036.469B767B28@ozlabs.org>
Michael Ellerman writes:
> There's a small period early in boot where we don't know which cpu we're
> running on. That's ok, except that it means we have no paca, or more
> correctly that our paca pointer points somewhere random.
>
> So that we can safely call things like smp_processor_id(), we need a paca,
> so just assume we're on cpu 0. No code should _write_ to the paca before
> we've set the correct one up.
OK, but why not just do a setup_paca(0) at the start of early_setup(),
in C code? You can also remove the redundant paca setting in
start_here_common() in head_64.S.
Paul.
^ permalink raw reply
* [PATCH] Clean up it_lp_queue.h
From: Stephen Rothwell @ 2006-06-28 1:49 UTC (permalink / raw)
To: paulus; +Cc: ppc-dev
No more StudlyCaps.
Remove from a couple of places it is no longer needed.
Use C style comments.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
arch/powerpc/kernel/paca.c | 1 -
arch/powerpc/platforms/iseries/lpevents.c | 55 +++++++++++++++--------------
arch/powerpc/platforms/iseries/proc.c | 1 -
include/asm-powerpc/iseries/it_lp_queue.h | 40 +++++++++++----------
4 files changed, 48 insertions(+), 49 deletions(-)
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index f505a88..a0bb354 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -16,7 +16,6 @@ #include <asm/processor.h>
#include <asm/ptrace.h>
#include <asm/page.h>
#include <asm/lppaca.h>
-#include <asm/iseries/it_lp_queue.h>
#include <asm/iseries/it_lp_reg_save.h>
#include <asm/paca.h>
diff --git a/arch/powerpc/platforms/iseries/lpevents.c b/arch/powerpc/platforms/iseries/lpevents.c
index 8ca7b93..2a9f81e 100644
--- a/arch/powerpc/platforms/iseries/lpevents.c
+++ b/arch/powerpc/platforms/iseries/lpevents.c
@@ -51,20 +51,21 @@ static unsigned lpEventHandlerPaths[HvLp
static struct HvLpEvent * get_next_hvlpevent(void)
{
struct HvLpEvent * event;
- event = (struct HvLpEvent *)hvlpevent_queue.xSlicCurEventPtr;
+ event = (struct HvLpEvent *)hvlpevent_queue.hq_current_event;
if (hvlpevent_is_valid(event)) {
/* rmb() needed only for weakly consistent machines (regatta) */
rmb();
/* Set pointer to next potential event */
- hvlpevent_queue.xSlicCurEventPtr += ((event->xSizeMinus1 +
- LpEventAlign) / LpEventAlign) * LpEventAlign;
+ hvlpevent_queue.hq_current_event += ((event->xSizeMinus1 +
+ IT_LP_EVENT_ALIGN) / IT_LP_EVENT_ALIGN) *
+ IT_LP_EVENT_ALIGN;
/* Wrap to beginning if no room at end */
- if (hvlpevent_queue.xSlicCurEventPtr >
- hvlpevent_queue.xSlicLastValidEventPtr) {
- hvlpevent_queue.xSlicCurEventPtr =
- hvlpevent_queue.xSlicEventStackPtr;
+ if (hvlpevent_queue.hq_current_event >
+ hvlpevent_queue.hq_last_event) {
+ hvlpevent_queue.hq_current_event =
+ hvlpevent_queue.hq_event_stack;
}
} else {
event = NULL;
@@ -82,10 +83,10 @@ int hvlpevent_is_pending(void)
if (smp_processor_id() >= spread_lpevents)
return 0;
- next_event = (struct HvLpEvent *)hvlpevent_queue.xSlicCurEventPtr;
+ next_event = (struct HvLpEvent *)hvlpevent_queue.hq_current_event;
return hvlpevent_is_valid(next_event) ||
- hvlpevent_queue.xPlicOverflowIntPending;
+ hvlpevent_queue.hq_overflow_pending;
}
static void hvlpevent_clear_valid(struct HvLpEvent * event)
@@ -95,18 +96,18 @@ static void hvlpevent_clear_valid(struct
* ie. on 64-byte boundaries.
*/
struct HvLpEvent *tmp;
- unsigned extra = ((event->xSizeMinus1 + LpEventAlign) /
- LpEventAlign) - 1;
+ unsigned extra = ((event->xSizeMinus1 + IT_LP_EVENT_ALIGN) /
+ IT_LP_EVENT_ALIGN) - 1;
switch (extra) {
case 3:
- tmp = (struct HvLpEvent*)((char*)event + 3 * LpEventAlign);
+ tmp = (struct HvLpEvent*)((char*)event + 3 * IT_LP_EVENT_ALIGN);
hvlpevent_invalidate(tmp);
case 2:
- tmp = (struct HvLpEvent*)((char*)event + 2 * LpEventAlign);
+ tmp = (struct HvLpEvent*)((char*)event + 2 * IT_LP_EVENT_ALIGN);
hvlpevent_invalidate(tmp);
case 1:
- tmp = (struct HvLpEvent*)((char*)event + 1 * LpEventAlign);
+ tmp = (struct HvLpEvent*)((char*)event + 1 * IT_LP_EVENT_ALIGN);
hvlpevent_invalidate(tmp);
}
@@ -120,7 +121,7 @@ void process_hvlpevents(struct pt_regs *
struct HvLpEvent * event;
/* If we have recursed, just return */
- if (!spin_trylock(&hvlpevent_queue.lock))
+ if (!spin_trylock(&hvlpevent_queue.hq_lock))
return;
for (;;) {
@@ -148,17 +149,17 @@ void process_hvlpevents(struct pt_regs *
printk(KERN_INFO "Unexpected Lp Event type=%d\n", event->xType );
hvlpevent_clear_valid(event);
- } else if (hvlpevent_queue.xPlicOverflowIntPending)
+ } else if (hvlpevent_queue.hq_overflow_pending)
/*
* No more valid events. If overflow events are
* pending process them
*/
- HvCallEvent_getOverflowLpEvents(hvlpevent_queue.xIndex);
+ HvCallEvent_getOverflowLpEvents(hvlpevent_queue.hq_index);
else
break;
}
- spin_unlock(&hvlpevent_queue.lock);
+ spin_unlock(&hvlpevent_queue.hq_lock);
}
static int set_spread_lpevents(char *str)
@@ -184,20 +185,20 @@ void setup_hvlpevent_queue(void)
{
void *eventStack;
- spin_lock_init(&hvlpevent_queue.lock);
+ spin_lock_init(&hvlpevent_queue.hq_lock);
/* Allocate a page for the Event Stack. */
- eventStack = alloc_bootmem_pages(LpEventStackSize);
- memset(eventStack, 0, LpEventStackSize);
+ eventStack = alloc_bootmem_pages(IT_LP_EVENT_STACK_SIZE);
+ memset(eventStack, 0, IT_LP_EVENT_STACK_SIZE);
/* Invoke the hypervisor to initialize the event stack */
- HvCallEvent_setLpEventStack(0, eventStack, LpEventStackSize);
+ HvCallEvent_setLpEventStack(0, eventStack, IT_LP_EVENT_STACK_SIZE);
- hvlpevent_queue.xSlicEventStackPtr = (char *)eventStack;
- hvlpevent_queue.xSlicCurEventPtr = (char *)eventStack;
- hvlpevent_queue.xSlicLastValidEventPtr = (char *)eventStack +
- (LpEventStackSize - LpEventMaxSize);
- hvlpevent_queue.xIndex = 0;
+ hvlpevent_queue.hq_event_stack = eventStack;
+ hvlpevent_queue.hq_current_event = eventStack;
+ hvlpevent_queue.hq_last_event = (char *)eventStack +
+ (IT_LP_EVENT_STACK_SIZE - IT_LP_EVENT_MAX_SIZE);
+ hvlpevent_queue.hq_index = 0;
}
/* Register a handler for an LpEvent type */
diff --git a/arch/powerpc/platforms/iseries/proc.c b/arch/powerpc/platforms/iseries/proc.c
index e68b6b5..c241413 100644
--- a/arch/powerpc/platforms/iseries/proc.c
+++ b/arch/powerpc/platforms/iseries/proc.c
@@ -24,7 +24,6 @@ #include <asm/paca.h>
#include <asm/processor.h>
#include <asm/time.h>
#include <asm/lppaca.h>
-#include <asm/iseries/it_lp_queue.h>
#include <asm/iseries/hv_call_xm.h>
#include "processor_vpd.h"
diff --git a/include/asm-powerpc/iseries/it_lp_queue.h b/include/asm-powerpc/iseries/it_lp_queue.h
index b7c6fc1..284c5a7 100644
--- a/include/asm-powerpc/iseries/it_lp_queue.h
+++ b/include/asm-powerpc/iseries/it_lp_queue.h
@@ -29,20 +29,20 @@ #include <asm/ptrace.h>
struct HvLpEvent;
-#define ITMaxLpQueues 8
+#define IT_LP_MAX_QUEUES 8
-#define NotUsed 0 // Queue will not be used by PLIC
-#define DedicatedIo 1 // Queue dedicated to IO processor specified
-#define DedicatedLp 2 // Queue dedicated to LP specified
-#define Shared 3 // Queue shared for both IO and LP
+#define IT_LP_NOT_USED 0 /* Queue will not be used by PLIC */
+#define IT_LP_DEDICATED_IO 1 /* Queue dedicated to IO processor specified */
+#define IT_LP_DEDICATED_LP 2 /* Queue dedicated to LP specified */
+#define IT_LP_SHARED 3 /* Queue shared for both IO and LP */
-#define LpEventStackSize 4096
-#define LpEventMaxSize 256
-#define LpEventAlign 64
+#define IT_LP_EVENT_STACK_SIZE 4096
+#define IT_LP_EVENT_MAX_SIZE 256
+#define IT_LP_EVENT_ALIGN 64
struct hvlpevent_queue {
/*
- * The xSlicCurEventPtr is the pointer to the next event stack entry
+ * The hq_current_event is the pointer to the next event stack entry
* that will become valid. The OS must peek at this entry to determine
* if it is valid. PLIC will set the valid indicator as the very last
* store into that entry.
@@ -52,23 +52,23 @@ struct hvlpevent_queue {
* location again.
*
* If the event stack fills and there are overflow events, then PLIC
- * will set the xPlicOverflowIntPending flag in which case the OS will
+ * will set the hq_overflow_pending flag in which case the OS will
* have to fetch the additional LP events once they have drained the
* event stack.
*
* The first 16-bytes are known by both the OS and PLIC. The remainder
* of the cache line is for use by the OS.
*/
- u8 xPlicOverflowIntPending;// 0x00 Overflow events are pending
- u8 xPlicStatus; // 0x01 DedicatedIo or DedicatedLp or NotUsed
- u16 xSlicLogicalProcIndex; // 0x02 Logical Proc Index for correlation
- u8 xPlicRsvd[12]; // 0x04
- char *xSlicCurEventPtr; // 0x10
- char *xSlicLastValidEventPtr; // 0x18
- char *xSlicEventStackPtr; // 0x20
- u8 xIndex; // 0x28 unique sequential index.
- u8 xSlicRsvd[3]; // 0x29-2b
- spinlock_t lock;
+ u8 hq_overflow_pending; /* 0x00 Overflow events are pending */
+ u8 hq_status; /* 0x01 DedicatedIo or DedicatedLp or NotUsed */
+ u16 hq_proc_index; /* 0x02 Logical Proc Index for correlation */
+ u8 hq_reserved1[12]; /* 0x04 */
+ char *hq_current_event; /* 0x10 */
+ char *hq_last_event; /* 0x18 */
+ char *hq_event_stack; /* 0x20 */
+ u8 hq_index; /* 0x28 unique sequential index. */
+ u8 hq_reserved2[3]; /* 0x29-2b */
+ spinlock_t hq_lock;
};
extern struct hvlpevent_queue hvlpevent_queue;
--
1.4.0
^ permalink raw reply related
* [PATCH] update asm-powerpc/time.h
From: Stephen Rothwell @ 2006-06-28 1:51 UTC (permalink / raw)
To: paulus; +Cc: ppc-dev
If we ever build a combined kernel including iSeries, then this will
be needed.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
include/asm-powerpc/time.h | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h
index 912118d..db8a57e 100644
--- a/include/asm-powerpc/time.h
+++ b/include/asm-powerpc/time.h
@@ -19,8 +19,9 @@ #include <linux/types.h>
#include <linux/percpu.h>
#include <asm/processor.h>
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_ISERIES
#include <asm/paca.h>
+#include <asm/firmware.h>
#include <asm/iseries/hv_call.h>
#endif
@@ -178,7 +179,8 @@ #else
#ifdef CONFIG_PPC_ISERIES
int cur_dec;
- if (get_lppaca()->shared_proc) {
+ if (firmware_has_feature(FW_FEATURE_ISERIES) &&
+ get_lppaca()->shared_proc) {
get_lppaca()->virtual_decr = val;
cur_dec = get_dec();
if (cur_dec > val)
--
1.3.3.g16a4
^ permalink raw reply related
* [PATCH] Remove unused function call_with_mmu_off
From: Stephen Rothwell @ 2006-06-28 1:53 UTC (permalink / raw)
To: paulus; +Cc: ppc-dev
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
arch/powerpc/kernel/misc_64.S | 42 -----------------------------------------
1 files changed, 0 insertions(+), 42 deletions(-)
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index e8883d4..6bf4a46 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -101,48 +101,6 @@ _GLOBAL(call___do_IRQ)
blr
#endif /* CONFIG_IRQSTACKS */
- /*
- * To be called by C code which needs to do some operations with MMU
- * disabled. Note that interrupts have to be disabled by the caller
- * prior to calling us. The code called _MUST_ be in the RMO of course
- * and part of the linear mapping as we don't attempt to translate the
- * stack pointer at all. The function is called with the stack switched
- * to this CPU emergency stack
- *
- * prototype is void *call_with_mmu_off(void *func, void *data);
- *
- * the called function is expected to be of the form
- *
- * void *called(void *data);
- */
-_GLOBAL(call_with_mmu_off)
- mflr r0 /* get link, save it on stackframe */
- std r0,16(r1)
- mr r1,r5 /* save old stack ptr */
- ld r1,PACAEMERGSP(r13) /* get emerg. stack */
- subi r1,r1,STACK_FRAME_OVERHEAD
- std r0,16(r1) /* save link on emerg. stack */
- std r5,0(r1) /* save old stack ptr in backchain */
- ld r3,0(r3) /* get to real function ptr (assume same TOC) */
- bl 2f /* we need LR to return, continue at label 2 */
-
- ld r0,16(r1) /* we return here from the call, get LR and */
- ld r1,0(r1) /* .. old stack ptr */
- mtspr SPRN_SRR0,r0 /* and get back to virtual mode with these */
- mfmsr r4
- ori r4,r4,MSR_IR|MSR_DR
- mtspr SPRN_SRR1,r4
- rfid
-
-2: mtspr SPRN_SRR0,r3 /* coming from above, enter real mode */
- mr r3,r4 /* get parameter */
- mfmsr r0
- ori r0,r0,MSR_IR|MSR_DR
- xori r0,r0,MSR_IR|MSR_DR
- mtspr SPRN_SRR1,r0
- rfid
-
-
.section ".toc","aw"
PPC64_CACHES:
.tc ppc64_caches[TC],ppc64_caches
--
1.4.0
^ permalink raw reply related
* [PATCH] Consolidate some of kernel/misc*.S
From: Stephen Rothwell @ 2006-06-28 1:55 UTC (permalink / raw)
To: paulus; +Cc: ppc-dev
There were some common functions (mainly i/o).
Also some small white space cleanups and remove a couple of small unused
functions.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
arch/powerpc/kernel/Makefile | 3 -
arch/powerpc/kernel/misc.S | 203 +++++++++++++++++++++++++++++++++++++++++
arch/powerpc/kernel/misc_32.S | 156 --------------------------------
arch/powerpc/kernel/misc_64.S | 181 +------------------------------------
4 files changed, 209 insertions(+), 334 deletions(-)
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 803858e..814f242 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -50,7 +50,8 @@ extra-$(CONFIG_FSL_BOOKE) := head_fsl_bo
extra-$(CONFIG_8xx) := head_8xx.o
extra-y += vmlinux.lds
-obj-y += time.o prom.o traps.o setup-common.o udbg.o
+obj-y += time.o prom.o traps.o setup-common.o \
+ udbg.o misc.o
obj-$(CONFIG_PPC32) += entry_32.o setup_32.o misc_32.o
obj-$(CONFIG_PPC64) += misc_64.o dma_64.o iommu.o
obj-$(CONFIG_PPC_MULTIPLATFORM) += prom_init.o
diff --git a/arch/powerpc/kernel/misc.S b/arch/powerpc/kernel/misc.S
new file mode 100644
index 0000000..fc23040
--- /dev/null
+++ b/arch/powerpc/kernel/misc.S
@@ -0,0 +1,203 @@
+/*
+ * This file contains miscellaneous low-level functions.
+ * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
+ *
+ * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
+ * and Paul Mackerras.
+ *
+ * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
+ * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <asm/ppc_asm.h>
+
+ .text
+
+#ifdef CONFIG_PPC64
+#define IN_SYNC twi 0,r5,0; isync
+#define EIEIO_32
+#define SYNC_64 sync
+#else /* CONFIG_PPC32 */
+#define IN_SYNC
+#define EIEIO_32 eieio
+#define SYNC_64
+#endif
+/*
+ * Returns (address we are running at) - (address we were linked at)
+ * for use before the text and data are mapped to KERNELBASE.
+ */
+
+_GLOBAL(reloc_offset)
+ mflr r0
+ bl 1f
+1: mflr r3
+ LOAD_REG_IMMEDIATE(r4,1b)
+ subf r3,r4,r3
+ mtlr r0
+ blr
+
+/*
+ * add_reloc_offset(x) returns x + reloc_offset().
+ */
+_GLOBAL(add_reloc_offset)
+ mflr r0
+ bl 1f
+1: mflr r5
+ LOAD_REG_IMMEDIATE(r4,1b)
+ subf r5,r4,r5
+ add r3,r3,r5
+ mtlr r0
+ blr
+
+/*
+ * I/O string operations
+ *
+ * insb(port, buf, len)
+ * outsb(port, buf, len)
+ * insw(port, buf, len)
+ * outsw(port, buf, len)
+ * insl(port, buf, len)
+ * outsl(port, buf, len)
+ * insw_ns(port, buf, len)
+ * outsw_ns(port, buf, len)
+ * insl_ns(port, buf, len)
+ * outsl_ns(port, buf, len)
+ *
+ * The *_ns versions don't do byte-swapping.
+ */
+_GLOBAL(_insb)
+ cmpwi 0,r5,0
+ mtctr r5
+ subi r4,r4,1
+ blelr-
+00: lbz r5,0(r3)
+ eieio
+ stbu r5,1(r4)
+ bdnz 00b
+ IN_SYNC
+ blr
+
+_GLOBAL(_outsb)
+ cmpwi 0,r5,0
+ mtctr r5
+ subi r4,r4,1
+ blelr-
+00: lbzu r5,1(r4)
+ stb r5,0(r3)
+ EIEIO_32
+ bdnz 00b
+ SYNC_64
+ blr
+
+_GLOBAL(_insw)
+ cmpwi 0,r5,0
+ mtctr r5
+ subi r4,r4,2
+ blelr-
+00: lhbrx r5,0,r3
+ eieio
+ sthu r5,2(r4)
+ bdnz 00b
+ IN_SYNC
+ blr
+
+_GLOBAL(_outsw)
+ cmpwi 0,r5,0
+ mtctr r5
+ subi r4,r4,2
+ blelr-
+00: lhzu r5,2(r4)
+ EIEIO_32
+ sthbrx r5,0,r3
+ bdnz 00b
+ SYNC_64
+ blr
+
+_GLOBAL(_insl)
+ cmpwi 0,r5,0
+ mtctr r5
+ subi r4,r4,4
+ blelr-
+00: lwbrx r5,0,r3
+ eieio
+ stwu r5,4(r4)
+ bdnz 00b
+ IN_SYNC
+ blr
+
+_GLOBAL(_outsl)
+ cmpwi 0,r5,0
+ mtctr r5
+ subi r4,r4,4
+ blelr-
+00: lwzu r5,4(r4)
+ stwbrx r5,0,r3
+ EIEIO_32
+ bdnz 00b
+ SYNC_64
+ blr
+
+#ifdef CONFIG_PPC32
+_GLOBAL(__ide_mm_insw)
+#endif
+_GLOBAL(_insw_ns)
+ cmpwi 0,r5,0
+ mtctr r5
+ subi r4,r4,2
+ blelr-
+00: lhz r5,0(r3)
+ eieio
+ sthu r5,2(r4)
+ bdnz 00b
+ IN_SYNC
+ blr
+
+#ifdef CONFIG_PPC32
+_GLOBAL(__ide_mm_outsw)
+#endif
+_GLOBAL(_outsw_ns)
+ cmpwi 0,r5,0
+ mtctr r5
+ subi r4,r4,2
+ blelr-
+00: lhzu r5,2(r4)
+ sth r5,0(r3)
+ EIEIO_32
+ bdnz 00b
+ SYNC_64
+ blr
+
+#ifdef CONFIG_PPC32
+_GLOBAL(__ide_mm_insl)
+#endif
+_GLOBAL(_insl_ns)
+ cmpwi 0,r5,0
+ mtctr r5
+ subi r4,r4,4
+ blelr-
+00: lwz r5,0(r3)
+ eieio
+ stwu r5,4(r4)
+ bdnz 00b
+ IN_SYNC
+ blr
+
+#ifdef CONFIG_PPC32
+_GLOBAL(__ide_mm_outsl)
+#endif
+_GLOBAL(_outsl_ns)
+ cmpwi 0,r5,0
+ mtctr r5
+ subi r4,r4,4
+ blelr-
+00: lwzu r5,4(r4)
+ stw r5,0(r3)
+ EIEIO_32
+ bdnz 00b
+ SYNC_64
+ blr
+
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 01d3916..c74774e 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -61,32 +61,6 @@ _GLOBAL(mulhdu)
blr
/*
- * Returns (address we're running at) - (address we were linked at)
- * for use before the text and data are mapped to KERNELBASE.
- */
-_GLOBAL(reloc_offset)
- mflr r0
- bl 1f
-1: mflr r3
- LOAD_REG_IMMEDIATE(r4,1b)
- subf r3,r4,r3
- mtlr r0
- blr
-
-/*
- * add_reloc_offset(x) returns x + reloc_offset().
- */
-_GLOBAL(add_reloc_offset)
- mflr r0
- bl 1f
-1: mflr r5
- LOAD_REG_IMMEDIATE(r4,1b)
- subf r5,r4,r5
- add r3,r3,r5
- mtlr r0
- blr
-
-/*
* sub_reloc_offset(x) returns x - reloc_offset().
*/
_GLOBAL(sub_reloc_offset)
@@ -781,136 +755,6 @@ _GLOBAL(atomic_set_mask)
blr
/*
- * I/O string operations
- *
- * insb(port, buf, len)
- * outsb(port, buf, len)
- * insw(port, buf, len)
- * outsw(port, buf, len)
- * insl(port, buf, len)
- * outsl(port, buf, len)
- * insw_ns(port, buf, len)
- * outsw_ns(port, buf, len)
- * insl_ns(port, buf, len)
- * outsl_ns(port, buf, len)
- *
- * The *_ns versions don't do byte-swapping.
- */
-_GLOBAL(_insb)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,1
- blelr-
-00: lbz r5,0(r3)
- eieio
- stbu r5,1(r4)
- bdnz 00b
- blr
-
-_GLOBAL(_outsb)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,1
- blelr-
-00: lbzu r5,1(r4)
- stb r5,0(r3)
- eieio
- bdnz 00b
- blr
-
-_GLOBAL(_insw)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,2
- blelr-
-00: lhbrx r5,0,r3
- eieio
- sthu r5,2(r4)
- bdnz 00b
- blr
-
-_GLOBAL(_outsw)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,2
- blelr-
-00: lhzu r5,2(r4)
- eieio
- sthbrx r5,0,r3
- bdnz 00b
- blr
-
-_GLOBAL(_insl)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,4
- blelr-
-00: lwbrx r5,0,r3
- eieio
- stwu r5,4(r4)
- bdnz 00b
- blr
-
-_GLOBAL(_outsl)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,4
- blelr-
-00: lwzu r5,4(r4)
- stwbrx r5,0,r3
- eieio
- bdnz 00b
- blr
-
-_GLOBAL(__ide_mm_insw)
-_GLOBAL(_insw_ns)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,2
- blelr-
-00: lhz r5,0(r3)
- eieio
- sthu r5,2(r4)
- bdnz 00b
- blr
-
-_GLOBAL(__ide_mm_outsw)
-_GLOBAL(_outsw_ns)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,2
- blelr-
-00: lhzu r5,2(r4)
- sth r5,0(r3)
- eieio
- bdnz 00b
- blr
-
-_GLOBAL(__ide_mm_insl)
-_GLOBAL(_insl_ns)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,4
- blelr-
-00: lwz r5,0(r3)
- eieio
- stwu r5,4(r4)
- bdnz 00b
- blr
-
-_GLOBAL(__ide_mm_outsl)
-_GLOBAL(_outsl_ns)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,4
- blelr-
-00: lwzu r5,4(r4)
- stw r5,0(r3)
- eieio
- bdnz 00b
- blr
-
-/*
* Extended precision shifts.
*
* Updated to be valid for shift counts from 0 to 63 inclusive.
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index 6bf4a46..580891c 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -1,14 +1,12 @@
/*
- * arch/powerpc/kernel/misc64.S
- *
* This file contains miscellaneous low-level functions.
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
*
* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
* and Paul Mackerras.
* Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
- * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
- *
+ * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
+ *
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
@@ -30,41 +28,10 @@ #include <asm/thread_info.h>
.text
-/*
- * Returns (address we are running at) - (address we were linked at)
- * for use before the text and data are mapped to KERNELBASE.
- */
-
-_GLOBAL(reloc_offset)
- mflr r0
- bl 1f
-1: mflr r3
- LOAD_REG_IMMEDIATE(r4,1b)
- subf r3,r4,r3
- mtlr r0
- blr
-
-/*
- * add_reloc_offset(x) returns x + reloc_offset().
- */
-_GLOBAL(add_reloc_offset)
- mflr r0
- bl 1f
-1: mflr r5
- LOAD_REG_IMMEDIATE(r4,1b)
- subf r5,r4,r5
- add r3,r3,r5
- mtlr r0
- blr
-
_GLOBAL(get_msr)
mfmsr r3
blr
-_GLOBAL(get_dar)
- mfdar r3
- blr
-
_GLOBAL(get_srr0)
mfsrr0 r3
blr
@@ -72,10 +39,6 @@ _GLOBAL(get_srr0)
_GLOBAL(get_srr1)
mfsrr1 r3
blr
-
-_GLOBAL(get_sp)
- mr r3,r1
- blr
#ifdef CONFIG_IRQSTACKS
_GLOBAL(call_do_softirq)
@@ -281,144 +244,6 @@ _GLOBAL(__flush_dcache_icache)
bdnz 1b
isync
blr
-
-/*
- * I/O string operations
- *
- * insb(port, buf, len)
- * outsb(port, buf, len)
- * insw(port, buf, len)
- * outsw(port, buf, len)
- * insl(port, buf, len)
- * outsl(port, buf, len)
- * insw_ns(port, buf, len)
- * outsw_ns(port, buf, len)
- * insl_ns(port, buf, len)
- * outsl_ns(port, buf, len)
- *
- * The *_ns versions don't do byte-swapping.
- */
-_GLOBAL(_insb)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,1
- blelr-
-00: lbz r5,0(r3)
- eieio
- stbu r5,1(r4)
- bdnz 00b
- twi 0,r5,0
- isync
- blr
-
-_GLOBAL(_outsb)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,1
- blelr-
-00: lbzu r5,1(r4)
- stb r5,0(r3)
- bdnz 00b
- sync
- blr
-
-_GLOBAL(_insw)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,2
- blelr-
-00: lhbrx r5,0,r3
- eieio
- sthu r5,2(r4)
- bdnz 00b
- twi 0,r5,0
- isync
- blr
-
-_GLOBAL(_outsw)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,2
- blelr-
-00: lhzu r5,2(r4)
- sthbrx r5,0,r3
- bdnz 00b
- sync
- blr
-
-_GLOBAL(_insl)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,4
- blelr-
-00: lwbrx r5,0,r3
- eieio
- stwu r5,4(r4)
- bdnz 00b
- twi 0,r5,0
- isync
- blr
-
-_GLOBAL(_outsl)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,4
- blelr-
-00: lwzu r5,4(r4)
- stwbrx r5,0,r3
- bdnz 00b
- sync
- blr
-
-/* _GLOBAL(ide_insw) now in drivers/ide/ide-iops.c */
-_GLOBAL(_insw_ns)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,2
- blelr-
-00: lhz r5,0(r3)
- eieio
- sthu r5,2(r4)
- bdnz 00b
- twi 0,r5,0
- isync
- blr
-
-/* _GLOBAL(ide_outsw) now in drivers/ide/ide-iops.c */
-_GLOBAL(_outsw_ns)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,2
- blelr-
-00: lhzu r5,2(r4)
- sth r5,0(r3)
- bdnz 00b
- sync
- blr
-
-_GLOBAL(_insl_ns)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,4
- blelr-
-00: lwz r5,0(r3)
- eieio
- stwu r5,4(r4)
- bdnz 00b
- twi 0,r5,0
- isync
- blr
-
-_GLOBAL(_outsl_ns)
- cmpwi 0,r5,0
- mtctr r5
- subi r4,r4,4
- blelr-
-00: lwzu r5,4(r4)
- stw r5,0(r3)
- bdnz 00b
- sync
- blr
/*
* identify_cpu and calls setup_cpu
@@ -563,6 +388,7 @@ _GLOBAL(real_writeb)
blr
#endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
+#ifdef CONFIG_CPU_FREQ_PMAC64
/*
* SCOM access functions for 970 (FX only for now)
*
@@ -631,6 +457,7 @@ _GLOBAL(scom970_write)
/* restore interrupts */
mtmsrd r5,1
blr
+#endif /* CONFIG_CPU_FREQ_PMAC64 */
/*
--
1.4.0
^ permalink raw reply related
* [PATCH] Make lparcfg.c work when both iseries and pseries are selected
From: Stephen Rothwell @ 2006-06-28 1:57 UTC (permalink / raw)
To: paulus; +Cc: ppc-dev
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
---
arch/powerpc/kernel/lparcfg.c | 69 +++++++++++++++++++----------------------
1 files changed, 32 insertions(+), 37 deletions(-)
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
diff --git a/arch/powerpc/kernel/lparcfg.c b/arch/powerpc/kernel/lparcfg.c
index c02deaa..bcc358d 100644
--- a/arch/powerpc/kernel/lparcfg.c
+++ b/arch/powerpc/kernel/lparcfg.c
@@ -45,11 +45,9 @@ #define MODULE_NAME "lparcfg"
static struct proc_dir_entry *proc_ppc64_lparcfg;
#define LPARCFG_BUFF_SIZE 4096
-#ifdef CONFIG_PPC_ISERIES
-
/*
- * For iSeries legacy systems, the PPA purr function is available from the
- * emulated_time_base field in the paca.
+ * Track sum of all purrs across all processors. This is used to further
+ * calculate usage values by different applications
*/
static unsigned long get_purr(void)
{
@@ -57,30 +55,30 @@ static unsigned long get_purr(void)
int cpu;
for_each_possible_cpu(cpu) {
- sum_purr += lppaca[cpu].emulated_time_base;
+ if (firmware_has_feature(FW_FEATURE_ISERIES))
+ sum_purr += lppaca[cpu].emulated_time_base;
+ else {
+ struct cpu_usage *cu;
-#ifdef PURR_DEBUG
- printk(KERN_INFO "get_purr for cpu (%d) has value (%ld) \n",
- cpu, lppaca[cpu].emulated_time_base);
-#endif
+ cu = &per_cpu(cpu_usage_array, cpu);
+ sum_purr += cu->current_tb;
+ }
}
return sum_purr;
}
-#define lparcfg_write NULL
+#ifdef CONFIG_PPC_ISERIES
/*
* Methods used to fetch LPAR data when running on an iSeries platform.
*/
-static int lparcfg_data(struct seq_file *m, void *v)
+static int iseries_lparcfg_data(struct seq_file *m, void *v)
{
unsigned long pool_id, lp_index;
int shared, entitled_capacity, max_entitled_capacity;
int processors, max_processors;
unsigned long purr = get_purr();
- seq_printf(m, "%s %s \n", MODULE_NAME, MODULE_VERS);
-
shared = (int)(get_lppaca()->shared_proc);
seq_printf(m, "serial_number=%c%c%c%c%c%c%c\n",
e2a(xItExtVpdPanel.mfgID[2]),
@@ -213,22 +211,6 @@ static void h_pic(unsigned long *pool_id
log_plpar_hcall_return(rc, "H_PIC");
}
-/* Track sum of all purrs across all processors. This is used to further */
-/* calculate usage values by different applications */
-
-static unsigned long get_purr(void)
-{
- unsigned long sum_purr = 0;
- int cpu;
- struct cpu_usage *cu;
-
- for_each_possible_cpu(cpu) {
- cu = &per_cpu(cpu_usage_array, cpu);
- sum_purr += cu->current_tb;
- }
- return sum_purr;
-}
-
#define SPLPAR_CHARACTERISTICS_TOKEN 20
#define SPLPAR_MAXLENGTH 1026*(sizeof(char))
@@ -333,7 +315,7 @@ #endif
return count;
}
-static int lparcfg_data(struct seq_file *m, void *v)
+static int pseries_lparcfg_data(struct seq_file *m, void *v)
{
int partition_potential_processors;
int partition_active_processors;
@@ -354,8 +336,6 @@ static int lparcfg_data(struct seq_file
lp_index = *lp_index_ptr;
}
- seq_printf(m, "%s %s \n", MODULE_NAME, MODULE_VERS);
-
seq_printf(m, "serial_number=%s\n", system_id);
seq_printf(m, "system_type=%s\n", model);
@@ -456,6 +436,21 @@ static int lparcfg_data(struct seq_file
return 0;
}
+#endif /* CONFIG_PPC_PSERIES */
+
+static int lparcfg_data(struct seq_file *m, void *v)
+{
+ seq_printf(m, "%s %s \n", MODULE_NAME, MODULE_VERS);
+
+#ifdef CONFIG_PPC_ISERIES
+ if (firmware_has_feature(FW_FEATURE_ISERIES))
+ return iseries_lparcfg_data(m, v);
+#endif
+#ifdef CONFIG_PPC_PSERIES
+ return pseries_lparcfg_data(m, v);
+#endif
+}
+
/*
* Interface for changing system parameters (variable capacity weight
* and entitled capacity). Format of input is "param_name=value";
@@ -469,6 +464,8 @@ static int lparcfg_data(struct seq_file
static ssize_t lparcfg_write(struct file *file, const char __user * buf,
size_t count, loff_t * off)
{
+ ssize_t retval = -ENOMEM;
+#ifdef CONFIG_PPC_PSERIES
char *kbuf;
char *tmp;
u64 new_entitled, *new_entitled_ptr = &new_entitled;
@@ -479,8 +476,6 @@ static ssize_t lparcfg_write(struct file
unsigned long resource;
u8 current_weight;
- ssize_t retval = -ENOMEM;
-
kbuf = kmalloc(count, GFP_KERNEL);
if (!kbuf)
goto out;
@@ -546,11 +541,10 @@ static ssize_t lparcfg_write(struct file
out:
kfree(kbuf);
+#endif /* CONFIG_PPC_PSERIES */
return retval;
}
-#endif /* CONFIG_PPC_PSERIES */
-
static int lparcfg_open(struct inode *inode, struct file *file)
{
return single_open(file, lparcfg_data, NULL);
@@ -569,7 +563,8 @@ int __init lparcfg_init(void)
mode_t mode = S_IRUSR | S_IRGRP | S_IROTH;
/* Allow writing if we have FW_FEATURE_SPLPAR */
- if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
+ if (firmware_has_feature(FW_FEATURE_SPLPAR) &&
+ !firmware_has_feature(FW_FEATURE_ISERIES)) {
lparcfg_fops.write = lparcfg_write;
mode |= S_IWUSR;
}
--
1.4.0
^ permalink raw reply related
* Can anyone tell me if it is a bug of the ELDK4.0?
From: Denny @ 2006-06-28 1:53 UTC (permalink / raw)
To: linuxppc-embedded, wolfgangdenk
In-Reply-To: <e7rcok$fe9$1@sea.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1687 bytes --]
Hi,
I failed to compile the uboot on my 440GP platform, I set the compile switch as "-m440 -mcpu=440",
But the interest thing is when I change the switch to "-m405 -mcpu=440", I can compile my uboot successfully, why?
Also I find all the instructions are existed both in user manual of PPC_405 and PPC440.
make[1]: Leaving directory `/opt/glacier_boot/post/cpu'
ppc_4xx-gcc -Wa,-gstabs -D__ASSEMBLY__ -g -Os -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -D__KERNEL__ -DTEXT_BASE=0xFFC40000 -I/opt/glacier_boot/include -fno-builtin -ffreestanding -nostdinc -isystem /opt/eldk4.0/usr/bin/../lib/gcc/powerpc-linux/4.0.0/include -pipe -DCONFIG_PPC -D__powerpc__ -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -Wa,-m440 -mcpu=440 -msoft-float -c -o cpu/ppc4xx/start.o /opt/glacier_boot/cpu/ppc4xx/start.S
/opt/glacier_boot/cpu/ppc4xx/start.S: Assembler messages:
/opt/glacier_boot/cpu/ppc4xx/start.S:996: Error: Unrecognized opcode: `mfdccr'
/opt/glacier_boot/cpu/ppc4xx/start.S:998: Error: Unrecognized opcode: `mtdccr'
/opt/glacier_boot/cpu/ppc4xx/start.S:1016: Error: Unrecognized opcode: `mtdccr'
/opt/glacier_boot/cpu/ppc4xx/start.S:1027: Error: Unrecognized opcode: `mticcr'
/opt/glacier_boot/cpu/ppc4xx/start.S:1033: Error: Unrecognized opcode: `mticcr'
/opt/glacier_boot/cpu/ppc4xx/start.S:1039: Error: Unrecognized opcode: `mficcr'
/opt/glacier_boot/cpu/ppc4xx/start.S:1050: Error: Unrecognized opcode: `mtdccr'
/opt/glacier_boot/cpu/ppc4xx/start.S:1059: Error: Unrecognized opcode: `mtdccr'
/opt/glacier_boot/cpu/ppc4xx/start.S:1064: Error: Unrecognized opcode: `mfdccr'
make: *** [cpu/ppc4xx/start.o] Error 1
[root@localhost glacier_boot]#
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^ permalink raw reply
* Re: [PATCH] Assume we're on cpu 0 in early boot
From: Michael Ellerman @ 2006-06-28 2:11 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, Arnd Bergmann
In-Reply-To: <17569.56937.308576.848377@cargo.ozlabs.ibm.com>
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On Wed, 2006-06-28 at 11:42 +1000, Paul Mackerras wrote:
> Michael Ellerman writes:
>
> > There's a small period early in boot where we don't know which cpu we're
> > running on. That's ok, except that it means we have no paca, or more
> > correctly that our paca pointer points somewhere random.
> >
> > So that we can safely call things like smp_processor_id(), we need a paca,
> > so just assume we're on cpu 0. No code should _write_ to the paca before
> > we've set the correct one up.
>
> OK, but why not just do a setup_paca(0) at the start of early_setup(),
> in C code? You can also remove the redundant paca setting in
> start_here_common() in head_64.S.
Yep, duh. New patch RSN.
cheers
--
Michael Ellerman
IBM OzLabs
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
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^ permalink raw reply
* [PATCH] Assume we're on cpu 0 in early boot
From: Michael Ellerman @ 2006-06-28 3:18 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, Arnd Bergmann
In-Reply-To: <17569.56937.308576.848377@cargo.ozlabs.ibm.com>
There's a small period early in boot where we don't know which cpu we're
running on. That's ok, except that it means we have no paca, or more
correctly that our paca pointer points somewhere random.
So that we can safely call things like smp_processor_id(), we need a paca,
so just assume we're on cpu 0. No code should _write_ to the paca before
we've set the correct one up.
We setup the proper paca after we've scanned the flat device tree in
early_setup(), so there's no need to do it again in start_here_common.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/kernel/head_64.S | 11 -----------
arch/powerpc/kernel/setup_64.c | 3 +++
2 files changed, 3 insertions(+), 11 deletions(-)
Index: to-merge/arch/powerpc/kernel/head_64.S
===================================================================
--- to-merge.orig/arch/powerpc/kernel/head_64.S
+++ to-merge/arch/powerpc/kernel/head_64.S
@@ -1602,9 +1602,6 @@ _GLOBAL(__start_initialization_multiplat
/* Setup some critical 970 SPRs before switching MMU off */
bl .__970_cpu_preinit
- /* cpu # */
- li r24,0
-
/* Switch off MMU if not already */
LOAD_REG_IMMEDIATE(r4, .__after_prom_start - KERNELBASE)
add r4,r4,r30
@@ -1962,14 +1959,6 @@ _STATIC(start_here_common)
li r3,0
bl .do_cpu_ftr_fixups
- LOAD_REG_IMMEDIATE(r26, boot_cpuid)
- lwz r26,0(r26)
-
- LOAD_REG_IMMEDIATE(r24, paca) /* Get base vaddr of paca array */
- mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
- add r13,r13,r24 /* for this processor. */
- mtspr SPRN_SPRG3,r13
-
/* ptr to current */
LOAD_REG_IMMEDIATE(r4, init_task)
std r4,PACACURRENT(r13)
Index: to-merge/arch/powerpc/kernel/setup_64.c
===================================================================
--- to-merge.orig/arch/powerpc/kernel/setup_64.c
+++ to-merge/arch/powerpc/kernel/setup_64.c
@@ -177,6 +177,9 @@ void __init setup_paca(int cpu)
void __init early_setup(unsigned long dt_ptr)
{
+ /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
+ setup_paca(0);
+
/* Enable early debugging if any specified (see udbg.h) */
udbg_early_init();
^ permalink raw reply
* Re: [PATCH] Make lparcfg.c work when both iseries and pseries are selected
From: Nathan Lynch @ 2006-06-28 4:05 UTC (permalink / raw)
To: Stephen Rothwell; +Cc: ppc-dev, paulus
In-Reply-To: <20060628115728.17f1a04d.sfr@canb.auug.org.au>
Stephen Rothwell wrote:
> static ssize_t lparcfg_write(struct file *file, const char __user * buf,
> size_t count, loff_t * off)
> {
> + ssize_t retval = -ENOMEM;
> +#ifdef CONFIG_PPC_PSERIES
> char *kbuf;
> char *tmp;
> u64 new_entitled, *new_entitled_ptr = &new_entitled;
> @@ -479,8 +476,6 @@ static ssize_t lparcfg_write(struct file
> unsigned long resource;
> u8 current_weight;
>
> - ssize_t retval = -ENOMEM;
> -
> kbuf = kmalloc(count, GFP_KERNEL);
> if (!kbuf)
> goto out;
> @@ -546,11 +541,10 @@ static ssize_t lparcfg_write(struct file
>
> out:
> kfree(kbuf);
> +#endif /* CONFIG_PPC_PSERIES */
> return retval;
> }
Erm... this is kind of gross, and will return -ENOMEM on iSeries when
it should really return -ENOSYS (I think).
Would it be over-engineering to have an lparcfg_ops struct, with
lparcfg_read and lparcfg_write methods (and the latter would be null
on iSeries)? All the additional #ifdeffery doesn't really improve
the readability of this code IMO.
^ permalink raw reply
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