* Re: [PATCH] Use check_legacy_ioport() for ISAPnP
From: David Woodhouse @ 2006-10-02 9:42 UTC (permalink / raw)
To: Olaf Hering; +Cc: paulus, linuxppc-dev
In-Reply-To: <20061002093853.GA13880@aepfle.de>
On Mon, 2006-10-02 at 11:38 +0200, Olaf Hering wrote:
>
> The new check in parport_pc_init() will prevent the probing of PCI
> devices. I guess the correct fix would be a sophisticated
> pmac_check_legacy_ioport() that checks if baseport is available on
> some PCI device:
That or only call check_legacy_ioport() when we're poking _gratuitously_
at legacy space, not when there's a properly-detected port.
--
dwmw2
^ permalink raw reply
* Re: [PATCH] Use check_legacy_ioport() for ISAPnP
From: Olaf Hering @ 2006-10-02 9:38 UTC (permalink / raw)
To: David Woodhouse, Benjamin Herrenschmidt; +Cc: linuxppc-dev, paulus
In-Reply-To: <20060927130525.GA7550@aepfle.de>
[-- Attachment #1: Type: text/plain, Size: 1303 bytes --]
On Wed, Sep 27, Olaf Hering wrote:
> On Wed, Sep 27, David Woodhouse wrote:
>
> > And did you fix the case of PCI parallel ports? We only want to do the
> > check_legacy_ioport() thing for the 'default' built-in ports, not for
> > all ports.
>
> I have to check if my multiport IO card still works, but I'm sure it
> will.
The new check in parport_pc_init() will prevent the probing of PCI
devices. I guess the correct fix would be a sophisticated
pmac_check_legacy_ioport() that checks if baseport is available on some
PCI device:
0001:10:13.0 Serial controller: Timedia Technology Co Ltd PCI2S550 (Dual 16550 UART) (rev 01) (prog-if 02 [16550])
Subsystem: Timedia Technology Co Ltd Unknown device 5079
Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B-
Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Interrupt: pin A routed to IRQ 53
Region 0: I/O ports at f2000800 [size=32]
Region 2: I/O ports at f2000870 [size=8]
Region 3: I/O ports at f2000860 [size=8]
PCI: Enabling device 0001:10:13.0 (0080 -> 0081)
PCI parallel port detected: 1409:7168, I/O at 0x870(0x860)
parport0: PC-style at 0x870 [PCSPP,TRISTATE,EPP]
lp0: using parport0 (polling).
[-- Attachment #2: date-2.6.18-date-serial.txt --]
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Using PowerMac machine description
Total memory = 256MB; using 512kB for hash table (at cff80000)
Linux version 2.6.18-date-serial (olaf@pomegranate) (gcc version 4.1.0 (SUSE Linux)) #20 Mon Oct 2 11:30:24 CEST 2006
Found UniNorth memory controller & host bridge @ 0xf8000000 revision: 0x11
Mapped at 0xfdfc0000
Found a Keylargo mac-io controller, rev: 3, mapped at 0xfdf40000
Processor NAP mode on idle enabled.
PowerMac motherboard: PowerMac G4 Silver
Found UniNorth PCI host bridge at 0x00000000f0000000. Firmware bus number: 0->0
Found UniNorth PCI host bridge at 0x00000000f2000000. Firmware bus number: 0->0
Found UniNorth PCI host bridge at 0x00000000f4000000. Firmware bus number: 0->0
via-pmu: Server Mode is disabled
PMU driver v2 initialized for Core99, firmware: 0c
nvram: Checking bank 0...
nvram: gen0=356, gen1=355
nvram: Active bank is: 0
nvram: OF partition at 0x210
nvram: XP partition at 0x1220
nvram: NR partition at 0x1320
Top of RAM: 0x10000000, Total RAM: 0x10000000
Memory hole size: 0MB
On node 0 totalpages: 65536
DMA zone: 65536 pages, LIFO batch:15
Built 1 zonelists. Total pages: 65536
Kernel command line: root=/dev/hda13 quiet sysrq=1 video=aty128fb:1024x768@75 debug video=aty128fb:1024x768@85
mpic: Setting up MPIC " MPIC 1 " version 1.2 at 80040000, max 4 CPUs
mpic: ISU size: 64, shift: 6, mask: 3f
mpic: Initializing for 64 sources
PID hash table entries: 2048 (order: 11, 8192 bytes)
GMT Delta read from XPRAM: 120 minutes, DST: on
time_init: decrementer frequency = 33.290001 MHz
time_init: processor frequency = 466.666665 MHz
Console: colour dummy device 80x25
pmac_zilog: i2c-modem detected, id: 1
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 252416k/262144k available (3844k kernel code, 9460k reserved, 368k data, 2205k bss, 156k init)
Calibrating delay loop... 66.56 BogoMIPS (lpj=332800)
Mount-cache hash table entries: 512
device-tree: Duplicate name in /cpus/PowerPC,G4@0, renamed to "l2-cache#1"
PM: Adding info for No Bus:platform
NET: Registered protocol family 16
KeyWest i2c @0xf8001003 irq 42 /uni-n@f8000000/i2c@f8001000
channel 0 bus <multibus>
channel 1 bus <multibus>
KeyWest i2c @0x80018000 irq 26 /pci@f2000000/mac-io@17/i2c@18000
channel 0 bus <multibus>
PMU i2c /pci@f2000000/mac-io@17/via-pmu@16000
channel 1 bus <multibus>
channel 2 bus <multibus>
PCI: Probing PCI hardware
PM: Adding info for No Bus:pci0000:00
PM: Adding info for pci:0000:00:0b.0
PM: Adding info for pci:0000:00:10.0
PM: Adding info for No Bus:pci0001:10
PM: Adding info for pci:0001:10:0b.0
PM: Adding info for pci:0001:10:12.0
PM: Adding info for pci:0001:10:12.1
PM: Adding info for pci:0001:10:12.2
PM: Adding info for pci:0001:10:12.3
PM: Adding info for pci:0001:10:13.0
PM: Adding info for pci:0001:10:14.0
PM: Adding info for pci:0001:10:17.0
PM: Adding info for pci:0001:10:18.0
PM: Adding info for pci:0001:10:19.0
PM: Adding info for No Bus:pci0002:20
PM: Adding info for pci:0002:20:0b.0
PM: Adding info for pci:0002:20:0e.0
PM: Adding info for pci:0002:20:0f.0
PM: Adding info for platform:i2c-powermac.0
PM: Adding info for platform:i2c-powermac.1
PM: Adding info for platform:i2c-powermac.2
PM: Adding info for platform:i2c-powermac.3
PM: Adding info for platform:i2c-powermac.4
SCSI subsystem initialized
usbcore: registered new driver usbfs
usbcore: registered new driver hub
NET: Registered protocol family 2
IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 8192 bind 4096)
TCP reno registered
Initializing Cryptographic API
io scheduler noop registered
io scheduler anticipatory registered (default)
io scheduler deadline registered
io scheduler cfq registered
PCI: Enabling device 0000:00:10.0 (0086 -> 0087)
aty128fb: Invalid ROM signature 1111 should be 0xaa55
aty128fb: BIOS not located, guessing timings.
aty128fb: Rage128 PF PRO AGP [chip rev 0x1] 16M 128-bit SDR SGRAM (1:1)
Console: switching to colour frame buffer device 128x48
fb0: ATY Rage128 frame buffer device on Rage128 PF PRO AGP
lp: driver loaded but no devices found
Generic RTC Driver v1.07
Macintosh non-volatile memory driver v1.1
ppdev: user-space parallel port driver
pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)
ttyS0 at MMIO 0x80013020 (irq = 22) is a Z85c30 ESCC - Internal modem
ttyS1 at MMIO 0x80013000 (irq = 50) is a Z85c30 ESCC - Serial port
parport_default_proc_register(485)
parport_pc_init(3377)
IN from bad port 3f1 at c01dd058
IN from bad port 3f1 at c01dd07c
IN from bad port 3f1 at c01dd0a0
IN from bad port 3f1 at c01dd0dc
IN from bad port 3f1 at c01dd100
IN from bad port 3f1 at c01dd124
IN from bad port 371 at c01dd058
IN from bad port 371 at c01dd07c
IN from bad port 371 at c01dd0a0
IN from bad port 371 at c01dd0dc
IN from bad port 371 at c01dd100
IN from bad port 371 at c01dd124
IN from bad port 2f at c01dd058
IN from bad port 2f at c01dd07c
IN from bad port 2f at c01dd0a0
IN from bad port 2f at c01dd0dc
IN from bad port 2f at c01dd100
IN from bad port 2f at c01dd124
IN from bad port 4f at c01dd058
IN from bad port 4f at c01dd07c
IN from bad port 4f at c01dd0a0
IN from bad port 4f at c01dd0dc
IN from bad port 4f at c01dd100
IN from bad port 4f at c01dd124
IN from bad port 3f1 at c01dd058
IN from bad port 3f1 at c01dd07c
IN from bad port 3f1 at c01dd0a0
IN from bad port 3f1 at c01dd0dc
IN from bad port 3f1 at c01dd100
IN from bad port 3f1 at c01dd124
IN from bad port 252 at c01dceb8
IN from bad port 252 at c01dcee4
IN from bad port 252 at c01dcf08
IN from bad port 252 at c01dcf3c
IN from bad port 252 at c01dcf60
IN from bad port 252 at c01dcf84
IN from bad port 252 at c01dceb8
IN from bad port 252 at c01dcee4
IN from bad port 252 at c01dcf08
IN from bad port 252 at c01dcf3c
IN from bad port 252 at c01dcf60
IN from bad port 252 at c01dcf84
IN from bad port 3f1 at c01dcc28
IN from bad port 3f1 at c01dcc4c
IN from bad port 3f1 at c01dcc70
IN from bad port 3f1 at c01dcc94
IN from bad port 3f1 at c01dccd0
IN from bad port 3f1 at c01dccf4
IN from bad port 3f1 at c01dcd18
IN from bad port 3f1 at c01dcd3c
IN from bad port 371 at c01dcc28
IN from bad port 371 at c01dcc4c
IN from bad port 371 at c01dcc70
IN from bad port 371 at c01dcc94
IN from bad port 371 at c01dccd0
IN from bad port 371 at c01dccf4
IN from bad port 371 at c01dcd18
IN from bad port 371 at c01dcd3c
IN from bad port 3f1 at c01dcc28
IN from bad port 3f1 at c01dcc4c
IN from bad port 3f1 at c01dcc70
IN from bad port 3f1 at c01dcc94
IN from bad port 3f1 at c01dccd0
IN from bad port 3f1 at c01dccf4
IN from bad port 3f1 at c01dcd18
IN from bad port 3f1 at c01dcd3c
IN from bad port 371 at c01dcc28
IN from bad port 371 at c01dcc4c
IN from bad port 371 at c01dcc70
IN from bad port 371 at c01dcc94
IN from bad port 371 at c01dccd0
IN from bad port 371 at c01dccf4
IN from bad port 371 at c01dcd18
IN from bad port 371 at c01dcd3c
PCI: Enabling device 0001:10:13.0 (0080 -> 0081)
PCI parallel port detected: 1409:7168, I/O at 0x870(0x860)
parport0: PC-style at 0x870 [PCSPP,TRISTATE,EPP]
lp0: using parport0 (polling).
loop: loaded (max 8 devices)
sungem.c:v0.98 8/24/03 David S. Miller (davem@redhat.com)
PHY ID: 206053, addr: 0
eth0: Sun GEM (PCI) 10/100/1000BaseT Ethernet 00:30:65:f3:4c:ae
eth0: Found BCM5401 PHY
MacIO PCI driver attached to Keylargo chipset
PM: Adding info for macio:0.80000000:mac-io
PM: Adding info for macio:0.00040000:interrup
PM: Adding info for macio:0.00000050:gpio
PM: Adding info for macio:0.00013000:escc
PM: Adding info for macio:0.00010000:i2s
PM: Adding info for macio:0.00015000:timer
PM: Adding info for macio:0.00016000:via-pmu
PM: Adding info for macio:0.00018000:i2c
PM: Adding info for macio:0.0001f000:ata-4
PM: Adding info for macio:0.00020000:ata-3
PM: Adding info for macio:0.00021000:ata-3
PM: Adding info for macio:0.00013020:ch-a
PM: Adding info for macio:0.00013000:ch-b
input: Macintosh mouse button emulation as /class/input/input0
apm_emu: APM Emulation 0.5 initialized.
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx
adb: starting probe task...
adb: finished probe task...
ide0: Found Apple KeyLargo ATA-4 controller, bus ID 2, irq 19
Probing IDE interface ide0...
hda: Maxtor 33073H3 B, ATA DISK drive
PM: Adding info for No Bus:ide0
hda: Enabling Ultra DMA 4
ide0 at 0xd101e000-0xd101e007,0xd101e160 on irq 19
PM: Adding info for ide:0.0
eth0: Link is up at 100 Mbps, full-duplex.
ide1: Found Apple KeyLargo ATA-3 controller, bus ID 0, irq 20
Probing IDE interface ide1...
hdc: SONY CD-RW CRX140E, ATAPI CD/DVD-ROM drive
PM: Adding info for No Bus:ide1
hdd: IOMEGA ZIP 250 ATAPI, ATAPI FLOPPY drive
hdc: Enabling MultiWord DMA 2
ide1 at 0xd1026000-0xd1026007,0xd1026160 on irq 20
PM: Adding info for ide:1.0
PM: Adding info for ide:1.1
ide2: Found Apple KeyLargo ATA-3 controller, bus ID 1, irq 21
Probing IDE interface ide2...
hda: max request size: 128KiB
hda: 60032448 sectors (30736 MB) w/2048KiB Cache, CHS=59556/16/63, UDMA(66)
hda: cache flushes not supported
hda: [mac] hda1 hda2 hda3 hda4 hda5 hda6 hda7 hda8 hda9 hda10 hda11 hda12 hda13 hda14 hda15
hdc: ATAPI 32X CD-ROM CD-R/RW drive, 4096kB Cache, (U)DMA
Uniform CD-ROM driver Revision: 3.20
mesh: configured for synchronous 5 MB/s
ieee1394: Initialized config rom entry `ip1394'
PCI: Enabling device 0001:10:12.3 (0090 -> 0093)
PM: Adding info for ieee1394:fw-host0
ohci1394: fw-host0: OHCI-1394 1.0 (PCI): IRQ=[52] MMIO=[80084000-800847ff] Max Packet=[2048] IR/IT contexts=[8/8]
PM: Adding info for ieee1394:fw-host1
ohci1394: fw-host1: OHCI-1394 1.0 (PCI): IRQ=[40] MMIO=[f5000000-f50007ff] Max Packet=[2048] IR/IT contexts=[8/8]
video1394: Installed video1394 module
ieee1394: raw1394: /dev/raw1394 device initialized
ieee1394: sbp2: Driver forced to serialize I/O (serialize_io=1)
ieee1394: sbp2: Try serialize_io=0 for better performance
eth1394: eth1: IEEE-1394 IPv4 over 1394 Ethernet (fw-host0)
eth1394: eth2: IEEE-1394 IPv4 over 1394 Ethernet (fw-host1)
ohci_hcd: 2005 April 22 USB 1.1 'Open' Host Controller (OHCI) Driver (PCI)
PCI: Enabling device 0001:10:18.0 (0000 -> 0002)
ohci_hcd 0001:10:18.0: OHCI Host Controller
ohci_hcd 0001:10:18.0: new USB bus registered, assigned bus number 1
ohci_hcd 0001:10:18.0: irq 27, io mem 0x80083000
PM: Adding info for usb:usb1
PM: Adding info for No Bus:usbdev1.1_ep00
usb usb1: configuration #1 chosen from 1 choice
PM: Adding info for usb:1-0:1.0
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 2 ports detected
PM: Adding info for No Bus:usbdev1.1_ep81
PCI: Enabling device 0001:10:19.0 (0000 -> 0002)
ohci_hcd 0001:10:19.0: OHCI Host Controller
ohci_hcd 0001:10:19.0: new USB bus registered, assigned bus number 2
ohci_hcd 0001:10:19.0: irq 28, io mem 0x80082000
PM: Adding info for usb:usb2
PM: Adding info for No Bus:usbdev2.1_ep00
usb usb2: configuration #1 chosen from 1 choice
PM: Adding info for usb:2-0:1.0
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 2 ports detected
PM: Adding info for No Bus:usbdev2.1_ep81
usb 1-1: new full speed USB device using ohci_hcd and address 2
PM: Adding info for usb:1-1
PM: Adding info for No Bus:usbdev1.2_ep00
usb 1-1: configuration #1 chosen from 1 choice
PM: Adding info for usb:1-1:1.0
hub 1-1:1.0: USB hub found
hub 1-1:1.0: 3 ports detected
PM: Adding info for No Bus:usbdev1.2_ep81
usb 1-1.1: new low speed USB device using ohci_hcd and address 3
PM: Adding info for ieee1394:0011060000006685
ieee1394: Host added: ID:BUS[0-00:1023] GUID[0011060000006685]
PM: Adding info for ieee1394:0011060000006685-0
PM: Adding info for usb:1-1.1
PM: Adding info for No Bus:usbdev1.3_ep00
usb 1-1.1: configuration #1 chosen from 1 choice
PM: Adding info for usb:1-1.1:1.0
PM: Adding info for No Bus:usbdev1.3_ep81
usb 1-1.2: new low speed USB device using ohci_hcd and address 4
PM: Adding info for ieee1394:003065fffef34cae
ieee1394: Host added: ID:BUS[1-00:1023] GUID[003065fffef34cae]
PM: Adding info for ieee1394:003065fffef34cae-0
PM: Adding info for usb:1-1.2
PM: Adding info for No Bus:usbdev1.4_ep00
usb 1-1.2: configuration #1 chosen from 1 choice
PM: Adding info for usb:1-1.2:1.0
PM: Adding info for No Bus:usbdev1.4_ep81
input: Alps Electric Apple USB Keyboard as /class/input/input1
input: USB HID v1.00 Keyboard [Alps Electric Apple USB Keyboard] on usb-0001:10:18.0-1.1
input: Logitech Apple Optical USB Mouse as /class/input/input2
input: USB HID v1.10 Mouse [Logitech Apple Optical USB Mouse] on usb-0001:10:18.0-1.2
usbcore: registered new driver usbhid
/home/olaf/kernel/olh/mainline-porting/linux-2.6.18/drivers/usb/input/hid-core.c: v2.6:USB HID core driver
usbcore: registered new driver appletouch
mice: PS/2 mouse device common for all mice
PM: Adding info for No Bus:i2c-0
PowerMac i2c bus pmu 2 registered
PM: Adding info for No Bus:i2c-1
PowerMac i2c bus pmu 1 registered
PM: Adding info for No Bus:i2c-2
PowerMac i2c bus mac-io 0 registered
PM: Adding info for No Bus:i2c-3
PowerMac i2c bus uni-n 1 registered
PM: Adding info for No Bus:i2c-4
PowerMac i2c bus uni-n 0 registered
TCP bic registered
NET: Registered protocol family 1
NET: Registered protocol family 17
input: PMU as /class/input/input3
kjournald starting. Commit interval 5 seconds
EXT3-fs: mounted filesystem with ordered data mode.
VFS: Mounted root (ext3 filesystem) readonly.
Freeing unused kernel memory: 156k init
Adding 131064k swap on /dev/hda12. Priority:-1 extents:1 across:131064k
EXT3 FS on hda13, internal journal
kjournald starting. Commit interval 5 seconds
EXT3-fs: mounted filesystem with ordered data mode.
eth1: Link is up at 100 Mbps, full-duplex.
eth1: Pause is enabled (rxfifo: 10240 off: 7168 on: 5632)
hub 2-0:1.0: resuming
hub 2-0:1.0: resuming
00:0b.0 Host bridge: Apple Computer Inc. UniNorth 1.5 AGP
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
Latency: 16, Cache Line Size 08
Capabilities: [80] AGP version 1.0
Status: RQ=8 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW+ AGP3- Rate=x1,x2,x4
Command: RQ=1 ArqSz=0 Cal=0 SBA- AGP- GART64- 64bit- FW- Rate=<none>
00: 6b 10 2d 00 16 00 b0 22 00 00 00 06 08 10 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00
00:10.0 VGA compatible controller: ATI Technologies Inc Rage 128 PF/PRO AGP 4x TMDS (prog-if 00 [VGA])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B-
Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 255 (2000ns min), Cache Line Size 08
Interrupt: pin A routed to IRQ 48
Region 0: Memory at 94000000 (32-bit, prefetchable) [size=64M]
Region 1: I/O ports at f0000400 [size=256]
Region 2: Memory at 90000000 (32-bit, non-prefetchable) [size=16K]
Expansion ROM at f1000000 [disabled] [size=128K]
Capabilities: [50] AGP version 2.0
Status: RQ=32 Iso- ArqSz=0 Cal=0 SBA+ ITACoh- GART64- HTrans- 64bit- FW- AGP3- Rate=x1,x2,x4
Command: RQ=1 ArqSz=0 Cal=0 SBA+ AGP- GART64- 64bit- FW- Rate=<none>
Capabilities: [5c] Power Management version 2
Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 02 10 46 50 87 00 b0 02 00 00 00 03 08 ff 00 00
10: 08 00 00 94 01 04 00 00 00 00 00 90 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 f1 50 00 00 00 00 00 00 00 30 01 08 00
0001:10:0b.0 Host bridge: Apple Computer Inc. UniNorth 1.5 PCI
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
Latency: 16, Cache Line Size 08
00: 6b 10 2e 00 16 00 a0 22 00 00 00 06 08 10 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0001:10:12.0 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 61) (prog-if 00 [UHCI])
Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller
Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 16, Cache Line Size 08
Interrupt: pin A routed to IRQ 52
Region 4: I/O ports at f2000840 [disabled] [size=32]
Capabilities: [80] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 38 30 14 00 10 02 61 00 03 0c 08 10 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 41 08 00 00 00 00 00 00 00 00 00 00 06 11 38 30
30: 00 00 00 00 80 00 00 00 00 00 00 00 34 01 00 00
0001:10:12.1 USB Controller: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller (rev 61) (prog-if 00 [UHCI])
Subsystem: VIA Technologies, Inc. VT82xxxxx UHCI USB 1.1 Controller
Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 16, Cache Line Size 08
Interrupt: pin B routed to IRQ 52
Region 4: I/O ports at f2000820 [disabled] [size=32]
Capabilities: [80] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 38 30 14 00 10 02 61 00 03 0c 08 10 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 21 08 00 00 00 00 00 00 00 00 00 00 06 11 38 30
30: 00 00 00 00 80 00 00 00 00 00 00 00 34 02 00 00
0001:10:12.2 USB Controller: VIA Technologies, Inc. USB 2.0 (rev 62) (prog-if 20 [EHCI])
Subsystem: VIA Technologies, Inc. USB 2.0
Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 16, Cache Line Size 08
Interrupt: pin C routed to IRQ 52
Region 0: Memory at 80081000 (32-bit, non-prefetchable) [disabled] [size=256]
Capabilities: [80] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 04 31 14 00 10 02 62 20 03 0c 08 10 80 00
10: 00 10 08 80 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 04 31
30: 00 00 00 00 80 00 00 00 00 00 00 00 34 03 00 00
0001:10:12.3 FireWire (IEEE 1394): VIA Technologies, Inc. IEEE 1394 Host Controller (rev 46) (prog-if 10 [OHCI])
Subsystem: VIA Technologies, Inc. Unknown device e8e9
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping+ SERR- FastB2B-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 16 (8000ns max), Cache Line Size 08
Interrupt: pin A routed to IRQ 52
Region 0: Memory at 80084000 (32-bit, non-prefetchable) [size=2K]
Region 1: I/O ports at f2000000 [size=128]
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1- D2+ AuxCurrent=0mA PME(D0-,D1-,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: 06 11 44 30 97 00 10 02 46 10 00 0c 08 10 00 00
10: 00 40 08 80 01 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 e9 e8
30: 00 00 00 00 50 00 00 00 00 00 00 00 34 01 00 20
0001:10:13.0 Serial controller: Timedia Technology Co Ltd PCI2S550 (Dual 16550 UART) (rev 01) (prog-if 02 [16550])
Subsystem: Timedia Technology Co Ltd Unknown device 5079
Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR- FastB2B-
Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Interrupt: pin A routed to IRQ 53
Region 0: I/O ports at f2000800 [size=32]
Region 2: I/O ports at f2000870 [size=8]
Region 3: I/O ports at f2000860 [size=8]
00: 09 14 68 71 81 00 80 02 01 02 00 07 00 00 00 00
10: 01 08 00 00 00 00 00 00 71 08 00 00 61 08 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 09 14 79 50
30: 00 00 00 00 00 00 00 00 00 00 00 00 35 01 00 00
0001:10:14.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ (rev 10)
Subsystem: Realtek Semiconductor Co., Ltd. RT8139
Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 16 (8000ns min, 16000ns max)
Interrupt: pin A routed to IRQ 54
Region 0: I/O ports at f2000400 [disabled] [size=256]
Region 1: Memory at 80080000 (32-bit, non-prefetchable) [disabled] [size=256]
Expansion ROM at 80090000 [disabled] [size=64K]
Capabilities: [50] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA PME(D0-,D1+,D2+,D3hot+,D3cold+)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00: ec 10 39 81 04 00 90 02 10 00 00 02 00 10 00 00
10: 01 04 00 00 00 00 08 80 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ec 10 39 81
30: 00 00 09 80 50 00 00 00 00 00 00 00 36 01 20 40
0001:10:17.0 Class ff00: Apple Computer Inc. KeyLargo Mac I/O (rev 03)
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 16, Cache Line Size 08
Region 0: Memory at 80000000 (32-bit, non-prefetchable) [size=512K]
00: 6b 10 22 00 16 00 00 02 03 00 00 ff 08 10 00 00
10: 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0001:10:18.0 USB Controller: Apple Computer Inc. KeyLargo USB (prog-if 10 [OHCI])
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 16 (750ns min, 21500ns max)
Interrupt: pin A routed to IRQ 27
Region 0: Memory at 80083000 (32-bit, non-prefetchable) [size=4K]
00: 6b 10 19 00 06 00 00 02 00 10 03 0c 00 10 00 00
10: 00 30 08 80 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 1b 01 03 56
0001:10:19.0 USB Controller: Apple Computer Inc. KeyLargo USB (prog-if 10 [OHCI])
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 16 (750ns min, 21500ns max)
Interrupt: pin A routed to IRQ 28
Region 0: Memory at 80082000 (32-bit, non-prefetchable) [size=4K]
00: 6b 10 19 00 06 00 00 02 00 10 03 0c 00 10 00 00
10: 00 20 08 80 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 1c 01 03 56
0002:20:0b.0 Host bridge: Apple Computer Inc. UniNorth 1.5 Internal PCI
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
Latency: 16, Cache Line Size 08
00: 6b 10 2f 00 16 00 a0 22 00 00 00 06 08 10 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0002:20:0e.0 FireWire (IEEE 1394): Agere Systems FW323 (prog-if 10 [OHCI])
Subsystem: Agere Systems FW323
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 16 (3000ns min, 6000ns max), Cache Line Size 08
Interrupt: pin A routed to IRQ 40
Region 0: Memory at f5000000 (32-bit, non-prefetchable) [size=4K]
Capabilities: [44] Power Management version 2
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME+
00: c1 11 11 58 16 00 90 02 00 10 00 0c 08 10 00 00
10: 00 00 00 f5 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 c1 11 11 58
30: 00 00 00 00 44 00 00 00 00 00 00 00 28 01 0c 18
0002:20:0f.0 Ethernet controller: Apple Computer Inc. UniNorth GMAC (Sun GEM) (rev 01)
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort- >SERR- <PERR+
Latency: 16 (16000ns min, 16000ns max), Cache Line Size 08
Interrupt: pin A routed to IRQ 41
Region 0: Memory at f5200000 (32-bit, non-prefetchable) [size=2M]
Expansion ROM at f5100000 [disabled] [size=1M]
00: 6b 10 21 00 16 00 a0 84 01 00 00 02 08 10 00 00
10: 00 00 20 f5 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 10 f5 00 00 00 00 00 00 00 00 29 01 40 40
name ""
linux,phandle ff83c1c8
AAPL,add-fcode-file ff81f498
clock-frequency 07efdc44 (133160004)
#size-cells 00000001
#address-cells 00000001
system-id "0000000000000"
device_type "bootrom"
copyright "Copyright 1983-2001 Apple Computer, Inc. All Rights Reserved"
scb# 00000000
color-code ff 06 ..
customer-sw-config " "
serial-number "JQF"
""
""
""
""
""
""
""
""
""
"CK113H2Q"
""
""
""
""
""
""
""
""
""
""
""
""
""
""
""
""
""
""
""
""
""
compatible "PowerMac3,4"
"MacRISC2"
"MacRISC"
"Power Macintosh"
model "PowerMac3,4"
/proc/device-tree/pci@f4000000:
name "pci"
linux,phandle ff90a950
interrupt-map-mask 0000f800 00000000 00000000 00000000
interrupt-map 00007000 00000000 00000000 00000000
ff90fa80 00000028 00000001 00007800
00000000 00000000 00000000 ff90fa80
00000029 00000001
interrupt-parent ff90fa80
interrupts 0000002b 00000001
bus-range 00000000 00000000
ranges 02000000 00000000 f5000000 f5000000 00000000 01000000
01000000 00000000 00000000 f4000000 00000000 00800000
write-combining
built-in-names 00 00 c0 00 46 69 72 65 57 69 72 65 00 45 74 68....FireWire.Eth
65 72 6e 65 74 00 ernet.
clock-frequency 03f940aa (66666666)
#interrupt-cells 00000001
#size-cells 00000002
#address-cells 00000003
reg f4000000 02000000
compatible "uni-north"
model "AAPL,UniNorth"
device_type "pci"
/proc/device-tree/pci@f4000000/ethernet@f:
name "ethernet"
linux,phandle ff9497b8
gbit-phy
assigned-addresses 82007810 00000000 f5200000 00000000 00200000
82007830 00000000 f5100000 00000000 00100000
local-mac-address 00 30 65 f3 4c ae .0e.L.
stats 00000001 00000001 00000ff4 00000000 00000000
reg 00007800 00000000 00000000 00000000 00000000
02007810 00000000 00000000 00000000 00020000
02007830 00000000 00000000 00000000 00010000
max-frame-size 000005ee (1518)
address-bits 00000030 (48)
built-in
compatible "gmac"
category "net"
removable "network"
network-type "ethernet"
device_type "network"
fast-back-to-back
devsel-speed 00000002
max-latency 00000040 (64)
min-grant 00000040 (64)
interrupts 00000001
class-code 00020000 (131072)
revision-id 00000001
device-id 00000021 (33)
vendor-id 0000106b (4203)
/proc/device-tree/pci@f4000000/ethernet@f/ethernet-phy:
name "ethernet-phy"
linux,phandle ff971830
gpio-parent ff90fcd0
gpio-value 00000001
gpio-mask 00000001
gpio-reg 00000010 (16)
interrupt-parent ff90fa80
interrupts 00000033 00000000
compatible "B5401"
phy-id 00006053 (24659)
device_type "ethernet-phy"
/proc/device-tree/pci@f4000000/firewire@e:
name "firewire"
linux,phandle ff940e40
assigned-addresses 82007010 00000000 f5000000 00000000 00001000
local-guid 003065ff fef34cae
#size-cells 00000002
#address-cells 00000004
compatible "pci11c1,5811"
"pci11c1,5811"
"pciclass,0c0010"
reg 00007000 00000000 00000000 00000000 00000000
02007010 00000000 00000000 00000000 00001000
device_type "ieee1394"
fast-back-to-back
devsel-speed 00000001
subsystem-id 00005811 (22545)
subsystem-vendor-id 000011c1 (4545)
max-latency 00000018 (24)
min-grant 0000000c (12)
interrupts 00000001
class-code 000c0010 (786448)
revision-id 00000000
device-id 00005811 (22545)
vendor-id 000011c1 (4545)
/proc/device-tree/pci@f2000000:
name "pci"
linux,phandle ff909798
interrupt-map-mask 0000f800 00000000 00000000 00000000
interrupt-map 00009000 00000000 00000000 00000000
ff90fa80 00000034 00000001 00009800
00000000 00000000 00000000 ff90fa80
00000035 00000001 0000a000 00000000
00000000 00000000 ff90fa80 00000036
00000001 0000a800 00000000 00000000
00000000 ff90fa80 0000003a 00000001
0000d000 00000000 00000000 00000000
ff90fa80 0000003f 00000001 0000c000
00000000 00000000 00000000 ff90fa80
0000001b 00000001 0000c800 00000000
00000000 00000000 ff90fa80 0000001c
00000001
interrupt-parent ff90fa80
interrupts 0000002c 00000001
bus-range 00000000 00000000
ranges 02000000 00000000 f3000000 f3000000 00000000 01000000
01000000 00000000 00000000 f2000000 00000000 00800000
02000000 00000000 80000000 80000000 00000000 10000000
write-combining
slot-names 003c0000 534c4f54 2d330053 4c4f542d
3400534c 4f542d35 00534c4f 542d3200
built-in-names 03 80 00 00 4d 41 43 2d 49 4f 00 55 53 42 30 00....MAC-IO.USB0.
55 53 42 31 00 USB1.
clock-frequency 01fca055 (33333333)
#interrupt-cells 00000001
#size-cells 00000002
#address-cells 00000003
reg f2000000 02000000
compatible "uni-north"
model "AAPL,UniNorth"
device_type "pci"
/proc/device-tree/pci@f2000000/usb@19:
name "usb"
linux,phandle ff938ea8
AAPL,bus-id 00000002
AAPL,clock-data 02dc6c00 00000038 01000000 00000038 00400000 00000000
00000000 00000044 00000008 6e756c6c 6e756c6c 01e84800
AAPL,clock-aux-data 00000002 00000048 0f0f0000 00000001
00000008 00000038 10000000 00000000
AAPL,clock-id 75736231 75313438
assigned-addresses 8200c810 00000000 80082000 00000000 00001000
compatible "pci106b,19"
"pciclass,0c0310"
#size-cells 00000000
#address-cells 00000001
reg 0000c800 00000000 00000000 00000000 00000000
0200c810 00000000 00000000 00000000 00001000
device_type "usb"
devsel-speed 00000001
max-latency 00000056 (86)
min-grant 00000003
interrupts 00000001
class-code 000c0310 (787216)
revision-id 00000001
device-id 00000019 (25)
vendor-id 0000106b (4203)
/proc/device-tree/pci@f2000000/usb@18:
name "usb"
linux,phandle ff931220
AAPL,bus-id 00000001
AAPL,clock-data 02dc6c00 00000038 00100000 00000038 00040000 00000000
00000000 00000044 00000008 6e756c6c 6e756c6c 01e84800
AAPL,clock-aux-data 00000002 00000048 00000f0f 00000001
00000008 00000038 10000000 00000000
AAPL,clock-id 75736230 75303438
assigned-addresses 8200c010 00000000 80083000 00000000 00001000
compatible "pci106b,19"
"pciclass,0c0310"
#size-cells 00000000
#address-cells 00000001
reg 0000c000 00000000 00000000 00000000 00000000
0200c010 00000000 00000000 00000000 00001000
device_type "usb"
devsel-speed 00000001
max-latency 00000056 (86)
min-grant 00000003
interrupts 00000001
class-code 000c0310 (787216)
revision-id 00000001
device-id 00000019 (25)
vendor-id 0000106b (4203)
/proc/device-tree/pci@f2000000/usb@18/hub@1:
name "hub"
linux,phandle ff970090
#size-cells 00000000
#address-cells 00000001
device_type "hub"
assigned-address 00000001
reg 00000001
/proc/device-tree/pci@f2000000/usb@18/hub@1/mouse@2:
name "mouse"
linux,phandle ff970650
endpoints 00040381 (263041)
#buttons 00000001
device_type "mouse"
assigned-address 00000003
reg 00000002
/proc/device-tree/pci@f2000000/usb@18/hub@1/keyboard@1:
name "keyboard"
linux,phandle ff970298
endpoints 00080381 (525185)
device_type "keyboard"
assigned-address 00000002
reg 00000001
/proc/device-tree/pci@f2000000/pci10ec,8139@14:
name "pci10ec,8139"
linux,phandle ff930ec8
assigned-addresses 8100a010 00000000 00000400 00000000 00000100
8200a030 00000000 80090000 00000000 00010000
8200a014 00000000 80080000 00000000 00000100
reg 0000a000 00000000 00000000 00000000 00000000
0100a010 00000000 00000000 00000000 00000100
0200a014 00000000 00000000 00000000 00000100
0200a030 00000000 00000000 00000000 00010000
compatible "pci10ec,8139"
"pci10ec,8139"
"pciclass,020000"
fast-back-to-back
devsel-speed 00000001
subsystem-id 00008139 (33081)
subsystem-vendor-id 000010ec (4332)
max-latency 00000040 (64)
min-grant 00000020 (32)
interrupts 00000001
class-code 00020000 (131072)
revision-id 00000010 (16)
device-id 00008139 (33081)
vendor-id 000010ec (4332)
/proc/device-tree/pci@f2000000/pci1409,5079@13:
name "pci1409,5079"
linux,phandle ff930b70
assigned-addresses 81009818 00000000 00000870 00000000 00000010
8100981c 00000000 00000860 00000000 00000010
81009810 00000000 00000800 00000000 00000020
reg 00009800 00000000 00000000 00000000 00000000
01009810 00000000 00000000 00000000 00000020
01009818 00000000 00000000 00000000 00000010
0100981c 00000000 00000000 00000000 00000010
compatible "pci1409,5079"
"pci1409,7168"
"pciclass,070002"
fast-back-to-back
devsel-speed 00000001
subsystem-id 00005079 (20601)
subsystem-vendor-id 00001409 (5129)
max-latency 00000000
min-grant 00000000
interrupts 00000001
class-code 00070002 (458754)
revision-id 00000001
device-id 00007168 (29032)
vendor-id 00001409 (5129)
/proc/device-tree/pci@f2000000/firewire@12,3:
name "firewire"
linux,phandle ff928220
assigned-addresses 82009310 00000000 80084000 00000000 00001000
local-guid 00110600 00006685
#size-cells 00000002
#address-cells 00000004
compatible "pci1106,e8e9"
"pci1106,3044"
"pciclass,0c0010"
reg 00009300 00000000 00000000 00000000 00000000
02009310 00000000 00000000 00000000 00001000
device_type "ieee1394"
devsel-speed 00000001
subsystem-id 0000e8e9 (59625)
subsystem-vendor-id 00001106 (4358)
max-latency 00000020 (32)
min-grant 00000000
interrupts 00000001
class-code 000c0010 (786448)
revision-id 00000046 (70)
device-id 00003044 (12356)
vendor-id 00001106 (4358)
/proc/device-tree/pci@f2000000/pci1106,3104@12,2:
name "pci1106,3104"
linux,phandle ff927f18
assigned-addresses 82009210 00000000 80081000 00000000 00000100
reg 00009200 00000000 00000000 00000000 00000000
02009210 00000000 00000000 00000000 00000100
compatible "pci1106,3104"
"pci1106,3104"
"pciclass,0c0320"
devsel-speed 00000001
subsystem-id 00003104 (12548)
subsystem-vendor-id 00001106 (4358)
max-latency 00000000
min-grant 00000000
interrupts 00000003
class-code 000c0320 (787232)
revision-id 00000062 (98)
device-id 00003104 (12548)
vendor-id 00001106 (4358)
/proc/device-tree/pci@f2000000/pci1106,3038@12,1:
name "pci1106,3038"
linux,phandle ff927c10
assigned-addresses 81009120 00000000 00000820 00000000 00000020
reg 00009100 00000000 00000000 00000000 00000000
01009120 00000000 00000000 00000000 00000020
compatible "pci1106,3038"
"pci1106,3038"
"pciclass,0c0300"
devsel-speed 00000001
subsystem-id 00003038 (12344)
subsystem-vendor-id 00001106 (4358)
max-latency 00000000
min-grant 00000000
interrupts 00000002
class-code 000c0300 (787200)
revision-id 00000061 (97)
device-id 00003038 (12344)
vendor-id 00001106 (4358)
/proc/device-tree/pci@f2000000/pci1106,3038@12:
name "pci1106,3038"
linux,phandle ff927908
assigned-addresses 81009020 00000000 00000840 00000000 00000020
reg 00009000 00000000 00000000 00000000 00000000
01009020 00000000 00000000 00000000 00000020
compatible "pci1106,3038"
"pci1106,3038"
"pciclass,0c0300"
devsel-speed 00000001
subsystem-id 00003038 (12344)
subsystem-vendor-id 00001106 (4358)
max-latency 00000000
min-grant 00000000
interrupts 00000001
class-code 000c0300 (787200)
revision-id 00000061 (97)
device-id 00003038 (12344)
vendor-id 00001106 (4358)
/proc/device-tree/pci@f2000000/mac-io@17:
linux,device c08f1008
name "mac-io"
linux,phandle ff90bac8
ranges 00000000 8200b810 00000000 80000000 00080000
#interrupt-cells 00000002
#size-cells 00000001
#address-cells 00000001
assigned-addresses 8200b810 00000000 80000000 00000000 00080000
devsel-speed 00000001
max-latency 00000000
min-grant 00000000
class-code 00ff0000 (16711680)
revision-id 00000003
device-id 00000022 (34)
vendor-id 0000106b (4203)
reg 0000b800 00000000 00000000 00000000 00000000
0200b810 00000000 00000000 00000000 00080000
compatible "Keylargo"
model "AAPL,Keylargo"
device_type "mac-io"
/proc/device-tree/pci@f2000000/mac-io@17/ata-3@21000:
linux,device cfeb4808
name "ata-3"
linux,phandle ff91e5d0
interrupt-parent ff90fa80
interrupts 00000015 00000001 0000000d 00000000
built-in
model "ata-3"
AAPL,pio-timing 00000526 00000085 00000025 00000025
00000025 00000000 00000000 00000000
#size-cells 00000000
#address-cells 00000001
reg 00021000 00001000 00008c00 00000100
AAPL,bus-id 00000001
compatible "keylargo-ata"
AAPL,connector "ata"
device_type "ata"
/proc/device-tree/pci@f2000000/mac-io@17/ata-3@21000/disk:
name "disk"
linux,phandle ff920cc0
device_type "block"
/proc/device-tree/pci@f2000000/mac-io@17/ata-3@20000:
linux,device cfeb4c08
name "ata-3"
linux,phandle ff91b780
AAPL,clock-aux-data 00000010 0000003c 00800000 00000000
00000010 00000040 00000002 00000000
AAPL,clock-data 03ef1480 00000000 00000000 00000000 00000000 00000044
00000100 00000044 00000080 6e756c6c 6e756c6c 00000000
AAPL,clock-id 61746161 61613636
interrupt-parent ff90fa80
interrupts 00000014 00000001 0000000c 00000000
built-in
model "ata-3"
AAPL,pio-timing 00000526 00000085 00000025 00000025
00000025 00000000 00000000 00000000
#size-cells 00000000
#address-cells 00000001
reg 00020000 00001000 00008b00 00000100
AAPL,bus-id 00000000
compatible "keylargo-ata"
AAPL,connector "ata"
device_type "ata"
/proc/device-tree/pci@f2000000/mac-io@17/ata-3@20000/disk:
name "disk"
linux,phandle ff91de70
device_type "block"
/proc/device-tree/pci@f2000000/mac-io@17/ata-4@1f000:
linux,device cfebc008
name "ata-4"
linux,phandle ff918930
AAPL,clock-aux-data 00000010 0000003c 20000000 00000000
AAPL,clock-data 03ef1480 00000000 00000000 00000000 00000000 00000044
00000100 00000044 00000080 6e756c6c 6e756c6c 00000000
AAPL,clock-id 75617461 61743636
cable-type "80-conductor"
interrupt-parent ff90fa80
interrupts 00000013 00000001 0000000b 00000000
model "ata-4"
AAPL,pio-timing 00000526 00000085 00000025 00000025
00000025 00000000 00000000 00000000
#size-cells 00000000
#address-cells 00000001
reg 0001f000 00001000 00008a00 00000100
AAPL,bus-id 00000002
compatible "keylargo-ata"
AAPL,connector "ata"
device_type "ata"
/proc/device-tree/pci@f2000000/mac-io@17/ata-4@1f000/disk:
name "disk"
linux,phandle ff91b020
category "hd"
device_type "block"
/proc/device-tree/pci@f2000000/mac-io@17/i2c@18000:
linux,device cfebc408
name "i2c"
linux,phandle ff9177b8
AAPL,driver-name ".i2c-mac-io"
AAPL,i2c-rate 00000064 (100)
AAPL,address-step 00000010 (16)
AAPL,address 80018000
interrupt-parent ff90fa80
interrupts 0000001a 00000001
reg 00018000 00001000
built-in
compatible "keywest-i2c"
device_type "i2c"
/proc/device-tree/pci@f2000000/mac-io@17/i2c@18000/i2c-modem:
name "i2c-modem"
linux,phandle ff9713b0
slot-names 00 00 00 01 4d 6f 64 65 6d 00 ....Modem.
compatible "spring"
modem-id 01010201 342e3046 31372e30 46310301 03000000 00000000
device_type "i2c-modem"
/proc/device-tree/pci@f2000000/mac-io@17/i2c@18000/deq:
name "deq"
linux,phandle ff9187f0
i2c-address 00000068 (104)
device_type "deq"
/proc/device-tree/pci@f2000000/mac-io@17/i2c@18000/cereal:
name "cereal"
linux,phandle ff9180c0
device_type "serial"
/proc/device-tree/pci@f2000000/mac-io@17/via-pmu@16000:
linux,device cfebc808
name "via-pmu"
linux,phandle ff913788
AAPL,clock-data 01de2000 00000044 00008000 00000000 00000000 00000044
00008000 00000044 00000010 6e756c6c 6e756c6c 012ad400
AAPL,clock-id 73706920 73703331
pmu-version 00d04a0c (13650444)
interrupt-parent ff90fa80
interrupts 00000019 00000001
reg 00016000 00002000
compatible "pmu"
device_type "via-pmu"
/proc/device-tree/pci@f2000000/mac-io@17/via-pmu@16000/power-mgt:
name "power-mgt"
linux,phandle ff9174d0
prim-info 00 00 00 ff 00 00 00 2c 00 03 0d 40 00 01 e7 05.......,...@....
00 00 34 00 00 00 00 00 00 00 26 0d 46 00 02 78..4.......&.F..x
78 3c 00 x<.
registry-name "extint-gpio1"
max-aux-power 000000da (218)
compatible "via-pmu-99"
device_type "power-mgt"
/proc/device-tree/pci@f2000000/mac-io@17/via-pmu@16000/power-mgt/usb-power-mgt:
name "usb-power-mgt"
linux,phandle ff971630
interrupt-parent ff90fa80
interrupts 0000001d 00000001
compatible "usb-power-mgt"
device_type "usb-power-mgt"
/proc/device-tree/pci@f2000000/mac-io@17/via-pmu@16000/rtc:
name "rtc"
linux,phandle ff916d60
compatible "rtc,via-pmu"
device_type "rtc"
/proc/device-tree/pci@f2000000/mac-io@17/timer@15000:
linux,device cfebcc08
name "timer"
linux,phandle ff913578
clock-frequency 01194000 (18432000)
interrupt-parent ff90fa80
interrupts 00000020 00000001
compatible "keylargo-timer"
reg 00015000 00001000
built-in
device_type "timer"
/proc/device-tree/pci@f2000000/mac-io@17/i2s@10000:
linux,device cfec3008
name "i2s"
linux,phandle ff912920
ranges
#address-cells 00000001
reg 00010000 00001000 00008000 00000100 00008100
00000100 00008200 00000100 00008300 00000100
built-in
device_type "i2s"
/proc/device-tree/pci@f2000000/mac-io@17/i2s@10000/i2s-a@10000:
name "i2s-a"
linux,phandle ff912b50
AAPL,clock-data 02b11000 0000003c 00003400 00000044 00004000 00000044
00000400 00000044 00000004 69303439 6e756c6c 00000000
02ee0000 0000003c 00003400 00000044 00004000 00000044
00000200 00000044 00000002 69303435 6e756c6c 00000000
01194000 0000003c 00003000 0000003c 00000400 00000044
00004000 00000000 00000000 6e756c6c 6e756c6c 00000000
AAPL,clock-id 69327330 69303435 69303439 69303138
AAPL,requested-priorities 00000002 00000004 00000004
interrupt-parent ff90fa80
interrupts 0000001e 00000001 00000001 00000000 00000002 00000000
reg 00010000 00001000 00008000 00000100 00008100 00000100
built-in
compatible "i2sbus"
device_type "soundbus"
/proc/device-tree/pci@f2000000/mac-io@17/i2s@10000/i2s-a@10000/sound:
name "sound"
linux,phandle ff912e80
sound-objects "feature index 0 model Proj14PowerControl"
"feature index 1 model USBSubwoofer"
"feature index 2 model Equalizer"
"detect index 0 bit-mask 2 bit-match 0 device 2 registry-name extint-gpio15 model GPIOGenericDetect"
"detect index 1 bit-mask 2 bit-match 0 device 4 registry-name extint-gpio16 model GPIOGenericDetect"
"output index 0 device-mask 6 device-match 0 icon-id -16563 name-id -20525 port-connection 2 port-type 0x6973706B model OutputEQPort"
"output index 1 device-mask 6 device-match 4 icon-id -16563 name-id -20523 port-connection 3 port-type 0x6573706B model OutputDallasEQPort"
"output index 2 device-mask 2 device-match 2 icon-id -16563 name-id -20524 port-connection 1 port-type 0x6864706E model OutputEQPort"
""
sub-frame 00000000
mclk-sample-rate-ratio 00000100 (256)
i2s-serial-format 00000002
sample-rates 00000002 ac440000 bb800000
object-model-version 00000001
name-id ffffbf4d (-16563)
model "355S0056"
info-id ffffbf44 (-16572)
icon-id ffffbf4d (-16563)
hardware-types 00000002
equalizer-id 33353553 30303537
device-id 0000000e (14)
default-monitor "none"
#-outputs 00000003
#-features 00000003
#-inputs 00000000
#-detects 00000002
vendor-id 0000106b (4203)
compatible "tumbler"
device_type "soundchip"
/proc/device-tree/pci@f2000000/mac-io@17/escc@13000:
linux,device cfec3408
name "escc"
linux,phandle ff9112d8
ranges
#address-cells 00000001
reg 00013000 00001000 00008400 00000100 00008500
00000100 00008600 00000100 00008700 00000100
built-in
compatible "chrp,es0"
device_type "escc"
/proc/device-tree/pci@f2000000/mac-io@17/escc@13000/ch-b@13000:
linux,device cfeb4008
name "ch-b"
linux,phandle ff911f88
slot-names 00000000
interrupt-parent ff90fa80
interrupts 00000032 00000001 00000007 00000000 00000008 00000000
reg 00013000 00000001 00013010 00000001 00013040
00000001 00008600 00000100 00008700 00000100
built-in
compatible "chrp,es3"
device_type "serial"
/proc/device-tree/pci@f2000000/mac-io@17/escc@13000/ch-a@13020:
linux,device cfeb4408
name "ch-a"
linux,phandle ff911560
slot-names 00 00 00 01 4d 6f 64 65 6d 00 ....Modem.
modem-id 01010201 342e3046 31372e30 46310301 03000000 00000000
AAPL,clock-data 01de2000 00000038 00000054 00000000 00000000 00000044
00000800 00000044 00000010 73613435 73623331 012ad400
02b11000 00000038 00000050 00000038 00000004 00000044
00000400 00000044 00000004 73613331 73623435 00000000
AAPL,clock-id 73636361 73613331 73613435
interrupt-parent ff90fa80
interrupts 00000016 00000001 00000005 00000000 00000006 00000000
reg 00013020 00000001 00013030 00000001 00013050
00000001 00008400 00000100 00008500 00000100
built-in
compatible "chrp,es2"
"cobalt"
device_type "serial"
/proc/device-tree/pci@f2000000/mac-io@17/escc-legacy@12000:
name "escc-legacy"
linux,phandle ff910c68
ranges
#address-cells 00000001
reg 00012000 00001000 00008400 00000100 00008500
00000100 00008600 00000100 00008700 00000100
built-in
compatible "chrp,es1"
device_type "escc-legacy"
/proc/device-tree/pci@f2000000/mac-io@17/escc-legacy@12000/ch-b@12000:
name "ch-b"
linux,phandle ff9110d8
interrupt-parent ff90fa80
interrupts 00000032 00000001 00000007 00000000 00000008 00000000
reg 00012000 00000001 00012002 00000001 00012008
00000001 00008600 00000100 00008700 00000100
built-in
compatible "chrp,es5"
device_type "serial"
/proc/device-tree/pci@f2000000/mac-io@17/escc-legacy@12000/ch-a@12004:
name "ch-a"
linux,phandle ff910ed8
interrupt-parent ff90fa80
interrupts 00000016 00000001 00000005 00000000 00000006 00000000
reg 00012004 00000001 00012006 00000001 0001200a
00000001 00008400 00000100 00008500 00000100
built-in
compatible "chrp,es4"
device_type "serial"
/proc/device-tree/pci@f2000000/mac-io@17/gpio@50:
linux,device cfec3808
name "gpio"
linux,phandle ff90fcd0
reg 00000050 00000030
built-in
device_type "gpio"
/proc/device-tree/pci@f2000000/mac-io@17/gpio@50/extint-gpio16:
name "extint-gpio16"
linux,phandle ff910a00
interrupt-parent ff90fa80
interrupts 0000003e 00000000
AAPL,address 80000068
built-in
one-wire-bus "speaker-id"
AAPL,driver-name ".DallasDriver"
compatible "keywest-gpio16"
device_type "extint-gpio16"
/proc/device-tree/pci@f2000000/mac-io@17/gpio@50/extint-gpio15:
name "extint-gpio15"
linux,phandle ff9107f8
interrupt-parent ff90fa80
interrupts 0000003d 00000000
AAPL,address 80000067
built-in
compatible "keywest-gpio15"
device_type "extint-gpio15"
/proc/device-tree/pci@f2000000/mac-io@17/gpio@50/gpio11:
name "gpio11"
linux,phandle ff9105f8
AAPL,address 80000075
built-in
audio-gpio-active-state 00000000
audio-gpio "audio-hw-reset"
compatible "keywest-11"
device_type "gpio11"
/proc/device-tree/pci@f2000000/mac-io@17/gpio@50/gpio6:
name "gpio6"
linux,phandle ff910400
AAPL,address 80000070
built-in
audio-gpio-active-state 00000000
audio-gpio "amp-mute"
compatible "keywest-6"
device_type "gpio6"
/proc/device-tree/pci@f2000000/mac-io@17/gpio@50/gpio5:
name "gpio5"
linux,phandle ff910208
AAPL,address 8000006f
built-in
audio-gpio-active-state 00000000
audio-gpio "headphone-mute"
compatible "keywest-5"
device_type "gpio5"
/proc/device-tree/pci@f2000000/mac-io@17/gpio@50/programmer-switch:
name "programmer-switch"
linux,phandle ff910058
interrupt-parent ff90fa80
interrupts 00000037 00000000
built-in
device_type "programmer-switch"
/proc/device-tree/pci@f2000000/mac-io@17/gpio@50/extint-gpio1:
name "extint-gpio1"
linux,phandle ff90fe38
AAPL,interrupt-priorities 00000001
interrupt-parent ff90fa80
interrupts 0000002f 00000001
built-in
compatible "keywest-gpio1"
device_type "extint-gpio1"
/proc/device-tree/pci@f2000000/mac-io@17/interrupt-controller@40000:
linux,device cfec3c08
name "interrupt-controller"
linux,phandle ff90fa80
clock-frequency 003f940a (4166666)
interrupt-controller
#address-cells 00000000
#interrupt-cells 00000002
reg 00040000 00040000
built-in
compatible "chrp,open-pic"
device_type "open-pic"
/proc/device-tree/pci@f0000000:
name "pci"
linux,phandle ff9085f0
interrupt-map-mask 0000f800 00000000 00000000 00000000
interrupt-map 00008000 00000000 00000000 00000000
ff90fa80 00000030 00000001
interrupt-parent ff90fa80
interrupts 0000002d 00000001
bus-range 00000000 00000000
ranges 02000000 00000000 f1000000 f1000000 00000000 01000000
01000000 00000000 00000000 f0000000 00000000 00800000
02000000 00000000 90000000 90000000 00000000 10000000
write-combining
slot-names 00 03 00 00 53 4c 4f 54 2d 31 00 53 4c 4f 54 2d....SLOT-1.SLOT-
31 41 00 1A.
built-in-names 00 00 08 00 55 4e 49 2d 4e 00 ....UNI-N.
clock-frequency 03f940aa (66666666)
#interrupt-cells 00000001
#size-cells 00000002
#address-cells 00000003
reg f0000000 02000000
compatible "uni-north"
model "AAPL,UniNorth"
device_type "pci"
/proc/device-tree/pci@f0000000/ATY,Rage128Pd@10:
name "ATY,Rage128Pd"
linux,phandle ff94e4f0
linux,opened
linux,boot-display
iso6429-1983-colors
AAPL,gray-page 00000001
address 96008000
ATYN 002a0717 00820b4c 00000000 00000000
00000000 00000000 00000000 00000000
AGP_Master
assigned-addresses c2008010 00000000 94000000 00000000 04000000
82008030 00000000 90020000 00000000 00020000
82008018 00000000 90000000 00000000 00004000
driver,AAPL,MacOS,PowerPC 4a6f7921 70656666 70777063 00000001
b6246498 00000000 00000000 00000000
00030002 00000000 ffffffff 00000000
00013b1c 00013b1c 00013b1c 00000710
00040400 ffffffff 00000000 00004c4c
000043a4 00003349 00014230 02010400
ffffffff 00000000 00000000 00000000
0000068c 00000080 04040400 00000000
ffffffff 00000000 ffffffff 00000000
ffffffff 00000000 00000005 0000002e
00000001 00000174 000001f0 00000628
00000002 00000006 00000000 00000000
00000000 00000015 00000000 00000000
00000012 00000000 00000000 00000001
00000015 00000000 0000001f 00000000
00000000 0000000e 00000016 00000000
0000002f 00000000 00000000 00000005
00000024 00000000 00000036 00000000
00000001 00000005 00000029 40000000
02000047 0200005a 0200006d 02000076
0200008b 0200009c 020000aa 020000c4
020000dc 020000e4 020000f8 020000ff
02000107 0200011a 02000130 02000146
0200014e 0200015d 02000173 0200017d
02000193 020001a6 020001b8 020001cf
020001e7 020001fe 02000215 0200022d
02000241 02000255 02000269 0200027d
02000295 020002b4 020002cb 020002e9
02000301 02000316 02000326 02000336
0200034c 82000361 82000378 82000393
820003ae 820003c4 00010000 0000003d
00000000 4a2d42bd 03c480c7 465380ff
400aa000 1bac4200 855f420d 16d5807b
4020868b 42030783 00c20102 01020103
00c20102 01020102 01020102 01020102
01020102 01020102 01020102 01020102
01020102 01020102 01020102 01020102
01020102 01020102 01020102 01020102
0102866f 420489db 42bd0343 11950000
44726976 65725365 72766963 65734c69
6200496e 74657266 6163654c 6962004e
616d6552 65676973 7472794c 69620050
43494c69 62005669 64656f53 65727669
6365734c 69620047 65745061 6765496e
666f726d 6174696f 6e004475 72617469
6f6e546f 4162736f 6c757465 00435374
72436f70 7900506f 6f6c416c 6c6f6361
74655265 73696465 6e740044 656c6179
466f7248 61726477 61726500 53796e63
68726f6e 697a6549 4f00496e 7374616c
6c496e74 65727275 70744675 6e637469
6f6e7300 4162736f 6c757465 44656c74
61546f44 75726174 696f6e00 43537472
43617400 494f436f 6d6d616e 64497343
6f6d706c 65746500 55705469 6d650043
5374724c 656e0044 656c6574 65496e74
65727275 70745365 74004164 64447572
6174696f 6e546f41 62736f6c 75746500
53657450 726f6365 73736f72 43616368
654d6f64 65004353 7472436d 7000506f
6f6c4465 616c6c6f 63617465 00447572
6174696f 6e546f4e 616e6f73 65636f6e
64730042 6c6f636b 436f7079 00476574
496e7465 72727570 7446756e 6374696f
6e730043 72656174 65496e74 65727275
70745365 74004361 6c6c556e 69766572
73616c50 726f6300 52656769 73747279
50726f70 65727479 43726561 74650052
65676973 74727943 53747245 6e747279
43726561 74650052 65676973 74727950
726f7065 72747953 65744d6f 64005265
67697374 72795072 6f706572 74794765
744d6f64 00526567 69737472 79435374
72456e74 72794c6f 6f6b7570 00526567
69737472 79456e74 72794465 6c657465
00526567 69737472 79456e74 72794944
496e6974 00526567 69737472 7950726f
70657274 79536574 00526567 69737472
7950726f 70657274 79476574 00526567
69737472 7950726f 70657274 79497465
72617465 00526567 69737472 7950726f
70657274 79497465 72617465 44697370
6f736500 52656769 73747279 50726f70
65727479 44656c65 74650052 65676973
74727950 726f7065 72747949 74657261
74654372 65617465 00526567 69737472
7950726f 70657274 79476574 53697a65
00457870 4d677243 6f6e6669 67526561
64427974 6500456e 6469616e 53776170
33324269 7400456e 6469616e 53776170
31364269 74004578 704d6772 436f6e66
69675772 6974654c 6f6e6700 4578704d
6772436f 6e666967 52656164 4c6f6e67
0056534c 4e657749 6e746572 72757074
53657276 69636500 56534c44 6973706f
7365496e 74657272 75707453 65727669
63650056 534c5365 74446973 706c6179
436f6e66 69677572 6174696f 6e005653
4c446f49 6e746572 72757074 53657276
69636500 56534c50 72657061 72654375
72736f72 466f7248 61726477 61726543
7572736f 72006465 62756753 65746465
62756747 65745468 65447269 76657244
65736372 69707469 6f6e446f 44726976
6572494f 54686544 72697665 72506f77
65724361 70616269 6c697469 65736465
62756749 4f000000 000c0000 00000003
00080003 00040005 0008229a 000822ca
0014bde0 000ad1fd 001accfd 00071169
010003e6 00004c44 00010100 03ee0000
4c400001 010003f6 00000764 00010200
040a0000 04c40001 01000414 000007e4
00010100 042e0000 4c3c0001 00000000
7c0802a6 bf61ffec 90010008 9421ffb0
7c7b1b78 7c9c2378 7cbd2b78 7cde3378
387b0038 7f84e378 7fa5eb78 7fc6f378
48012989 80410014 7c7f0734 7fe00734
2c000000 4182001c 387b0038 7f84e378
7fa5eb78 7fc6f378 48012979 80410014
7fe3fb78 80010058 38210050 7c0803a6
bb61ffec 4e800020 7c0802a6 93e1fffc
90010008 9421ffb0 90610068 9081006c
90a10070 90c10074 80010074 90010038
80610068 38630038 8081006c 80a10070
38c10038 480128bd 80410014 7c7f0734
7fe3fb78 80010058 38210050 7c0803a6
83e1fffc 4e800020 7c0802a6 bf61ffec
90010008 9421ffb0 7c7b1b78 7c9c2378
7cbd2b78 7cde3378 7f63db78 7f84e378
7fa5eb78 7fc6f378 480128b1 80410014
7c7f0734 7fe00734 2c000000 4182001c
7f63db78 7f84e378 7fa5eb78 7fc6f378
480128a1 80410014 7fe3fb78 80010058
38210050 7c0803a6 bb61ffec 4e800020
7c0802a6 93e1fffc 90010008 9421ffb0
90610068 9081006c 90a10070 90c10074
80010074 90010038 80610068 8081006c
80a10070 38c10038 480127e9 80410014
7c7f0734 7fe3fb78 80010058 38210050
7c0803a6 83e1fffc 4e800020 7c0802a6
bf41ffe8 90010008 9421feb0 7c7a1b78
7c9b2378 98a10173 90c10174 38000000
901b0000 3ba00000 380000c8 90010038
7f43d378 388207f4 38a10064 38c10038
48012781 80410014 7c7f1b78 80610038
38000014 7c030396 2800000a 4081000c
3860ffed 480000fc 2c1f0000 408200ec
80010038 28000000 418200e0 80610038
38000014 7f830396 38000028 90010038
7f43d378 38820807 38a1003c 38c10038
48012721 80410014 7c7f1b78 2c1f0000
408200a0 80010038 28000000 41820094
3bc00000 48000060 88010173 5405063e
57c0043e 1c800014 38610064 38040003
7c0300ae 7c050040 40820038 57c0043e
1c800014 38610064 38040010 7c03002e
80610174 90030000 57c0043e 5400103a
3861003c 7c03002e 901b0000 3ba00001
3bde0001 57c0043e 7c00e040 40800010
57a0063e 28000000 4182ff90 57a0063e
28000000 40820018 3be0ffed 48000010
3be0ffed 48000008 3be0ffed 7fe3fb78
80010158 38210150 7c0803a6 bb41ffe8
4e800020 7c0802a6 bfc1fff8 90010008
9421ffb0 7c7e1b78 3be0ffed 7fc3f378
3881003c 38a00010 38c10038 4bfffe61
7c7f0734 7fe00734 2c000000 4182001c
7fc3f378 38800010 38a1003c 4801261d
80410014 7c7f1b78 8061003c 80010058
38210050 7c0803a6 bbc1fff8 4e800020
7c0802a6 bfc1fff8 90010008 9421ffb0
7c7e1b78 3be0ffed 7fc3f378 3881003c
38a00018 38c10038 4bfffdf5 7c7f0734
7fe00734 2c000000 41820028 7fc3f378
38800018 38a1003c 480125b1 80410014
7c7f1b78 8001003c 54000022 9001003c
8061003c 80010058 38210050 7c0803a6
bbc1fff8 4e800020 7c0802a6 93e1fffc
90010008 9421ffc0 7c7f1b78 807f00e0
38030001 901f00e0 801f00d4 28000000
41820010 807f00d4 48012701 80410014
80010048 38210040 7c0803a6 83e1fffc
4e800020 7c0802a6 90010008 9421ffc0
386243a4 80630000 4bffffa1 38600000
80010048 38210040 7c0803a6 4e800020
7c0802a6 bfc1fff8 90010008 9421ffb0
7c7f1b78 38000004 90010038 387f0038
38820814 38bf00dc 38c10038 480124c5
80410014 7c7e0734 38000018 90010038
387f0038 3882081f 38bf00ac 38c10038
480124a1 80410014 7c7e0734 7fc3f378
80010058 38210050 7c0803a6 bbc1fff8
4e800020 7c0802a6 bfa1fff4 90010008
9421ffb0 7c7f1b78 7c9d2378 3c600072
386370e0 907f00e8 3c600072 386370e0
907f00ec 38000010 9001003c 7fa3eb78
3882082a 38bf00e8 38c1003c 48012435
80410014 7c7e0734 38000004 9001003c
7fa3eb78 3882083c 38a10038 38c1003c
48012411 80410014 7c7e0734 7fc00734
2c000000 40820068 80010038 540007fe
28000000 4182001c 80010038 54000738
28000000 4182000c 38000001 981f0154
80010038 54000420 28000000 4182000c
38000001 981f0160 80010038 540005ee
28000000 4182000c 38000001 981f05c9
80010038 540006f6 981f0153 7fc3f378
80010058 38210050 7c0803a6 bba1fff4
4e800020 7c0802a6 90010008 9421ffc0
90610058 388243a4 80640000 80630000
38030001 80640000 90030000 386243a4
80630000 80030000 2c000001 40820020
38000001 386243a8 98030000 80610058
48000845 60000000 48000008 38600000
80010048 38210040 7c0803a6 4e800020
7c0802a6 90010008 9421ffc0 90610058
388243a4 80640000 80630000 3803ffff
80640000 90030000 386243a4 80630000
80030000 2c000000 40820014 80610058
480010e9 60000000 48000008 38600000
80010048 38210040 7c0803a6 4e800020
38600000 4e800020 7c0802a6 bfa1fff4
90010008 9421ff90 b061008a 9081008c
90a10090 90c10094 90e10098 9901009f
3be243a4 3bc00000 38600688 38800001
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3880009c 4bff6bb9 60000000 7fe3fb78
388000a0 4bff6be5 60000000 5465028e
7fe3fb78 388000a0 4bff6b95 60000000
7fe3fb78 388000a8 4bff6bc1 60000000
5460028e 7fc50378 7fe3fb78 388000a8
4bff6b6d 60000000 80010058 38210050
7c0803a6 bba1fff4 4e800020 7c0802a6
bfc1fff8 90010008 9421ffc0 90610058
3be00000 80610058 388000a4 4bff6b6d
60000000 7c7e1b78 57c00252 28000000
4182000c 38000004 48000008 38000000
7fff0378 57c00210 28000000 4182000c
38000002 48000008 38000000 7fff0378
7fe3fb78 80010048 38210040 7c0803a6
bbc1fff8 4e800020 7c0802a6 90010008
9421ffc0 90610058 b081005e b0a10062
80600544 3c800073 38843002 3ca00001
38a5a051 80c10058 a001005e 5407801e
a0010062 7ce70214 48003cf9 80410014
80010048 38210040 7c0803a6 4e800020
7c0802a6 93e1fffc 90010008 9421ffb0
7c7f1b78 38610038 38800004 38a000fc
4bffff89 281f0000 4182000c 80010038
901f0000 80610038 3c03adb2 2800494e
4082000c 38600001 48000008 38600000
80010058 38210050 7c0803a6 83e1fffc
4e800020 7c0802a6 bfa1fff4 90010008
9421ffa0 7c7d1b78 7c9f2378 3bc0ffef
801d0000 2c000080 41820268 4080002c
2c000002 41820104 40800014 2c000000
4182003c 408000b8 48000408 2c000004
40800400 48000120 2c000083 418202bc
40800010 2c000082 40800278 4800024c
2c000085 408003dc 48000334 7fe3fb78
38800000 48000469 60000000 7fe3fb78
38800059 4bff67fd 60000000 60650080
7fe3fb78 38800059 4bff67a5 60000000
7fe3fb78 3880002a 4bffdc85 60000000
98620490 7fe3fb78 3880002a 88020490
7c000e70 7c000194 5405063e 4bffdb49
60000000 7fe3fb78 3880000f 4bff61c5
60000000 3bc00000 4800035c 7fe3fb78
38800000 480003e9 60000000 7fe3fb78
38800059 4bff677d 60000000 60650080
7fe3fb78 38800059 4bff6725 60000000
3bc00000 48000320 7fe3fb78 38800000
480003ad 60000000 7fe3fb78 38800059
4bff6741 60000000 60650080 7fe3fb78
38800059 4bff66e9 60000000 3bc00000
480002e4 88020491 28000000 41820020
7fe3fb78 38800029 88a20491 4bffda99
60000000 38000000 98020491 88020492
28000000 4182002c 7fe3fb78 38800143
88a20492 4bff6699 60000000 7fe3fb78
4bffd8d1 60000000 38000000 98020492
88020490 28000000 41820020 7fe3fb78
3880002a 88a20490 4bffda3d 60000000
38000000 98020490 7fe3fb78 38800008
4bffdb3d 60000000 546507fa 7fe3fb78
38800008 4bffda11 60000000 7fe3fb78
38800059 4bff666d 60000000 5465066e
7fe3fb78 38800059 4bff6615 60000000
801f0100 90010048 881f0681 28000000
41820014 7fe3fb78 38800001 48000291
60000000 38000007 9801003d 38000000
9801003c 3861003c 7fe4fb78 4bff7fc9
60000000 7c7e1b78 3bc00000 480001c8
38000000 901d0000 38000000 98010040
38610040 7fe4fb78 48002f85 60000000
7c7e1b78 480001a0 38000003 901d0000
38000001 98010040 38610040 7fe4fb78
48002f5d 60000000 7c7e1b78 48000178
38000001 981f05c9 38000003 901d0000
38000001 98010040 38610040 7fe4fb78
48002f2d 60000000 7c7e1b78 38000000
981f05c9 48000140 38000003 901d0000
38000001 98010040 38610040 7fe4fb78
48002efd 60000000 7c7e1b78 7fc00734
2c000000 40820110 38000007 9801003b
38000007 9801003a 3861003a 7fe4fb78
4bff7ee5 60000000 7c7e1b78 7fe3fb78
38800000 48000179 60000000 7fe3fb78
38800059 4bff650d 60000000 60650080
7fe3fb78 38800059 4bff64b5 60000000
38000002 901d0000 480000ac 38000001
981f05c9 38000003 901d0000 38000001
98010040 38610040 7fe4fb78 48002e61
60000000 7c7e1b78 38000000 981f05c9
7fc00734 2c000000 4082006c 38000007
98010039 38000007 98010038 38610038
7fe4fb78 4bff7e41 60000000 7c7e1b78
7fe3fb78 38800000 480000d5 60000000
7fe3fb78 38800059 4bff6469 60000000
60650080 7fe3fb78 38800059 4bff6411
60000000 38000002 901d0000 48000008
3bc00000 801d0000 901f00f8 801f00fc
901d0004 7fc3f378 80010068 38210060
7c0803a6 bba1fff4 4e800020 7c0802a6
93e1fffc 90010008 9421ffc0 7c7f1b78
387f0644 38823394 38bf0659 38c00005
4bff0f91 60000000 387f0644 3882339e
38bf0654 38c00005 4bff0f79 60000000
881f0654 981f062d 881f0655 981f062e
881f0656 981f062f 80010048 38210040
7c0803a6 83e1fffc 4e800020 7c0802a6
93e1fffc 90010008 9421ffc0 7c7f1b78
9881005f 7fe3fb78 4bffff75 881f0654
5403063e 881f062c 7c030040 40820220
8801005f 2c000001 41820108 40800104
2c000000 40800008 480000f8 7fe3fb78
38800288 4bff6515 60000000 546507fa
7fe3fb78 38800288 4bff64c5 60000000
7fe3fb78 38800284 4bff64f1 60000000
5465003c 7fe3fb78 38800284 4bff64a1
60000000 7fe3fb78 38800284 4bff64cd
60000000 60650002 7fe3fb78 38800284
4bff647d 60000000 7fe3fb78 38800284
4bff64a9 60000000 546507b8 7fe3fb78
38800284 4bff6459 60000000 7fe3fb78
38800054 4bff6485 60000000 54650290
7fe3fb78 38800054 4bff6435 60000000
7fe3fb78 3880000a 4bff5cb9 60000000
7fe3fb78 38800288 4bff6451 60000000
5465003c 7fe3fb78 38800288 4bff6401
60000000 38000000 981f0659 480000f4
7fe3fb78 38800288 4bff6421 60000000
60650001 7fe3fb78 38800288 4bff63d1
60000000 7fe3fb78 3880000a 4bff5c55
60000000 7fe3fb78 38800284 4bff63ed
60000000 60650001 7fe3fb78 38800284
4bff639d 60000000 7fe3fb78 38800284
4bff63c9 60000000 546507fa 7fe3fb78
38800284 4bff6379 60000000 7fe3fb78
38800284 4bff63a5 60000000 60650004
7fe3fb78 38800284 4bff6355 60000000
7fe3fb78 38800054 4bff6381 60000000
64650040 7fe3fb78 38800054 4bff6331
60000000 7fe3fb78 38800288 4bff635d
60000000 60650002 7fe3fb78 38800288
4bff630d 60000000 881f062c 981f0659
7fe3fb78 388233a7 38a1005f 38c00001
4bff0bb1 60000000 4800000c 38000000
9801005f 387f0644 388233ae 38bf0659
38c00005 4bff0c65 60000000 7fe3fb78
4bfffd1d 8801005f 981f0603 80010048
38210040 7c0803a6 83e1fffc 4e800020
7c0802a6 93e1fffc 90010008 9421ffc0
7c7f1b78 9881005f 7fe3fb78 4bfffce1
881f0655 5403063e 881f062c 7c030040
408200e4 8801005f 2c000001 41820068
40800064 2c000000 40800008 48000058
7fe3fb78 38800054 4bff6281 60000000
60653300 7fe3fb78 38800054 4bff6231
60000000 7fe3fb78 38800058 4bff625d
60000000 60658000 7fe3fb78 38800058
4bff620d 60000000 38000000 981f065a
48000058 7fe3fb78 38800054 4bff622d
60000000 3800ccff 7c650038 7fe3fb78
38800054 4bff61d9 60000000 7fe3fb78
38800058 4bff6205 60000000 5465045e
7fe3fb78 38800058 4bff61b5 60000000
881f062c 981f065a 7fe3fb78 388233b8
38a1005f 38c00001 4bff0a59 60000000
4800000c 38000000 9801005f 387f0644
388233c0 38bf0659 38c00005 4bff0b0d
60000000 7fe3fb78 4bfffbc5 8801005f
981f0604 80010048 38210040 7c0803a6
83e1fffc 4e800020 7c0802a6 bfa1fff4
90010008 9421ffb0 7c7f1b78 7c9d2378
3bc00000 57a0063e 2c000002 41820178
40800014 2c000000 41820014 408000bc
48000210 2c000004 48000208 7fe3fb78
38800288 4bff6135 60000000 546007bc
28000000 41820038 7fe3fb78 38800288
4bff6119 60000000 546507fa 7fe3fb78
38800288 4bff60c9 60000000 7fe3fb78
38800032 4bff594d 60000000 7fe3fb78
38800f60 4bff5f1d 60000000 5460003a
60050003 7fe3fb78 38800f60 4bff5ec1
60000000 7fe3fb78 38800032 4bff5915
60000000 7fe3fb78 38800f60 4bff60ad
60000000 546007be 28000003 418201b8
3bc0ffef 480001b0 7fe3fb78 38800288
4bff6089 60000000 546007bc 28000000
41820038 7fe3fb78 38800288 4bff606d
60000000 546507fa 7fe3fb78 38800288
4bff601d 60000000 7fe3fb78 38800032
4bff58a1 60000000 7fe3fb78 38800f60
4bff5e71 60000000 5460003a 60050001
7fe3fb78 38800f60 4bff5e15 60000000
7fe3fb78 38800032 4bff5869 60000000
7fe3fb78 38800f60 4bff6001 60000000
546007be 28000001 4182010c 3bc0ffef
48000104 7fe3fb78 38800288 4bff5fdd
60000000 546007bc 28000000 41820038
7fe3fb78 38800288 4bff5fc1 60000000
546507fa 7fe3fb78 38800288 4bff5f71
60000000 7fe3fb78 38800032 4bff57f5
60000000 7fe3fb78 38800f60 4bff5dc5
60000000 5460003a 60050002 7fe3fb78
38800f60 4bff5d69 60000000 7fe3fb78
38800032 4bff57bd 60000000 7fe3fb78
38800f60 4bff5f55 60000000 546007be
28000002 41820060 3bc0ffef 48000058
7fe3fb78 38800f60 4bff5d69 60000000
5465003a 7fe3fb78 38800f60 4bff5d11
60000000 7fe3fb78 38800032 4bff5765
60000000 7fe3fb78 38800f60 4bff5efd
60000000 546007be 28000000 41820008
3bc0ffef 57a0063e 901f00f8 7fc3f378
80010058 38210050 7c0803a6 bba1fff4
4e800020 7c0802a6 93e1fffc 90010008
9421ffc0 7c7f1b78 9081005c 7fe3fb78
38800284 4bff5ea5 60000000 5463077e
8001005c 7c051b78 7fe3fb78 38800284
[95609 bytes total]
ATY,Fcode "1.75"
ATY,Card# "109-72700-00"
ATY,Rom# "113-72701-130"
model "ATY,Rage128Pro"
AGP_AllowOverlap 00000001
AGP_Alignment 02000000 (33554432)
AGP_Address_Block 02000000 (33554432)
AGP_Address_Range 00000000 ffffffff
reg 00008000 00000000 00000000 00000000 00000000
02008030 00000000 00000000 00000000 00020000
42008010 00000000 00000000 00000000 04000000
02008018 00000000 00000000 00000000 00004000
character-set "ISO8859-1"
device_type "display"
display-type "CRT"
linebytes 00000300 (768)
depth 00000008
height 000001e0 (480)
width 00000280 (640)
ATY,SCLK 0001ccf0 (118000)
ATY,MCLK 000222e0 (140000)
ATY,RefCLK 0000733c (29500)
ATY,Flags 07170190 (118948240)
ATY,Status 00000000
fcode-rom-offset 00000000
fast-back-to-back
devsel-speed 00000001
max-latency 00000000
min-grant 00000008
interrupts 00000001
class-code 00030000 (196608)
revision-id 00000000
device-id 00005046 (20550)
vendor-id 00001002 (4098)
/proc/device-tree/pci@f0000000/uni-north-agp@b:
name "uni-north-agp"
linux,phandle ff94e1e0
assigned-addresses
reg 00005800 00000000 00000000 00000000 00000000
AGP_Target
compatible "uni-north-agp"
device_type "uni-north-agp"
fast-back-to-back
devsel-speed 00000001
max-latency 00000000
min-grant 00000000
class-code 00060000 (393216)
revision-id 00000000
device-id 0000002d (45)
vendor-id 0000106b (4203)
/proc/device-tree/uni-n@f8000000:
name "uni-n"
linux,phandle ff907330
device-rev 00000011 (17)
#size-cells 00000001
#address-cells 00000001
reg f8000000 01000000
compatible "uni-north"
device_type "memory-controller"
model "AAPL,UniNorth"
/proc/device-tree/uni-n@f8000000/i2c@f8001000:
name "i2c"
linux,phandle ff9075f8
interrupt-parent ff90fa80
interrupts 0000002a 00000001
AAPL,driver-name ".i2c-uni-n"
AAPL,i2c-rate 00000064 (100)
AAPL,address-step 00000010 (16)
AAPL,address f8001003
built-in
compatible "keywest-i2c"
reg f8001000 00001000
device_type "i2c"
/proc/device-tree/uni-n@f8000000/i2c@f8001000/cereal:
name "cereal"
linux,phandle ff907ec0
device_type "serial"
/proc/device-tree/nvram@fff04000:
name "nvram"
linux,phandle ff906730
#bytes 00002000 (8192)
reg fff04000 00004000
compatible "nvram,flash"
device_type "nvram"
/proc/device-tree/diagnostics:
name "diagnostics"
linux,phandle ff906650
post-results 00000000
post
/proc/device-tree/multiboot:
name "multiboot"
linux,phandle ff8f3660
/proc/device-tree/pseudo-sound:
name "pseudo-sound"
linux,phandle ff8f3330
/proc/device-tree/pseudo-hid:
name "pseudo-hid"
linux,phandle ff8f20d0
/proc/device-tree/pseudo-hid/eject-key:
name "eject-key"
linux,phandle ff8f2e60
device_type "eject-key"
/proc/device-tree/pseudo-hid/mouse:
name "mouse"
linux,phandle ff8f28c8
device_type "mouse"
/proc/device-tree/pseudo-hid/keyboard:
name "keyboard"
linux,phandle ff8f21d0
device_type "keyboard"
/proc/device-tree/firewire-disk-mode:
name "firewire-disk-mode"
linux,phandle ff8dd818
/proc/device-tree/packages:
name "packages"
linux,phandle ff8413c0
/proc/device-tree/packages/terminal-emulator:
name "terminal-emulator"
linux,phandle ff8dd708
iso6429-1983-colors
/proc/device-tree/packages/bootpath-search:
name "bootpath-search"
linux,phandle ff8d6d78
/proc/device-tree/packages/atapi-disk:
name "atapi-disk"
linux,phandle ff8d4e30
/proc/device-tree/packages/ata-disk:
name "ata-disk"
linux,phandle ff8d30c8
/proc/device-tree/packages/sbp2-disk:
name "sbp2-disk"
linux,phandle ff8d0728
/proc/device-tree/packages/usb-audio-class:
name "usb-audio-class"
linux,phandle ff862bb0
/proc/device-tree/packages/usb-ms-class:
name "usb-ms-class"
linux,phandle ff85ff60
/proc/device-tree/packages/usb-hid-class:
name "usb-hid-class"
linux,phandle ff85d420
/proc/device-tree/packages/elf-loader:
name "elf-loader"
linux,phandle ff85bd78
/proc/device-tree/packages/pe-loader:
name "pe-loader"
linux,phandle ff85b328
/proc/device-tree/packages/xcoff-loader:
name "xcoff-loader"
linux,phandle ff85a890
/proc/device-tree/packages/bootinfo-loader:
name "bootinfo-loader"
linux,phandle ff858bb8
/proc/device-tree/packages/iso-9660-files:
name "iso-9660-files"
linux,phandle ff857d58
/proc/device-tree/packages/fat-files:
name "fat-files"
linux,phandle ff855f60
/proc/device-tree/packages/hfs-plus-files:
name "hfs-plus-files"
linux,phandle ff851140
/proc/device-tree/packages/mac-files:
name "mac-files"
linux,phandle ff84e288
/proc/device-tree/packages/mac-parts:
name "mac-parts"
linux,phandle ff84cae0
/proc/device-tree/packages/telnet:
name "telnet"
linux,phandle ff84c1e0
/proc/device-tree/packages/obp-tftp:
name "obp-tftp"
linux,phandle ff842900
log 00007a4f 00000000 00000000 0000000d
ffbbc1c0 31302e31 302e312e 3135362c
64000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00007a4f ffbbbc00 00000400 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00007a4f 00000000 00000001 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00007a50 00000000 00000052 00000022
ffbbbc00 003065f3 4cae0090 27ee9023
08004510 01480000 00001011 16bf0a0a
7d100a0a 01b30000 00000000 00000000
00007a50 00000000 00000053 00000134
ffbbbc2a 02010600 00007a50 00000000
00000000 0a0a01b3 0a0a7d10 00000000
003065f3 4cae0000 00000000 00000000
00007a50 00000000 00000054 0000003c
ffbbbd1a 35010236 040a0a7d 10330400
278d0001 04ffff00 0003040a 0a00083c
09414150 4c425344 5043ff00 00000000
00007a50 00000000 00000002 00000134
ffbbbc2a 02010600 00007a50 00000000
00000000 0a0a01b3 0a0a7d10 00000000
003065f3 4cae0000 00000000 00000000
00007a50 00000000 00000005 00000000
ffbbc180 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00007a50 00000000 00000003 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00007a50 ffbbc170 0000000a 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00007a50 ffbbba00 0000012c 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00007a50 ffbbb400 00000400 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00007a52 00000000 00030352 00000022
ffbbb400 003065f3 4cae0090 27ee9023
08004510 01480000 00001011 16bf0a0a
7d100a0a 01b30000 00000000 00000000
00007a52 00000000 00030353 00000134
ffbbb42a 02010600 00007a50 00000000
00000000 0a0a01b3 0a0a7d10 00000000
003065f3 4cae0000 00000000 00000000
00007a52 00000000 00030354 0000003c
ffbbb51a 35010536 040a0a7d 10330400
278d0001 04ffff00 0003040a 0a00083c
09414150 4c425344 5043ff00 00000000
00007a52 00000000 00030302 00000134
ffbbb42a 02010600 00007a50 00000000
00000000 0a0a01b3 0a0a7d10 00000000
003065f3 4cae0000 00000000 00000000
00007a52 00000000 00030305 00000000
ffbbc180 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00007a52 00000000 00030350 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00007a52 ffbbb000 00000400 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00007c47 ffbbb800 0000012c 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00007c47 00000000 00050350 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00007e3c ffbbc160 00000001 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00007e59 00000000 00050359 00000001
ffbbc160 64000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
000082cb 00000001 ffbbc160 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
stats 00000ff3 00000001 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000
/proc/device-tree/packages/disk-label:
name "disk-label"
linux,phandle ff841e38
/proc/device-tree/packages/deblocker:
name "deblocker"
linux,phandle ff8414a0
/proc/device-tree/aliases:
name "aliases"
linux,phandle ff8408d8
screen "/pci@f0000000/ATY,Rage128Pd@10"
last-boot "/pci@f4000000/ethernet@f"
"/pci@f2000000/pci@d/ethernet@b"
"/pci@f2000000/ethernet@13"
eject-key "/pseudo-hid/eject-key"
sound "/pseudo-sound"
nvram "/nvram"
mouse "/pseudo-hid/mouse"
keyboard "/pseudo-hid/keyboard"
fw "/pci@f4000000/firewire"
enet "/pci@f4000000/ethernet"
ui2c-serial "/uni-n/i2c/cereal"
ui2c "/uni-n/i2c"
wireless "/pci@f2000000/mac-io@17/@30000"
adb-eject-key "/pci@f2000000/mac-io@17/via-pmu/adb/eject-key"
adb-mouse "/pci@f2000000/mac-io@17/via-pmu/adb/mouse"
adb-keyboard "/pci@f2000000/mac-io@17/via-pmu/adb/keyboard"
adb "/pci@f2000000/mac-io@17/via-pmu/adb"
rtc "/pci@f2000000/mac-io@17/via-pmu/rtc"
via-pmu "/pci@f2000000/mac-io@17/via-pmu"
ki2c-serial "/pci@f2000000/mac-io@17/i2c/cereal"
ki2c "/pci@f2000000/mac-io@17/i2c"
sccb "/pci@f2000000/mac-io@17/escc/ch-b"
scca "/pci@f2000000/mac-io@17/escc/ch-a"
ultra1 "/pci@f2000000/mac-io@17/ata-4@1f000/disk@1"
ultra0 "/pci@f2000000/mac-io@17/ata-4@1f000/disk@0"
zip "/pci@f2000000/mac-io@17/ata-3@20000/disk@1"
cd "/pci@f2000000/mac-io@17/ata-3@20000/disk@0"
hd "/pci@f2000000/mac-io@17/ata-4@1f000/disk@0"
ide1 "/pci@f2000000/mac-io@17/ata-3@20000/disk@1"
ide0 "/pci@f2000000/mac-io@17/ata-3@20000/disk@0"
mpic "/pci@f2000000/mac-io@17/interrupt-controller"
mac-io "/pci@f2000000/mac-io@17"
usb1 "/pci@f2000000/usb@19"
usb0 "/pci@f2000000/usb@18"
cbx "/pci@f2000000/cardbus@1a/pci-bridge/pci-bridge"
cb "/pci@f2000000/cardbus@1a"
fw1 "/pci@f2000000/firewire"
enet1 "/pci@f2000000/ethernet"
enetx "/pci@f2000000/ethernet@13"
fwx "/pci@f2000000/firewire@12"
pci "/pci@f2000000"
pci2 "/pci@f4000000"
pci1 "/pci@f2000000"
agp "/pci@f0000000"
pci0 "/pci@f0000000"
/proc/device-tree/options:
name "options"
linux,phandle ff8407d0
boot-args
snakebitecpu0 70 61 73 73 65 64 passed
snakebitecpu1 66 61 69 6c 65 64 failed
medusa 74727565 (1953658213)
ASVP 30313037 31373030 323a343c
aapl,pci 2f 6f 66 66 73 63 72 65 65 6e 2d 64 69 73 70 6c/offscreen-displ
61 79 ff 01 67 70 72 66 ff 01 ff 81 01 07 01 01ay..gprf........
ff 81 04 ff 01 2f 40 66 30 30 30 30 30 30 30 2f...../@f0000000/
40 31 30 ff 01 41 54 59 4e ff 01 ff 81 01 2a 07@10..ATYN.....*.
17 ff 81 01 82 0b 4c ff 81 18 ff 01 00 ......L......
boot-script ""
default-router-ip ""
default-subnet-mask ""
default-gateway-ip ""
default-server-ip ""
default-client-ip ""
boot-command "mac-boot"
nvramrc ""
oem-logo ""
oem-banner ""
mouse-device "mouse"
output-device-1 "scca"
input-device-1 "scca"
output-device "screen"
input-device "keyboard"
diag-file ",diags"
diag-device "enet"
console-screen ""
boot-screen ""
boot-file ""
boot-device "/pci@f2000000/mac-io@17/ata-4@1f000/disk@0:11,\\:tbxi"
selftest-#megs "0"
screen-#rows "40"
screen-#columns "100"
pci-probe-mask "-1"
virt-size "-1"
virt-base "-1"
load-base "0x800000"
real-size "-1"
real-base "-1"
default-mac-address? "false"
use-generic? "false"
use-nvramrc? "false"
oem-logo? "false"
oem-banner? "false"
fcode-debug? "false"
diag-switch? "false"
auto-boot? "true"
real-mode? "false"
little-endian? "false"
/proc/device-tree/rom@ff800000:
name "rom"
linux,phandle ff840298
#address-cells 00000001
ranges ff800000 00800000 ff800000
reg ff800000 00000000
/proc/device-tree/rom@ff800000/macos:
name "macos"
linux,phandle ff8406c8
/proc/device-tree/rom@ff800000/boot-rom@fff00000:
name "boot-rom"
linux,phandle ff840498
has-config-block
info fff00000 00003f00 000418f5 20010321 b9456725 fff08000
00078001 000418f5 20010321 624ad24b fff80000 00080002
000418f5 20010321 a564aa82 fff03f00 00000083 000418f5
20010321 29ed3241 fff03f80 00000084 f34cae84 15a81001
ffffffff fff04000 00004005 6e767261 6d000000 00000000
security-modes 6e 6f 6e 65 2c 20 66 75 6c 6c 2c 20 63 6f 6d 6dnone,.full,.comm
61 6e 64 and
BootROM-build-date "03/21/01 at 11:49:53"
BootROM-version "$0004.18f5"
model "Apple PowerMac3,4 4.1.8f5 BootROM built on 03/21/01 at 11:49:53"
write-characteristic "flash"
reg fff00000 00100000
/proc/device-tree/openprom:
name "openprom"
linux,phandle ff83ee00
boot-syntax 00000001
supports-bootinfo
relative-addressing
model "OpenFirmware 3"
device_type "BootROM"
/proc/device-tree/openprom/client-services:
name "client-services"
linux,phandle ff83efa8
/proc/device-tree/memory@0:
name "memory"
linux,phandle ff83eb60
dimm-speeds "PC100-222S"
"PC100-222S"
""
""
dimm-types "SDRAM"
"SDRAM"
""
""
dimm-info 8008040c 09024000 01755400 80080001
8f040601 01000ea0 60000014 0f142d10
15081508 00000000 00000000 00000000
00000000 00000000 00000000 0000129f
adffffff ffffffff 02373656 31363633
35484754 382d4820 20202041 410b6560
87612e00 00000000 00000000 00000000
00000000 00000000 00000000 000064ff
8008040c 0a014000 01755400 80080001
0f040601 010006a0 60000014 0f142d20
15081508 ffffffff ffffffff ffffffff
ffffffff ffffffff ffffffff ffff120d
7f7f6400 00000000 354d4454 3132384d
20504331 33332d33 33332032 310108c2
0a200457 57572e4d 44542e44 45204330
30313930 324c3141 2050324d 303464a7
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
available 00003000 001fd000 0022c000 000d4000 00400000
01c00000 029647a0 00004860 02a69000 0d197000
slot-names 0000000f 44494d4d 302f4a32 31004449
4d4d312f 4a323200 44494d4d 322f4a32
33004449 4d4d332f 4a323400
reg 00000000 08000000 08000000 08000000
00000000 00000000 00000000 00000000
device_type "memory"
/proc/device-tree/chosen:
name "chosen"
linux,phandle ff83e948
linux,stdout-path "/pci@f0000000/ATY,Rage128Pd@10"
linux,stdout-package ff94e4f0
yaboot,image "enet:10.10.1.156,d"
dhcp-response 02010600 00007a50 00000000 00000000 0a0a01b3
0a0a7d10 00000000 003065f3 4cae0000 00000000
00000000 626f6574 74676572 2e737573 652e6465
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000
00000000 00000000 6f732d63 686f6f73 65720000
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 63825363
35010536 040a0a7d 10330400 278d0001 04ffff00
0003040a 0a00083c 09414150 4c425344 5043ff00
00000000 00000000 00000000 00000000 00000000
bsdp-response 02010600 00007a50 00000000 00000000 0a0a01b3
0a0a7d10 00000000 003065f3 4cae0000 00000000
00000000 626f6574 74676572 2e737573 652e6465
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000
00000000 00000000 6f732d63 686f6f73 65720000
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 63825363
35010236 040a0a7d 10330400 278d0001 04ffff00
0003040a 0a00083c 09414150 4c425344 5043ff00
00000000 00000000 00000000 00000000 00000000
mac-address 00 30 65 f3 4c ae .0e.L.
yaboot,bootpath "/pci@f2000000/mac-io@17/ata-4@1f000/disk@0:11,\\yaboot"
interrupt-controller ff90fa80
cpu ffbdd640
bootargs "root=/dev/hda13 quiet sysrq=1 video=aty128fb:1024x768@75 debug video=aty128fb:1024x768@85 "
bootpath "/pci@f2000000/mac-io@17/ata-4@1f000/disk@0:11,\\yaboot"
pmu ffbd8c00
nvram ffbd8d40
mmu ffbdd640
memory ffbdd5c0
stdout ffbbc400
stdin ffbc54c0
/proc/device-tree/cpus:
name "cpus"
linux,phandle ff83d620
#cpus 00000001
#size-cells 00000000
#address-cells 00000001
/proc/device-tree/cpus/PowerPC,G4@0:
name "PowerPC,G4"
linux,phandle ff83d8d0
translations 00000000 00003000 00000000 00000010
00200000 0002c000 00200000 00000002
00300000 00100000 00300000 00000010
02000000 00300000 02000000 00000010
02300000 00665000 02300000 00000010
02969000 00100000 02969000 00000010
80000000 00080000 80000000 00000028
80082000 00001000 80082000 00000028
80083000 00001000 80083000 00000028
80084000 00001000 80084000 00000028
90000000 00004000 90000000 00000028
94000000 04000000 94000000 00000028
f0000000 00010000 f0000000 00000028
f0800000 00001000 f0800000 00000028
f0c00000 00001000 f0c00000 00000028
f2000000 00010000 f2000000 00000028
f2800000 00001000 f2800000 00000028
f2c00000 00001000 f2c00000 00000028
f4000000 00010000 f4000000 00000028
f4800000 00001000 f4800000 00000028
f4c00000 00001000 f4c00000 00000028
f5000000 00001000 f5000000 00000028
f5200000 00200000 f5200000 00000028
f5200000 00200000 f5200000 00000028
f8000000 00003000 f8000000 00000028
ff800000 00400000 0fc00000 00000010
fff04000 00002000 fff04000 00000028
fff06000 00002000 fff06000 00000028
available 00003000 7fffd000 d0000000 20000000
existing 00000000 80000000 80000000 80000000
l2cr b9000000
l2-cache#1 ff83dcc8
data-streams
altivec
performance-monitor
graphics
d-cache-block-size 00000020 (32)
i-cache-block-size 00000020 (32)
i-cache-sets 00000080 (128)
d-cache-sets 00000080 (128)
i-cache-size 00008000 (32768)
d-cache-size 00008000 (32768)
tlb-size 00000080 (128)
tlb-sets 00000040 (64)
reservation-granule-size 00000020 (32)
timebase-frequency 01fbf711 (33290001)
bus-frequency 07efdc44 (133160004)
clock-frequency 1bd0c4a9 (466666665)
state "running"
cpu-version 000c0209 (786953)
reg 00000000
device_type "cpu"
/proc/device-tree/cpus/PowerPC,G4@0/l2-cache:
name "l2-cache"
linux,phandle ff83dcc8
clock-frequency 0de86254 (233333332)
cache-unified
d-cache-line-size 00000040 (64)
i-cache-line-size 00000040 (64)
d-cache-sets 00002000 (8192)
i-cache-sets 00002000 (8192)
d-cache-size 00100000 (1048576)
i-cache-size 00100000 (1048576)
device_type "cache"
^ permalink raw reply
* Re: ML403 patch for UBOOT
From: alayrac @ 2006-10-02 9:28 UTC (permalink / raw)
To: Ameet Patil; +Cc: Linuxppc-embedded
In-Reply-To: <4520CADB.4020004@gmail.com>
Hi Ameet,
Thanks for your reply
> you got the URL wrong. Its http://linux.get2knowmore.com
I've got the right address but I've made an error in the email.
Following your instrcutions I've succeed to run the 2.6.17.1 kernel on
my ML403 board. The process stop when I try to mount the NFS root file
system. This is because there is no Etehrnet drivers.
It seems that Xilinx will release SP2 for EDK 8.2 very soon and that
issue should be solved.
We decide to work on u-boot on that ML403 board (and linux 2.4.26 very
well documented on byu web site, link on your web page) . To do so I use
ML403 ppc ref design and I've dowloaded the u-boot.zip from xilinx
website.
This u-boot.zip have empty files for sw_services (tcl script...), and
I've noticed that memory map found in u-boot/board/ml403/xparameters.h
did not match the one of the design from Xilinx.
I've then modify the address in this file and I succesfully start U-boot
on that board.
Unfortunately, the process stop on the last line of do_boot_linux when
whe are supposed to get back to entry point at address 0x00000000.
(the uImage is properly unzip, and CRC OK).
I did not know why the process stop?
Do you think it has something to do with the hardware design?
Should I modify the mapping of the hardware to macth the original memory
map of the xparameters.h that comes with this u-boot.zip file?
(that is the next track I'm working on).
I did not found PartII on your web site, it is an error from me or you
did not find time to publish it?
Thanks any way for your contribution and your help.
Kinds Regards
Chris
^ permalink raw reply
* Re: ML403 patch for UBOOT
From: Ameet Patil @ 2006-10-02 8:16 UTC (permalink / raw)
To: christophe.alayrac; +Cc: Linuxppc-embedded
In-Reply-To: <1159183304.11649.17.camel@Serge-Linux>
alayrac wrote:
> I'm new member of this mailing list an I'm looking for some information
> on UBOOT on ML403.
>
> stevea-mdi talk about a pacth from Ameet
> (http://www.linux2knowmore.com) but I did not succeed to find this
> pacth.
>
you got the URL wrong. Its http://linux.get2knowmore.com
cheers,
-Ameet
> The one attached to the mail
> (http://patchwork.ozlabs.org/linuxppc/patch?id=6502) seems to be for
> linux 2.6.17-4 and not for UBOOT.
>
> Is there something I'm doing wrong?
>
> Where can I found a pacth for UBOOT for ML403?
>
> Thank you in advance for any help
>
> Chris
>
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
^ permalink raw reply
* Re: [PATCH 3/15] qe_lib: Add common files
From: Paul Mackerras @ 2006-10-02 7:37 UTC (permalink / raw)
To: Kim Phillips; +Cc: linuxppc-dev
In-Reply-To: <20060930183333.0ec7fe0f.kim.phillips@freescale.com>
Kim Phillips writes:
> qe_lib: Add common files
> diff --git a/arch/powerpc/sysdev/qe_lib/Makefile b/arch/powerpc/sysdev/qe_lib/Makefile
> new file mode 100644
> index 0000000..9a54a81
> --- /dev/null
> +++ b/arch/powerpc/sysdev/qe_lib/Makefile
> @@ -0,0 +1,8 @@
> +#
> +# Makefile for the linux ppc-specific parts of QE
> +#
> +obj-$(CONFIG_QUICC_ENGINE)+= qe_common.o qe.o qe_ic.o qe_io.o
But qe.c, qe_ic.c and qe_io.c don't exist as of this patch, so the
kernel won't build.
Also I notice that qe_common.c gets added by this patch and then
modified by subsequent patches. Why don't we just add the final
version instead?
It looks to me like most of this series needs to be committed as one
commit so that git bisect still works. Please re-send the patches
(except the rheap fix) as a series where the kernel will build and run
after each patch in the series.
Also, when you are sending on a patch that someone else created,
please make the first non-blank line of the message say "From: "
followed by the author's name and email address, so we get the
attribution right in the git repository.
Paul.
^ permalink raw reply
* Re: [PATCH 1/15] Update for ucc_geth driver
From: Paul Mackerras @ 2006-10-02 7:24 UTC (permalink / raw)
To: Kim Phillips; +Cc: linuxppc-dev
In-Reply-To: <20060930183311.1d50638c.kim.phillips@freescale.com>
Kim Phillips writes:
> if (bcsr_regs == NULL)
> - bcsr_regs = (u8 *) ioremap(BCSR_PHYS_ADDR, BCSR_SIZE);
> + bcsr_regs = get_bcsr();
> bcsr_regs[14] |= 0x40;
Umm, if the BSCR is really so unique to each board, how come this
driver is frobbing a specific bit? How does the ucc_geth driver know
about the layout of a given board's BCSR?
Also, this patch means that the kernel won't build (assuming you have
the ucc_geth driver in your config) until we get to patch 9/15, where
get_bcsr gets defined.
Lastly, shouldn't this patch be going through Jeff Garzik?
Paul.
^ permalink raw reply
* Re: [PATCH 2/2] enable generic rtc hook for the MPC8349 mITX
From: Mark A. Greer @ 2006-10-02 1:51 UTC (permalink / raw)
To: Tom Rini; +Cc: linuxppc-dev
In-Reply-To: <20060929232541.GN2385@smtp.west.cox.net>
On Fri, Sep 29, 2006 at 04:25:41PM -0700, Tom Rini wrote:
> Does this mean we can then rip out some existing code, so long as
> there's associated cleanup / rtc class support additions?
Long term, the todc stuff should disappear.
Mark
^ permalink raw reply
* RE: [PATCH 2/2] Add support for MPC832x MDS evaluation board
From: Joakim Tjernlund @ 2006-10-01 11:00 UTC (permalink / raw)
To: 'Kim Phillips', linuxppc-dev
In-Reply-To: <20060930215509.2989794a.kim.phillips@freescale.com>
> -----Original Message-----
> From:
> linuxppc-dev-bounces+joakim.tjernlund=transmode.se@ozlabs.org
> [mailto:linuxppc-dev-bounces+joakim.tjernlund=transmode.se@ozl
abs.org] On Behalf Of Kim Phillips
> Sent: den 1 oktober 2006 04:55
> To: linuxppc-dev@ozlabs.org
> Subject: [PATCH 2/2] Add support for MPC832x MDS evaluation board
>
> Add support for MPC832x MDS evaluation board.
>
> This patch depends on the 8360+QE patches by Leo Li.
Thank you, I have been struggling with adapting Leo's earlier 8360 patches
on top of 2.6.17 but could not get UCC2 and UCC4(only UCC3 worked) to work
as network i/f's.
Hopefully I will get some time next week to try this out on our MPC832x MDS evaluation board and/or our custom board.
I hope you will be able to address the of_device conversation problem
you mentioned until then.
Jocke
^ permalink raw reply
* Re: [PATCH 1/2] Add support for the e300c2 core
From: Kumar Gala @ 2006-10-01 4:48 UTC (permalink / raw)
To: Kim Phillips; +Cc: linuxppc-dev
In-Reply-To: <20060930215500.5ae1cec8.kim.phillips@freescale.com>
On Sep 30, 2006, at 9:55 PM, Kim Phillips wrote:
> Add support for the Freescale e300c2 core found in the MPC832x
> processor line.
>
> As far as the kernel is concerned, the e300c2 core is identical to
> the e300c1 found in the mpc834x, except that it's had its floating
> point unit chopped off.
>
> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
> ---
> arch/powerpc/kernel/cputable.c | 18 +++++++++++++++---
> 1 files changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/
> cputable.c
> index 190a57e..ce13830 100644
> --- a/arch/powerpc/kernel/cputable.c
> +++ b/arch/powerpc/kernel/cputable.c
> @@ -63,6 +63,7 @@ #define COMMON_USER_PA6T (COMMON_USER_PP
> PPC_FEATURE_HAS_ALTIVEC_COMP)
> #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
> PPC_FEATURE_BOOKE)
> +#define COMMON_USER_E300 (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU)
Lets just drop COMMON_USER_E300 and explicitly set this like we do on
8xx.
> /* We only set the spe features if the kernel was compiled with
> * spe support
> @@ -763,12 +764,23 @@ #if CLASSIC_PPC
> .cpu_setup = __setup_cpu_603,
> .platform = "ppc603",
> },
> - { /* e300 (a 603e core, plus some) on 83xx */
> + { /* e300c1 (a 603e core, plus some) on 83xx */
> .pvr_mask = 0x7fff0000,
> .pvr_value = 0x00830000,
> - .cpu_name = "e300",
> + .cpu_name = "e300c1",
> .cpu_features = CPU_FTRS_E300,
> - .cpu_user_features = COMMON_USER,
> + .cpu_user_features = COMMON_USER_E300 | PPC_FEATURE_HAS_FPU,
This seems point less, why not just leave this as COMMON_USER for e300c1
> + .icache_bsize = 32,
> + .dcache_bsize = 32,
> + .cpu_setup = __setup_cpu_603,
> + .platform = "ppc603",
> + },
> + { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
> + .pvr_mask = 0x7fff0000,
> + .pvr_value = 0x00840000,
> + .cpu_name = "e300c2",
> + .cpu_features = CPU_FTRS_E300,
> + .cpu_user_features = COMMON_USER_E300,
Why don't we just set .cpu_user_features = PPC_FEATURE_32 |
PPC_FEATURE_HAS_MMU like we do on 8xx.
> .icache_bsize = 32,
> .dcache_bsize = 32,
> .cpu_setup = __setup_cpu_603,
- kumar
^ permalink raw reply
* Re: [PATCH] Change ucc_geth driver to use of_device
From: Kumar Gala @ 2006-10-01 4:37 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, Li Yang
In-Reply-To: <17694.23677.886959.674776@cargo.ozlabs.ibm.com>
On Sep 30, 2006, at 7:01 AM, Paul Mackerras wrote:
> Li Yang writes:
>
>> This patch change ucc_geth driver to use of_device from
>> platform_device. It also fix a bug that bcsr_regs gets
>> accidentally unmapped. Remove trailing space.
>
> So, does this go on top of your series of 9 patches, or is it instead
> of one of them?
I'm not quite sure myself at this point, but would like to see the
patches merged into one set, instead of patches on top of patches. I
still have a number of comments before I think the QE lib code is in
a form that we should accept.
However, the "[PATCH] Fix rheap alignment problem" can go into tree
at any time.
http://patchwork.ozlabs.org/linuxppc/patch?id=7202
- kumar
^ permalink raw reply
* Support for 36-bit physical addresses on 8641?
From: David A. Brown @ 2006-10-01 3:16 UTC (permalink / raw)
To: linuxppc-dev
All,
Does anybody know if there is any development effort being expended on
support for 36-bit physical addressing on the 8641? If so, who is leading
the project?
Thanks,
David Brown
^ permalink raw reply
* [PATCH 2/2] Add support for MPC832x MDS evaluation board
From: Kim Phillips @ 2006-10-01 2:55 UTC (permalink / raw)
To: linuxppc-dev
Add support for MPC832x MDS evaluation board.
This patch depends on the 8360+QE patches by Leo Li.
The MPC832x processors (MPC8323E, MPC8323, MPC8321E, MPC8321) sport the e300c2 core plus a QUICC Engine (QE). This patch adds support for the 832x MDS evaluation board.
The 832x MDS dts and defconfig files are pending more tests.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/Kconfig | 2
arch/powerpc/platforms/83xx/Kconfig | 13 ++
arch/powerpc/platforms/83xx/Makefile | 1
arch/powerpc/platforms/83xx/mpc832x_mds.c | 215 +++++++++++++++++++++++++++++
arch/powerpc/platforms/83xx/mpc832x_mds.h | 19 +++
5 files changed, 249 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 0402209..2ae7083 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -357,7 +357,7 @@ endchoice
config QUICC_ENGINE
bool
- depends on PPC_MPC836x
+ depends on PPC_MPC836x || PPC_MPC832x
default y
help
The QE(QUICC Engine) is a new generation of coprocessor on
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 83dfded..7edb6b4 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -5,6 +5,13 @@ choice
prompt "Machine Type"
default MPC834x_SYS
+config MPC832x_MDS
+ bool "Freescale MPC832x MDS"
+ select DEFAULT_UIMAGE
+ select QUICC_ENGINE
+ help
+ This option enables support for the MPC832x MDS evaluation board.
+
config MPC834x_SYS
bool "Freescale MPC834x SYS"
select DEFAULT_UIMAGE
@@ -34,6 +41,12 @@ config MPC8360E_PB
endchoice
+config PPC_MPC832x
+ bool
+ select PPC_UDBG_16550
+ select PPC_INDIRECT_PCI
+ default y if MPC832x_MDS
+
config MPC834x
bool
select PPC_UDBG_16550
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
index 0da2d0d..5cf1ac0 100644
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile
@@ -3,6 +3,7 @@ # Makefile for the PowerPC 83xx linux ke
#
obj-y := misc.o
obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_MPC832x_MDS) += mpc832x_mds.o
obj-$(CONFIG_MPC834x_SYS) += mpc834x_sys.o
obj-$(CONFIG_MPC834x_ITX) += mpc834x_itx.o
obj-$(CONFIG_MPC8360E_PB) += mpc8360e_pb.o
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
new file mode 100644
index 0000000..54dea9d
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Description:
+ * MPC832xE MDS board specific routines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/initrd.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ipic.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <sysdev/fsl_soc.h>
+#include <asm/qe.h>
+#include <asm/qe_ic.h>
+
+#include "mpc83xx.h"
+#include "mpc832x_mds.h"
+
+#undef DEBUG
+#ifdef DEBUG
+#define DBG(fmt...) udbg_printf(fmt)
+#else
+#define DBG(fmt...)
+#endif
+
+#ifndef CONFIG_PCI
+unsigned long isa_io_base = 0;
+unsigned long isa_mem_base = 0;
+#endif
+
+static u8 *bcsr_regs = NULL;
+
+u8 *get_bcsr(void)
+{
+ return bcsr_regs;
+}
+
+/* ************************************************************************
+ *
+ * Setup the architecture
+ *
+ */
+static void __init mpc832x_sys_setup_arch(void)
+{
+ struct device_node *np;
+
+ if (ppc_md.progress)
+ ppc_md.progress("mpc832x_sys_setup_arch()", 0);
+
+ np = of_find_node_by_type(NULL, "cpu");
+ if (np != 0) {
+ unsigned int *fp =
+ (int *)get_property(np, "clock-frequency", NULL);
+ if (fp != 0)
+ loops_per_jiffy = *fp / HZ;
+ else
+ loops_per_jiffy = 50000000 / HZ;
+ of_node_put(np);
+ }
+
+ /* Map BCSR area */
+ np = of_find_node_by_name(NULL, "bcsr");
+ if (np != 0) {
+ struct resource res;
+
+ of_address_to_resource(np, 0, &res);
+ bcsr_regs = ioremap(res.start, res.end - res.start +1);
+ of_node_put(np);
+ }
+
+#ifdef CONFIG_PCI
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+ add_bridge(np);
+
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_exclude_device = mpc83xx_exclude_device;
+#endif
+
+#ifdef CONFIG_QUICC_ENGINE
+ qe_reset();
+
+ if ((np = of_find_node_by_name(np, "par_io")) != NULL) {
+ par_io_init(np);
+ of_node_put(np);
+
+ for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
+ par_io_of_config(np);
+ }
+
+ if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
+ != NULL){
+ /* Reset the Ethernet PHY */
+ bcsr_regs[9] &= ~0x20;
+ udelay(1000);
+ bcsr_regs[9] |= 0x20;
+ iounmap(bcsr_regs);
+ of_node_put(np);
+ }
+
+#endif /* CONFIG_QUICC_ENGINE */
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ if (initrd_start)
+ ROOT_DEV = Root_RAM0;
+ else
+#endif
+#ifdef CONFIG_ROOT_NFS
+ ROOT_DEV = Root_NFS;
+#else
+ ROOT_DEV = Root_HDA1;
+#endif
+}
+
+void __init mpc832x_sys_init_IRQ(void)
+{
+
+ struct device_node *np;
+
+ np = of_find_node_by_type(NULL, "ipic");
+ if (!np)
+ return;
+
+ ipic_init(np, 0);
+
+ /* Initialize the default interrupt mapping priorities,
+ * in case the boot rom changed something on us.
+ */
+ ipic_set_default_priority();
+ of_node_put(np);
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_node_by_type(NULL, "qeic");
+ if (!np)
+ return;
+
+ qe_ic_init(np, 0);
+ of_node_put(np);
+#endif /* CONFIG_QUICC_ENGINE */
+}
+
+#if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
+extern ulong ds1374_get_rtc_time(void);
+extern int ds1374_set_rtc_time(ulong);
+
+static int __init mpc832x_rtc_hookup(void)
+{
+ struct timespec tv;
+
+ ppc_md.get_rtc_time = ds1374_get_rtc_time;
+ ppc_md.set_rtc_time = ds1374_set_rtc_time;
+
+ tv.tv_nsec = 0;
+ tv.tv_sec = (ppc_md.get_rtc_time) ();
+ do_settimeofday(&tv);
+
+ return 0;
+}
+
+late_initcall(mpc832x_rtc_hookup);
+#endif
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init mpc832x_sys_probe(void)
+{
+ char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
+ "model", NULL);
+
+ if (model == NULL)
+ return 0;
+ if (strcmp(model, "MPC8323EMDS"))
+ return 0;
+
+ DBG("%s found\n", model);
+
+ return 1;
+}
+
+define_machine(mpc832x_mds) {
+ .name = "MPC832x MDS",
+ .probe = mpc832x_sys_probe,
+ .setup_arch = mpc832x_sys_setup_arch,
+ .init_IRQ = mpc832x_sys_init_IRQ,
+ .get_irq = ipic_get_irq,
+ .restart = mpc83xx_restart,
+ .time_init = mpc83xx_time_init,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.h b/arch/powerpc/platforms/83xx/mpc832x_mds.h
new file mode 100644
index 0000000..a495889
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Description:
+ * MPC832x MDS board specific header.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MACH_MPC832x_MDS_H__
+#define __MACH_MPC832x_MDS_H__
+
+extern u8 *get_bcsr(void);
+
+#endif /* __MACH_MPC832x_MDS_H__ */
--
1.4.2.1
^ permalink raw reply related
* [PATCH 1/2] Add support for the e300c2 core
From: Kim Phillips @ 2006-10-01 2:55 UTC (permalink / raw)
To: linuxppc-dev
Add support for the Freescale e300c2 core found in the MPC832x processor line.
As far as the kernel is concerned, the e300c2 core is identical to the e300c1 found in the mpc834x, except that it's had its floating point unit chopped off.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/kernel/cputable.c | 18 +++++++++++++++---
1 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 190a57e..ce13830 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -63,6 +63,7 @@ #define COMMON_USER_PA6T (COMMON_USER_PP
PPC_FEATURE_HAS_ALTIVEC_COMP)
#define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
PPC_FEATURE_BOOKE)
+#define COMMON_USER_E300 (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU)
/* We only set the spe features if the kernel was compiled with
* spe support
@@ -763,12 +764,23 @@ #if CLASSIC_PPC
.cpu_setup = __setup_cpu_603,
.platform = "ppc603",
},
- { /* e300 (a 603e core, plus some) on 83xx */
+ { /* e300c1 (a 603e core, plus some) on 83xx */
.pvr_mask = 0x7fff0000,
.pvr_value = 0x00830000,
- .cpu_name = "e300",
+ .cpu_name = "e300c1",
.cpu_features = CPU_FTRS_E300,
- .cpu_user_features = COMMON_USER,
+ .cpu_user_features = COMMON_USER_E300 | PPC_FEATURE_HAS_FPU,
+ .icache_bsize = 32,
+ .dcache_bsize = 32,
+ .cpu_setup = __setup_cpu_603,
+ .platform = "ppc603",
+ },
+ { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
+ .pvr_mask = 0x7fff0000,
+ .pvr_value = 0x00840000,
+ .cpu_name = "e300c2",
+ .cpu_features = CPU_FTRS_E300,
+ .cpu_user_features = COMMON_USER_E300,
.icache_bsize = 32,
.dcache_bsize = 32,
.cpu_setup = __setup_cpu_603,
--
1.4.2.1
^ permalink raw reply related
* Re: Linux not booting consistantly
From: Jeff Stevens @ 2006-10-01 2:30 UTC (permalink / raw)
To: Muruga Ganapathy, Stefan Roese, linuxppc-embedded
In-Reply-To: <200609301538.k8UFcBs05081@sierra.gdatech.com>
Ok, my initial finding (that it was hanging after
do_init_bootmem) was incorrect. I enabled the early
serial debug interface in the kernel, and it is
failing when initializing the PCI busses. So I tried
typing "pci 0" in U-Boot, and I get
"pci_bus_to_hose(): failed" for busses 1 and 2 (0
returns fine). If I comment out the board's pci_init
function, the kernel will boot every time, though it
crashes when it tries to probe the pci busses (as
expected). So it seems to be an issue in my U-Boot
configuration or bootstrap settings.
Thanks for the help though!
--- Muruga Ganapathy <gmuruga@gdatech.com> wrote:
>
> I would like to suggest to check the (quality of)
> clocks to memory
> under
>
> a. normal condition ( before loading the linux)
> b. during the linux booting
>
> Usually the clock needs to be buffered if it needs
> to drive
> more memory chips ( banks).
>
> Another suggestion is to increase the cas latency to
> a higher
> value in the memory controller. ( say from 2 to 2.5
> or to a higher
> values.
>
> Also there are configuration registers to introduce
> wait states to
> memory read and write cycles. So you may want to
> introduce more wait
> states by programming the memory controller
> register.
>
> Thanks
> G.Muruganandam
>
>
>
> > I have been working with the hardware guys trying
> to
> > find any issues with the memory, and we haven't
> seen
> > anything yet, and we have talked to AMCC, and they
> > said they couldn't see anything wrong with the
> > hardware. I did do a post-mordum dump of the log
> > buffer, and this is what I get:
> >
> > 001e40c4: 3c353e4c 696e7578 20766572 73696f6e
> > <5>Linux version
> > 001e40d4: 20322e36 2e313520 28726f6f 74406c6f
> > 2.6.15 (root@lo
> > 001e40e4: 63616c68 6f73742e 6c6f6361 6c646f6d
> > calhost.localdom
> > 001e40f4: 61696e29 20286763 63207665 7273696f
> ain)
> > (gcc versio
> > 001e4104: 6e20342e 302e3020 2844454e 5820454c n
> > 4.0.0 (DENX EL
> > 001e4114: 444b2034 2e302034 2e302e30 29292023
> DK
> > 4.0 4.0.0)) #
> > 001e4124: 38205475 65205365 70203236 2031373a 8
> Tue
> > Sep 26 17:
> > 001e4134: 34393a31 33204544 54203230 30360a3c
> 49:13
> > EDT 2006.<
> > 001e4144: 343e4a4a 533a2057 41532048 4552454a
> > 4>JJS: WAS HEREJ
> > 001e4154: 4a53324a 4a53334a 4a53335f 314a4a53
> > JS2JJS3JJS3_1JJS
> > 001e4164: 345f4a4a 53345f31 5f4a4a53 345f325f
> > 4_JJS4_1_JJS4_2_
> > 001e4174: 4a4a5334 5f335f4a 4a53345f 00000000
> > JJS4_3_JJS4_....
> > 001e4184: 00000000 00000000 ........
> >
> > I placed a few printks in arch/ppc/kernel/start.c
> and
> > found that it crashed right after
> do_init_bootmem(),
> > right after placing the first character of
> "_JJS4_1".
> >
> > printk("JJS3");
> > parse_early_param();
> > printk("JJS3_1");
> > for (i = 0; i < 1000000; i++)
> > {
> > if (i > 999999)
> > {
> > break;
> > }
> > }
> >
> > printk("JJS4");
> > /* set up the bootmem stuff with available
> > memory */
> > do_init_bootmem();
> > printk("_JJS4_1");
> > if ( ppc_md.progress )
> > ppc_md.progress("setup_arch: bootmem", 0x3eab);
> > printk("_JJS4_2");
> >
> >
> > When it does decide to work, most of the time it
> gets
> > through the whole kernel and everything runs fine,
> > though I have seen it hang after probing for PCI
> > devices a couple of times. This looks like it is
> a
> > memory issue, but I don't know what else to try.
> Does
> > anyone have any ideas? I would appreciate any
> input.
> >
> > Thanks,
> > Jeff Stevens
> >
> >
> > __________________________________________________
> > Do You Yahoo!?
> > Tired of spam? Yahoo! Mail has the best spam
> protection around
> > http://mail.yahoo.com
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> >
>
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
> >
> >
>
>
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> San Jose CA, 95131
> Phone (408) 432-3090
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>
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> Technologies Inc and
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^ permalink raw reply
* [PATCH 14/15] removed typedefs from ucc_geth driver
From: Kim Phillips @ 2006-09-30 23:36 UTC (permalink / raw)
To: linuxppc-dev
removed typedefs from ucc_geth driver
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
drivers/net/ucc_geth.c | 348 ++++++++++++++++++++++---------------------
drivers/net/ucc_geth.h | 248 +++++++++++++++----------------
drivers/net/ucc_geth_phy.c | 12 +
drivers/net/ucc_geth_phy.h | 2
include/linux/fsl_devices.h | 6 -
5 files changed, 307 insertions(+), 309 deletions(-)
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index ef6cc2a..b6bf4ea 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -67,7 +67,7 @@ #endif /* UGETH_VERBOSE_DEBUG */
static DEFINE_SPINLOCK(ugeth_lock);
-static ucc_geth_info_t ugeth_primary_info = {
+static struct ucc_geth_info ugeth_primary_info = {
.uf_info = {
.bd_mem_part = MEM_PART_SYSTEM,
.rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
@@ -160,7 +160,7 @@ #endif
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
};
-static ucc_geth_info_t ugeth_info[8];
+static struct ucc_geth_info ugeth_info[8];
#ifdef DEBUG
static void mem_disp(u8 *addr, int size)
@@ -216,8 +216,8 @@ static struct list_head *dequeue(struct
}
}
-static int get_interface_details(enet_interface_e enet_interface,
- enet_speed_e *speed,
+static int get_interface_details(enum enet_interface enet_interface,
+ enum enet_speed *speed,
int *r10m,
int *rmm,
int *rpm,
@@ -280,7 +280,7 @@ static int get_interface_details(enet_in
return 0;
}
-static struct sk_buff *get_new_skb(ucc_geth_private_t *ugeth, u8 *bd)
+static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth, u8 *bd)
{
struct sk_buff *skb = NULL;
@@ -314,7 +314,7 @@ static struct sk_buff *get_new_skb(ucc_g
return skb;
}
-static int rx_bd_buffer_set(ucc_geth_private_t *ugeth, u8 rxQ)
+static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
{
u8 *bd;
u32 bd_status;
@@ -342,12 +342,12 @@ static int rx_bd_buffer_set(ucc_geth_pri
return 0;
}
-static int fill_init_enet_entries(ucc_geth_private_t *ugeth,
+static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
volatile u32 *p_start,
u8 num_entries,
u32 thread_size,
u32 thread_alignment,
- qe_risc_allocation_e risc,
+ enum qe_risc_allocation risc,
int skip_page_for_first_entry)
{
u32 init_enet_offset;
@@ -380,10 +380,10 @@ static int fill_init_enet_entries(ucc_ge
return 0;
}
-static int return_init_enet_entries(ucc_geth_private_t *ugeth,
+static int return_init_enet_entries(struct ucc_geth_private *ugeth,
volatile u32 *p_start,
u8 num_entries,
- qe_risc_allocation_e risc,
+ enum qe_risc_allocation risc,
int skip_page_for_first_entry)
{
u32 init_enet_offset;
@@ -413,11 +413,11 @@ static int return_init_enet_entries(ucc_
}
#ifdef DEBUG
-static int dump_init_enet_entries(ucc_geth_private_t *ugeth,
+static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
volatile u32 *p_start,
u8 num_entries,
u32 thread_size,
- qe_risc_allocation_e risc,
+ enum qe_risc_allocation risc,
int skip_page_for_first_entry)
{
u32 init_enet_offset;
@@ -453,14 +453,14 @@ static int dump_init_enet_entries(ucc_ge
#endif
#ifdef CONFIG_UGETH_FILTERING
-static enet_addr_container_t *get_enet_addr_container(void)
+static struct enet_addr_container *get_enet_addr_container(void)
{
- enet_addr_container_t *enet_addr_cont;
+ struct enet_addr_container *enet_addr_cont;
/* allocate memory */
- enet_addr_cont = kmalloc(sizeof(enet_addr_container_t), GFP_KERNEL);
+ enet_addr_cont = kmalloc(sizeof(struct enet_addr_container), GFP_KERNEL);
if (!enet_addr_cont) {
- ugeth_err("%s: No memory for enet_addr_container_t object.",
+ ugeth_err("%s: No memory for enet_addr_container object.",
__FUNCTION__);
return NULL;
}
@@ -469,16 +469,16 @@ static enet_addr_container_t *get_enet_a
}
#endif /* CONFIG_UGETH_FILTERING */
-static void put_enet_addr_container(enet_addr_container_t *enet_addr_cont)
+static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
{
kfree(enet_addr_cont);
}
#ifdef CONFIG_UGETH_FILTERING
-static int hw_add_addr_in_paddr(ucc_geth_private_t *ugeth,
- enet_addr_t *p_enet_addr, u8 paddr_num)
+static int hw_add_addr_in_paddr(struct ucc_geth_private *ugeth,
+ u8 **p_enet_addr, u8 paddr_num)
{
- ucc_geth_82xx_address_filtering_pram_t *p_82xx_addr_filt;
+ struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
if (!(paddr_num < NUM_OF_PADDRS)) {
ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__);
@@ -486,7 +486,7 @@ static int hw_add_addr_in_paddr(ucc_geth
}
p_82xx_addr_filt =
- (ucc_geth_82xx_address_filtering_pram_t *) ugeth->p_rx_glbl_pram->
+ (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
addressfiltering;
/* Ethernet frames are defined in Little Endian mode, */
@@ -505,9 +505,9 @@ static int hw_add_addr_in_paddr(ucc_geth
}
#endif /* CONFIG_UGETH_FILTERING */
-static int hw_clear_addr_in_paddr(ucc_geth_private_t *ugeth, u8 paddr_num)
+static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
{
- ucc_geth_82xx_address_filtering_pram_t *p_82xx_addr_filt;
+ struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
if (!(paddr_num < NUM_OF_PADDRS)) {
ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__);
@@ -515,7 +515,7 @@ static int hw_clear_addr_in_paddr(ucc_ge
}
p_82xx_addr_filt =
- (ucc_geth_82xx_address_filtering_pram_t *) ugeth->p_rx_glbl_pram->
+ (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
addressfiltering;
/* Writing address ff.ff.ff.ff.ff.ff disables address
@@ -527,14 +527,14 @@ static int hw_clear_addr_in_paddr(ucc_ge
return 0;
}
-static void hw_add_addr_in_hash(ucc_geth_private_t *ugeth,
- enet_addr_t *p_enet_addr)
+static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
+ u8 **p_enet_addr)
{
- ucc_geth_82xx_address_filtering_pram_t *p_82xx_addr_filt;
+ struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
u32 cecr_subblock;
p_82xx_addr_filt =
- (ucc_geth_82xx_address_filtering_pram_t *) ugeth->p_rx_glbl_pram->
+ (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
addressfiltering;
cecr_subblock =
@@ -558,10 +558,10 @@ static void hw_add_addr_in_hash(ucc_geth
}
#ifdef CONFIG_UGETH_MAGIC_PACKET
-static void magic_packet_detection_enable(ucc_geth_private_t *ugeth)
+static void magic_packet_detection_enable(struct ucc_geth_private *ugeth)
{
- ucc_fast_private_t *uccf;
- ucc_geth_t *ug_regs;
+ struct ucc_fast_private *uccf;
+ struct ucc_geth *ug_regs;
u32 maccfg2, uccm;
uccf = ugeth->uccf;
@@ -578,10 +578,10 @@ static void magic_packet_detection_enabl
out_be32(&ug_regs->maccfg2, maccfg2);
}
-static void magic_packet_detection_disable(ucc_geth_private_t *ugeth)
+static void magic_packet_detection_disable(struct ucc_geth_private *ugeth)
{
- ucc_fast_private_t *uccf;
- ucc_geth_t *ug_regs;
+ struct ucc_fast_private *uccf;
+ struct ucc_geth *ug_regs;
u32 maccfg2, uccm;
uccf = ugeth->uccf;
@@ -599,26 +599,26 @@ static void magic_packet_detection_disab
}
#endif /* MAGIC_PACKET */
-static inline int compare_addr(enet_addr_t *addr1, enet_addr_t *addr2)
+static inline int compare_addr(u8 **addr1, u8 **addr2)
{
return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
}
#ifdef DEBUG
-static void get_statistics(ucc_geth_private_t *ugeth,
- ucc_geth_tx_firmware_statistics_t *
+static void get_statistics(struct ucc_geth_private *ugeth,
+ struct ucc_geth_tx_firmware_statistics *
tx_firmware_statistics,
- ucc_geth_rx_firmware_statistics_t *
+ struct ucc_geth_rx_firmware_statistics *
rx_firmware_statistics,
- ucc_geth_hardware_statistics_t *hardware_statistics)
+ struct ucc_geth_hardware_statistics *hardware_statistics)
{
- ucc_fast_t *uf_regs;
- ucc_geth_t *ug_regs;
- ucc_geth_tx_firmware_statistics_pram_t *p_tx_fw_statistics_pram;
- ucc_geth_rx_firmware_statistics_pram_t *p_rx_fw_statistics_pram;
+ struct ucc_fast *uf_regs;
+ struct ucc_geth *ug_regs;
+ struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
+ struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
ug_regs = ugeth->ug_regs;
- uf_regs = (ucc_fast_t *) ug_regs;
+ uf_regs = (struct ucc_fast *) ug_regs;
p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
@@ -724,7 +724,7 @@ static void get_statistics(ucc_geth_priv
}
}
-static void dump_bds(ucc_geth_private_t *ugeth)
+static void dump_bds(struct ucc_geth_private *ugeth)
{
int i;
int length;
@@ -749,7 +749,7 @@ static void dump_bds(ucc_geth_private_t
}
}
-static void dump_regs(ucc_geth_private_t *ugeth)
+static void dump_regs(struct ucc_geth_private *ugeth)
{
int i;
@@ -890,7 +890,7 @@ static void dump_regs(ucc_geth_private_t
ugeth_info("Base address: 0x%08x",
(u32) & ugeth->p_thread_data_tx[i]);
mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
- sizeof(ucc_geth_thread_data_tx_t));
+ sizeof(struct ucc_geth_thread_data_tx));
}
}
if (ugeth->p_thread_data_rx) {
@@ -924,7 +924,7 @@ static void dump_regs(ucc_geth_private_t
ugeth_info("Base address: 0x%08x",
(u32) & ugeth->p_thread_data_rx[i]);
mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
- sizeof(ucc_geth_thread_data_rx_t));
+ sizeof(struct ucc_geth_thread_data_rx));
}
}
if (ugeth->p_exf_glbl_param) {
@@ -1102,7 +1102,7 @@ static void dump_regs(ucc_geth_private_t
ugeth_info("Base address: 0x%08x",
(u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
- sizeof(ucc_geth_send_queue_qd_t));
+ sizeof(struct ucc_geth_send_queue_qd));
}
}
if (ugeth->p_scheduler) {
@@ -1184,7 +1184,7 @@ static void dump_regs(ucc_geth_private_t
qe_muram_addr(in_be32
(&ugeth->p_rx_bd_qs_tbl[i].
bdbaseptr)),
- sizeof(ucc_geth_rx_prefetched_bds_t));
+ sizeof(struct ucc_geth_rx_prefetched_bds));
}
}
if (ugeth->p_init_enet_param_shadow) {
@@ -1195,7 +1195,7 @@ static void dump_regs(ucc_geth_private_t
mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
sizeof(*ugeth->p_init_enet_param_shadow));
- size = sizeof(ucc_geth_thread_rx_pram_t);
+ size = sizeof(struct ucc_geth_thread_rx_pram);
if (ugeth->ug_info->rxExtendedFiltering) {
size +=
THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
@@ -1213,7 +1213,7 @@ static void dump_regs(ucc_geth_private_t
&(ugeth->p_init_enet_param_shadow->
txthread[0]),
ENET_INIT_PARAM_MAX_ENTRIES_TX,
- sizeof(ucc_geth_thread_tx_pram_t),
+ sizeof(struct ucc_geth_thread_tx_pram),
ugeth->ug_info->riscTx, 0);
dump_init_enet_entries(ugeth,
&(ugeth->p_init_enet_param_shadow->
@@ -1575,12 +1575,12 @@ static int init_min_frame_len(u16 min_fr
return 0;
}
-static int adjust_enet_interface(ucc_geth_private_t *ugeth)
+static int adjust_enet_interface(struct ucc_geth_private *ugeth)
{
- ucc_geth_info_t *ug_info;
- ucc_geth_t *ug_regs;
- ucc_fast_t *uf_regs;
- enet_speed_e speed;
+ struct ucc_geth_info *ug_info;
+ struct ucc_geth *ug_regs;
+ struct ucc_fast *uf_regs;
+ enum enet_speed speed;
int ret_val, rpm = 0, tbi = 0, r10m = 0, rmm =
0, limited_to_full_duplex = 0;
u32 upsmr, maccfg2, utbipar, tbiBaseAddress;
@@ -1688,8 +1688,8 @@ static int adjust_enet_interface(ucc_get
*/
static void adjust_link(struct net_device *dev)
{
- ucc_geth_private_t *ugeth = netdev_priv(dev);
- ucc_geth_t *ug_regs;
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
+ struct ucc_geth *ug_regs;
u32 tempval;
struct ugeth_mii_info *mii_info = ugeth->mii_info;
@@ -1824,9 +1824,9 @@ #endif /* CONFIG_MPC8360 */
*/
static int init_phy(struct net_device *dev)
{
- ucc_geth_private_t *ugeth = netdev_priv(dev);
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
struct phy_info *curphy;
- ucc_mii_mng_t *mii_regs;
+ struct ucc_mii_mng *mii_regs;
struct ugeth_mii_info *mii_info;
int err;
@@ -1911,17 +1911,17 @@ static int init_phy(struct net_device *d
}
#ifdef CONFIG_UGETH_TX_ON_DEMOND
-static int ugeth_transmit_on_demand(ucc_geth_private_t *ugeth)
+static int ugeth_transmit_on_demand(struct ucc_geth_private *ugeth)
{
- ucc_fast_transmit_on_demand(ugeth->uccf);
+ struct ucc_fastransmit_on_demand(ugeth->uccf);
return 0;
}
#endif
-static int ugeth_graceful_stop_tx(ucc_geth_private_t *ugeth)
+static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
{
- ucc_fast_private_t *uccf;
+ struct ucc_fast_private *uccf;
u32 cecr_subblock;
u32 temp;
@@ -1949,9 +1949,9 @@ static int ugeth_graceful_stop_tx(ucc_ge
return 0;
}
-static int ugeth_graceful_stop_rx(ucc_geth_private_t * ugeth)
+static int ugeth_graceful_stop_rx(struct ucc_geth_private * ugeth)
{
- ucc_fast_private_t *uccf;
+ struct ucc_fast_private *uccf;
u32 cecr_subblock;
u8 temp;
@@ -1980,9 +1980,9 @@ static int ugeth_graceful_stop_rx(ucc_ge
return 0;
}
-static int ugeth_restart_tx(ucc_geth_private_t *ugeth)
+static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
{
- ucc_fast_private_t *uccf;
+ struct ucc_fast_private *uccf;
u32 cecr_subblock;
uccf = ugeth->uccf;
@@ -1996,9 +1996,9 @@ static int ugeth_restart_tx(ucc_geth_pri
return 0;
}
-static int ugeth_restart_rx(ucc_geth_private_t *ugeth)
+static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
{
- ucc_fast_private_t *uccf;
+ struct ucc_fast_private *uccf;
u32 cecr_subblock;
uccf = ugeth->uccf;
@@ -2012,9 +2012,9 @@ static int ugeth_restart_rx(ucc_geth_pri
return 0;
}
-static int ugeth_enable(ucc_geth_private_t *ugeth, comm_dir_e mode)
+static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
{
- ucc_fast_private_t *uccf;
+ struct ucc_fast_private *uccf;
int enabled_tx, enabled_rx;
uccf = ugeth->uccf;
@@ -2041,9 +2041,9 @@ static int ugeth_enable(ucc_geth_private
}
-static int ugeth_disable(ucc_geth_private_t * ugeth, comm_dir_e mode)
+static int ugeth_disable(struct ucc_geth_private * ugeth, enum comm_dir mode)
{
- ucc_fast_private_t *uccf;
+ struct ucc_fast_private *uccf;
uccf = ugeth->uccf;
@@ -2066,7 +2066,7 @@ static int ugeth_disable(ucc_geth_privat
return 0;
}
-static void ugeth_dump_regs(ucc_geth_private_t *ugeth)
+static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
{
#ifdef DEBUG
ucc_fast_dump_regs(ugeth->uccf);
@@ -2076,9 +2076,9 @@ #endif
}
#ifdef CONFIG_UGETH_FILTERING
-static int ugeth_ext_filtering_serialize_tad(ucc_geth_tad_params_t *
+static int ugeth_ext_filtering_serialize_tad(struct ucc_geth_tad_params *
p_UccGethTadParams,
- qe_fltr_tad_t *qe_fltr_tad)
+ struct qe_fltr_tad *qe_fltr_tad)
{
u16 temp;
@@ -2116,11 +2116,11 @@ static int ugeth_ext_filtering_serialize
return 0;
}
-static enet_addr_container_t
- *ugeth_82xx_filtering_get_match_addr_in_hash(ucc_geth_private_t *ugeth,
- enet_addr_t *p_enet_addr)
+static struct enet_addr_container_t
+ *ugeth_82xx_filtering_get_match_addr_in_hash(struct ucc_geth_private *ugeth,
+ struct enet_addr *p_enet_addr)
{
- enet_addr_container_t *enet_addr_cont;
+ struct enet_addr_container *enet_addr_cont;
struct list_head *p_lh;
u16 i, num;
int32_t j;
@@ -2141,7 +2141,7 @@ static enet_addr_container_t
for (i = 0; i < num; i++) {
enet_addr_cont =
- (enet_addr_container_t *)
+ (struct enet_addr_container *)
ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
for (j = ENET_NUM_OCTETS_PER_ADDRESS - 1; j >= 0; j--) {
if ((*p_enet_addr)[j] != (enet_addr_cont->address)[j])
@@ -2154,11 +2154,11 @@ static enet_addr_container_t
return NULL;
}
-static int ugeth_82xx_filtering_add_addr_in_hash(ucc_geth_private_t *ugeth,
- enet_addr_t *p_enet_addr)
+static int ugeth_82xx_filtering_add_addr_in_hash(struct ucc_geth_private *ugeth,
+ struct enet_addr *p_enet_addr)
{
- ucc_geth_enet_address_recognition_location_e location;
- enet_addr_container_t *enet_addr_cont;
+ enum ucc_geth_enet_address_recognition_location location;
+ struct enet_addr_container *enet_addr_cont;
struct list_head *p_lh;
u8 i;
u32 limit;
@@ -2198,13 +2198,13 @@ static int ugeth_82xx_filtering_add_addr
return 0;
}
-static int ugeth_82xx_filtering_clear_addr_in_hash(ucc_geth_private_t *ugeth,
- enet_addr_t *p_enet_addr)
+static int ugeth_82xx_filtering_clear_addr_in_hash(struct ucc_geth_private *ugeth,
+ struct enet_addr *p_enet_addr)
{
- ucc_geth_82xx_address_filtering_pram_t *p_82xx_addr_filt;
- enet_addr_container_t *enet_addr_cont;
- ucc_fast_private_t *uccf;
- comm_dir_e comm_dir;
+ struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
+ struct enet_addr_container *enet_addr_cont;
+ struct ucc_fast_private *uccf;
+ enum comm_dir comm_dir;
u16 i, num;
struct list_head *p_lh;
u32 *addr_h, *addr_l;
@@ -2213,7 +2213,7 @@ static int ugeth_82xx_filtering_clear_ad
uccf = ugeth->uccf;
p_82xx_addr_filt =
- (ucc_geth_82xx_address_filtering_pram_t *) ugeth->p_rx_glbl_pram->
+ (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
addressfiltering;
if (!
@@ -2253,7 +2253,7 @@ static int ugeth_82xx_filtering_clear_ad
num = --(*p_counter);
for (i = 0; i < num; i++) {
enet_addr_cont =
- (enet_addr_container_t *)
+ (struct enet_addr_container *)
ENET_ADDR_CONT_ENTRY(dequeue(p_lh));
hw_add_addr_in_hash(ugeth, &(enet_addr_cont->address));
enqueue(p_lh, &enet_addr_cont->node); /* Put it back */
@@ -2266,14 +2266,14 @@ static int ugeth_82xx_filtering_clear_ad
}
#endif /* CONFIG_UGETH_FILTERING */
-static int ugeth_82xx_filtering_clear_all_addr_in_hash(ucc_geth_private_t *
+static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
ugeth,
- enet_addr_type_e
+ enum enet_addr_type
enet_addr_type)
{
- ucc_geth_82xx_address_filtering_pram_t *p_82xx_addr_filt;
- ucc_fast_private_t *uccf;
- comm_dir_e comm_dir;
+ struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
+ struct ucc_fast_private *uccf;
+ enum comm_dir comm_dir;
struct list_head *p_lh;
u16 i, num;
u32 *addr_h, *addr_l;
@@ -2282,7 +2282,7 @@ static int ugeth_82xx_filtering_clear_al
uccf = ugeth->uccf;
p_82xx_addr_filt =
- (ucc_geth_82xx_address_filtering_pram_t *) ugeth->p_rx_glbl_pram->
+ (struct ucc_geth_82xx_address_filtering_pram *) ugeth->p_rx_glbl_pram->
addressfiltering;
if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
@@ -2328,8 +2328,8 @@ static int ugeth_82xx_filtering_clear_al
}
#ifdef CONFIG_UGETH_FILTERING
-static int ugeth_82xx_filtering_add_addr_in_paddr(ucc_geth_private_t *ugeth,
- enet_addr_t *p_enet_addr,
+static int ugeth_82xx_filtering_add_addr_in_paddr(struct ucc_geth_private *ugeth,
+ struct enet_addr *p_enet_addr,
u8 paddr_num)
{
int i;
@@ -2349,14 +2349,14 @@ static int ugeth_82xx_filtering_add_addr
}
#endif /* CONFIG_UGETH_FILTERING */
-static int ugeth_82xx_filtering_clear_addr_in_paddr(ucc_geth_private_t *ugeth,
+static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
u8 paddr_num)
{
ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
}
-static void ucc_geth_memclean(ucc_geth_private_t *ugeth)
+static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
{
u16 i, j;
u8 *bd;
@@ -2493,11 +2493,11 @@ static void ucc_geth_memclean(ucc_geth_p
static void ucc_geth_set_multi(struct net_device *dev)
{
- ucc_geth_private_t *ugeth;
+ struct ucc_geth_private *ugeth;
struct dev_mc_list *dmi;
- ucc_fast_t *uf_regs;
- ucc_geth_82xx_address_filtering_pram_t *p_82xx_addr_filt;
- enet_addr_t tempaddr;
+ struct ucc_fast *uf_regs;
+ struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
+ u8 *tempaddr;
u8 *mcptr, *tdptr;
int i, j;
@@ -2514,7 +2514,7 @@ static void ucc_geth_set_multi(struct ne
uf_regs->upsmr &= ~UPSMR_PRO;
p_82xx_addr_filt =
- (ucc_geth_82xx_address_filtering_pram_t *) ugeth->
+ (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
p_rx_glbl_pram->addressfiltering;
if (dev->flags & IFF_ALLMULTI) {
@@ -2557,9 +2557,9 @@ static void ucc_geth_set_multi(struct ne
}
}
-static void ucc_geth_stop(ucc_geth_private_t *ugeth)
+static void ucc_geth_stop(struct ucc_geth_private *ugeth)
{
- ucc_geth_t *ug_regs = ugeth->ug_regs;
+ struct ucc_geth *ug_regs = ugeth->ug_regs;
u32 tempval;
ugeth_vdbg("%s: IN", __FUNCTION__);
@@ -2602,15 +2602,15 @@ static void ucc_geth_stop(ucc_geth_priva
ucc_geth_memclean(ugeth);
}
-static int ucc_geth_startup(ucc_geth_private_t *ugeth)
+static int ucc_geth_startup(struct ucc_geth_private *ugeth)
{
- ucc_geth_82xx_address_filtering_pram_t *p_82xx_addr_filt;
- ucc_geth_init_pram_t *p_init_enet_pram;
- ucc_fast_private_t *uccf;
- ucc_geth_info_t *ug_info;
- ucc_fast_info_t *uf_info;
- ucc_fast_t *uf_regs;
- ucc_geth_t *ug_regs;
+ struct ucc_geth_82xx_address_filtering_pram *p_82xx_addr_filt;
+ struct ucc_geth_init_pram *p_init_enet_pram;
+ struct ucc_fast_private *uccf;
+ struct ucc_geth_info *ug_info;
+ struct ucc_fast_info *uf_info;
+ struct ucc_fast *uf_regs;
+ struct ucc_geth *ug_regs;
int ret_val = -EINVAL;
u32 remoder = UCC_GETH_REMODER_INIT;
u32 init_enet_pram_offset, cecr_subblock, command, maccfg1;
@@ -2785,7 +2785,7 @@ static int ucc_geth_startup(ucc_geth_pri
UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
uf_regs = uccf->uf_regs;
- ug_regs = (ucc_geth_t *) (uccf->uf_regs);
+ ug_regs = (struct ucc_geth *) (uccf->uf_regs);
ugeth->ug_regs = ug_regs;
init_default_reg_vals(&uf_regs->upsmr,
@@ -3000,7 +3000,7 @@ static int ucc_geth_startup(ucc_geth_pri
/* Tx global PRAM */
/* Allocate global tx parameter RAM page */
ugeth->tx_glbl_pram_offset =
- qe_muram_alloc(sizeof(ucc_geth_tx_global_pram_t),
+ qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
if (IS_MURAM_ERR(ugeth->tx_glbl_pram_offset)) {
ugeth_err
@@ -3010,10 +3010,10 @@ static int ucc_geth_startup(ucc_geth_pri
return -ENOMEM;
}
ugeth->p_tx_glbl_pram =
- (ucc_geth_tx_global_pram_t *) qe_muram_addr(ugeth->
+ (struct ucc_geth_tx_global_pram *) qe_muram_addr(ugeth->
tx_glbl_pram_offset);
/* Zero out p_tx_glbl_pram */
- memset(ugeth->p_tx_glbl_pram, 0, sizeof(ucc_geth_tx_global_pram_t));
+ memset(ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
/* Fill global PRAM */
@@ -3021,7 +3021,7 @@ static int ucc_geth_startup(ucc_geth_pri
/* Size varies with number of Tx threads */
ugeth->thread_dat_tx_offset =
qe_muram_alloc(numThreadsTxNumerical *
- sizeof(ucc_geth_thread_data_tx_t) +
+ sizeof(struct ucc_geth_thread_data_tx) +
32 * (numThreadsTxNumerical == 1),
UCC_GETH_THREAD_DATA_ALIGNMENT);
if (IS_MURAM_ERR(ugeth->thread_dat_tx_offset)) {
@@ -3033,7 +3033,7 @@ static int ucc_geth_startup(ucc_geth_pri
}
ugeth->p_thread_data_tx =
- (ucc_geth_thread_data_tx_t *) qe_muram_addr(ugeth->
+ (struct ucc_geth_thread_data_tx *) qe_muram_addr(ugeth->
thread_dat_tx_offset);
out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
@@ -3050,7 +3050,7 @@ static int ucc_geth_startup(ucc_geth_pri
/* Size varies with number of Tx queues */
ugeth->send_q_mem_reg_offset =
qe_muram_alloc(ug_info->numQueuesTx *
- sizeof(ucc_geth_send_queue_qd_t),
+ sizeof(struct ucc_geth_send_queue_qd),
UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
if (IS_MURAM_ERR(ugeth->send_q_mem_reg_offset)) {
ugeth_err
@@ -3061,7 +3061,7 @@ static int ucc_geth_startup(ucc_geth_pri
}
ugeth->p_send_q_mem_reg =
- (ucc_geth_send_queue_mem_region_t *) qe_muram_addr(ugeth->
+ (struct ucc_geth_send_queue_mem_region *) qe_muram_addr(ugeth->
send_q_mem_reg_offset);
out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
@@ -3093,7 +3093,7 @@ static int ucc_geth_startup(ucc_geth_pri
if (ug_info->numQueuesTx > 1) {
/* scheduler exists only if more than 1 tx queue */
ugeth->scheduler_offset =
- qe_muram_alloc(sizeof(ucc_geth_scheduler_t),
+ qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
UCC_GETH_SCHEDULER_ALIGNMENT);
if (IS_MURAM_ERR(ugeth->scheduler_offset)) {
ugeth_err
@@ -3104,12 +3104,12 @@ static int ucc_geth_startup(ucc_geth_pri
}
ugeth->p_scheduler =
- (ucc_geth_scheduler_t *) qe_muram_addr(ugeth->
+ (struct ucc_geth_scheduler *) qe_muram_addr(ugeth->
scheduler_offset);
out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
ugeth->scheduler_offset);
/* Zero out p_scheduler */
- memset(ugeth->p_scheduler, 0, sizeof(ucc_geth_scheduler_t));
+ memset(ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
/* Set values in scheduler */
out_be32(&ugeth->p_scheduler->mblinterval,
@@ -3141,7 +3141,7 @@ static int ucc_geth_startup(ucc_geth_pri
statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
ugeth->tx_fw_statistics_pram_offset =
qe_muram_alloc(sizeof
- (ucc_geth_tx_firmware_statistics_pram_t),
+ (struct ucc_geth_tx_firmware_statistics_pram),
UCC_GETH_TX_STATISTICS_ALIGNMENT);
if (IS_MURAM_ERR(ugeth->tx_fw_statistics_pram_offset)) {
ugeth_err
@@ -3151,11 +3151,11 @@ static int ucc_geth_startup(ucc_geth_pri
return -ENOMEM;
}
ugeth->p_tx_fw_statistics_pram =
- (ucc_geth_tx_firmware_statistics_pram_t *)
+ (struct ucc_geth_tx_firmware_statistics_pram *)
qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
/* Zero out p_tx_fw_statistics_pram */
memset(ugeth->p_tx_fw_statistics_pram,
- 0, sizeof(ucc_geth_tx_firmware_statistics_pram_t));
+ 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
}
/* temoder */
@@ -3180,7 +3180,7 @@ static int ucc_geth_startup(ucc_geth_pri
/* Rx global PRAM */
/* Allocate global rx parameter RAM page */
ugeth->rx_glbl_pram_offset =
- qe_muram_alloc(sizeof(ucc_geth_rx_global_pram_t),
+ qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
if (IS_MURAM_ERR(ugeth->rx_glbl_pram_offset)) {
ugeth_err
@@ -3190,10 +3190,10 @@ static int ucc_geth_startup(ucc_geth_pri
return -ENOMEM;
}
ugeth->p_rx_glbl_pram =
- (ucc_geth_rx_global_pram_t *) qe_muram_addr(ugeth->
+ (struct ucc_geth_rx_global_pram *) qe_muram_addr(ugeth->
rx_glbl_pram_offset);
/* Zero out p_rx_glbl_pram */
- memset(ugeth->p_rx_glbl_pram, 0, sizeof(ucc_geth_rx_global_pram_t));
+ memset(ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
/* Fill global PRAM */
@@ -3201,7 +3201,7 @@ static int ucc_geth_startup(ucc_geth_pri
/* Size varies with number of Rx threads */
ugeth->thread_dat_rx_offset =
qe_muram_alloc(numThreadsRxNumerical *
- sizeof(ucc_geth_thread_data_rx_t),
+ sizeof(struct ucc_geth_thread_data_rx),
UCC_GETH_THREAD_DATA_ALIGNMENT);
if (IS_MURAM_ERR(ugeth->thread_dat_rx_offset)) {
ugeth_err
@@ -3212,7 +3212,7 @@ static int ucc_geth_startup(ucc_geth_pri
}
ugeth->p_thread_data_rx =
- (ucc_geth_thread_data_rx_t *) qe_muram_addr(ugeth->
+ (struct ucc_geth_thread_data_rx *) qe_muram_addr(ugeth->
thread_dat_rx_offset);
out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
@@ -3224,7 +3224,7 @@ static int ucc_geth_startup(ucc_geth_pri
statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
ugeth->rx_fw_statistics_pram_offset =
qe_muram_alloc(sizeof
- (ucc_geth_rx_firmware_statistics_pram_t),
+ (struct ucc_geth_rx_firmware_statistics_pram),
UCC_GETH_RX_STATISTICS_ALIGNMENT);
if (IS_MURAM_ERR(ugeth->rx_fw_statistics_pram_offset)) {
ugeth_err
@@ -3234,11 +3234,11 @@ static int ucc_geth_startup(ucc_geth_pri
return -ENOMEM;
}
ugeth->p_rx_fw_statistics_pram =
- (ucc_geth_rx_firmware_statistics_pram_t *)
+ (struct ucc_geth_rx_firmware_statistics_pram *)
qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
/* Zero out p_rx_fw_statistics_pram */
memset(ugeth->p_rx_fw_statistics_pram, 0,
- sizeof(ucc_geth_rx_firmware_statistics_pram_t));
+ sizeof(struct ucc_geth_rx_firmware_statistics_pram));
}
/* intCoalescingPtr */
@@ -3246,7 +3246,7 @@ static int ucc_geth_startup(ucc_geth_pri
/* Size varies with number of Rx queues */
ugeth->rx_irq_coalescing_tbl_offset =
qe_muram_alloc(ug_info->numQueuesRx *
- sizeof(ucc_geth_rx_interrupt_coalescing_entry_t),
+ sizeof(struct ucc_geth_rx_interrupt_coalescing_entry),
UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
if (IS_MURAM_ERR(ugeth->rx_irq_coalescing_tbl_offset)) {
ugeth_err
@@ -3257,7 +3257,7 @@ static int ucc_geth_startup(ucc_geth_pri
}
ugeth->p_rx_irq_coalescing_tbl =
- (ucc_geth_rx_interrupt_coalescing_table_t *)
+ (struct ucc_geth_rx_interrupt_coalescing_table *)
qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
ugeth->rx_irq_coalescing_tbl_offset);
@@ -3313,8 +3313,8 @@ static int ucc_geth_startup(ucc_geth_pri
/* Size varies with number of Rx queues */
ugeth->rx_bd_qs_tbl_offset =
qe_muram_alloc(ug_info->numQueuesRx *
- (sizeof(ucc_geth_rx_bd_queues_entry_t) +
- sizeof(ucc_geth_rx_prefetched_bds_t)),
+ (sizeof(struct ucc_geth_rx_bd_queues_entry) +
+ sizeof(struct ucc_geth_rx_prefetched_bds)),
UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
if (IS_MURAM_ERR(ugeth->rx_bd_qs_tbl_offset)) {
ugeth_err
@@ -3325,14 +3325,14 @@ static int ucc_geth_startup(ucc_geth_pri
}
ugeth->p_rx_bd_qs_tbl =
- (ucc_geth_rx_bd_queues_entry_t *) qe_muram_addr(ugeth->
+ (struct ucc_geth_rx_bd_queues_entry *) qe_muram_addr(ugeth->
rx_bd_qs_tbl_offset);
out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
/* Zero out p_rx_bd_qs_tbl */
memset(ugeth->p_rx_bd_qs_tbl,
0,
- ug_info->numQueuesRx * (sizeof(ucc_geth_rx_bd_queues_entry_t) +
- sizeof(ucc_geth_rx_prefetched_bds_t)));
+ ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
+ sizeof(struct ucc_geth_rx_prefetched_bds)));
/* Setup the table */
/* Assume BD rings are already established */
@@ -3403,7 +3403,7 @@ static int ucc_geth_startup(ucc_geth_pri
/* Allocate memory for extended filtering Mode Global
Parameters */
ugeth->exf_glbl_param_offset =
- qe_muram_alloc(sizeof(ucc_geth_exf_global_pram_t),
+ qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
if (IS_MURAM_ERR(ugeth->exf_glbl_param_offset)) {
ugeth_err
@@ -3414,7 +3414,7 @@ static int ucc_geth_startup(ucc_geth_pri
}
ugeth->p_exf_glbl_param =
- (ucc_geth_exf_global_pram_t *) qe_muram_addr(ugeth->
+ (struct ucc_geth_exf_global_pram *) qe_muram_addr(ugeth->
exf_glbl_param_offset);
out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
ugeth->exf_glbl_param_offset);
@@ -3436,7 +3436,7 @@ static int ucc_geth_startup(ucc_geth_pri
INIT_LIST_HEAD(&ugeth->ind_hash_q);
}
p_82xx_addr_filt =
- (ucc_geth_82xx_address_filtering_pram_t *) ugeth->
+ (struct ucc_geth_82xx_address_filtering_pram *) ugeth->
p_rx_glbl_pram->addressfiltering;
ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
@@ -3459,7 +3459,7 @@ static int ucc_geth_startup(ucc_geth_pri
* allocated resources can be released when the channel is freed.
*/
if (!(ugeth->p_init_enet_param_shadow =
- (ucc_geth_init_pram_t *) kmalloc(sizeof(ucc_geth_init_pram_t),
+ (struct ucc_geth_init_pram *) kmalloc(sizeof(struct ucc_geth_init_pram),
GFP_KERNEL))) {
ugeth_err
("%s: Can not allocate memory for"
@@ -3469,7 +3469,7 @@ static int ucc_geth_startup(ucc_geth_pri
}
/* Zero out *p_init_enet_param_shadow */
memset((char *)ugeth->p_init_enet_param_shadow,
- 0, sizeof(ucc_geth_init_pram_t));
+ 0, sizeof(struct ucc_geth_init_pram));
/* Fill shadow InitEnet command parameter structure */
@@ -3503,7 +3503,7 @@ static int ucc_geth_startup(ucc_geth_pri
}
ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
ug_info->largestexternallookupkeysize;
- size = sizeof(ucc_geth_thread_rx_pram_t);
+ size = sizeof(struct ucc_geth_thread_rx_pram);
if (ug_info->rxExtendedFiltering) {
size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
if (ug_info->largestexternallookupkeysize ==
@@ -3534,7 +3534,7 @@ static int ucc_geth_startup(ucc_geth_pri
fill_init_enet_entries(ugeth,
&(ugeth->p_init_enet_param_shadow->
txthread[0]), numThreadsTxNumerical,
- sizeof(ucc_geth_thread_tx_pram_t),
+ sizeof(struct ucc_geth_thread_tx_pram),
UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
ug_info->riscTx, 0)) != 0) {
ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
@@ -3554,7 +3554,7 @@ static int ucc_geth_startup(ucc_geth_pri
}
/* Allocate InitEnet command parameter structure */
- init_enet_pram_offset = qe_muram_alloc(sizeof(ucc_geth_init_pram_t), 4);
+ init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
if (IS_MURAM_ERR(init_enet_pram_offset)) {
ugeth_err
("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
@@ -3563,7 +3563,7 @@ static int ucc_geth_startup(ucc_geth_pri
return -ENOMEM;
}
p_init_enet_pram =
- (ucc_geth_init_pram_t *) qe_muram_addr(init_enet_pram_offset);
+ (struct ucc_geth_init_pram *) qe_muram_addr(init_enet_pram_offset);
/* Copy shadow InitEnet command parameter structure into PRAM */
p_init_enet_pram->resinit1 = ugeth->p_init_enet_param_shadow->resinit1;
@@ -3600,7 +3600,7 @@ static int ucc_geth_startup(ucc_geth_pri
/* returns a net_device_stats structure pointer */
static struct net_device_stats *ucc_geth_get_stats(struct net_device *dev)
{
- ucc_geth_private_t *ugeth = netdev_priv(dev);
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
return &(ugeth->stats);
}
@@ -3611,7 +3611,7 @@ static struct net_device_stats *ucc_geth
* starting over will fix the problem. */
static void ucc_geth_timeout(struct net_device *dev)
{
- ucc_geth_private_t *ugeth = netdev_priv(dev);
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
ugeth_vdbg("%s: IN", __FUNCTION__);
@@ -3631,7 +3631,7 @@ static void ucc_geth_timeout(struct net_
/* It is pointed to by the dev->hard_start_xmit function pointer */
static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
{
- ucc_geth_private_t *ugeth = netdev_priv(dev);
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
u8 *bd; /* BD pointer */
u32 bd_status;
u8 txQ = 0;
@@ -3692,7 +3692,7 @@ static int ucc_geth_start_xmit(struct sk
return 0;
}
-static int ucc_geth_rx(ucc_geth_private_t *ugeth, u8 rxQ, int rx_work_limit)
+static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
{
struct sk_buff *skb;
u8 *bd;
@@ -3778,7 +3778,7 @@ #endif /* CONFIG_UGETH_NAPI */
static int ucc_geth_tx(struct net_device *dev, u8 txQ)
{
/* Start from the next BD that should be filled */
- ucc_geth_private_t *ugeth = netdev_priv(dev);
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
u8 *bd; /* BD pointer */
u32 bd_status;
@@ -3820,7 +3820,7 @@ static int ucc_geth_tx(struct net_device
#ifdef CONFIG_UGETH_NAPI
static int ucc_geth_poll(struct net_device *dev, int *budget)
{
- ucc_geth_private_t *ugeth = netdev_priv(dev);
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
int howmany;
int rx_work_limit = *budget;
u8 rxQ = 0;
@@ -3845,9 +3845,9 @@ static irqreturn_t ucc_geth_irq_handler(
struct pt_regs *regs)
{
struct net_device *dev = (struct net_device *)info;
- ucc_geth_private_t *ugeth = netdev_priv(dev);
- ucc_fast_private_t *uccf;
- ucc_geth_info_t *ug_info;
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
+ struct ucc_fast_private *uccf;
+ struct ucc_geth_info *ug_info;
register u32 ucce = 0;
register u32 bit_mask = UCCE_RXBF_SINGLE_MASK;
register u32 tx_mask = UCCE_TXBF_SINGLE_MASK;
@@ -3910,7 +3910,7 @@ static irqreturn_t ucc_geth_irq_handler(
static irqreturn_t phy_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
struct net_device *dev = (struct net_device *)dev_id;
- ucc_geth_private_t *ugeth = netdev_priv(dev);
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
ugeth_vdbg("%s: IN", __FUNCTION__);
@@ -3930,8 +3930,8 @@ static irqreturn_t phy_interrupt(int irq
static void ugeth_phy_change(void *data)
{
struct net_device *dev = (struct net_device *)data;
- ucc_geth_private_t *ugeth = netdev_priv(dev);
- ucc_geth_t *ug_regs;
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
+ struct ucc_geth *ug_regs;
int result = 0;
ugeth_vdbg("%s: IN", __FUNCTION__);
@@ -3961,7 +3961,7 @@ static void ugeth_phy_change(void *data)
static void ugeth_phy_timer(unsigned long data)
{
struct net_device *dev = (struct net_device *)data;
- ucc_geth_private_t *ugeth = netdev_priv(dev);
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
schedule_work(&ugeth->tq);
@@ -3977,7 +3977,7 @@ static void ugeth_phy_timer(unsigned lon
static void ugeth_phy_startup_timer(unsigned long data)
{
struct ugeth_mii_info *mii_info = (struct ugeth_mii_info *)data;
- ucc_geth_private_t *ugeth = netdev_priv(mii_info->dev);
+ struct ucc_geth_private *ugeth = netdev_priv(mii_info->dev);
static int secondary = UGETH_AN_TIMEOUT;
int result;
@@ -4032,7 +4032,7 @@ static void ugeth_phy_startup_timer(unsi
/* Returns 0 for success. */
static int ucc_geth_open(struct net_device *dev)
{
- ucc_geth_private_t *ugeth = netdev_priv(dev);
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
int err;
ugeth_vdbg("%s: IN", __FUNCTION__);
@@ -4109,7 +4109,7 @@ #endif /* CONFIG_UGETH_NAPI */
/* Stops the kernel queue, and halts the controller */
static int ucc_geth_close(struct net_device *dev)
{
- ucc_geth_private_t *ugeth = netdev_priv(dev);
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
ugeth_vdbg("%s: IN", __FUNCTION__);
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h
index 005965f..a665612 100644
--- a/drivers/net/ucc_geth.h
+++ b/drivers/net/ucc_geth.h
@@ -36,24 +36,24 @@ #define NUM_OF_PADDRS
#define ENET_INIT_PARAM_MAX_ENTRIES_RX 9
#define ENET_INIT_PARAM_MAX_ENTRIES_TX 8
-typedef struct ucc_mii_mng {
+struct ucc_mii_mng {
u32 miimcfg; /* MII management configuration reg */
u32 miimcom; /* MII management command reg */
u32 miimadd; /* MII management address reg */
u32 miimcon; /* MII management control reg */
u32 miimstat; /* MII management status reg */
u32 miimind; /* MII management indication reg */
-} __attribute__ ((packed)) ucc_mii_mng_t;
+} __attribute__ ((packed));
-typedef struct ucc_geth {
- ucc_fast_t uccf;
+struct ucc_geth {
+ struct ucc_fast uccf;
u32 maccfg1; /* mac configuration reg. 1 */
u32 maccfg2; /* mac configuration reg. 2 */
u32 ipgifg; /* interframe gap reg. */
u32 hafdup; /* half-duplex reg. */
u8 res1[0x10];
- ucc_mii_mng_t miimng; /* MII management structure */
+ struct ucc_mii_mng miimng; /* MII management structure */
u32 ifctl; /* interface control reg */
u32 ifstat; /* interface statux reg */
u32 macstnaddr1; /* mac station address part 1 reg */
@@ -111,7 +111,7 @@ typedef struct ucc_geth {
u32 scar; /* Statistics carry register */
u32 scam; /* Statistics caryy mask register */
u8 res5[0x200 - 0x1c4];
-} __attribute__ ((packed)) ucc_geth_t;
+} __attribute__ ((packed));
/* UCC GETH TEMODR Register */
#define TEMODER_TX_RMON_STATISTICS_ENABLE 0x0100 /* enable Tx statistics
@@ -508,39 +508,39 @@ #define UESCR_SCOV_SHIFT
/* UCC GETH UDSR (Data Synchronization Register) */
#define UDSR_MAGIC 0x067E
-typedef struct ucc_geth_thread_data_tx {
+struct ucc_geth_thread_data_tx {
u8 res0[104];
-} __attribute__ ((packed)) ucc_geth_thread_data_tx_t;
+} __attribute__ ((packed));
-typedef struct ucc_geth_thread_data_rx {
+struct ucc_geth_thread_data_rx {
u8 res0[40];
-} __attribute__ ((packed)) ucc_geth_thread_data_rx_t;
+} __attribute__ ((packed));
/* Send Queue Queue-Descriptor */
-typedef struct ucc_geth_send_queue_qd {
+struct ucc_geth_send_queue_qd {
u32 bd_ring_base; /* pointer to BD ring base address */
u8 res0[0x8];
u32 last_bd_completed_address;/* initialize to last entry in BD ring */
u8 res1[0x30];
-} __attribute__ ((packed)) ucc_geth_send_queue_qd_t;
+} __attribute__ ((packed));
-typedef struct ucc_geth_send_queue_mem_region {
- ucc_geth_send_queue_qd_t sqqd[NUM_TX_QUEUES];
-} __attribute__ ((packed)) ucc_geth_send_queue_mem_region_t;
+struct ucc_geth_send_queue_mem_region {
+ struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
+} __attribute__ ((packed));
-typedef struct ucc_geth_thread_tx_pram {
+struct ucc_geth_thread_tx_pram {
u8 res0[64];
-} __attribute__ ((packed)) ucc_geth_thread_tx_pram_t;
+} __attribute__ ((packed));
-typedef struct ucc_geth_thread_rx_pram {
+struct ucc_geth_thread_rx_pram {
u8 res0[128];
-} __attribute__ ((packed)) ucc_geth_thread_rx_pram_t;
+} __attribute__ ((packed));
#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING 64
#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8 64
#define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16 96
-typedef struct ucc_geth_scheduler {
+struct ucc_geth_scheduler {
u16 cpucount0; /* CPU packet counter */
u16 cpucount1; /* CPU packet counter */
u16 cecount0; /* QE packet counter */
@@ -574,9 +574,9 @@ typedef struct ucc_geth_scheduler {
/**< weight factor for queues */
u32 minw; /* temporary variable handled by QE */
u8 res1[0x70 - 0x64];
-} __attribute__ ((packed)) ucc_geth_scheduler_t;
+} __attribute__ ((packed));
-typedef struct ucc_geth_tx_firmware_statistics_pram {
+struct ucc_geth_tx_firmware_statistics_pram {
u32 sicoltx; /* single collision */
u32 mulcoltx; /* multiple collision */
u32 latecoltxfr; /* late collision */
@@ -596,9 +596,9 @@ typedef struct ucc_geth_tx_firmware_stat
and 1518 octets */
u32 txpktsjumbo; /* total packets (including bad) between 1024
and MAXLength octets */
-} __attribute__ ((packed)) ucc_geth_tx_firmware_statistics_pram_t;
+} __attribute__ ((packed));
-typedef struct ucc_geth_rx_firmware_statistics_pram {
+struct ucc_geth_rx_firmware_statistics_pram {
u32 frrxfcser; /* frames with crc error */
u32 fraligner; /* frames with alignment error */
u32 inrangelenrxer; /* in range length error */
@@ -630,33 +630,33 @@ typedef struct ucc_geth_rx_firmware_stat
replaced */
u32 insertvlan; /* total frames that had their VLAN tag
inserted */
-} __attribute__ ((packed)) ucc_geth_rx_firmware_statistics_pram_t;
+} __attribute__ ((packed));
-typedef struct ucc_geth_rx_interrupt_coalescing_entry {
+struct ucc_geth_rx_interrupt_coalescing_entry {
u32 interruptcoalescingmaxvalue; /* interrupt coalescing max
value */
u32 interruptcoalescingcounter; /* interrupt coalescing counter,
initialize to
interruptcoalescingmaxvalue */
-} __attribute__ ((packed)) ucc_geth_rx_interrupt_coalescing_entry_t;
+} __attribute__ ((packed));
-typedef struct ucc_geth_rx_interrupt_coalescing_table {
- ucc_geth_rx_interrupt_coalescing_entry_t coalescingentry[NUM_RX_QUEUES];
+struct ucc_geth_rx_interrupt_coalescing_table {
+ struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];
/**< interrupt coalescing entry */
-} __attribute__ ((packed)) ucc_geth_rx_interrupt_coalescing_table_t;
+} __attribute__ ((packed));
-typedef struct ucc_geth_rx_prefetched_bds {
- qe_bd_t bd[NUM_BDS_IN_PREFETCHED_BDS]; /* prefetched bd */
-} __attribute__ ((packed)) ucc_geth_rx_prefetched_bds_t;
+struct ucc_geth_rx_prefetched_bds {
+ struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS]; /* prefetched bd */
+} __attribute__ ((packed));
-typedef struct ucc_geth_rx_bd_queues_entry {
+struct ucc_geth_rx_bd_queues_entry {
u32 bdbaseptr; /* BD base pointer */
u32 bdptr; /* BD pointer */
u32 externalbdbaseptr; /* external BD base pointer */
u32 externalbdptr; /* external BD pointer */
-} __attribute__ ((packed)) ucc_geth_rx_bd_queues_entry_t;
+} __attribute__ ((packed));
-typedef struct ucc_geth_tx_global_pram {
+struct ucc_geth_tx_global_pram {
u16 temoder;
u8 res0[0x38 - 0x02];
u32 sqptr; /* a base pointer to send queue memory region */
@@ -670,15 +670,15 @@ typedef struct ucc_geth_tx_global_pram {
u32 tqptr; /* a base pointer to the Tx Queues Memory
Region */
u8 res2[0x80 - 0x74];
-} __attribute__ ((packed)) ucc_geth_tx_global_pram_t;
+} __attribute__ ((packed));
/* structure representing Extended Filtering Global Parameters in PRAM */
-typedef struct ucc_geth_exf_global_pram {
+struct ucc_geth_exf_global_pram {
u32 l2pcdptr; /* individual address filter, high */
u8 res0[0x10 - 0x04];
-} __attribute__ ((packed)) ucc_geth_exf_global_pram_t;
+} __attribute__ ((packed));
-typedef struct ucc_geth_rx_global_pram {
+struct ucc_geth_rx_global_pram {
u32 remoder; /* ethernet mode reg. */
u32 rqptr; /* base pointer to the Rx Queues Memory Region*/
u32 res0[0x1];
@@ -710,12 +710,12 @@ typedef struct ucc_geth_rx_global_pram {
u32 exfGlobalParam; /* base address for extended filtering global
parameters */
u8 res6[0x100 - 0xC4]; /* Initialize to zero */
-} __attribute__ ((packed)) ucc_geth_rx_global_pram_t;
+} __attribute__ ((packed));
#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
/* structure representing InitEnet command */
-typedef struct ucc_geth_init_pram {
+struct ucc_geth_init_pram {
u8 resinit1;
u8 resinit2;
u8 resinit3;
@@ -729,7 +729,7 @@ typedef struct ucc_geth_init_pram {
u32 txglobal; /* tx global */
u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX]; /* tx threads */
u8 res3[0x1];
-} __attribute__ ((packed)) ucc_geth_init_pram_t;
+} __attribute__ ((packed));
#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
@@ -746,27 +746,27 @@ #define ENET_INIT_PARAM_MAGIC_RES_INIT4
#define ENET_INIT_PARAM_MAGIC_RES_INIT5 0x0400
/* structure representing 82xx Address Filtering Enet Address in PRAM */
-typedef struct ucc_geth_82xx_enet_address {
+struct ucc_geth_82xx_enet_address {
u8 res1[0x2];
u16 h; /* address (MSB) */
u16 m; /* address */
u16 l; /* address (LSB) */
-} __attribute__ ((packed)) ucc_geth_82xx_enet_address_t;
+} __attribute__ ((packed));
/* structure representing 82xx Address Filtering PRAM */
-typedef struct ucc_geth_82xx_address_filtering_pram {
+struct ucc_geth_82xx_address_filtering_pram {
u32 iaddr_h; /* individual address filter, high */
u32 iaddr_l; /* individual address filter, low */
u32 gaddr_h; /* group address filter, high */
u32 gaddr_l; /* group address filter, low */
- ucc_geth_82xx_enet_address_t taddr;
- ucc_geth_82xx_enet_address_t paddr[NUM_OF_PADDRS];
+ struct ucc_geth_82xx_enet_address taddr;
+ struct ucc_geth_82xx_enet_address paddr[NUM_OF_PADDRS];
u8 res0[0x40 - 0x38];
-} __attribute__ ((packed)) ucc_geth_82xx_address_filtering_pram_t;
+} __attribute__ ((packed));
/* GETH Tx firmware statistics structure, used when calling
UCC_GETH_GetStatistics. */
-typedef struct ucc_geth_tx_firmware_statistics {
+struct ucc_geth_tx_firmware_statistics {
u32 sicoltx; /* single collision */
u32 mulcoltx; /* multiple collision */
u32 latecoltxfr; /* late collision */
@@ -786,11 +786,11 @@ typedef struct ucc_geth_tx_firmware_stat
and 1518 octets */
u32 txpktsjumbo; /* total packets (including bad) between 1024
and MAXLength octets */
-} __attribute__ ((packed)) ucc_geth_tx_firmware_statistics_t;
+} __attribute__ ((packed));
/* GETH Rx firmware statistics structure, used when calling
UCC_GETH_GetStatistics. */
-typedef struct ucc_geth_rx_firmware_statistics {
+struct ucc_geth_rx_firmware_statistics {
u32 frrxfcser; /* frames with crc error */
u32 fraligner; /* frames with alignment error */
u32 inrangelenrxer; /* in range length error */
@@ -822,11 +822,11 @@ typedef struct ucc_geth_rx_firmware_stat
replaced */
u32 insertvlan; /* total frames that had their VLAN tag
inserted */
-} __attribute__ ((packed)) ucc_geth_rx_firmware_statistics_t;
+} __attribute__ ((packed));
/* GETH hardware statistics structure, used when calling
UCC_GETH_GetStatistics. */
-typedef struct ucc_geth_hardware_statistics {
+struct ucc_geth_hardware_statistics {
u32 tx64; /* Total number of frames (including bad
frames) transmitted that were exactly of the
minimal length (64 for un tagged, 68 for
@@ -871,7 +871,7 @@ typedef struct ucc_geth_hardware_statist
u32 rbca; /* Total number of frames received succesfully
that had destination address equal to the
broadcast address */
-} __attribute__ ((packed)) ucc_geth_hardware_statistics_t;
+} __attribute__ ((packed));
/* UCC GETH Tx errors returned via TxConf callback */
#define TX_ERRORS_DEF 0x0200
@@ -1013,21 +1013,21 @@ #define UCC_GETH_MIIMCFG_MNGMNT_CLC_DIV_
(MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_112)
/* Ethernet speed */
-typedef enum enet_speed {
+enum enet_speed {
ENET_SPEED_10BT, /* 10 Base T */
ENET_SPEED_100BT, /* 100 Base T */
ENET_SPEED_1000BT /* 1000 Base T */
-} enet_speed_e;
+};
/* Ethernet Address Type. */
-typedef enum enet_addr_type {
+enum enet_addr_type {
ENET_ADDR_TYPE_INDIVIDUAL,
ENET_ADDR_TYPE_GROUP,
ENET_ADDR_TYPE_BROADCAST
-} enet_addr_type_e;
+};
/* TBI / MII Set Register */
-typedef enum enet_tbi_mii_reg {
+enum enet_tbi_mii_reg {
ENET_TBI_MII_CR = 0x00, /* Control (CR ) */
ENET_TBI_MII_SR = 0x01, /* Status (SR ) */
ENET_TBI_MII_ANA = 0x04, /* AN advertisement (ANA ) */
@@ -1040,10 +1040,10 @@ typedef enum enet_tbi_mii_reg {
ENET_TBI_MII_EXST = 0x0F, /* Extended status (EXST ) */
ENET_TBI_MII_JD = 0x10, /* Jitter diagnostics (JD ) */
ENET_TBI_MII_TBICON = 0x11 /* TBI control (TBICON ) */
-} enet_tbi_mii_reg_e;
+};
/* UCC GETH 82xx Ethernet Address Recognition Location */
-typedef enum ucc_geth_enet_address_recognition_location {
+enum ucc_geth_enet_address_recognition_location {
UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station
address */
UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional
@@ -1065,10 +1065,10 @@ typedef enum ucc_geth_enet_address_recog
UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH, /* group hash */
UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual
hash */
-} ucc_geth_enet_address_recognition_location_e;
+};
/* UCC GETH vlan operation tagged */
-typedef enum ucc_geth_vlan_operation_tagged {
+enum ucc_geth_vlan_operation_tagged {
UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0, /* Tagged - nop */
UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
= 0x1, /* Tagged - replace vid portion of q tag */
@@ -1076,18 +1076,18 @@ typedef enum ucc_geth_vlan_operation_tag
= 0x2, /* Tagged - if vid0 replace vid with default value */
UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
= 0x3 /* Tagged - extract q tag from frame */
-} ucc_geth_vlan_operation_tagged_e;
+};
/* UCC GETH vlan operation non-tagged */
-typedef enum ucc_geth_vlan_operation_non_tagged {
+enum ucc_geth_vlan_operation_non_tagged {
UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0, /* Non tagged - nop */
UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1 /* Non tagged -
q tag insert
*/
-} ucc_geth_vlan_operation_non_tagged_e;
+};
/* UCC GETH Rx Quality of Service Mode */
-typedef enum ucc_geth_qos_mode {
+enum ucc_geth_qos_mode {
UCC_GETH_QOS_MODE_DEFAULT = 0x0, /* default queue */
UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1, /* queue
determined
@@ -1097,11 +1097,11 @@ typedef enum ucc_geth_qos_mode {
determined
by L3
criteria */
-} ucc_geth_qos_mode_e;
+};
/* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
for combined functionality */
-typedef enum ucc_geth_statistics_gathering_mode {
+enum ucc_geth_statistics_gathering_mode {
UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000, /* No
statistics
gathering */
@@ -1122,10 +1122,10 @@ typedef enum ucc_geth_statistics_gatheri
statistics
gathering
*/
-} ucc_geth_statistics_gathering_mode_e;
+};
/* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */
-typedef enum ucc_geth_maccfg2_pad_and_crc_mode {
+enum ucc_geth_maccfg2_pad_and_crc_mode {
UCC_GETH_PAD_AND_CRC_MODE_NONE
= MACCFG2_PAD_AND_CRC_MODE_NONE, /* Neither Padding
short frames
@@ -1135,61 +1135,59 @@ typedef enum ucc_geth_maccfg2_pad_and_cr
CRC only */
UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =
MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
-} ucc_geth_maccfg2_pad_and_crc_mode_e;
+};
/* UCC GETH upsmr Flow Control Mode */
-typedef enum ucc_geth_flow_control_mode {
+enum ucc_geth_flow_control_mode {
UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000, /* No automatic
flow control
*/
UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
= 0x00004000 /* Send pause frame when RxFIFO reaches its
emergency threshold */
-} ucc_geth_flow_control_mode_e;
+};
/* UCC GETH number of threads */
-typedef enum ucc_geth_num_of_threads {
+enum ucc_geth_num_of_threads {
UCC_GETH_NUM_OF_THREADS_1 = 0x1, /* 1 */
UCC_GETH_NUM_OF_THREADS_2 = 0x2, /* 2 */
UCC_GETH_NUM_OF_THREADS_4 = 0x0, /* 4 */
UCC_GETH_NUM_OF_THREADS_6 = 0x3, /* 6 */
UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */
-} ucc_geth_num_of_threads_e;
+};
/* UCC GETH number of station addresses */
-typedef enum ucc_geth_num_of_station_addresses {
+enum ucc_geth_num_of_station_addresses {
UCC_GETH_NUM_OF_STATION_ADDRESSES_1, /* 1 */
UCC_GETH_NUM_OF_STATION_ADDRESSES_5 /* 5 */
-} ucc_geth_num_of_station_addresses_e;
-
-typedef u8 enet_addr_t[ENET_NUM_OCTETS_PER_ADDRESS];
+};
/* UCC GETH 82xx Ethernet Address Container */
-typedef struct enet_addr_container {
- enet_addr_t address; /* ethernet address */
- ucc_geth_enet_address_recognition_location_e location; /* location in
+struct enet_addr_container {
+ u8 address[ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */
+ enum ucc_geth_enet_address_recognition_location location; /* location in
82xx address
recognition
hardware */
struct list_head node;
-} enet_addr_container_t;
+};
-#define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, enet_addr_container_t, node)
+#define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)
/* UCC GETH Termination Action Descriptor (TAD) structure. */
-typedef struct ucc_geth_tad_params {
+struct ucc_geth_tad_params {
int rx_non_dynamic_extended_features_mode;
int reject_frame;
- ucc_geth_vlan_operation_tagged_e vtag_op;
- ucc_geth_vlan_operation_non_tagged_e vnontag_op;
- ucc_geth_qos_mode_e rqos;
+ enum ucc_geth_vlan_operation_tagged vtag_op;
+ enum ucc_geth_vlan_operation_non_tagged vnontag_op;
+ enum ucc_geth_qos_mode rqos;
u8 vpri;
u16 vid;
-} ucc_geth_tad_params_t;
+};
/* GETH protocol initialization structure */
-typedef struct ucc_geth_info {
- ucc_fast_info_t uf_info;
+struct ucc_geth_info {
+ struct ucc_fast_info uf_info;
u8 numQueuesTx;
u8 numQueuesRx;
int ipCheckSumCheck;
@@ -1251,51 +1249,51 @@ typedef struct ucc_geth_info {
u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
u16 bdRingLenTx[NUM_TX_QUEUES];
u16 bdRingLenRx[NUM_RX_QUEUES];
- enet_interface_e enet_interface;
- ucc_geth_num_of_station_addresses_e numStationAddresses;
- qe_fltr_largest_external_tbl_lookup_key_size_e
+ enum enet_interface enet_interface;
+ enum ucc_geth_num_of_station_addresses numStationAddresses;
+ enum qe_fltr_largest_external_tbl_lookup_key_size
largestexternallookupkeysize;
- ucc_geth_statistics_gathering_mode_e statisticsMode;
- ucc_geth_vlan_operation_tagged_e vlanOperationTagged;
- ucc_geth_vlan_operation_non_tagged_e vlanOperationNonTagged;
- ucc_geth_qos_mode_e rxQoSMode;
- ucc_geth_flow_control_mode_e aufc;
- ucc_geth_maccfg2_pad_and_crc_mode_e padAndCrc;
- ucc_geth_num_of_threads_e numThreadsTx;
- ucc_geth_num_of_threads_e numThreadsRx;
- qe_risc_allocation_e riscTx;
- qe_risc_allocation_e riscRx;
-} ucc_geth_info_t;
+ enum ucc_geth_statistics_gathering_mode statisticsMode;
+ enum ucc_geth_vlan_operation_tagged vlanOperationTagged;
+ enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;
+ enum ucc_geth_qos_mode rxQoSMode;
+ enum ucc_geth_flow_control_mode aufc;
+ enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
+ enum ucc_geth_num_of_threads numThreadsTx;
+ enum ucc_geth_num_of_threads numThreadsRx;
+ enum qe_risc_allocation riscTx;
+ enum qe_risc_allocation riscRx;
+};
/* structure representing UCC GETH */
-typedef struct ucc_geth_private {
- ucc_geth_info_t *ug_info;
- ucc_fast_private_t *uccf;
+struct ucc_geth_private {
+ struct ucc_geth_info *ug_info;
+ struct ucc_fast_private *uccf;
struct net_device *dev;
struct net_device_stats stats; /* linux network statistics */
- ucc_geth_t *ug_regs;
- ucc_geth_init_pram_t *p_init_enet_param_shadow;
- ucc_geth_exf_global_pram_t *p_exf_glbl_param;
+ struct ucc_geth *ug_regs;
+ struct ucc_geth_init_pram *p_init_enet_param_shadow;
+ struct ucc_geth_exf_global_pram *p_exf_glbl_param;
u32 exf_glbl_param_offset;
- ucc_geth_rx_global_pram_t *p_rx_glbl_pram;
+ struct ucc_geth_rx_global_pram *p_rx_glbl_pram;
u32 rx_glbl_pram_offset;
- ucc_geth_tx_global_pram_t *p_tx_glbl_pram;
+ struct ucc_geth_tx_global_pram *p_tx_glbl_pram;
u32 tx_glbl_pram_offset;
- ucc_geth_send_queue_mem_region_t *p_send_q_mem_reg;
+ struct ucc_geth_send_queue_mem_region *p_send_q_mem_reg;
u32 send_q_mem_reg_offset;
- ucc_geth_thread_data_tx_t *p_thread_data_tx;
+ struct ucc_geth_thread_data_tx *p_thread_data_tx;
u32 thread_dat_tx_offset;
- ucc_geth_thread_data_rx_t *p_thread_data_rx;
+ struct ucc_geth_thread_data_rx *p_thread_data_rx;
u32 thread_dat_rx_offset;
- ucc_geth_scheduler_t *p_scheduler;
+ struct ucc_geth_scheduler *p_scheduler;
u32 scheduler_offset;
- ucc_geth_tx_firmware_statistics_pram_t *p_tx_fw_statistics_pram;
+ struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
u32 tx_fw_statistics_pram_offset;
- ucc_geth_rx_firmware_statistics_pram_t *p_rx_fw_statistics_pram;
+ struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
u32 rx_fw_statistics_pram_offset;
- ucc_geth_rx_interrupt_coalescing_table_t *p_rx_irq_coalescing_tbl;
+ struct ucc_geth_rx_interrupt_coalescing_table *p_rx_irq_coalescing_tbl;
u32 rx_irq_coalescing_tbl_offset;
- ucc_geth_rx_bd_queues_entry_t *p_rx_bd_qs_tbl;
+ struct ucc_geth_rx_bd_queues_entry *p_rx_bd_qs_tbl;
u32 rx_bd_qs_tbl_offset;
u8 *p_tx_bd_ring[NUM_TX_QUEUES];
u32 tx_bd_ring_offset[NUM_TX_QUEUES];
@@ -1308,7 +1306,7 @@ typedef struct ucc_geth_private {
u16 cpucount[NUM_TX_QUEUES];
volatile u16 *p_cpucount[NUM_TX_QUEUES];
int indAddrRegUsed[NUM_OF_PADDRS];
- enet_addr_t paddr[NUM_OF_PADDRS];
+ u8 paddr[NUM_OF_PADDRS][ENET_NUM_OCTETS_PER_ADDRESS]; /* ethernet address */
u8 numGroupAddrInHash;
u8 numIndAddrInHash;
u8 numIndAddrInReg;
@@ -1334,6 +1332,6 @@ typedef struct ucc_geth_private {
int oldspeed;
int oldduplex;
int oldlink;
-} ucc_geth_private_t;
+};
#endif /* __UCC_GETH_H__ */
diff --git a/drivers/net/ucc_geth_phy.c b/drivers/net/ucc_geth_phy.c
index cc4fffb..2b5d74e 100644
--- a/drivers/net/ucc_geth_phy.c
+++ b/drivers/net/ucc_geth_phy.c
@@ -80,9 +80,9 @@ static u8 *bcsr_regs = NULL;
/* configuration has to be done through the TSEC1 MIIM regs */
void write_phy_reg(struct net_device *dev, int mii_id, int regnum, int value)
{
- ucc_geth_private_t *ugeth = netdev_priv(dev);
- ucc_mii_mng_t *mii_regs;
- enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
+ struct ucc_mii_mng *mii_regs;
+ enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg) regnum;
u32 tmp_reg;
ugphy_vdbg("%s: IN", __FUNCTION__);
@@ -117,9 +117,9 @@ void write_phy_reg(struct net_device *de
/* configuration has to be done through the TSEC1 MIIM regs */
int read_phy_reg(struct net_device *dev, int mii_id, int regnum)
{
- ucc_geth_private_t *ugeth = netdev_priv(dev);
- ucc_mii_mng_t *mii_regs;
- enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
+ struct ucc_geth_private *ugeth = netdev_priv(dev);
+ struct ucc_mii_mng *mii_regs;
+ enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg) regnum;
u32 tmp_reg;
u16 value;
diff --git a/drivers/net/ucc_geth_phy.h b/drivers/net/ucc_geth_phy.h
index 2f98b8f..f574078 100644
--- a/drivers/net/ucc_geth_phy.h
+++ b/drivers/net/ucc_geth_phy.h
@@ -126,7 +126,7 @@ struct ugeth_mii_info {
/* And management functions */
struct phy_info *phyinfo;
- ucc_mii_mng_t *mii_regs;
+ struct ucc_mii_mng *mii_regs;
/* forced speed & duplex (no autoneg)
* partner speed & duplex & pause (autoneg)
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index a16d82f..8a684ca 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -122,7 +122,7 @@ struct fsl_spi_platform_data {
/* Ethernet interface (phy management and speed)
*/
-typedef enum enet_interface {
+enum enet_interface {
ENET_10_MII, /* 10 Base T, MII interface */
ENET_10_RMII, /* 10 Base T, RMII interface */
ENET_10_RGMII, /* 10 Base T, RGMII interface */
@@ -133,7 +133,7 @@ typedef enum enet_interface {
ENET_1000_RGMII, /* 1000 Base T, RGMII interface */
ENET_1000_TBI, /* 1000 Base T, TBI interface */
ENET_1000_RTBI /* 1000 Base T, RTBI interface */
-} enet_interface_e;
+};
struct ucc_geth_platform_data {
/* device specific information */
@@ -145,7 +145,7 @@ struct ucc_geth_platform_data {
u8 rx_clock;
u8 tx_clock;
u32 phy_id;
- enet_interface_e phy_interface;
+ enum enet_interface phy_interface;
u32 phy_interrupt;
u8 mac_addr[6];
};
--
1.4.2.1
^ permalink raw reply related
* [PATCH 15/15] uint to u32 conversion
From: Kim Phillips @ 2006-09-30 23:36 UTC (permalink / raw)
To: linuxppc-dev
Convert some uint types to u32 types
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/sysdev/qe_lib/qe_common.c | 22 +++++++++++-----------
include/asm-powerpc/immap_qe.h | 14 +++++++-------
include/asm-powerpc/qe.h | 16 ++++++++--------
include/asm-powerpc/ucc_slow.h | 6 +++---
4 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/qe_common.c b/arch/powerpc/sysdev/qe_lib/qe_common.c
index 3780eae..fe6527a 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_common.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_common.c
@@ -100,7 +100,7 @@ void qe_reset(void)
}
EXPORT_SYMBOL(qe_issue_cmd);
-int qe_issue_cmd(uint cmd, uint device, u8 mcn_protocol, u32 cmd_input)
+int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
{
unsigned long flags;
u32 cecr;
@@ -172,13 +172,13 @@ unsigned int get_brg_clk(void)
/* This function is used by UARTS, or anything else that uses a 16x
* oversampled clock.
*/
-void qe_setbrg(uint brg, uint rate)
+void qe_setbrg(u32 brg, u32 rate)
{
- volatile uint *bp;
+ volatile u32 *bp;
u32 divisor;
int div16 = 0;
- bp = (uint *) & qe_immr->brg.brgc1;
+ bp = (u32 *) & qe_immr->brg.brgc1;
bp += brg;
divisor = (get_brg_clk() / rate);
@@ -271,7 +271,7 @@ EXPORT_SYMBOL(qe_put_snum);
static int qe_sdma_init(void)
{
struct sdma *sdma = &qe_immr->sdma;
- uint sdma_buf_offset;
+ u32 sdma_buf_offset;
if (!sdma)
return -ENODEV;
@@ -325,7 +325,7 @@ static void qe_muram_init(void)
/* This function returns an index into the MURAM area.
*/
-uint qe_muram_alloc(uint size, uint align)
+u32 qe_muram_alloc(u32 size, u32 align)
{
void *start;
unsigned long flags;
@@ -334,12 +334,12 @@ uint qe_muram_alloc(uint size, uint alig
start = rh_alloc_align(&qe_muram_info, size, align, "QE");
spin_unlock_irqrestore(&qe_muram_lock, flags);
- return (uint) start;
+ return (u32) start;
}
EXPORT_SYMBOL(qe_muram_alloc);
-int qe_muram_free(uint offset)
+int qe_muram_free(u32 offset)
{
int ret;
unsigned long flags;
@@ -354,7 +354,7 @@ int qe_muram_free(uint offset)
EXPORT_SYMBOL(qe_muram_free);
/* not sure if this is ever needed */
-uint qe_muram_alloc_fixed(uint offset, uint size)
+u32 qe_muram_alloc_fixed(u32 offset, u32 size)
{
void *start;
unsigned long flags;
@@ -364,7 +364,7 @@ uint qe_muram_alloc_fixed(uint offset, u
rh_alloc_fixed(&qe_muram_info, (void *)offset, size, "commproc");
spin_unlock_irqrestore(&qe_muram_lock, flags);
- return (uint) start;
+ return (u32) start;
}
EXPORT_SYMBOL(qe_muram_alloc_fixed);
@@ -376,7 +376,7 @@ void qe_muram_dump(void)
EXPORT_SYMBOL(qe_muram_dump);
-void *qe_muram_addr(uint offset)
+void *qe_muram_addr(u32 offset)
{
return (void *)&qe_immr->muram[offset];
}
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index 229ac58..118caa2 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -486,18 +486,18 @@ extern phys_addr_t get_qe_base(void);
static inline unsigned long immrbar_virt_to_phys(volatile void * address)
{
- if ( ((uint)address >= (uint)qe_immr) &&
- ((uint)address < ((uint)qe_immr + QE_IMMAP_SIZE)) )
- return (unsigned long)(address - (uint)qe_immr +
- (uint)get_qe_base());
+ if ( ((u32)address >= (u32)qe_immr) &&
+ ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
+ return (unsigned long)(address - (u32)qe_immr +
+ (u32)get_qe_base());
return (unsigned long)virt_to_phys(address);
}
static inline void * immrbar_phys_to_virt(unsigned long address)
{
- if ( (address >= (uint)get_qe_base()) &&
- (address < ((uint)get_qe_base() + QE_IMMAP_SIZE)) )
- return (void *)(address - (uint)get_qe_base() + (uint)qe_immr);
+ if ( (address >= (u32)get_qe_base()) &&
+ (address < ((u32)get_qe_base() + QE_IMMAP_SIZE)) )
+ return (void *)(address - (u32)get_qe_base() + (u32)qe_immr);
return (void *)phys_to_virt(address);
}
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index 2e43e45..2f18ff9 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -19,9 +19,9 @@ #define __QE_H__
#include <asm/immap_qe.h>
-static inline long IS_MURAM_ERR(const uint offset)
+static inline long IS_MURAM_ERR(const u32 offset)
{
- return (uint) offset > (uint) - 1000L;
+ return (u32) offset > (u32) - 1000L;
}
#define QE_NUM_OF_SNUM 28
@@ -40,15 +40,15 @@ extern int par_io_init(struct device_nod
extern int par_io_of_config(struct device_node *np);
/* QE internal APIs */
-int qe_issue_cmd(uint cmd, uint device, u8 mcn_protocol, u32 cmd_input);
-void qe_setbrg(uint brg, uint rate);
+int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
+void qe_setbrg(u32 brg, u32 rate);
int qe_get_snum(void);
void qe_put_snum(u8 snum);
-uint qe_muram_alloc(uint size, uint align);
-int qe_muram_free(uint offset);
-uint qe_muram_alloc_fixed(uint offset, uint size);
+u32 qe_muram_alloc(u32 size, u32 align);
+int qe_muram_free(u32 offset);
+u32 qe_muram_alloc_fixed(u32 offset, u32 size);
void qe_muram_dump(void);
-void *qe_muram_addr(uint offset);
+void *qe_muram_addr(u32 offset);
/* Buffer descriptors.
*/
struct qe_bd {
diff --git a/include/asm-powerpc/ucc_slow.h b/include/asm-powerpc/ucc_slow.h
index 4bca460..0dd96ec 100644
--- a/include/asm-powerpc/ucc_slow.h
+++ b/include/asm-powerpc/ucc_slow.h
@@ -202,7 +202,7 @@ struct ucc_slow_private {
struct ucc_slow_info *us_info;
struct ucc_slow *us_regs; /* a pointer to memory map of UCC regs. */
struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM. */
- uint us_pram_offset;
+ u32 us_pram_offset;
int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
int stopped_tx; /* Whether channel has been stopped for Tx
@@ -211,8 +211,8 @@ struct ucc_slow_private {
struct list_head confQ; /* frames passed to chip waiting for tx */
u32 first_tx_bd_mask; /* mask is used in Tx routine to save status
and length for first BD in a frame. */
- uint tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */
- uint rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */
+ u32 tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */
+ u32 rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */
u8 *confBd; /* next BD for confirm after Tx */
u8 *tx_bd; /* next BD for new Tx request */
u8 *rx_bd; /* next BD to collect after Rx */
--
1.4.2.1
^ permalink raw reply related
* [PATCH 13/15] QE: remove typedefs
From: Kim Phillips @ 2006-09-30 23:36 UTC (permalink / raw)
To: linuxppc-dev
remove typedefs from QE code
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/sysdev/qe_lib/qe_common.c | 18 ++--
arch/powerpc/sysdev/qe_lib/ucc.c | 2
arch/powerpc/sysdev/qe_lib/ucc_fast.c | 32 ++++----
arch/powerpc/sysdev/qe_lib/ucc_slow.c | 38 ++++-----
include/asm-powerpc/immap_qe.h | 136 ++++++++++++++++----------------
include/asm-powerpc/qe.h | 40 +++++----
include/asm-powerpc/ucc.h | 10 +-
include/asm-powerpc/ucc_fast.h | 76 +++++++++---------
include/asm-powerpc/ucc_slow.h | 78 +++++++++---------
9 files changed, 215 insertions(+), 215 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/qe_common.c b/arch/powerpc/sysdev/qe_lib/qe_common.c
index 5c3381f..3780eae 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_common.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_common.c
@@ -35,24 +35,24 @@ #include <asm/rheap.h>
/* QE snum state
*/
-typedef enum qe_snum_state {
+enum qe_snum_state {
QE_SNUM_STATE_USED, /* used */
QE_SNUM_STATE_FREE /* free */
-} qe_snum_state_e;
+};
/* QE snum
*/
-typedef struct qe_snum {
+struct qe_snum {
u8 num; /* snum */
- qe_snum_state_e state; /* state */
-} qe_snum_t;
+ enum qe_snum_state state; /* state */
+};
/* We allocate this here because it is used almost exclusively for
* the communication processor devices.
*/
EXPORT_SYMBOL(qe_immr);
-qe_map_t *qe_immr = NULL;
-static qe_snum_t snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
+struct qe_immap *qe_immr = NULL;
+static struct qe_snum snums[QE_NUM_OF_SNUM]; /* Dynamically allocated SNUMs */
static void qe_snums_init(void);
static void qe_muram_init(void);
@@ -85,7 +85,7 @@ EXPORT_SYMBOL(get_qe_base);
void qe_reset(void)
{
if (qe_immr == NULL)
- qe_immr = (qe_map_t *) ioremap(get_qe_base(), QE_IMMAP_SIZE);
+ qe_immr = (struct qe_immap *) ioremap(get_qe_base(), QE_IMMAP_SIZE);
qe_snums_init();
@@ -270,7 +270,7 @@ EXPORT_SYMBOL(qe_put_snum);
static int qe_sdma_init(void)
{
- sdma_t *sdma = &qe_immr->sdma;
+ struct sdma *sdma = &qe_immr->sdma;
uint sdma_buf_offset;
if (!sdma)
diff --git a/arch/powerpc/sysdev/qe_lib/ucc.c b/arch/powerpc/sysdev/qe_lib/ucc.c
index edb0acb..d19f5e2 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc.c
@@ -150,7 +150,7 @@ int ucc_mux_set_grant_tsa_bkpt(int ucc_n
return 0;
}
-int ucc_set_qe_mux_rxtx(int ucc_num, qe_clock_e clock, comm_dir_e mode)
+int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode)
{
volatile u32 *p_cmxucr;
u8 reg_num;
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_fast.c b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
index 4312083..b078d4e 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_fast.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
@@ -44,7 +44,7 @@ #else
#define uccf_vdbg(fmt, args...) do { } while (0)
#endif /* UCCF_VERBOSE_DEBUG */
-void ucc_fast_dump_regs(ucc_fast_private_t * uccf)
+void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
{
uccf_info("UCC%d Fast registers:", uccf->uf_info->ucc_num);
uccf_info("Base address: 0x%08x", (u32) uccf->uf_regs);
@@ -112,14 +112,14 @@ u32 ucc_fast_get_qe_cr_subblock(int uccf
}
}
-void ucc_fast_transmit_on_demand(ucc_fast_private_t * uccf)
+void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
{
out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
}
-void ucc_fast_enable(ucc_fast_private_t * uccf, comm_dir_e mode)
+void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
{
- ucc_fast_t *uf_regs;
+ struct ucc_fast *uf_regs;
u32 gumr;
uf_regs = uccf->uf_regs;
@@ -137,9 +137,9 @@ void ucc_fast_enable(ucc_fast_private_t
out_be32(&uf_regs->gumr, gumr);
}
-void ucc_fast_disable(ucc_fast_private_t * uccf, comm_dir_e mode)
+void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
{
- ucc_fast_t *uf_regs;
+ struct ucc_fast *uf_regs;
u32 gumr;
uf_regs = uccf->uf_regs;
@@ -157,10 +157,10 @@ void ucc_fast_disable(ucc_fast_private_t
out_be32(&uf_regs->gumr, gumr);
}
-int ucc_fast_init(ucc_fast_info_t * uf_info, ucc_fast_private_t ** uccf_ret)
+int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret)
{
- ucc_fast_private_t *uccf;
- ucc_fast_t *uf_regs;
+ struct ucc_fast_private *uccf;
+ struct ucc_fast *uf_regs;
u32 gumr = 0;
int ret;
@@ -225,20 +225,20 @@ int ucc_fast_init(ucc_fast_info_t * uf_i
}
uccf =
- (ucc_fast_private_t *) kmalloc(sizeof(ucc_fast_private_t),
+ (struct ucc_fast_private *) kmalloc(sizeof(struct ucc_fast_private),
GFP_KERNEL);
if (!uccf) {
uccf_err
("ucc_fast_init: No memory for UCC slow data structure!");
return -ENOMEM;
}
- memset(uccf, 0, sizeof(ucc_fast_private_t));
+ memset(uccf, 0, sizeof(struct ucc_fast_private));
/* Fill fast UCC structure */
uccf->uf_info = uf_info;
/* Set the PHY base address */
uccf->uf_regs =
- (ucc_fast_t *) ioremap(uf_info->regs, sizeof(ucc_fast_t));
+ (struct ucc_fast *) ioremap(uf_info->regs, sizeof(struct ucc_fast));
if (uccf->uf_regs == NULL) {
uccf_err
("ucc_fast_init: No memory map for UCC slow controller!");
@@ -259,7 +259,7 @@ #ifdef STATISTICS
#endif /* STATISTICS */
/* Init Guemr register */
- if ((ret = ucc_init_guemr((ucc_common_t *) (uf_regs)))) {
+ if ((ret = ucc_init_guemr((struct ucc_common *) (uf_regs)))) {
uccf_err("ucc_fast_init: Could not init the guemr register.");
ucc_fast_free(uccf);
return ret;
@@ -267,7 +267,7 @@ #endif /* STATISTICS */
/* Set UCC to fast type */
if ((ret = ucc_set_type(uf_info->ucc_num,
- (ucc_common_t *) (uf_regs),
+ (struct ucc_common *) (uf_regs),
UCC_SPEED_TYPE_FAST))) {
uccf_err("ucc_fast_init: Could not set type to fast.");
ucc_fast_free(uccf);
@@ -311,7 +311,7 @@ #endif /* STATISTICS */
if (IS_MURAM_ERR(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
uccf_err
("ucc_fast_init: Can not allocate MURAM memory for "
- "ucc_fast_tx_virtual_fifo_base_offset.");
+ "struct ucc_fastx_virtual_fifo_base_offset.");
uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
ucc_fast_free(uccf);
return -ENOMEM;
@@ -393,7 +393,7 @@ #endif /* STATISTICS */
return 0;
}
-void ucc_fast_free(ucc_fast_private_t * uccf)
+void ucc_fast_free(struct ucc_fast_private * uccf)
{
if (!uccf)
return;
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_slow.c b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
index a8232cd..0059de4 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_slow.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
@@ -69,14 +69,14 @@ u32 ucc_slow_get_qe_cr_subblock(int uccs
}
}
-void ucc_slow_poll_transmitter_now(ucc_slow_private_t * uccs)
+void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs)
{
out_be16(&uccs->us_regs->utodr, UCC_SLOW_TOD);
}
-void ucc_slow_graceful_stop_tx(ucc_slow_private_t * uccs)
+void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs)
{
- ucc_slow_info_t *us_info = uccs->us_info;
+ struct ucc_slow_info *us_info = uccs->us_info;
u32 id;
id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
@@ -84,27 +84,27 @@ void ucc_slow_graceful_stop_tx(ucc_slow_
0);
}
-void ucc_slow_stop_tx(ucc_slow_private_t * uccs)
+void ucc_slow_stop_tx(struct ucc_slow_private * uccs)
{
- ucc_slow_info_t *us_info = uccs->us_info;
+ struct ucc_slow_info *us_info = uccs->us_info;
u32 id;
id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
qe_issue_cmd(QE_STOP_TX, id, (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
}
-void ucc_slow_restart_tx(ucc_slow_private_t * uccs)
+void ucc_slow_restart_tx(struct ucc_slow_private * uccs)
{
- ucc_slow_info_t *us_info = uccs->us_info;
+ struct ucc_slow_info *us_info = uccs->us_info;
u32 id;
id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
qe_issue_cmd(QE_RESTART_TX, id, (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
}
-void ucc_slow_enable(ucc_slow_private_t * uccs, comm_dir_e mode)
+void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
{
- ucc_slow_t *us_regs;
+ struct ucc_slow *us_regs;
u32 gumr_l;
us_regs = uccs->us_regs;
@@ -122,9 +122,9 @@ void ucc_slow_enable(ucc_slow_private_t
out_be32(&us_regs->gumr_l, gumr_l);
}
-void ucc_slow_disable(ucc_slow_private_t * uccs, comm_dir_e mode)
+void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
{
- ucc_slow_t *us_regs;
+ struct ucc_slow *us_regs;
u32 gumr_l;
us_regs = uccs->us_regs;
@@ -142,14 +142,14 @@ void ucc_slow_disable(ucc_slow_private_t
out_be32(&us_regs->gumr_l, gumr_l);
}
-int ucc_slow_init(ucc_slow_info_t * us_info, ucc_slow_private_t ** uccs_ret)
+int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret)
{
u32 i;
- ucc_slow_t *us_regs;
+ struct ucc_slow *us_regs;
u32 gumr;
u8 function_code = 0;
u8 *bd;
- ucc_slow_private_t *uccs;
+ struct ucc_slow_private *uccs;
u32 id;
u32 command;
int ret;
@@ -176,14 +176,14 @@ int ucc_slow_init(ucc_slow_info_t * us_i
}
uccs =
- (ucc_slow_private_t *) kmalloc(sizeof(ucc_slow_private_t),
+ (struct ucc_slow_private *) kmalloc(sizeof(struct ucc_slow_private),
GFP_KERNEL);
if (!uccs) {
uccs_err
("ucc_slow_init: No memory for UCC slow data structure!");
return -ENOMEM;
}
- memset(uccs, 0, sizeof(ucc_slow_private_t));
+ memset(uccs, 0, sizeof(struct ucc_slow_private));
/* Fill slow UCC structure */
uccs->us_info = us_info;
@@ -216,7 +216,7 @@ #endif /* STATISTICS */
uccs->us_pram = qe_muram_addr(uccs->us_pram_offset);
/* Init Guemr register */
- if ((ret = ucc_init_guemr((ucc_common_t *) (us_info->us_regs)))) {
+ if ((ret = ucc_init_guemr((struct ucc_common *) (us_info->us_regs)))) {
uccs_err("ucc_slow_init: Could not init the guemr register.");
ucc_slow_free(uccs);
return ret;
@@ -224,7 +224,7 @@ #endif /* STATISTICS */
/* Set UCC to slow type */
if ((ret = ucc_set_type(us_info->ucc_num,
- (ucc_common_t *) (us_info->us_regs),
+ (struct ucc_common *) (us_info->us_regs),
UCC_SPEED_TYPE_SLOW))) {
uccs_err("ucc_slow_init: Could not init the guemr register.");
ucc_slow_free(uccs);
@@ -386,7 +386,7 @@ #endif /* STATISTICS */
return 0;
}
-void ucc_slow_free(ucc_slow_private_t * uccs)
+void ucc_slow_free(struct ucc_slow_private * uccs)
{
if (!uccs)
return;
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index 754df2d..229ac58 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -25,15 +25,15 @@ #define QE_IMMAP_SIZE (1024 * 1024) /* 1
/* QE I-RAM
*/
-typedef struct qe_iram {
+struct qe_iram {
u32 iadd; /* I-RAM Address Register */
u32 idata; /* I-RAM Data Register */
u8 res0[0x78];
-} __attribute__ ((packed)) qe_iram_t;
+} __attribute__ ((packed));
/* QE Interrupt Controller
*/
-typedef struct qe_ic_regs {
+struct qe_ic_regs {
u32 qicr;
u32 qivec;
u32 qripnr;
@@ -53,11 +53,11 @@ typedef struct qe_ic_regs {
u8 res2[0x20];
u32 qhivec;
u8 res3[0x1C];
-} __attribute__ ((packed)) qe_ic_t;
+} __attribute__ ((packed));
/* Communications Processor
*/
-typedef struct cp_qe {
+struct cp_qe {
u32 cecr; /* QE command register */
u32 ceccr; /* QE controller configuration register */
u32 cecdr; /* QE command data register */
@@ -91,11 +91,11 @@ typedef struct cp_qe {
u16 ceexm4; /* QE external request 4 mask register */
u8 res12[0x2];
u8 res13[0x280];
-} __attribute__ ((packed)) cp_qe_t;
+} __attribute__ ((packed));
/* QE Multiplexer
*/
-typedef struct qe_mux {
+struct qe_mux {
u32 cmxgcr; /* CMX general clock route register */
u32 cmxsi1cr_l; /* CMX SI1 clock route low register */
u32 cmxsi1cr_h; /* CMX SI1 clock route high register */
@@ -106,11 +106,11 @@ typedef struct qe_mux {
u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
u32 cmxupcr; /* CMX UPC clock route register */
u8 res0[0x1C];
-} __attribute__ ((packed)) qe_mux_t;
+} __attribute__ ((packed));
/* QE Timers
*/
-typedef struct qe_timers {
+struct qe_timers {
u8 gtcfr1; /* Timer 1 and Timer 2 global configuration
register */
u8 res0[0x3];
@@ -139,11 +139,11 @@ typedef struct qe_timers {
u16 gtevr4; /* Timer 4 event register */
u16 gtps; /* Timer 1 prescale register */
u8 res2[0x46];
-} __attribute__ ((packed)) qe_timers_t;
+} __attribute__ ((packed));
/* BRG
*/
-typedef struct qe_brg {
+struct qe_brg {
u32 brgc1; /* BRG1 configuration register */
u32 brgc2; /* BRG2 configuration register */
u32 brgc3; /* BRG3 configuration register */
@@ -161,11 +161,11 @@ typedef struct qe_brg {
u32 brgc15; /* BRG15 configuration register */
u32 brgc16; /* BRG16 configuration register */
u8 res0[0x40];
-} __attribute__ ((packed)) qe_brg_t;
+} __attribute__ ((packed));
/* SPI
*/
-typedef struct spi {
+struct spi {
u8 res0[0x20];
u32 spmode; /* SPI mode register */
u8 res1[0x2];
@@ -180,11 +180,11 @@ typedef struct spi {
u32 spitd; /* SPI transmit data register (cpu mode) */
u32 spird; /* SPI receive data register (cpu mode) */
u8 res7[0x8];
-} __attribute__ ((packed)) spi_t;
+} __attribute__ ((packed));
/* SI
*/
-typedef struct si1 {
+struct si1 {
u16 siamr1; /* SI1 TDMA mode register */
u16 sibmr1; /* SI1 TDMB mode register */
u16 sicmr1; /* SI1 TDMC mode register */
@@ -229,19 +229,19 @@ typedef struct si1 {
u32 siml1; /* SI1 multiframe limit register */
u8 siedm1; /* SI1 extended diagnostic mode register */
u8 res9[0xBB];
-} __attribute__ ((packed)) si1_t;
+} __attribute__ ((packed));
/* SI Routing Tables
*/
-typedef struct sir {
+struct sir {
u8 tx[0x400];
u8 rx[0x400];
u8 res0[0x800];
-} __attribute__ ((packed)) sir_t;
+} __attribute__ ((packed));
/* USB Controller.
*/
-typedef struct usb_ctlr {
+struct usb_ctlr {
u8 usb_usmod;
u8 usb_usadr;
u8 usb_uscom;
@@ -260,21 +260,21 @@ typedef struct usb_ctlr {
u8 res5[2];
u16 usb_usfrn;
u8 res6[0x22];
-} __attribute__ ((packed)) usb_t;
+} __attribute__ ((packed));
/* MCC
*/
-typedef struct mcc {
+struct mcc {
u32 mcce; /* MCC event register */
u32 mccm; /* MCC mask register */
u32 mccf; /* MCC configuration register */
u32 merl; /* MCC emergency request level register */
u8 res0[0xF0];
-} __attribute__ ((packed)) mcc_t;
+} __attribute__ ((packed));
/* QE UCC Slow
*/
-typedef struct ucc_slow {
+struct ucc_slow {
u32 gumr_l; /* UCCx general mode register (low) */
u32 gumr_h; /* UCCx general mode register (high) */
u16 upsmr; /* UCCx protocol-specific mode register */
@@ -290,11 +290,11 @@ typedef struct ucc_slow {
u16 utpt;
u8 guemr; /* UCC general extended mode register */
u8 res4[0x200 - 0x091];
-} __attribute__ ((packed)) ucc_slow_t;
+} __attribute__ ((packed));
/* QE UCC Fast
*/
-typedef struct ucc_fast {
+struct ucc_fast {
u32 gumr; /* UCCx general mode register */
u32 upsmr; /* UCCx protocol-specific mode register */
u16 utodr; /* UCCx transmit on demand register */
@@ -324,27 +324,27 @@ typedef struct ucc_fast {
u8 res8[0x4C];
u8 guemr; /* UCC general extended mode register */
u8 res9[0x100 - 0x091];
-} __attribute__ ((packed)) ucc_fast_t;
+} __attribute__ ((packed));
/* QE UCC
*/
-typedef struct ucc_common {
+struct ucc_common {
u8 res1[0x90];
u8 guemr;
u8 res2[0x200 - 0x091];
-} __attribute__ ((packed)) ucc_common_t;
+} __attribute__ ((packed));
-typedef struct ucc {
+struct ucc {
union {
- ucc_slow_t slow;
- ucc_fast_t fast;
- ucc_common_t common;
+ struct ucc_slow slow;
+ struct ucc_fast fast;
+ struct ucc_common common;
};
-} __attribute__ ((packed)) ucc_t;
+} __attribute__ ((packed));
/* MultiPHY UTOPIA POS Controllers (UPC)
*/
-typedef struct upc {
+struct upc {
u32 upgcr; /* UTOPIA/POS general configuration register */
u32 uplpa; /* UTOPIA/POS last PHY address */
u32 uphec; /* ATM HEC register */
@@ -397,11 +397,11 @@ typedef struct upc {
u32 uper3; /* Device 3 port enable register */
u32 uper4; /* Device 4 port enable register */
u8 res2[0x150];
-} __attribute__ ((packed)) upc_t;
+} __attribute__ ((packed));
/* SDMA
*/
-typedef struct sdma {
+struct sdma {
u32 sdsr; /* Serial DMA status register */
u32 sdmr; /* Serial DMA mode register */
u32 sdtr1; /* SDMA system bus threshold register */
@@ -418,11 +418,11 @@ typedef struct sdma {
u8 res1[0x4];
u32 sdebcr; /* SDMA CAM entries base register */
u8 res2[0x38];
-} __attribute__ ((packed)) sdma_t;
+} __attribute__ ((packed));
/* Debug Space
*/
-typedef struct dbg {
+struct dbg {
u32 bpdcr; /* Breakpoint debug command register */
u32 bpdsr; /* Breakpoint debug status register */
u32 bpdmr; /* Breakpoint debug mask register */
@@ -436,42 +436,42 @@ typedef struct dbg {
u32 bprmsr; /* Breakpoint request mode serial register */
u32 bpemr; /* Breakpoint exit mode register */
u8 res2[0x48];
-} __attribute__ ((packed)) dbg_t;
+} __attribute__ ((packed));
/* RISC Special Registers (Trap and Breakpoint)
*/
-typedef struct rsp {
+struct rsp {
u8 fixme[0x100];
-} __attribute__ ((packed)) rsp_t;
+} __attribute__ ((packed));
-typedef struct qe_immap {
- qe_iram_t iram; /* I-RAM */
- qe_ic_t ic; /* Interrupt Controller */
- cp_qe_t cp; /* Communications Processor */
- qe_mux_t qmx; /* QE Multiplexer */
- qe_timers_t qet; /* QE Timers */
- spi_t spi[0x2]; /* spi */
- mcc_t mcc; /* mcc */
- qe_brg_t brg; /* brg */
- usb_t usb; /* USB */
- si1_t si1; /* SI */
+struct qe_immap {
+ struct qe_iram iram; /* I-RAM */
+ struct qe_ic_regs ic; /* Interrupt Controller */
+ struct cp_qe cp; /* Communications Processor */
+ struct qe_mux qmx; /* QE Multiplexer */
+ struct qe_timers qet; /* QE Timers */
+ struct spi spi[0x2]; /* spi */
+ struct mcc mcc; /* mcc */
+ struct qe_brg brg; /* brg */
+ struct usb_ctlr usb; /* USB */
+ struct si1 si1; /* SI */
u8 res11[0x800];
- sir_t sir; /* SI Routing Tables */
- ucc_t ucc1; /* ucc1 */
- ucc_t ucc3; /* ucc3 */
- ucc_t ucc5; /* ucc5 */
- ucc_t ucc7; /* ucc7 */
+ struct sir sir; /* SI Routing Tables */
+ struct ucc ucc1; /* ucc1 */
+ struct ucc ucc3; /* ucc3 */
+ struct ucc ucc5; /* ucc5 */
+ struct ucc ucc7; /* ucc7 */
u8 res12[0x600];
- upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */
- ucc_t ucc2; /* ucc2 */
- ucc_t ucc4; /* ucc4 */
- ucc_t ucc6; /* ucc6 */
- ucc_t ucc8; /* ucc8 */
+ struct upc upc1; /* MultiPHY UTOPIA POS Controller 1 */
+ struct ucc ucc2; /* ucc2 */
+ struct ucc ucc4; /* ucc4 */
+ struct ucc ucc6; /* ucc6 */
+ struct ucc ucc8; /* ucc8 */
u8 res13[0x600];
- upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */
- sdma_t sdma; /* SDMA */
- dbg_t dbg; /* Debug Space */
- rsp_t rsp[0x2]; /* RISC Special Registers (Trap and Breakpoint)
+ struct upc upc2; /* MultiPHY UTOPIA POS Controller 2 */
+ struct sdma sdma; /* SDMA */
+ struct dbg dbg; /* Debug Space */
+ struct rsp rsp[0x2]; /* RISC Special Registers (Trap and Breakpoint)
*/
u8 res14[0x300];
u8 res15[0x3A00];
@@ -479,9 +479,9 @@ typedef struct qe_immap {
u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
-} __attribute__ ((packed)) qe_map_t;
+} __attribute__ ((packed));
-extern qe_map_t *qe_immr;
+extern struct qe_immap *qe_immr;
extern phys_addr_t get_qe_base(void);
static inline unsigned long immrbar_virt_to_phys(volatile void * address)
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index 94623ee..2e43e45 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -51,18 +51,18 @@ void qe_muram_dump(void);
void *qe_muram_addr(uint offset);
/* Buffer descriptors.
*/
-typedef struct qe_bd {
+struct qe_bd {
u16 status;
u16 length;
u32 buf;
-} __attribute__ ((packed)) qe_bd_t;
+} __attribute__ ((packed));
-#define QE_SIZEOF_BD sizeof(qe_bd_t)
+#define QE_SIZEOF_BD sizeof(struct qe_bd)
#define BD_STATUS_MASK 0xffff0000
#define BD_LENGTH_MASK 0x0000ffff
-#define BD_BUFFER_ARG(bd) ((qe_bd_t *)bd)->buf
+#define BD_BUFFER_ARG(bd) ((struct qe_bd *)bd)->buf
#define BD_BUFFER_CLEAR(bd) out_be32(&(BD_BUFFER_ARG(bd)), 0);
#define BD_BUFFER(bd) in_be32(&(BD_BUFFER_ARG(bd)))
#define BD_STATUS_AND_LENGTH_SET(bd, val) out_be32((u32*)bd, val)
@@ -83,66 +83,66 @@ #define QE_ALIGNMENT_OF_PRAM
/* RISC allocation
*/
-typedef enum qe_risc_allocation {
+enum qe_risc_allocation {
QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose RISC 1 or
RISC 2 */
-} qe_risc_allocation_e;
+};
/* QE extended filtering Table Lookup Key Size
*/
-typedef enum qe_fltr_tbl_lookup_key_size {
+enum qe_fltr_tbl_lookup_key_size {
QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
= 0x3f, /* LookupKey parsed by the Generate LookupKey
CMD is truncated to 8 bytes */
QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
= 0x5f, /* LookupKey parsed by the Generate LookupKey
CMD is truncated to 16 bytes */
-} qe_fltr_tbl_lookup_key_size_e;
+};
/* QE FLTR extended filtering Largest External Table Lookup Key Size
*/
-typedef enum qe_fltr_largest_external_tbl_lookup_key_size_ {
+enum qe_fltr_largest_external_tbl_lookup_key_size {
QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
= 0x0,/* not used */
QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
= QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES /* 16 bytes */
-} qe_fltr_largest_external_tbl_lookup_key_size_e;
+};
/* structure representing QE parameter RAM
*/
-typedef struct qe_timer_tables {
+struct qe_timer_tables {
u16 tm_base; /* QE timer table base adr */
u16 tm_ptr; /* QE timer table pointer */
u16 r_tmr; /* QE timer mode register */
u16 r_tmv; /* QE timer valid register */
u32 tm_cmd; /* QE timer cmd register */
u32 tm_cnt; /* QE timer internal cnt */
-} __attribute__ ((packed)) qe_timer_tables_t;
+} __attribute__ ((packed));
#define QE_FLTR_TAD_SIZE 8
/* QE extended filtering Termination Action Descriptor (TAD)
*/
-typedef struct qe_fltr_tad {
+struct qe_fltr_tad {
u8 serialized[QE_FLTR_TAD_SIZE];
-} __attribute__ ((packed)) qe_fltr_tad_t;
+} __attribute__ ((packed));
/* Communication Direction.
*/
-typedef enum comm_dir {
+enum comm_dir {
COMM_DIR_NONE = 0,
COMM_DIR_RX = 1,
COMM_DIR_TX = 2,
COMM_DIR_RX_AND_TX = 3
-} comm_dir_e;
+};
/* Clocks and GRG's
*/
-typedef enum qe_clock {
+enum qe_clock {
QE_CLK_NONE = 0
, QE_BRG1 /* Baud Rate Generator 1 */
, QE_BRG2 /* Baud Rate Generator 2 */
@@ -185,7 +185,7 @@ typedef enum qe_clock {
, QE_CLK23 /* Clock 23 */
, QE_CLK24 /* Clock 24 */
, QE_CLK_DUMMY
-} qe_clock_e;
+};
/* QE CMXUCR Registers.
* There are two UCCs represented in each of the four CMXUCR registers.
@@ -366,7 +366,7 @@ #define UCC_GUEMR_SET_RESERVED3 0x10 /*
/* structure representing UCC SLOW parameter RAM
*/
-typedef struct ucc_slow_pram {
+struct ucc_slow_pram {
u16 rbase; /* RX BD base address */
u16 tbase; /* TX BD base address */
u8 rfcr; /* Rx function code */
@@ -384,7 +384,7 @@ typedef struct ucc_slow_pram {
u32 ttemp; /* Tx temp */
u32 rcrc; /* temp receive CRC */
u32 tcrc; /* temp transmit CRC */
-} __attribute__ ((packed)) ucc_slow_pram_t;
+} __attribute__ ((packed));
/* General UCC SLOW Mode Register (GUMRH & GUMRL)
*/
diff --git a/include/asm-powerpc/ucc.h b/include/asm-powerpc/ucc.h
index 5c09df6..bca4966 100644
--- a/include/asm-powerpc/ucc.h
+++ b/include/asm-powerpc/ucc.h
@@ -24,13 +24,13 @@ #define UCC_MAX_NUM 8
/* Slow or fast type for UCCs.
*/
-typedef enum ucc_speed_type {
+enum ucc_speed_type {
UCC_SPEED_TYPE_FAST, UCC_SPEED_TYPE_SLOW
-} ucc_speed_type_e;
+};
/* Initial UCCs Parameter RAM address relative to: MEM_MAP_BASE (IMMR).
*/
-typedef enum ucc_pram_initial_offset {
+enum ucc_pram_initial_offset {
UCC_PRAM_OFFSET_UCC1 = 0x8400,
UCC_PRAM_OFFSET_UCC2 = 0x8500,
UCC_PRAM_OFFSET_UCC3 = 0x8600,
@@ -39,7 +39,7 @@ typedef enum ucc_pram_initial_offset {
UCC_PRAM_OFFSET_UCC6 = 0x8100,
UCC_PRAM_OFFSET_UCC7 = 0x8200,
UCC_PRAM_OFFSET_UCC8 = 0x8300
-} ucc_pram_initial_offset_e;
+};
/* ucc_set_type
* Sets UCC to slow or fast mode.
@@ -60,7 +60,7 @@ int ucc_init_guemr(struct ucc_common *re
int ucc_set_qe_mux_mii_mng(int ucc_num);
-int ucc_set_qe_mux_rxtx(int ucc_num, qe_clock_e clock, comm_dir_e mode);
+int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode);
int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask);
diff --git a/include/asm-powerpc/ucc_fast.h b/include/asm-powerpc/ucc_fast.h
index b1cfd00..1428e53 100644
--- a/include/asm-powerpc/ucc_fast.h
+++ b/include/asm-powerpc/ucc_fast.h
@@ -49,7 +49,7 @@ #define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SI
/* ucc_fast_channel_protocol_mode - UCC FAST mode.
*/
-typedef enum ucc_fast_channel_protocol_mode {
+enum ucc_fast_channel_protocol_mode {
UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000,
UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001,
UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002,
@@ -66,73 +66,73 @@ typedef enum ucc_fast_channel_protocol_m
UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D,
UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E,
UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F
-} ucc_fast_channel_protocol_mode_e;
+};
/* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX
*/
-typedef enum ucc_fast_transparent_txrx {
+enum ucc_fast_transparent_txrx {
UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000,
UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000
-} ucc_fast_transparent_txrx_e;
+};
/* UCC fast diagnostic mode
*/
-typedef enum ucc_fast_diag_mode {
+enum ucc_fast_diag_mode {
UCC_FAST_DIAGNOSTIC_NORMAL = 0x0,
UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000,
UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000,
UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000
-} ucc_fast_diag_mode_e;
+};
/* UCC fast Sync length (transparent mode only)
*/
-typedef enum ucc_fast_sync_len {
+enum ucc_fast_sync_len {
UCC_FAST_SYNC_LEN_NOT_USED = 0x0,
UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000,
UCC_FAST_SYNC_LEN_8_BIT = 0x00008000,
UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000
-} ucc_fast_sync_len_e;
+};
/* UCC fast RTS mode
*/
-typedef enum ucc_fast_ready_to_send {
+enum ucc_fast_ready_to_send {
UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000,
UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000
-} ucc_fast_ready_to_send_e;
+};
/* UCC fast receiver decoding mode
*/
-typedef enum ucc_fast_rx_decoding_method {
+enum ucc_fast_rx_decoding_method {
UCC_FAST_RX_ENCODING_NRZ = 0x00000000,
UCC_FAST_RX_ENCODING_NRZI = 0x00000800,
UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000,
UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800
-} ucc_fast_rx_decoding_method_e;
+};
/* UCC fast transmitter encoding mode
*/
-typedef enum ucc_fast_tx_encoding_method {
+enum ucc_fast_tx_encoding_method {
UCC_FAST_TX_ENCODING_NRZ = 0x00000000,
UCC_FAST_TX_ENCODING_NRZI = 0x00000100,
UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200,
UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300
-} ucc_fast_tx_encoding_method_e;
+};
/* UCC fast CRC length
*/
-typedef enum ucc_fast_transparent_tcrc {
+enum ucc_fast_transparent_tcrc {
UCC_FAST_16_BIT_CRC = 0x00000000,
UCC_FAST_CRC_RESERVED0 = 0x00000040,
UCC_FAST_32_BIT_CRC = 0x00000080,
UCC_FAST_CRC_RESERVED1 = 0x000000C0
-} ucc_fast_transparent_tcrc_e;
+};
/* Fast UCC initialization structure.
*/
-typedef struct ucc_fast_info {
+struct ucc_fast_info {
int ucc_num;
- qe_clock_e rx_clock;
- qe_clock_e tx_clock;
+ enum qe_clock rx_clock;
+ enum qe_clock tx_clock;
u32 regs;
int irq;
u32 uccm_mask;
@@ -157,17 +157,17 @@ typedef struct ucc_fast_info {
u16 utfet;
u16 utftt;
u16 ufpt;
- ucc_fast_channel_protocol_mode_e mode;
- ucc_fast_transparent_txrx_e ttx_trx;
- ucc_fast_tx_encoding_method_e tenc;
- ucc_fast_rx_decoding_method_e renc;
- ucc_fast_transparent_tcrc_e tcrc;
- ucc_fast_sync_len_e synl;
-} ucc_fast_info_t;
-
-typedef struct ucc_fast_private {
- ucc_fast_info_t *uf_info;
- ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs. */
+ enum ucc_fast_channel_protocol_mode mode;
+ enum ucc_fast_transparent_txrx ttx_trx;
+ enum ucc_fast_tx_encoding_method tenc;
+ enum ucc_fast_rx_decoding_method renc;
+ enum ucc_fast_transparent_tcrc tcrc;
+ enum ucc_fast_sync_len synl;
+};
+
+struct ucc_fast_private {
+ struct ucc_fast_info *uf_info;
+ struct ucc_fast *uf_regs; /* a pointer to memory map of UCC regs. */
u32 *p_ucce; /* a pointer to the event register in memory. */
u32 *p_uccm; /* a pointer to the mask register in memory. */
int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
@@ -191,7 +191,7 @@ #ifdef STATISTICS
*/
#endif /* STATISTICS */
u16 mrblr; /* maximum receive buffer length */
-} ucc_fast_private_t;
+};
/* ucc_fast_init
* Initializes Fast UCC according to user provided parameters.
@@ -199,14 +199,14 @@ #endif /* STATISTICS */
* uf_info - (In) pointer to the fast UCC info structure.
* uccf_ret - (Out) pointer to the fast UCC structure.
*/
-int ucc_fast_init(ucc_fast_info_t * uf_info, ucc_fast_private_t ** uccf_ret);
+int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret);
/* ucc_fast_free
* Frees all resources for fast UCC.
*
* uccf - (In) pointer to the fast UCC structure.
*/
-void ucc_fast_free(ucc_fast_private_t * uccf);
+void ucc_fast_free(struct ucc_fast_private * uccf);
/* ucc_fast_enable
* Enables a fast UCC port.
@@ -215,7 +215,7 @@ void ucc_fast_free(ucc_fast_private_t *
* uccf - (In) pointer to the fast UCC structure.
* mode - (In) TX, RX, or both.
*/
-void ucc_fast_enable(ucc_fast_private_t * uccf, comm_dir_e mode);
+void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode);
/* ucc_fast_disable
* Disables a fast UCC port.
@@ -224,7 +224,7 @@ void ucc_fast_enable(ucc_fast_private_t
* uccf - (In) pointer to the fast UCC structure.
* mode - (In) TX, RX, or both.
*/
-void ucc_fast_disable(ucc_fast_private_t * uccf, comm_dir_e mode);
+void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode);
/* ucc_fast_irq
* Handles interrupts on fast UCC.
@@ -232,7 +232,7 @@ void ucc_fast_disable(ucc_fast_private_t
*
* uccf - (In) pointer to the fast UCC structure.
*/
-void ucc_fast_irq(ucc_fast_private_t * uccf);
+void ucc_fast_irq(struct ucc_fast_private * uccf);
/* ucc_fast_transmit_on_demand
* Immediately forces a poll of the transmitter for data to be sent.
@@ -245,10 +245,10 @@ void ucc_fast_irq(ucc_fast_private_t * u
*
* uccf - (In) pointer to the fast UCC structure.
*/
-void ucc_fast_transmit_on_demand(ucc_fast_private_t * uccf);
+void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf);
u32 ucc_fast_get_qe_cr_subblock(int uccf_num);
-void ucc_fast_dump_regs(ucc_fast_private_t * uccf);
+void ucc_fast_dump_regs(struct ucc_fast_private * uccf);
#endif /* __UCC_FAST_H__ */
diff --git a/include/asm-powerpc/ucc_slow.h b/include/asm-powerpc/ucc_slow.h
index 07db339..4bca460 100644
--- a/include/asm-powerpc/ucc_slow.h
+++ b/include/asm-powerpc/ucc_slow.h
@@ -87,15 +87,15 @@ #define ALIGNMENT_OF_UCC_SLOW_PRAM 64
/* UCC Slow Channel Protocol Mode
*/
-typedef enum ucc_slow_channel_protocol_mode {
+enum ucc_slow_channel_protocol_mode {
UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002, /* QMC */
UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004, /* UART */
UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008 /* BISYNC */
-} ucc_slow_channel_protocol_mode_e;
+};
/* UCC Slow Transparent Transmit CRC (TCRC)
*/
-typedef enum ucc_slow_transparent_tcrc {
+enum ucc_slow_transparent_tcrc {
UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000, /* 16-bit
CCITT CRC
(HDLC).
@@ -109,11 +109,11 @@ typedef enum ucc_slow_transparent_tcrc {
(Ethernet
and HDLC).
*/
-} ucc_slow_transparent_tcrc_e;
+};
/* UCC Slow oversampling rate for transmitter (TDCR)
*/
-typedef enum ucc_slow_tx_oversampling_rate {
+enum ucc_slow_tx_oversampling_rate {
UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000, /* 1x clock
mode */
UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000, /* 8x clock
@@ -122,11 +122,11 @@ typedef enum ucc_slow_tx_oversampling_ra
mode */
UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000 /* 32x clock
mode */
-} ucc_slow_tx_oversampling_rate_e;
+};
/* UCC Slow Oversampling rate for receiver (RDCR)
*/
-typedef enum ucc_slow_rx_oversampling_rate {
+enum ucc_slow_rx_oversampling_rate {
UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000, /* 1x clock
mode */
UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000, /* 8x clock
@@ -135,36 +135,36 @@ typedef enum ucc_slow_rx_oversampling_ra
mode */
UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000 /* 32x clock
mode */
-} ucc_slow_rx_oversampling_rate_e;
+};
/* UCC Slow Transmitter encoding method (TENC)
*/
-typedef enum ucc_slow_tx_encoding_method {
+enum ucc_slow_tx_encoding_method {
UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000,
UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100
-} ucc_slow_tx_encoding_method_e;
+};
/* UCC Slow Receiver decoding method (RENC)
*/
-typedef enum ucc_slow_rx_decoding_method {
+enum ucc_slow_rx_decoding_method {
UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000,
UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800
-} ucc_slow_rx_decoding_method_e;
+};
/* UCC Slow Diagnostic mode (DIAG)
*/
-typedef enum ucc_slow_diag_mode {
+enum ucc_slow_diag_mode {
UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000,
UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040,
UCC_SLOW_DIAG_MODE_ECHO = 0x00000080,
UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0
-} ucc_slow_diag_mode_e;
+};
-typedef struct ucc_slow_info {
+struct ucc_slow_info {
int ucc_num;
- qe_clock_e rx_clock;
- qe_clock_e tx_clock;
- ucc_slow_t *us_regs;
+ enum qe_clock rx_clock;
+ enum qe_clock tx_clock;
+ struct ucc_slow *us_regs;
int irq;
u16 uccm_mask;
int data_mem_part;
@@ -189,19 +189,19 @@ typedef struct ucc_slow_info {
int tfl;
int txsy;
u16 max_rx_buf_length;
- ucc_slow_transparent_tcrc_e tcrc;
- ucc_slow_channel_protocol_mode_e mode;
- ucc_slow_diag_mode_e diag;
- ucc_slow_tx_oversampling_rate_e tdcr;
- ucc_slow_rx_oversampling_rate_e rdcr;
- ucc_slow_tx_encoding_method_e tenc;
- ucc_slow_rx_decoding_method_e renc;
-} ucc_slow_info_t;
+ enum ucc_slow_transparent_tcrc tcrc;
+ enum ucc_slow_channel_protocol_mode mode;
+ enum ucc_slow_diag_mode diag;
+ enum ucc_slow_tx_oversampling_rate tdcr;
+ enum ucc_slow_rx_oversampling_rate rdcr;
+ enum ucc_slow_tx_encoding_method tenc;
+ enum ucc_slow_rx_decoding_method renc;
+};
-typedef struct ucc_slow_private {
- ucc_slow_info_t *us_info;
- ucc_slow_t *us_regs; /* a pointer to memory map of UCC regs. */
- ucc_slow_pram_t *us_pram; /* a pointer to the parameter RAM. */
+struct ucc_slow_private {
+ struct ucc_slow_info *us_info;
+ struct ucc_slow *us_regs; /* a pointer to memory map of UCC regs. */
+ struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM. */
uint us_pram_offset;
int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
@@ -230,7 +230,7 @@ #ifdef STATISTICS
were discarded by the driver due to
errors). */
#endif /* STATISTICS */
-} ucc_slow_private_t;
+};
/* ucc_slow_init
* Initializes Slow UCC according to provided parameters.
@@ -238,14 +238,14 @@ #endif /* STATISTICS */
* us_info - (In) pointer to the slow UCC info structure.
* uccs_ret - (Out) pointer to the slow UCC structure.
*/
-int ucc_slow_init(ucc_slow_info_t * us_info, ucc_slow_private_t ** uccs_ret);
+int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret);
/* ucc_slow_free
* Frees all resources for slow UCC.
*
* uccs - (In) pointer to the slow UCC structure.
*/
-void ucc_slow_free(ucc_slow_private_t * uccs);
+void ucc_slow_free(struct ucc_slow_private * uccs);
/* ucc_slow_enable
* Enables a fast UCC port.
@@ -254,7 +254,7 @@ void ucc_slow_free(ucc_slow_private_t *
* uccs - (In) pointer to the slow UCC structure.
* mode - (In) TX, RX, or both.
*/
-void ucc_slow_enable(ucc_slow_private_t * uccs, comm_dir_e mode);
+void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode);
/* ucc_slow_disable
* Disables a fast UCC port.
@@ -263,7 +263,7 @@ void ucc_slow_enable(ucc_slow_private_t
* uccs - (In) pointer to the slow UCC structure.
* mode - (In) TX, RX, or both.
*/
-void ucc_slow_disable(ucc_slow_private_t * uccs, comm_dir_e mode);
+void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode);
/* ucc_slow_poll_transmitter_now
* Immediately forces a poll of the transmitter for data to be sent.
@@ -276,28 +276,28 @@ void ucc_slow_disable(ucc_slow_private_t
*
* uccs - (In) pointer to the slow UCC structure.
*/
-void ucc_slow_poll_transmitter_now(ucc_slow_private_t * uccs);
+void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs);
/* ucc_slow_graceful_stop_tx
* Smoothly stops transmission on a specified slow UCC.
*
* uccs - (In) pointer to the slow UCC structure.
*/
-void ucc_slow_graceful_stop_tx(ucc_slow_private_t * uccs);
+void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
/* ucc_slow_stop_tx
* Stops transmission on a specified slow UCC.
*
* uccs - (In) pointer to the slow UCC structure.
*/
-void ucc_slow_stop_tx(ucc_slow_private_t * uccs);
+void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
/* ucc_slow_restart_x
* Restarts transmitting on a specified slow UCC.
*
* uccs - (In) pointer to the slow UCC structure.
*/
-void ucc_slow_restart_x(ucc_slow_private_t * uccs);
+void ucc_slow_restart_x(struct ucc_slow_private * uccs);
u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
--
1.4.2.1
^ permalink raw reply related
* [PATCH 12/15] Change ucc_geth driver to use of_device
From: Kim Phillips @ 2006-09-30 23:35 UTC (permalink / raw)
To: linuxppc-dev
Change ucc_geth driver to use of_device
This patch change ucc_geth driver to use of_device from
platform_device. It also fix a bug that bcsr_regs gets
accidentally unmapped. Remove trailing space.
Sign-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/sysdev/qe_lib/Makefile | 2 -
arch/powerpc/sysdev/qe_lib/qe_common.c | 22 ++++++
drivers/net/ucc_geth.c | 119 +++++++++++++++++++++++---------
3 files changed, 110 insertions(+), 33 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/Makefile b/arch/powerpc/sysdev/qe_lib/Makefile
index 9a54a81..316a63c 100644
--- a/arch/powerpc/sysdev/qe_lib/Makefile
+++ b/arch/powerpc/sysdev/qe_lib/Makefile
@@ -1,7 +1,7 @@
#
# Makefile for the linux ppc-specific parts of QE
#
-obj-$(CONFIG_QUICC_ENGINE)+= qe_common.o qe.o qe_ic.o qe_io.o
+obj-$(CONFIG_QUICC_ENGINE)+= qe_common.o qe_ic.o qe_io.o
obj-$(CONFIG_UCC) += ucc.o
obj-$(CONFIG_UCC_SLOW) += ucc_slow.o
diff --git a/arch/powerpc/sysdev/qe_lib/qe_common.c b/arch/powerpc/sysdev/qe_lib/qe_common.c
index 0cde73c..5c3381f 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_common.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_common.c
@@ -60,6 +60,28 @@ static int qe_sdma_init(void);
static DEFINE_SPINLOCK(qe_lock);
+static phys_addr_t qebase = -1;
+
+phys_addr_t get_qe_base(void)
+{
+ struct device_node *qe;
+
+ if (qebase != -1)
+ return qebase;
+
+ qe = of_find_node_by_type(NULL, "qe");
+ if (qe) {
+ unsigned int size;
+ void *prop = get_property(qe, "reg", &size);
+ qebase = of_translate_address(qe, prop);
+ of_node_put(qe);
+ };
+
+ return qebase;
+}
+
+EXPORT_SYMBOL(get_qe_base);
+
void qe_reset(void)
{
if (qe_immr == NULL)
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index 625a9ab..ef6cc2a 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -2,14 +2,11 @@
* Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
*
* Author: Shlomi Gridish <gridish@freescale.com>
+ * Li Yang <leoli@freescale.com>
*
* Description:
* QE UCC Gigabit Ethernet Driver
*
- * Changelog:
- * Jul 6, 2006 Li Yang <LeoLi@freescale.com>
- * - Rearrange code and style fixes
- *
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
@@ -31,9 +28,9 @@ #include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/fsl_devices.h>
#include <linux/ethtool.h>
-#include <linux/platform_device.h>
#include <linux/mii.h>
+#include <asm/of_device.h>
#include <asm/uaccess.h>
#include <asm/irq.h>
#include <asm/io.h>
@@ -4131,30 +4128,47 @@ static int ucc_geth_close(struct net_dev
const struct ethtool_ops ucc_geth_ethtool_ops = { };
-static int ucc_geth_probe(struct device *device)
+static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
{
- struct platform_device *pdev = to_platform_device(device);
- struct ucc_geth_platform_data *ugeth_pdata;
+ struct device *device = &ofdev->dev;
+ struct device_node *np = ofdev->node;
struct net_device *dev = NULL;
struct ucc_geth_private *ugeth = NULL;
struct ucc_geth_info *ug_info;
- int err;
+ struct resource res;
+ struct device_node *phy;
+ int err, ucc_num, phy_interface;
static int mii_mng_configured = 0;
+ phandle *ph;
ugeth_vdbg("%s: IN", __FUNCTION__);
- ugeth_pdata = (struct ucc_geth_platform_data *)pdev->dev.platform_data;
+ ucc_num = *((int *) get_property(np, "device-id", NULL)) - 1;
+ if ((ucc_num < 0) || (ucc_num > 7))
+ return -ENODEV;
+
+ ug_info = &ugeth_info[ucc_num];
+ ug_info->uf_info.ucc_num = ucc_num;
+ ug_info->uf_info.rx_clock = *((uint *) get_property(np, "rx-clock", NULL));
+ ug_info->uf_info.tx_clock = *((uint *) get_property(np, "tx-clock", NULL));
+ err = of_address_to_resource(np, 0, &res);
+ if (err)
+ return -EINVAL;
+
+ ug_info->uf_info.regs = res.start;
+ ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
+
+ ph = (phandle *) get_property(np, "phy-handle", NULL);
+ phy = of_find_node_by_phandle(*ph);
- ug_info = &ugeth_info[pdev->id];
- ug_info->uf_info.ucc_num = pdev->id;
- ug_info->uf_info.rx_clock = ugeth_pdata->rx_clock;
- ug_info->uf_info.tx_clock = ugeth_pdata->tx_clock;
- ug_info->uf_info.regs = ugeth_pdata->phy_reg_addr;
- ug_info->uf_info.irq = platform_get_irq(pdev, 0);
- ug_info->phy_address = ugeth_pdata->phy_id;
- ug_info->enet_interface = ugeth_pdata->phy_interface;
- ug_info->board_flags = ugeth_pdata->board_flags;
- ug_info->phy_interrupt = ugeth_pdata->phy_interrupt;
+ if (phy == NULL)
+ return -ENODEV;
+
+ ug_info->phy_address = *(u8 *) get_property(phy, "reg", NULL);
+ ug_info->enet_interface = *((uint *) get_property(phy, "interface", NULL));
+ ug_info->phy_interrupt = irq_of_parse_and_map(phy, 0);
+ ug_info->board_flags = (ug_info->phy_interrupt == NO_IRQ)?
+ 0:FSL_UGETH_BRD_HAS_PHY_INTR;
printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
@@ -4162,12 +4176,43 @@ static int ucc_geth_probe(struct device
if (ug_info == NULL) {
ugeth_err("%s: [%d] Missing additional data!", __FUNCTION__,
- pdev->id);
+ ucc_num);
return -ENODEV;
}
+ /* FIXME: Work around for early chip rev. */
+ /* There's a bug in initial chip rev(s) in the RGMII ac */
+ /* timing. */
+ /* The following compensates by writing to the reserved */
+ /* QE Port Output Hold Registers (CPOH1?). */
+ phy_interface = *((int *) get_property(phy, "interface", NULL));
+ if ((phy_interface == ENET_1000_RGMII) ||
+ (phy_interface == ENET_100_RGMII) ||
+ (phy_interface == ENET_10_RGMII)) {
+ struct device_node *soc;
+ phys_addr_t immrbase = -1;
+ u32 *tmp_reg;
+ u32 tmp_val;
+
+ soc = of_find_node_by_type(NULL, "soc");
+ if (soc) {
+ unsigned int size;
+ void *prop = get_property(soc, "reg", &size);
+ immrbase = of_translate_address(soc, prop);
+ of_node_put(soc);
+ };
+
+ tmp_reg = (u32 *) ioremap(immrbase + 0x14A8, 0x4);
+ tmp_val = in_be32(tmp_reg);
+ if (ucc_num == 1)
+ out_be32(tmp_reg, tmp_val | 0x00003000);
+ else if (ucc_num == 2)
+ out_be32(tmp_reg, tmp_val | 0x0c000000);
+ iounmap(tmp_reg);
+ }
+
if (!mii_mng_configured) {
- ucc_set_qe_mux_mii_mng(ug_info->uf_info.ucc_num);
+ ucc_set_qe_mux_mii_mng(ucc_num);
mii_mng_configured = 1;
}
@@ -4214,13 +4259,14 @@ #endif /* CONFIG_UGETH_NAPI */
ugeth->ug_info = ug_info;
ugeth->dev = dev;
- memcpy(dev->dev_addr, ugeth_pdata->mac_addr, 6);
+ memcpy(dev->dev_addr, get_property(np, "mac-address", NULL), 6);
return 0;
}
-static int ucc_geth_remove(struct device *device)
+static int ucc_geth_remove(struct of_device* ofdev)
{
+ struct device *device = &ofdev->dev;
struct net_device *dev = dev_get_drvdata(device);
struct ucc_geth_private *ugeth = netdev_priv(dev);
@@ -4231,28 +4277,37 @@ static int ucc_geth_remove(struct device
return 0;
}
-/* Structure for a device driver */
-static struct device_driver ucc_geth_driver = {
- .name = DRV_NAME,
- .bus = &platform_bus_type,
- .probe = ucc_geth_probe,
- .remove = ucc_geth_remove,
+static struct of_device_id ucc_geth_match[] = {
+ {
+ .compatible = "ucc_geth",
+ },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, ucc_geth_match);
+
+static struct of_platform_driver ucc_geth_driver = {
+ .name = DRV_NAME,
+ .match_table = ucc_geth_match,
+ .probe = ucc_geth_probe,
+ .remove = ucc_geth_remove,
};
static int __init ucc_geth_init(void)
{
int i;
+
printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
for (i = 0; i < 8; i++)
memcpy(&(ugeth_info[i]), &ugeth_primary_info,
sizeof(ugeth_primary_info));
- return driver_register(&ucc_geth_driver);
+ return of_register_driver(&ucc_geth_driver);
}
static void __exit ucc_geth_exit(void)
{
- driver_unregister(&ucc_geth_driver);
+ of_unregister_driver(&ucc_geth_driver);
}
module_init(ucc_geth_init);
--
1.4.2.1
^ permalink raw reply related
* [PATCH 11/15] Add QE device tree node definition
From: Kim Phillips @ 2006-09-30 23:35 UTC (permalink / raw)
To: linuxppc-dev
Add QE device tree node definition
Here is OF device tree node spec used in QE/8360 support patches.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jiang Bo <Tanya.jiang@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
---
Documentation/powerpc/booting-without-of.txt | 252 ++++++++++++++++++++++++++
1 files changed, 252 insertions(+), 0 deletions(-)
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index 5c0ba23..b57e7da 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -1441,6 +1441,258 @@ platforms are moved over to use the flat
descriptor-types-mask = <012b0ebf>;
};
+ h) Board Control and Status (BCSR)
+
+ Required properties:
+
+ - device_type : Should be "board-control"
+ - reg : Offset and length of the register set for the device
+
+ Example:
+
+ bcsr@f8000000 {
+ device_type = "board-control";
+ reg = <f8000000 8000>;
+ };
+
+ i) Freescale QUICC Engine module (QE)
+ This represents qe module that is installed on PowerQUICC II Pro.
+ Hopefully it will merge backward compatibility with CPM/CPM2.
+ Basically, it is a bus of devices, that could act more or less
+ as a complete entity (UCC, USB etc ). All of them should be siblings on
+ the "root" qe node, using the common properties from there.
+ The description below applies to the the qe of MPC8360 and
+ more nodes and properties would be extended in the future.
+
+ i) Root QE device
+
+ Required properties:
+ - device_type : should be "qe";
+ - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
+ - reg : offset and length of the device registers.
+ - bus-frequency : the clock frequency for QUICC Engine.
+
+ Recommended properties
+ - brg-frequency : the internal clock source frequency for baud-rate
+ generators in Hz.
+
+ Example:
+ qe@e0100000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <2>;
+ device_type = "qe";
+ model = "QE";
+ ranges = <0 e0100000 00100000>;
+ reg = <e0100000 480>;
+ brg-frequency = <0>;
+ bus-frequency = <179A7B00>;
+ }
+
+
+ ii) SPI (Serial Peripheral Interface)
+
+ Required properties:
+ - device_type : should be "spi".
+ - compatible : should be "fsl_spi".
+ - mode : the spi operation mode, it can be "cpu" or "qe".
+ - reg : Offset and length of the register set for the device
+ - interrupts : <a b> where a is the interrupt number and b is a
+ field that represents an encoding of the sense and level
+ information for the interrupt. This should be encoded based on
+ the information in section 2) depending on the type of interrupt
+ controller you have.
+ - interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this device.
+
+ Example:
+ spi@4c0 {
+ device_type = "spi";
+ compatible = "fsl_spi";
+ reg = <4c0 40>;
+ interrupts = <82 0>;
+ interrupt-parent = <700>;
+ mode = "cpu";
+ };
+
+
+ iii) USB (Universal Serial Bus Controller)
+
+ Required properties:
+ - device_type : should be "usb".
+ - compatible : could be "qe_udc" or "fhci-hcd".
+ - mode : the could be "host" or "slave".
+ - reg : Offset and length of the register set for the device
+ - interrupts : <a b> where a is the interrupt number and b is a
+ field that represents an encoding of the sense and level
+ information for the interrupt. This should be encoded based on
+ the information in section 2) depending on the type of interrupt
+ controller you have.
+ - interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this device.
+
+ Example(slave):
+ usb@6c0 {
+ device_type = "usb";
+ compatible = "qe_udc";
+ reg = <6c0 40>;
+ interrupts = <8b 0>;
+ interrupt-parent = <700>;
+ mode = "slave";
+ };
+
+
+ iv) UCC (Unified Communications Controllers)
+
+ Required properties:
+ - device_type : should be "network", "hldc", "uart", "transparent"
+ "bisync" or "atm".
+ - compatible : could be "ucc_geth" or "fsl_atm" and so on.
+ - model : should be "UCC".
+ - device-id : the ucc number(1-8), corresponding to UCCx in UM.
+ - reg : Offset and length of the register set for the device
+ - interrupts : <a b> where a is the interrupt number and b is a
+ field that represents an encoding of the sense and level
+ information for the interrupt. This should be encoded based on
+ the information in section 2) depending on the type of interrupt
+ controller you have.
+ - interrupt-parent : the phandle for the interrupt controller that
+ services interrupts for this device.
+ - pio-handle : The phandle for the Parallel I/O port configuration.
+ - rx-clock : represents the UCC receive clock source.
+ 0x00 : clock source is disabled;
+ 0x1~0x10 : clock source is BRG1~BRG16 respectively;
+ 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
+ - tx-clock: represents the UCC transmit clock source;
+ 0x00 : clock source is disabled;
+ 0x1~0x10 : clock source is BRG1~BRG16 respectively;
+ 0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
+
+ Required properties for network device_type:
+ - mac-address : list of bytes representing the ethernet address.
+ - phy-handle : The phandle for the PHY connected to this controller.
+
+ Example:
+ ucc@2000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ model = "UCC";
+ device-id = <1>;
+ reg = <2000 200>;
+ interrupts = <a0 0>;
+ interrupt-parent = <700>;
+ mac-address = [ 00 04 9f 00 23 23 ];
+ rx-clock = "none";
+ tx-clock = "clk9";
+ phy-handle = <212000>;
+ pio-handle = <140001>;
+ };
+
+
+ v) Parallel I/O Ports
+
+ This node configures Parallel I/O ports for CPUs with QE support.
+ The node should reside in the "soc" node of the tree. For each
+ device that using parallel I/O ports, a child node should be created.
+ See the definition of the Pin configuration nodes below for more
+ information.
+
+ Required properties:
+ - device_type : should be "par_io".
+ - reg : offset to the register set and its length.
+ - num-ports : number of Parallel I/O ports
+
+ Example:
+ par_io@1400 {
+ reg = <1400 100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "par_io";
+ num-ports = <7>;
+ ucc_pin@01 {
+ ......
+ };
+
+
+ vi) Pin configuration nodes
+
+ Required properties:
+ - linux,phandle : phandle of this node; likely referenced by a QE
+ device.
+ - pio-map : array of pin configurations. Each pin is defined by 6
+ integers. The six numbers are respectively: port, pin, dir,
+ open_drain, assignment, has_irq.
+ - port : port number of the pin; 0-6 represent port A-G in UM.
+ - pin : pin number in the port.
+ - dir : direction of the pin, should encode as follows:
+
+ 0 = The pin is disabled
+ 1 = The pin is an output
+ 2 = The pin is an input
+ 3 = The pin is I/O
+
+ - open_drain : indicates the pin is normal or wired-OR:
+
+ 0 = The pin is actively driven as an output
+ 1 = The pin is an open-drain driver. As an output, the pin is
+ driven active-low, otherwise it is three-stated.
+
+ - assignment : function number of the pin according to the Pin Assignment
+ tables in User Manual. Each pin can have up to 4 possible functions in
+ QE and two options for CPM.
+ - has_irq : indicates if the pin is used as source of exteral
+ interrupts.
+
+ Example:
+ ucc_pin@01 {
+ linux,phandle = <140001>;
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 3 1 0 1 0 /* TxD0 */
+ 0 4 1 0 1 0 /* TxD1 */
+ 0 5 1 0 1 0 /* TxD2 */
+ 0 6 1 0 1 0 /* TxD3 */
+ 1 6 1 0 3 0 /* TxD4 */
+ 1 7 1 0 1 0 /* TxD5 */
+ 1 9 1 0 2 0 /* TxD6 */
+ 1 a 1 0 2 0 /* TxD7 */
+ 0 9 2 0 1 0 /* RxD0 */
+ 0 a 2 0 1 0 /* RxD1 */
+ 0 b 2 0 1 0 /* RxD2 */
+ 0 c 2 0 1 0 /* RxD3 */
+ 0 d 2 0 1 0 /* RxD4 */
+ 1 1 2 0 2 0 /* RxD5 */
+ 1 0 2 0 2 0 /* RxD6 */
+ 1 4 2 0 2 0 /* RxD7 */
+ 0 7 1 0 1 0 /* TX_EN */
+ 0 8 1 0 1 0 /* TX_ER */
+ 0 f 2 0 1 0 /* RX_DV */
+ 0 10 2 0 1 0 /* RX_ER */
+ 0 0 2 0 1 0 /* RX_CLK */
+ 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
+ 2 8 2 0 1 0>; /* GTX125 - CLK9 */
+ };
+
+ vii) Multi-User RAM (MURAM)
+
+ Required properties:
+ - device_type : should be "muram".
+ - mode : the could be "host" or "slave".
+ - ranges : Should be defined as specified in 1) to describe the
+ translation of MURAM addresses.
+ - data-only : sub-node which defines the address area under MURAM
+ bus that can be allocated as data/parameter
+
+ Example:
+
+ muram@10000 {
+ device_type = "muram";
+ ranges = <0 00010000 0000c000>;
+
+ data-only@0{
+ reg = <0 c000>;
+ };
+ };
More devices will be defined as this spec matures.
--
1.4.2.1
^ permalink raw reply related
* [PATCH 10/15] Add MPC8360EMDS default dts file
From: Kim Phillips @ 2006-09-30 23:35 UTC (permalink / raw)
To: linuxppc-dev
Add MPC8360EMDS default dts file
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jiang Bo <Tanya.jiang@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/boot/dts/mpc8360emds.dts | 375 +++++++++++++++++++++++++++++++++
1 files changed, 375 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8360emds.dts b/arch/powerpc/boot/dts/mpc8360emds.dts
new file mode 100644
index 0000000..9022192
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8360emds.dts
@@ -0,0 +1,375 @@
+/*
+ * MPC8360E EMDS Device Tree Source
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+
+/*
+/memreserve/ 00000000 1000000;
+*/
+
+/ {
+ model = "MPC8360EPB";
+ compatible = "MPC83xx";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ linux,phandle = <100>;
+
+ cpus {
+ #cpus = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ linux,phandle = <200>;
+
+ PowerPC,8360@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>; // 32 bytes
+ i-cache-line-size = <20>; // 32 bytes
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <3EF1480>;
+ bus-frequency = <FBC5200>;
+ clock-frequency = <1F78A400>;
+ 32-bit;
+ linux,phandle = <201>;
+ linux,boot-cpu;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ linux,phandle = <300>;
+ reg = <00000000 10000000>;
+ };
+
+ bcsr@f8000000 {
+ device_type = "board-control";
+ reg = <f8000000 8000>;
+ };
+
+ soc8360@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <2>;
+ device_type = "soc";
+ ranges = <0 e0000000 00100000>;
+ reg = <e0000000 00000200>;
+ bus-frequency = <FBC5200>;
+
+ wdt@200 {
+ device_type = "watchdog";
+ compatible = "mpc83xx_wdt";
+ reg = <200 100>;
+ };
+
+ i2c@3000 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3000 100>;
+ interrupts = <e 8>;
+ interrupt-parent = <700>;
+ dfsrr;
+ };
+
+ i2c@3100 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3100 100>;
+ interrupts = <f 8>;
+ interrupt-parent = <700>;
+ dfsrr;
+ };
+
+ serial@4500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>;
+ clock-frequency = <FBC5200>;
+ interrupts = <9 8>;
+ interrupt-parent = <700>;
+ };
+
+ serial@4600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>;
+ clock-frequency = <FBC5200>;
+ interrupts = <a 8>;
+ interrupt-parent = <700>;
+ };
+
+ crypto@30000 {
+ device_type = "crypto";
+ model = "SEC2";
+ compatible = "talitos";
+ reg = <30000 10000>;
+ interrupts = <b 8>;
+ interrupt-parent = <700>;
+ num-channels = <4>;
+ channel-fifo-len = <18>;
+ exec-units-mask = <0000007e>;
+ /* desc mask is for rev1.x, we need runtime fixup for >=2.x */
+ descriptor-types-mask = <01010ebf>;
+ };
+
+ pci@8500 {
+ linux,phandle = <8500>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x11 AD17 */
+ 8800 0 0 1 700 14 8
+ 8800 0 0 2 700 15 8
+ 8800 0 0 3 700 16 8
+ 8800 0 0 4 700 17 8
+
+ /* IDSEL 0x12 AD18 */
+ 9000 0 0 1 700 16 8
+ 9000 0 0 2 700 17 8
+ 9000 0 0 3 700 14 8
+ 9000 0 0 4 700 15 8
+
+ /* IDSEL 0x13 AD19 */
+ 9800 0 0 1 700 17 8
+ 9800 0 0 2 700 14 8
+ 9800 0 0 3 700 15 8
+ 9800 0 0 4 700 16 8
+
+ /* IDSEL 0x15 AD21*/
+ a800 0 0 1 700 14 8
+ a800 0 0 2 700 15 8
+ a800 0 0 3 700 16 8
+ a800 0 0 4 700 17 8
+
+ /* IDSEL 0x16 AD22*/
+ b000 0 0 1 700 17 8
+ b000 0 0 2 700 14 8
+ b000 0 0 3 700 15 8
+ b000 0 0 4 700 16 8
+
+ /* IDSEL 0x17 AD23*/
+ b800 0 0 1 700 16 8
+ b800 0 0 2 700 17 8
+ b800 0 0 3 700 14 8
+ b800 0 0 4 700 15 8
+
+ /* IDSEL 0x18 AD24*/
+ c000 0 0 1 700 15 8
+ c000 0 0 2 700 16 8
+ c000 0 0 3 700 17 8
+ c000 0 0 4 700 14 8>;
+ interrupt-parent = <700>;
+ interrupts = <42 8>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 a0000000 a0000000 0 10000000
+ 42000000 0 80000000 80000000 0 10000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <8500 100>;
+ compatible = "83xx";
+ device_type = "pci";
+ };
+
+ pic@700 {
+ linux,phandle = <700>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <700 100>;
+ built-in;
+ device_type = "ipic";
+ };
+
+ par_io@1400 {
+ reg = <1400 100>;
+ device_type = "par_io";
+ num-ports = <7>;
+
+ ucc_pin@01 {
+ linux,phandle = <140001>;
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 3 1 0 1 0 /* TxD0 */
+ 0 4 1 0 1 0 /* TxD1 */
+ 0 5 1 0 1 0 /* TxD2 */
+ 0 6 1 0 1 0 /* TxD3 */
+ 1 6 1 0 3 0 /* TxD4 */
+ 1 7 1 0 1 0 /* TxD5 */
+ 1 9 1 0 2 0 /* TxD6 */
+ 1 a 1 0 2 0 /* TxD7 */
+ 0 9 2 0 1 0 /* RxD0 */
+ 0 a 2 0 1 0 /* RxD1 */
+ 0 b 2 0 1 0 /* RxD2 */
+ 0 c 2 0 1 0 /* RxD3 */
+ 0 d 2 0 1 0 /* RxD4 */
+ 1 1 2 0 2 0 /* RxD5 */
+ 1 0 2 0 2 0 /* RxD6 */
+ 1 4 2 0 2 0 /* RxD7 */
+ 0 7 1 0 1 0 /* TX_EN */
+ 0 8 1 0 1 0 /* TX_ER */
+ 0 f 2 0 1 0 /* RX_DV */
+ 0 10 2 0 1 0 /* RX_ER */
+ 0 0 2 0 1 0 /* RX_CLK */
+ 2 9 1 0 3 0 /* GTX_CLK - CLK10 */
+ 2 8 2 0 1 0>; /* GTX125 - CLK9 */
+ };
+ ucc_pin@02 {
+ linux,phandle = <140002>;
+ pio-map = <
+ /* port pin dir open_drain assignment has_irq */
+ 0 11 1 0 1 0 /* TxD0 */
+ 0 12 1 0 1 0 /* TxD1 */
+ 0 13 1 0 1 0 /* TxD2 */
+ 0 14 1 0 1 0 /* TxD3 */
+ 1 2 1 0 1 0 /* TxD4 */
+ 1 3 1 0 2 0 /* TxD5 */
+ 1 5 1 0 3 0 /* TxD6 */
+ 1 8 1 0 3 0 /* TxD7 */
+ 0 17 2 0 1 0 /* RxD0 */
+ 0 18 2 0 1 0 /* RxD1 */
+ 0 19 2 0 1 0 /* RxD2 */
+ 0 1a 2 0 1 0 /* RxD3 */
+ 0 1b 2 0 1 0 /* RxD4 */
+ 1 c 2 0 2 0 /* RxD5 */
+ 1 d 2 0 3 0 /* RxD6 */
+ 1 b 2 0 2 0 /* RxD7 */
+ 0 15 1 0 1 0 /* TX_EN */
+ 0 16 1 0 1 0 /* TX_ER */
+ 0 1d 2 0 1 0 /* RX_DV */
+ 0 1e 2 0 1 0 /* RX_ER */
+ 0 1f 2 0 1 0 /* RX_CLK */
+ 2 2 1 0 2 0 /* GTX_CLK - CLK10 */
+ 2 3 2 0 1 0 /* GTX125 - CLK4 */
+ 0 1 3 0 2 0 /* MDIO */
+ 0 2 1 0 1 0>; /* MDC */
+ };
+
+ };
+ };
+
+ qe@e0100000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ model = "QE";
+ ranges = <0 e0100000 00100000>;
+ reg = <e0100000 480>;
+ brg-frequency = <0>;
+ bus-frequency = <179A7B00>;
+
+ muram@10000 {
+ device_type = "muram";
+ ranges = <0 00010000 0000c000>;
+
+ data-only@0{
+ reg = <0 c000>;
+ };
+ };
+
+ spi@4c0 {
+ device_type = "spi";
+ compatible = "fsl_spi";
+ reg = <4c0 40>;
+ interrupts = <2>;
+ interrupt-parent = <80>;
+ mode = "cpu";
+ };
+
+ spi@500 {
+ device_type = "spi";
+ compatible = "fsl_spi";
+ reg = <500 40>;
+ interrupts = <1>;
+ interrupt-parent = <80>;
+ mode = "cpu";
+ };
+
+ usb@6c0 {
+ device_type = "usb";
+ compatible = "qe_udc";
+ reg = <6c0 40 8B00 100>;
+ interrupts = <b>;
+ interrupt-parent = <80>;
+ mode = "slave";
+ };
+
+ ucc@2000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ model = "UCC";
+ device-id = <1>;
+ reg = <2000 200>;
+ interrupts = <20>;
+ interrupt-parent = <80>;
+ mac-address = [ 00 04 9f 00 23 23 ];
+ rx-clock = <0>;
+ tx-clock = <19>;
+ phy-handle = <212000>;
+ pio-handle = <140001>;
+ };
+
+ ucc@3000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ model = "UCC";
+ device-id = <2>;
+ reg = <3000 200>;
+ interrupts = <21>;
+ interrupt-parent = <80>;
+ mac-address = [ 00 11 22 33 44 55 ];
+ rx-clock = <0>;
+ tx-clock = <14>;
+ phy-handle = <212001>;
+ pio-handle = <140002>;
+ };
+
+ mdio@2120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2120 18>;
+ device_type = "mdio";
+ compatible = "ucc_geth_phy";
+
+ ethernet-phy@00 {
+ linux,phandle = <212000>;
+ interrupt-parent = <700>;
+ interrupts = <11 2>;
+ reg = <0>;
+ device_type = "ethernet-phy";
+ interface = <6>; //ENET_1000_GMII
+ };
+ ethernet-phy@01 {
+ linux,phandle = <212001>;
+ interrupt-parent = <700>;
+ interrupts = <12 2>;
+ reg = <1>;
+ device_type = "ethernet-phy";
+ interface = <6>;
+ };
+ };
+
+ qeic@80 {
+ linux,phandle = <80>;
+ interrupt-controller;
+ device_type = "qeic";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <80 80>;
+ built-in;
+ big-endian;
+ interrupts = <20 8 21 8>; //high:32 low:33
+ interrupt-parent = <700>;
+ };
+
+ };
+};
--
1.4.2.1
^ permalink raw reply related
* [PATCH 9/15] Add MPC8360EMDS board support
From: Kim Phillips @ 2006-09-30 23:35 UTC (permalink / raw)
To: linuxppc-dev
The patch adds MPC8360EMDS board support.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Yin Olivia <hong-hua.yin@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/configs/mpc8360emds_defconfig | 1018 ++++++++++++++++++++++++++++
arch/powerpc/platforms/83xx/Kconfig | 13
arch/powerpc/platforms/83xx/Makefile | 1
arch/powerpc/platforms/83xx/mpc8360e_pb.c | 220 ++++++
arch/powerpc/platforms/83xx/mpc8360e_pb.h | 25 +
5 files changed, 1277 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/mpc8360emds_defconfig b/arch/powerpc/configs/mpc8360emds_defconfig
new file mode 100644
index 0000000..c070341
--- /dev/null
+++ b/arch/powerpc/configs/mpc8360emds_defconfig
@@ -0,0 +1,1018 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.18
+# Thu Sep 21 18:14:27 2006
+#
+# CONFIG_PPC64 is not set
+CONFIG_PPC32=y
+CONFIG_PPC_MERGE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_IRQ_PER_CPU=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_PPC_UDBG_16550=y
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_DEFAULT_UIMAGE=y
+
+#
+# Processor support
+#
+# CONFIG_CLASSIC32 is not set
+# CONFIG_PPC_52xx is not set
+# CONFIG_PPC_82xx is not set
+CONFIG_PPC_83xx=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_86xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_8xx is not set
+# CONFIG_E200 is not set
+CONFIG_6xx=y
+CONFIG_83xx=y
+CONFIG_PPC_FPU=y
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_SMP is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+# CONFIG_RELAY is not set
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL=y
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+# CONFIG_EPOLL is not set
+CONFIG_SHMEM=y
+CONFIG_SLAB=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_SLOB is not set
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+# CONFIG_KMOD is not set
+
+#
+# Block layer
+#
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_QUICC_ENGINE=y
+CONFIG_PPC_GEN550=y
+# CONFIG_WANT_EARLY_SERIAL is not set
+
+#
+# Platform support
+#
+# CONFIG_MPC834x_SYS is not set
+# CONFIG_MPC834x_ITX is not set
+CONFIG_MPC8360E_PB=y
+CONFIG_PPC_MPC836x=y
+# CONFIG_MPIC is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+# CONFIG_PM is not set
+CONFIG_SECCOMP=y
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_GENERIC_ISA_DMA=y
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_FSL_SOC=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_PCIEPORTBUS is not set
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+
+#
+# PCI Hotplug Support
+#
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_HIGHMEM_START=0xfe000000
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_TASK_SIZE=0x80000000
+CONFIG_BOOT_LOAD=0x00800000
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+# CONFIG_NETDEBUG is not set
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_BIC=y
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+
+#
+# DCCP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_DCCP is not set
+
+#
+# SCTP Configuration (EXPERIMENTAL)
+#
+# CONFIG_IP_SCTP is not set
+
+#
+# TIPC Configuration (EXPERIMENTAL)
+#
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_IEEE80211 is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=32768
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# ATA/ATAPI/MFM/RLL support
+#
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+# CONFIG_BLK_DEV_SD is not set
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI Transport Attributes
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_SATA is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
+# CONFIG_FUSION_SAS is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+
+#
+# Macintosh device drivers
+#
+# CONFIG_WINDFARM is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+
+#
+# PHY device support
+#
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_PCI is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_GIANFAR is not set
+CONFIG_UCC_GETH=y
+# CONFIG_UGETH_NAPI is not set
+# CONFIG_UGETH_MAGIC_PACKET is not set
+# CONFIG_UGETH_FILTERING is not set
+# CONFIG_UGETH_TX_ON_DEMOND is not set
+
+#
+# Ethernet (10000 Mbit)
+#
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_MYRI10GE is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_TSDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+
+#
+# Watchdog Cards
+#
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_83xx_WDT=y
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_NVRAM is not set
+CONFIG_GEN_RTC=y
+# CONFIG_GEN_RTC_X is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+
+#
+# I2C support
+#
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+CONFIG_I2C_MPC=y
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+# CONFIG_I2C_PCA_ISA is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+
+#
+# Hardware Monitoring support
+#
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_ABITUGURU is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ASB100 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_FSCHER is not set
+# CONFIG_SENSORS_FSCPOS is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Misc devices
+#
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+CONFIG_VIDEO_V4L2=y
+
+#
+# Digital Video Broadcasting Devices
+#
+# CONFIG_DVB is not set
+
+#
+# Graphics support
+#
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# MMC/SD Card support
+#
+# CONFIG_MMC is not set
+
+#
+# LED devices
+#
+# CONFIG_NEW_LEDS is not set
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+#
+
+#
+# Real Time Clock
+#
+# CONFIG_RTC_CLASS is not set
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+# CONFIG_MSDOS_PARTITION is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+
+#
+# Native Language Support
+#
+# CONFIG_NLS is not set
+
+#
+# QE Options
+#
+# CONFIG_UCC_SLOW is not set
+CONFIG_UCC_FAST=y
+CONFIG_UCC=y
+
+#
+# Library routines
+#
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+CONFIG_CRC32=y
+# CONFIG_LIBCRC32C is not set
+CONFIG_PLIST=y
+
+#
+# Instrumentation Support
+#
+# CONFIG_PROFILING is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_DEBUG_FS is not set
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_SERIAL_TEXT_DEBUG is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Hardware crypto devices
+#
diff --git a/arch/powerpc/platforms/83xx/Kconfig b/arch/powerpc/platforms/83xx/Kconfig
index 5fe7b7f..83dfded 100644
--- a/arch/powerpc/platforms/83xx/Kconfig
+++ b/arch/powerpc/platforms/83xx/Kconfig
@@ -25,6 +25,13 @@ config MPC834x_ITX
Be aware that PCI initialization is the bootloader's
responsiblilty.
+config MPC8360E_PB
+ bool "Freescale MPC8360E PB"
+ select DEFAULT_UIMAGE
+ select QUICC_ENGINE
+ help
+ This option enables support for the MPC836x EMDS Processor Board.
+
endchoice
config MPC834x
@@ -33,4 +40,10 @@ config MPC834x
select PPC_INDIRECT_PCI
default y if MPC834x_SYS || MPC834x_ITX
+config PPC_MPC836x
+ bool
+ select PPC_UDBG_16550
+ select PPC_INDIRECT_PCI
+ default y if MPC8360E_PB
+
endmenu
diff --git a/arch/powerpc/platforms/83xx/Makefile b/arch/powerpc/platforms/83xx/Makefile
index 9387a11..0da2d0d 100644
--- a/arch/powerpc/platforms/83xx/Makefile
+++ b/arch/powerpc/platforms/83xx/Makefile
@@ -5,3 +5,4 @@ obj-y := misc.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_MPC834x_SYS) += mpc834x_sys.o
obj-$(CONFIG_MPC834x_ITX) += mpc834x_itx.o
+obj-$(CONFIG_MPC8360E_PB) += mpc8360e_pb.o
diff --git a/arch/powerpc/platforms/83xx/mpc8360e_pb.c b/arch/powerpc/platforms/83xx/mpc8360e_pb.c
new file mode 100644
index 0000000..4f9fd65
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/mpc8360e_pb.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Li Yang <LeoLi@freescale.com>
+ * Yin Olivia <Hong-hua.Yin@freescale.com>
+ *
+ * Description:
+ * MPC8360E MDS PB board specific routines.
+ *
+ * Changelog:
+ * Jun 21, 2006 Initial version
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/reboot.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/root_dev.h>
+#include <linux/initrd.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/time.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ipic.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <sysdev/fsl_soc.h>
+#include <asm/qe.h>
+#include <asm/qe_ic.h>
+
+#include "mpc83xx.h"
+#include "mpc8360e_pb.h"
+
+#undef DEBUG
+#ifdef DEBUG
+#define DBG(fmt...) udbg_printf(fmt)
+#else
+#define DBG(fmt...)
+#endif
+
+#ifndef CONFIG_PCI
+unsigned long isa_io_base = 0;
+unsigned long isa_mem_base = 0;
+#endif
+
+static u8 *bcsr_regs = NULL;
+
+u8 *get_bcsr(void)
+{
+ return bcsr_regs;
+}
+
+/* ************************************************************************
+ *
+ * Setup the architecture
+ *
+ */
+static void __init mpc8360_sys_setup_arch(void)
+{
+ struct device_node *np;
+
+ if (ppc_md.progress)
+ ppc_md.progress("mpc8360_sys_setup_arch()", 0);
+
+ np = of_find_node_by_type(NULL, "cpu");
+ if (np != 0) {
+ unsigned int *fp =
+ (int *)get_property(np, "clock-frequency", NULL);
+ if (fp != 0)
+ loops_per_jiffy = *fp / HZ;
+ else
+ loops_per_jiffy = 50000000 / HZ;
+ of_node_put(np);
+ }
+
+ /* Map BCSR area */
+ np = of_find_node_by_name(NULL, "bcsr");
+ if (np != 0) {
+ struct resource res;
+
+ of_address_to_resource(np, 0, &res);
+ bcsr_regs = ioremap(res.start, res.end - res.start +1);
+ of_node_put(np);
+ }
+
+#ifdef CONFIG_PCI
+ for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
+ add_bridge(np);
+
+ ppc_md.pci_swizzle = common_swizzle;
+ ppc_md.pci_exclude_device = mpc83xx_exclude_device;
+#endif
+
+#ifdef CONFIG_QUICC_ENGINE
+ qe_reset();
+
+ if ((np = of_find_node_by_name(np, "par_io")) != NULL) {
+ par_io_init(np);
+ of_node_put(np);
+
+ for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
+ par_io_of_config(np);
+ }
+
+ if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
+ != NULL){
+ /* Reset the Ethernet PHY */
+ bcsr_regs[9] &= ~0x20;
+ udelay(1000);
+ bcsr_regs[9] |= 0x20;
+ iounmap(bcsr_regs);
+ of_node_put(np);
+ }
+
+#endif /* CONFIG_QUICC_ENGINE */
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ if (initrd_start)
+ ROOT_DEV = Root_RAM0;
+ else
+#endif
+#ifdef CONFIG_ROOT_NFS
+ ROOT_DEV = Root_NFS;
+#else
+ ROOT_DEV = Root_HDA1;
+#endif
+}
+
+void __init mpc8360_sys_init_IRQ(void)
+{
+
+ struct device_node *np;
+
+ np = of_find_node_by_type(NULL, "ipic");
+ if (!np)
+ return;
+
+ ipic_init(np, 0);
+
+ /* Initialize the default interrupt mapping priorities,
+ * in case the boot rom changed something on us.
+ */
+ ipic_set_default_priority();
+ of_node_put(np);
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_node_by_type(NULL, "qeic");
+ if (!np)
+ return;
+
+ qe_ic_init(np, 0);
+ of_node_put(np);
+#endif /* CONFIG_QUICC_ENGINE */
+}
+
+#if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
+extern ulong ds1374_get_rtc_time(void);
+extern int ds1374_set_rtc_time(ulong);
+
+static int __init mpc8360_rtc_hookup(void)
+{
+ struct timespec tv;
+
+ ppc_md.get_rtc_time = ds1374_get_rtc_time;
+ ppc_md.set_rtc_time = ds1374_set_rtc_time;
+
+ tv.tv_nsec = 0;
+ tv.tv_sec = (ppc_md.get_rtc_time) ();
+ do_settimeofday(&tv);
+
+ return 0;
+}
+
+late_initcall(mpc8360_rtc_hookup);
+#endif
+
+/*
+ * Called very early, MMU is off, device-tree isn't unflattened
+ */
+static int __init mpc8360_sys_probe(void)
+{
+ char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
+ "model", NULL);
+ if (model == NULL)
+ return 0;
+ if (strcmp(model, "MPC8360EPB"))
+ return 0;
+
+ DBG("MPC8360EMDS-PB found\n");
+
+ return 1;
+}
+
+define_machine(mpc8360_sys) {
+ .name = "MPC8360E PB",
+ .probe = mpc8360_sys_probe,
+ .setup_arch = mpc8360_sys_setup_arch,
+ .init_IRQ = mpc8360_sys_init_IRQ,
+ .get_irq = ipic_get_irq,
+ .restart = mpc83xx_restart,
+ .time_init = mpc83xx_time_init,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/83xx/mpc8360e_pb.h b/arch/powerpc/platforms/83xx/mpc8360e_pb.h
new file mode 100644
index 0000000..02a05d9
--- /dev/null
+++ b/arch/powerpc/platforms/83xx/mpc8360e_pb.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Li Yang <LeoLi@freescale.com>
+ * Yin Olivia <Hong-hua.Yin@freescale.com>
+ *
+ * Description:
+ * MPC8360E MDS PB board specific header.
+ *
+ * Changelog:
+ * Jun 21, 2006 Initial version
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __MACH_MPC8360E_PB_H__
+#define __MACH_MPC8360E_PB_H__
+
+extern u8 *get_bcsr(void);
+
+#endif /* __MACH_MPC8360E_PB_H__ */
--
1.4.2.1
^ permalink raw reply related
* [PATCH 8/15] qe_lib: Add QE SoC support
From: Kim Phillips @ 2006-09-30 23:34 UTC (permalink / raw)
To: linuxppc-dev
qe_lib: Add QE SoC support
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/sysdev/qe_lib/qe.c | 176 +++++++++++++++++++++++++++++++++++++++
include/linux/fsl_devices.h | 39 ++++++++-
2 files changed, 214 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
new file mode 100644
index 0000000..f628759
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Author: Li Yang <LeoLi@freescale.com>
+ *
+ * Description:
+ * FSL QE SOC setup.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/major.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/prom.h>
+#include <sysdev/fsl_soc.h>
+#include <mm/mmu_decl.h>
+
+static phys_addr_t qebase = -1;
+
+phys_addr_t get_qe_base(void)
+{
+ struct device_node *qe;
+
+ if (qebase != -1)
+ return qebase;
+
+ qe = of_find_node_by_type(NULL, "qe");
+ if (qe) {
+ unsigned int size;
+ void *prop = get_property(qe, "reg", &size);
+ qebase = of_translate_address(qe, prop);
+ of_node_put(qe);
+ };
+
+ return qebase;
+}
+
+EXPORT_SYMBOL(get_qe_base);
+
+static int __init ucc_geth_of_init(void)
+{
+ struct device_node *np;
+ unsigned int i, ucc_num;
+ struct platform_device *ugeth_dev;
+ struct resource res;
+ int ret;
+
+ for (np = NULL, i = 0;
+ (np = of_find_compatible_node(np, "network", "ucc_geth")) != NULL;
+ i++) {
+ struct resource r[2];
+ struct device_node *phy, *mdio;
+ struct ucc_geth_platform_data ugeth_data;
+ unsigned int *id;
+ char *model;
+ void *mac_addr;
+ phandle *ph;
+
+ memset(r, 0, sizeof(r));
+ memset(&ugeth_data, 0, sizeof(ugeth_data));
+
+ ret = of_address_to_resource(np, 0, &r[0]);
+ if (ret)
+ goto err;
+
+ ugeth_data.phy_reg_addr = r[0].start;
+ r[1].start = r[1].end = irq_of_parse_and_map(np, 0);
+ r[1].flags = IORESOURCE_IRQ;
+
+ model = get_property(np, "model", NULL);
+ ucc_num = *((u32 *) get_property(np, "device-id", NULL));
+ if ((strstr(model, "UCC") == NULL) ||
+ (ucc_num < 1) || (ucc_num > 8)) {
+ ret = -ENODEV;
+ goto err;
+ }
+
+ ugeth_dev =
+ platform_device_register_simple("ucc_geth", ucc_num - 1,
+ &r[0], 2);
+
+ if (IS_ERR(ugeth_dev)) {
+ ret = PTR_ERR(ugeth_dev);
+ goto err;
+ }
+
+ mac_addr = get_property(np, "mac-address", NULL);
+
+ memcpy(ugeth_data.mac_addr, mac_addr, 6);
+
+ ugeth_data.rx_clock = *((u32 *) get_property(np, "rx-clock",
+ NULL));
+ ugeth_data.tx_clock = *((u32 *) get_property(np, "tx-clock",
+ NULL));
+
+ ph = (phandle *) get_property(np, "phy-handle", NULL);
+ phy = of_find_node_by_phandle(*ph);
+
+ if (phy == NULL) {
+ ret = -ENODEV;
+ goto unreg;
+ }
+
+ mdio = of_get_parent(phy);
+
+ id = (u32 *) get_property(phy, "reg", NULL);
+ ret = of_address_to_resource(mdio, 0, &res);
+ if (ret) {
+ of_node_put(phy);
+ of_node_put(mdio);
+ goto unreg;
+ }
+
+ ugeth_data.phy_id = *id;
+
+ ugeth_data.phy_interrupt = irq_of_parse_and_map(phy, 0);;
+ ugeth_data.phy_interface = *((u32 *) get_property(phy,
+ "interface", NULL));
+
+ /* FIXME: Work around for early chip rev. */
+ /* There's a bug in initial chip rev(s) in the RGMII ac */
+ /* timing. */
+ /* The following compensates by writing to the reserved */
+ /* QE Port Output Hold Registers (CPOH1?). */
+ if ((ugeth_data.phy_interface == ENET_1000_RGMII) ||
+ (ugeth_data.phy_interface == ENET_100_RGMII) ||
+ (ugeth_data.phy_interface == ENET_10_RGMII)) {
+ u32 *tmp_reg = (u32 *) ioremap(get_immrbase()
+ + 0x14A8, 0x4);
+ u32 tmp_val = in_be32(tmp_reg);
+ if (ucc_num == 1)
+ out_be32(tmp_reg, tmp_val | 0x00003000);
+ else if (ucc_num == 2)
+ out_be32(tmp_reg, tmp_val | 0x0c000000);
+ iounmap(tmp_reg);
+ }
+
+ if (ugeth_data.phy_interrupt != 0)
+ ugeth_data.board_flags |= FSL_UGETH_BRD_HAS_PHY_INTR;
+
+ of_node_put(phy);
+ of_node_put(mdio);
+
+ ret = platform_device_add_data(ugeth_dev, &ugeth_data,
+ sizeof(struct ucc_geth_platform_data));
+ if (ret)
+ goto unreg;
+ }
+
+ return 0;
+
+unreg:
+ platform_device_unregister(ugeth_dev);
+err:
+ return ret;
+}
+
+arch_initcall(ucc_geth_of_init);
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 16fbe59..a16d82f 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -83,7 +83,6 @@ struct fsl_i2c_platform_data {
#define FSL_I2C_DEV_SEPARATE_DFSRR 0x00000001
#define FSL_I2C_DEV_CLOCK_5200 0x00000002
-
enum fsl_usb2_operating_modes {
FSL_USB2_MPH_HOST,
FSL_USB2_DR_HOST,
@@ -121,5 +120,43 @@ struct fsl_spi_platform_data {
u32 sysclk;
};
+/* Ethernet interface (phy management and speed)
+*/
+typedef enum enet_interface {
+ ENET_10_MII, /* 10 Base T, MII interface */
+ ENET_10_RMII, /* 10 Base T, RMII interface */
+ ENET_10_RGMII, /* 10 Base T, RGMII interface */
+ ENET_100_MII, /* 100 Base T, MII interface */
+ ENET_100_RMII, /* 100 Base T, RMII interface */
+ ENET_100_RGMII, /* 100 Base T, RGMII interface */
+ ENET_1000_GMII, /* 1000 Base T, GMII interface */
+ ENET_1000_RGMII, /* 1000 Base T, RGMII interface */
+ ENET_1000_TBI, /* 1000 Base T, TBI interface */
+ ENET_1000_RTBI /* 1000 Base T, RTBI interface */
+} enet_interface_e;
+
+struct ucc_geth_platform_data {
+ /* device specific information */
+ u32 device_flags;
+ u32 phy_reg_addr;
+
+ /* board specific information */
+ u32 board_flags;
+ u8 rx_clock;
+ u8 tx_clock;
+ u32 phy_id;
+ enet_interface_e phy_interface;
+ u32 phy_interrupt;
+ u8 mac_addr[6];
+};
+
+/* Flags related to UCC Gigabit Ethernet device features */
+#define FSL_UGETH_DEV_HAS_GIGABIT 0x00000001
+#define FSL_UGETH_DEV_HAS_COALESCE 0x00000002
+#define FSL_UGETH_DEV_HAS_RMON 0x00000004
+
+/* Flags in ucc_geth_platform_data */
+#define FSL_UGETH_BRD_HAS_PHY_INTR 0x00000001 /* if not set use a timer */
+
#endif /* _FSL_DEVICE_H_ */
#endif /* __KERNEL__ */
--
1.4.2.1
^ permalink raw reply related
* [PATCH 6/15] qe_lib: Add UCC common API
From: Kim Phillips @ 2006-09-30 23:34 UTC (permalink / raw)
To: linuxppc-dev
qe_lib: Add UCC common API
Signed-off-by: Shlomi Gridish <gridish@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/sysdev/qe_lib/ucc.c | 346 ++++++++++++++++++++++++++++
arch/powerpc/sysdev/qe_lib/ucc_fast.c | 408 +++++++++++++++++++++++++++++++++
arch/powerpc/sysdev/qe_lib/ucc_slow.c | 406 +++++++++++++++++++++++++++++++++
include/asm-powerpc/ucc.h | 84 +++++++
include/asm-powerpc/ucc_fast.h | 254 +++++++++++++++++++++
include/asm-powerpc/ucc_slow.h | 304 +++++++++++++++++++++++++
6 files changed, 1802 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/ucc.c b/arch/powerpc/sysdev/qe_lib/ucc.c
new file mode 100644
index 0000000..edb0acb
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/ucc.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors: Shlomi Gridish <gridish@freescale.com>
+ * Li Yang <leoli@freescale.com>
+ *
+ * Description:
+ * QE UCC API Set - UCC specific routines implementations.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+#include <asm/ucc.h>
+
+static DEFINE_SPINLOCK(ucc_lock);
+
+int ucc_set_qe_mux_mii_mng(int ucc_num)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&ucc_lock, flags);
+ out_be32(&qe_immr->qmx.cmxgcr,
+ ((in_be32(&qe_immr->qmx.cmxgcr) &
+ ~QE_CMXGCR_MII_ENET_MNG) |
+ (ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT)));
+ spin_unlock_irqrestore(&ucc_lock, flags);
+
+ return 0;
+}
+
+int ucc_set_type(int ucc_num, struct ucc_common *regs,
+ enum ucc_speed_type speed)
+{
+ u8 guemr = 0;
+
+ /* check if the UCC number is in range. */
+ if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
+ return -EINVAL;
+
+ guemr = regs->guemr;
+ guemr &= ~(UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX);
+ switch (speed) {
+ case UCC_SPEED_TYPE_SLOW:
+ guemr |= (UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX);
+ break;
+ case UCC_SPEED_TYPE_FAST:
+ guemr |= (UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX);
+ break;
+ default:
+ return -EINVAL;
+ }
+ regs->guemr = guemr;
+
+ return 0;
+}
+
+int ucc_init_guemr(struct ucc_common *regs)
+{
+ u8 guemr = 0;
+
+ if (!regs)
+ return -EINVAL;
+
+ /* Set bit 3 (which is reserved in the GUEMR register) to 1 */
+ guemr = UCC_GUEMR_SET_RESERVED3;
+
+ regs->guemr = guemr;
+
+ return 0;
+}
+
+static void get_cmxucr_reg(int ucc_num, volatile u32 ** p_cmxucr, u8 * reg_num,
+ u8 * shift)
+{
+ switch (ucc_num) {
+ case (0):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr1);
+ *reg_num = 1;
+ *shift = 16;
+ break;
+ case (2):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr1);
+ *reg_num = 1;
+ *shift = 0;
+ break;
+ case (4):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr2);
+ *reg_num = 2;
+ *shift = 16;
+ break;
+ case (6):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr2);
+ *reg_num = 2;
+ *shift = 0;
+ break;
+ case (1):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr3);
+ *reg_num = 3;
+ *shift = 16;
+ break;
+ case (3):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr3);
+ *reg_num = 3;
+ *shift = 0;
+ break;
+ case (5):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr4);
+ *reg_num = 4;
+ *shift = 16;
+ break;
+ case (7):
+ *p_cmxucr = &(qe_immr->qmx.cmxucr4);
+ *reg_num = 4;
+ *shift = 0;
+ break;
+ default:
+ break;
+ }
+}
+
+int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask)
+{
+ volatile u32 *p_cmxucr;
+ u8 reg_num;
+ u8 shift;
+
+ /* check if the UCC number is in range. */
+ if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
+ return -EINVAL;
+
+ get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift);
+
+ if (set)
+ out_be32(p_cmxucr, in_be32(p_cmxucr) | (mask << shift));
+ else
+ out_be32(p_cmxucr, in_be32(p_cmxucr) & ~(mask << shift));
+
+ return 0;
+}
+
+int ucc_set_qe_mux_rxtx(int ucc_num, qe_clock_e clock, comm_dir_e mode)
+{
+ volatile u32 *p_cmxucr;
+ u8 reg_num;
+ u8 shift;
+ u32 clockBits;
+ u32 clockMask;
+ int source = -1;
+
+ /* check if the UCC number is in range. */
+ if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
+ return -EINVAL;
+
+ if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) {
+ printk(KERN_ERR
+ "ucc_set_qe_mux_rxtx: bad comm mode type passed.");
+ return -EINVAL;
+ }
+
+ get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift);
+
+ switch (reg_num) {
+ case (1):
+ switch (clock) {
+ case (QE_BRG1):
+ source = 1;
+ break;
+ case (QE_BRG2):
+ source = 2;
+ break;
+ case (QE_BRG7):
+ source = 3;
+ break;
+ case (QE_BRG8):
+ source = 4;
+ break;
+ case (QE_CLK9):
+ source = 5;
+ break;
+ case (QE_CLK10):
+ source = 6;
+ break;
+ case (QE_CLK11):
+ source = 7;
+ break;
+ case (QE_CLK12):
+ source = 8;
+ break;
+ case (QE_CLK15):
+ source = 9;
+ break;
+ case (QE_CLK16):
+ source = 10;
+ break;
+ default:
+ source = -1;
+ break;
+ }
+ break;
+ case (2):
+ switch (clock) {
+ case (QE_BRG5):
+ source = 1;
+ break;
+ case (QE_BRG6):
+ source = 2;
+ break;
+ case (QE_BRG7):
+ source = 3;
+ break;
+ case (QE_BRG8):
+ source = 4;
+ break;
+ case (QE_CLK13):
+ source = 5;
+ break;
+ case (QE_CLK14):
+ source = 6;
+ break;
+ case (QE_CLK19):
+ source = 7;
+ break;
+ case (QE_CLK20):
+ source = 8;
+ break;
+ case (QE_CLK15):
+ source = 9;
+ break;
+ case (QE_CLK16):
+ source = 10;
+ break;
+ default:
+ source = -1;
+ break;
+ }
+ break;
+ case (3):
+ switch (clock) {
+ case (QE_BRG9):
+ source = 1;
+ break;
+ case (QE_BRG10):
+ source = 2;
+ break;
+ case (QE_BRG15):
+ source = 3;
+ break;
+ case (QE_BRG16):
+ source = 4;
+ break;
+ case (QE_CLK3):
+ source = 5;
+ break;
+ case (QE_CLK4):
+ source = 6;
+ break;
+ case (QE_CLK17):
+ source = 7;
+ break;
+ case (QE_CLK18):
+ source = 8;
+ break;
+ case (QE_CLK7):
+ source = 9;
+ break;
+ case (QE_CLK8):
+ source = 10;
+ break;
+ default:
+ source = -1;
+ break;
+ }
+ break;
+ case (4):
+ switch (clock) {
+ case (QE_BRG13):
+ source = 1;
+ break;
+ case (QE_BRG14):
+ source = 2;
+ break;
+ case (QE_BRG15):
+ source = 3;
+ break;
+ case (QE_BRG16):
+ source = 4;
+ break;
+ case (QE_CLK5):
+ source = 5;
+ break;
+ case (QE_CLK6):
+ source = 6;
+ break;
+ case (QE_CLK21):
+ source = 7;
+ break;
+ case (QE_CLK22):
+ source = 8;
+ break;
+ case (QE_CLK7):
+ source = 9;
+ break;
+ case (QE_CLK8):
+ source = 10;
+ break;
+ default:
+ source = -1;
+ break;
+ }
+ break;
+ default:
+ source = -1;
+ break;
+ }
+
+ if (source == -1) {
+ printk(KERN_ERR
+ "ucc_set_qe_mux_rxtx: Bad combination of clock and UCC.");
+ return -ENOENT;
+ }
+
+ clockBits = (u32) source;
+ clockMask = QE_CMXUCR_TX_CLK_SRC_MASK;
+ if (mode == COMM_DIR_RX) {
+ clockBits <<= 4; /* Rx field is 4 bits to left of Tx field */
+ clockMask <<= 4; /* Rx field is 4 bits to left of Tx field */
+ }
+ clockBits <<= shift;
+ clockMask <<= shift;
+
+ out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clockMask) | clockBits);
+
+ return 0;
+}
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_fast.c b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
new file mode 100644
index 0000000..4312083
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
@@ -0,0 +1,408 @@
+/*
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors: Shlomi Gridish <gridish@freescale.com>
+ * Li Yang <leoli@freescale.com>
+ *
+ * Description:
+ * QE UCC Fast API Set - UCC Fast specific routines implementations.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+#include <linux/interrupt.h>
+
+#include <asm/io.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#include <asm/ucc.h>
+#include <asm/ucc_fast.h>
+
+#define uccf_printk(level, format, arg...) \
+ printk(level format "\n", ## arg)
+
+#define uccf_dbg(format, arg...) \
+ uccf_printk(KERN_DEBUG , format , ## arg)
+#define uccf_err(format, arg...) \
+ uccf_printk(KERN_ERR , format , ## arg)
+#define uccf_info(format, arg...) \
+ uccf_printk(KERN_INFO , format , ## arg)
+#define uccf_warn(format, arg...) \
+ uccf_printk(KERN_WARNING , format , ## arg)
+
+#ifdef UCCF_VERBOSE_DEBUG
+#define uccf_vdbg uccf_dbg
+#else
+#define uccf_vdbg(fmt, args...) do { } while (0)
+#endif /* UCCF_VERBOSE_DEBUG */
+
+void ucc_fast_dump_regs(ucc_fast_private_t * uccf)
+{
+ uccf_info("UCC%d Fast registers:", uccf->uf_info->ucc_num);
+ uccf_info("Base address: 0x%08x", (u32) uccf->uf_regs);
+
+ uccf_info("gumr : addr - 0x%08x, val - 0x%08x",
+ (u32) & uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
+ uccf_info("upsmr : addr - 0x%08x, val - 0x%08x",
+ (u32) & uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
+ uccf_info("utodr : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
+ uccf_info("udsr : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
+ uccf_info("ucce : addr - 0x%08x, val - 0x%08x",
+ (u32) & uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
+ uccf_info("uccm : addr - 0x%08x, val - 0x%08x",
+ (u32) & uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
+ uccf_info("uccs : addr - 0x%08x, val - 0x%02x",
+ (u32) & uccf->uf_regs->uccs, uccf->uf_regs->uccs);
+ uccf_info("urfb : addr - 0x%08x, val - 0x%08x",
+ (u32) & uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
+ uccf_info("urfs : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
+ uccf_info("urfet : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
+ uccf_info("urfset: addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->urfset,
+ in_be16(&uccf->uf_regs->urfset));
+ uccf_info("utfb : addr - 0x%08x, val - 0x%08x",
+ (u32) & uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
+ uccf_info("utfs : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
+ uccf_info("utfet : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
+ uccf_info("utftt : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
+ uccf_info("utpt : addr - 0x%08x, val - 0x%04x",
+ (u32) & uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
+ uccf_info("urtry : addr - 0x%08x, val - 0x%08x",
+ (u32) & uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
+ uccf_info("guemr : addr - 0x%08x, val - 0x%02x",
+ (u32) & uccf->uf_regs->guemr, uccf->uf_regs->guemr);
+}
+
+u32 ucc_fast_get_qe_cr_subblock(int uccf_num)
+{
+ switch (uccf_num) {
+ case (0):
+ return (QE_CR_SUBBLOCK_UCCFAST1);
+ case (1):
+ return (QE_CR_SUBBLOCK_UCCFAST2);
+ case (2):
+ return (QE_CR_SUBBLOCK_UCCFAST3);
+ case (3):
+ return (QE_CR_SUBBLOCK_UCCFAST4);
+ case (4):
+ return (QE_CR_SUBBLOCK_UCCFAST5);
+ case (5):
+ return (QE_CR_SUBBLOCK_UCCFAST6);
+ case (6):
+ return (QE_CR_SUBBLOCK_UCCFAST7);
+ case (7):
+ return (QE_CR_SUBBLOCK_UCCFAST8);
+ default:
+ return QE_CR_SUBBLOCK_INVALID;
+ }
+}
+
+void ucc_fast_transmit_on_demand(ucc_fast_private_t * uccf)
+{
+ out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
+}
+
+void ucc_fast_enable(ucc_fast_private_t * uccf, comm_dir_e mode)
+{
+ ucc_fast_t *uf_regs;
+ u32 gumr;
+
+ uf_regs = uccf->uf_regs;
+
+ /* Enable reception and/or transmission on this UCC. */
+ gumr = in_be32(&uf_regs->gumr);
+ if (mode & COMM_DIR_TX) {
+ gumr |= UCC_FAST_GUMR_ENT;
+ uccf->enabled_tx = 1;
+ }
+ if (mode & COMM_DIR_RX) {
+ gumr |= UCC_FAST_GUMR_ENR;
+ uccf->enabled_rx = 1;
+ }
+ out_be32(&uf_regs->gumr, gumr);
+}
+
+void ucc_fast_disable(ucc_fast_private_t * uccf, comm_dir_e mode)
+{
+ ucc_fast_t *uf_regs;
+ u32 gumr;
+
+ uf_regs = uccf->uf_regs;
+
+ /* Disable reception and/or transmission on this UCC. */
+ gumr = in_be32(&uf_regs->gumr);
+ if (mode & COMM_DIR_TX) {
+ gumr &= ~UCC_FAST_GUMR_ENT;
+ uccf->enabled_tx = 0;
+ }
+ if (mode & COMM_DIR_RX) {
+ gumr &= ~UCC_FAST_GUMR_ENR;
+ uccf->enabled_rx = 0;
+ }
+ out_be32(&uf_regs->gumr, gumr);
+}
+
+int ucc_fast_init(ucc_fast_info_t * uf_info, ucc_fast_private_t ** uccf_ret)
+{
+ ucc_fast_private_t *uccf;
+ ucc_fast_t *uf_regs;
+ u32 gumr = 0;
+ int ret;
+
+ uccf_vdbg("%s: IN", __FUNCTION__);
+
+ if (!uf_info)
+ return -EINVAL;
+
+ /* check if the UCC port number is in range. */
+ if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
+ uccf_err("ucc_fast_init: Illagal UCC number!");
+ return -EINVAL;
+ }
+
+ /* Check that 'max_rx_buf_length' is properly aligned (4). */
+ if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
+ uccf_err("ucc_fast_init: max_rx_buf_length not aligned.");
+ return -EINVAL;
+ }
+
+ /* Validate Virtual Fifo register values */
+ if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
+ uccf_err
+ ("ucc_fast_init: Virtual Fifo register urfs too small.");
+ return -EINVAL;
+ }
+
+ if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+ uccf_err
+ ("ucc_fast_init: Virtual Fifo register urfs not aligned.");
+ return -EINVAL;
+ }
+
+ if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+ uccf_err
+ ("ucc_fast_init: Virtual Fifo register urfet not aligned.");
+ return -EINVAL;
+ }
+
+ if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+ uccf_err
+ ("ucc_fast_init: Virtual Fifo register urfset not aligned.");
+ return -EINVAL;
+ }
+
+ if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+ uccf_err
+ ("ucc_fast_init: Virtual Fifo register utfs not aligned.");
+ return -EINVAL;
+ }
+
+ if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+ uccf_err
+ ("ucc_fast_init: Virtual Fifo register utfet not aligned.");
+ return -EINVAL;
+ }
+
+ if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
+ uccf_err
+ ("ucc_fast_init: Virtual Fifo register utftt not aligned.");
+ return -EINVAL;
+ }
+
+ uccf =
+ (ucc_fast_private_t *) kmalloc(sizeof(ucc_fast_private_t),
+ GFP_KERNEL);
+ if (!uccf) {
+ uccf_err
+ ("ucc_fast_init: No memory for UCC slow data structure!");
+ return -ENOMEM;
+ }
+ memset(uccf, 0, sizeof(ucc_fast_private_t));
+
+ /* Fill fast UCC structure */
+ uccf->uf_info = uf_info;
+ /* Set the PHY base address */
+ uccf->uf_regs =
+ (ucc_fast_t *) ioremap(uf_info->regs, sizeof(ucc_fast_t));
+ if (uccf->uf_regs == NULL) {
+ uccf_err
+ ("ucc_fast_init: No memory map for UCC slow controller!");
+ return -ENOMEM;
+ }
+
+ uccf->enabled_tx = 0;
+ uccf->enabled_rx = 0;
+ uccf->stopped_tx = 0;
+ uccf->stopped_rx = 0;
+ uf_regs = uccf->uf_regs;
+ uccf->p_ucce = (u32 *) & (uf_regs->ucce);
+ uccf->p_uccm = (u32 *) & (uf_regs->uccm);
+#ifdef STATISTICS
+ uccf->tx_frames = 0;
+ uccf->rx_frames = 0;
+ uccf->rx_discarded = 0;
+#endif /* STATISTICS */
+
+ /* Init Guemr register */
+ if ((ret = ucc_init_guemr((ucc_common_t *) (uf_regs)))) {
+ uccf_err("ucc_fast_init: Could not init the guemr register.");
+ ucc_fast_free(uccf);
+ return ret;
+ }
+
+ /* Set UCC to fast type */
+ if ((ret = ucc_set_type(uf_info->ucc_num,
+ (ucc_common_t *) (uf_regs),
+ UCC_SPEED_TYPE_FAST))) {
+ uccf_err("ucc_fast_init: Could not set type to fast.");
+ ucc_fast_free(uccf);
+ return ret;
+ }
+
+ uccf->mrblr = uf_info->max_rx_buf_length;
+
+ /* Set GUMR. */
+ /* For more details see the hardware spec. */
+ /* gumr starts as zero. */
+ if (uf_info->tci)
+ gumr |= UCC_FAST_GUMR_TCI;
+ gumr |= uf_info->ttx_trx;
+ if (uf_info->cdp)
+ gumr |= UCC_FAST_GUMR_CDP;
+ if (uf_info->ctsp)
+ gumr |= UCC_FAST_GUMR_CTSP;
+ if (uf_info->cds)
+ gumr |= UCC_FAST_GUMR_CDS;
+ if (uf_info->ctss)
+ gumr |= UCC_FAST_GUMR_CTSS;
+ if (uf_info->txsy)
+ gumr |= UCC_FAST_GUMR_TXSY;
+ if (uf_info->rsyn)
+ gumr |= UCC_FAST_GUMR_RSYN;
+ gumr |= uf_info->synl;
+ if (uf_info->rtsm)
+ gumr |= UCC_FAST_GUMR_RTSM;
+ gumr |= uf_info->renc;
+ if (uf_info->revd)
+ gumr |= UCC_FAST_GUMR_REVD;
+ gumr |= uf_info->tenc;
+ gumr |= uf_info->tcrc;
+ gumr |= uf_info->mode;
+ out_be32(&uf_regs->gumr, gumr);
+
+ /* Allocate memory for Tx Virtual Fifo */
+ uccf->ucc_fast_tx_virtual_fifo_base_offset =
+ qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+ if (IS_MURAM_ERR(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
+ uccf_err
+ ("ucc_fast_init: Can not allocate MURAM memory for "
+ "ucc_fast_tx_virtual_fifo_base_offset.");
+ uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
+ ucc_fast_free(uccf);
+ return -ENOMEM;
+ }
+
+ /* Allocate memory for Rx Virtual Fifo */
+ uccf->ucc_fast_rx_virtual_fifo_base_offset =
+ qe_muram_alloc(uf_info->urfs +
+ (u32)
+ UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
+ UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
+ if (IS_MURAM_ERR(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
+ uccf_err
+ ("ucc_fast_init: Can not allocate MURAM memory for "
+ "ucc_fast_rx_virtual_fifo_base_offset.");
+ uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
+ ucc_fast_free(uccf);
+ return -ENOMEM;
+ }
+
+ /* Set Virtual Fifo registers */
+ out_be16(&uf_regs->urfs, uf_info->urfs);
+ out_be16(&uf_regs->urfet, uf_info->urfet);
+ out_be16(&uf_regs->urfset, uf_info->urfset);
+ out_be16(&uf_regs->utfs, uf_info->utfs);
+ out_be16(&uf_regs->utfet, uf_info->utfet);
+ out_be16(&uf_regs->utftt, uf_info->utftt);
+ /* utfb, urfb are offsets from MURAM base */
+ out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
+ out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);
+
+ /* Mux clocking */
+ /* Grant Support */
+ ucc_set_qe_mux_grant(uf_info->ucc_num, uf_info->grant_support);
+ /* Breakpoint Support */
+ ucc_set_qe_mux_bkpt(uf_info->ucc_num, uf_info->brkpt_support);
+ /* Set Tsa or NMSI mode. */
+ ucc_set_qe_mux_tsa(uf_info->ucc_num, uf_info->tsa);
+ /* If NMSI (not Tsa), set Tx and Rx clock. */
+ if (!uf_info->tsa) {
+ /* Rx clock routing */
+ if (uf_info->rx_clock != QE_CLK_NONE) {
+ if (ucc_set_qe_mux_rxtx
+ (uf_info->ucc_num, uf_info->rx_clock,
+ COMM_DIR_RX)) {
+ uccf_err
+ ("ucc_fast_init: Illegal value for parameter 'RxClock'.");
+ ucc_fast_free(uccf);
+ return -EINVAL;
+ }
+ }
+ /* Tx clock routing */
+ if (uf_info->tx_clock != QE_CLK_NONE) {
+ if (ucc_set_qe_mux_rxtx
+ (uf_info->ucc_num, uf_info->tx_clock,
+ COMM_DIR_TX)) {
+ uccf_err
+ ("ucc_fast_init: Illegal value for parameter 'TxClock'.");
+ ucc_fast_free(uccf);
+ return -EINVAL;
+ }
+ }
+ }
+
+ /*
+ * INTERRUPTS
+ */
+ /* Set interrupt mask register at UCC level. */
+ out_be32(&uf_regs->uccm, uf_info->uccm_mask);
+
+ /* First, clear anything pending at UCC level, */
+ /* otherwise, old garbage may come through */
+ /* as soon as the dam is opened. */
+
+ /* Writing '1' clears */
+ out_be32(&uf_regs->ucce, 0xffffffff);
+
+ *uccf_ret = uccf;
+ return 0;
+}
+
+void ucc_fast_free(ucc_fast_private_t * uccf)
+{
+ if (!uccf)
+ return;
+
+ if (uccf->ucc_fast_tx_virtual_fifo_base_offset)
+ qe_muram_free(uccf->ucc_fast_tx_virtual_fifo_base_offset);
+
+ if (uccf->ucc_fast_rx_virtual_fifo_base_offset)
+ qe_muram_free(uccf->ucc_fast_rx_virtual_fifo_base_offset);
+
+ kfree(uccf);
+}
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_slow.c b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
new file mode 100644
index 0000000..a8232cd
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
@@ -0,0 +1,406 @@
+/*
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors: Shlomi Gridish <gridish@freescale.com>
+ * Li Yang <leoli@freescale.com>
+ *
+ * Description:
+ * QE UCC Slow API Set - UCC Slow specific routines implementations.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/stddef.h>
+#include <linux/interrupt.h>
+
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#include <asm/ucc.h>
+#include <asm/ucc_slow.h>
+
+#define uccs_printk(level, format, arg...) \
+ printk(level format "\n", ## arg)
+
+#define uccs_dbg(format, arg...) \
+ uccs_printk(KERN_DEBUG , format , ## arg)
+#define uccs_err(format, arg...) \
+ uccs_printk(KERN_ERR , format , ## arg)
+#define uccs_info(format, arg...) \
+ uccs_printk(KERN_INFO , format , ## arg)
+#define uccs_warn(format, arg...) \
+ uccs_printk(KERN_WARNING , format , ## arg)
+
+#ifdef UCCS_VERBOSE_DEBUG
+#define uccs_vdbg uccs_dbg
+#else
+#define uccs_vdbg(fmt, args...) do { } while (0)
+#endif /* UCCS_VERBOSE_DEBUG */
+
+u32 ucc_slow_get_qe_cr_subblock(int uccs_num)
+{
+ switch (uccs_num) {
+ case (0):
+ return (QE_CR_SUBBLOCK_UCCSLOW1);
+ case (1):
+ return (QE_CR_SUBBLOCK_UCCSLOW2);
+ case (2):
+ return (QE_CR_SUBBLOCK_UCCSLOW3);
+ case (3):
+ return (QE_CR_SUBBLOCK_UCCSLOW4);
+ case (4):
+ return (QE_CR_SUBBLOCK_UCCSLOW5);
+ case (5):
+ return (QE_CR_SUBBLOCK_UCCSLOW6);
+ case (6):
+ return (QE_CR_SUBBLOCK_UCCSLOW7);
+ case (7):
+ return (QE_CR_SUBBLOCK_UCCSLOW8);
+ default:
+ return QE_CR_SUBBLOCK_INVALID;
+ }
+}
+
+void ucc_slow_poll_transmitter_now(ucc_slow_private_t * uccs)
+{
+ out_be16(&uccs->us_regs->utodr, UCC_SLOW_TOD);
+}
+
+void ucc_slow_graceful_stop_tx(ucc_slow_private_t * uccs)
+{
+ ucc_slow_info_t *us_info = uccs->us_info;
+ u32 id;
+
+ id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+ qe_issue_cmd(QE_GRACEFUL_STOP_TX, id, (u8) QE_CR_PROTOCOL_UNSPECIFIED,
+ 0);
+}
+
+void ucc_slow_stop_tx(ucc_slow_private_t * uccs)
+{
+ ucc_slow_info_t *us_info = uccs->us_info;
+ u32 id;
+
+ id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+ qe_issue_cmd(QE_STOP_TX, id, (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
+}
+
+void ucc_slow_restart_tx(ucc_slow_private_t * uccs)
+{
+ ucc_slow_info_t *us_info = uccs->us_info;
+ u32 id;
+
+ id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+ qe_issue_cmd(QE_RESTART_TX, id, (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
+}
+
+void ucc_slow_enable(ucc_slow_private_t * uccs, comm_dir_e mode)
+{
+ ucc_slow_t *us_regs;
+ u32 gumr_l;
+
+ us_regs = uccs->us_regs;
+
+ /* Enable reception and/or transmission on this UCC. */
+ gumr_l = in_be32(&us_regs->gumr_l);
+ if (mode & COMM_DIR_TX) {
+ gumr_l |= UCC_SLOW_GUMR_L_ENT;
+ uccs->enabled_tx = 1;
+ }
+ if (mode & COMM_DIR_RX) {
+ gumr_l |= UCC_SLOW_GUMR_L_ENR;
+ uccs->enabled_rx = 1;
+ }
+ out_be32(&us_regs->gumr_l, gumr_l);
+}
+
+void ucc_slow_disable(ucc_slow_private_t * uccs, comm_dir_e mode)
+{
+ ucc_slow_t *us_regs;
+ u32 gumr_l;
+
+ us_regs = uccs->us_regs;
+
+ /* Disable reception and/or transmission on this UCC. */
+ gumr_l = in_be32(&us_regs->gumr_l);
+ if (mode & COMM_DIR_TX) {
+ gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
+ uccs->enabled_tx = 0;
+ }
+ if (mode & COMM_DIR_RX) {
+ gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
+ uccs->enabled_rx = 0;
+ }
+ out_be32(&us_regs->gumr_l, gumr_l);
+}
+
+int ucc_slow_init(ucc_slow_info_t * us_info, ucc_slow_private_t ** uccs_ret)
+{
+ u32 i;
+ ucc_slow_t *us_regs;
+ u32 gumr;
+ u8 function_code = 0;
+ u8 *bd;
+ ucc_slow_private_t *uccs;
+ u32 id;
+ u32 command;
+ int ret;
+
+ uccs_vdbg("%s: IN", __FUNCTION__);
+
+ if (!us_info)
+ return -EINVAL;
+
+ /* check if the UCC port number is in range. */
+ if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
+ uccs_err("ucc_slow_init: Illagal UCC number!");
+ return -EINVAL;
+ }
+
+ /* Set mrblr */
+ /* Check that 'max_rx_buf_length' is properly aligned (4), unless
+ rfw is 1, meaning that QE accepts one byte at a time, unlike normal
+ case when QE accepts 32 bits at a time. */
+ if ((!us_info->rfw)
+ && (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) {
+ uccs_err("max_rx_buf_length not aligned.");
+ return -EINVAL;
+ }
+
+ uccs =
+ (ucc_slow_private_t *) kmalloc(sizeof(ucc_slow_private_t),
+ GFP_KERNEL);
+ if (!uccs) {
+ uccs_err
+ ("ucc_slow_init: No memory for UCC slow data structure!");
+ return -ENOMEM;
+ }
+ memset(uccs, 0, sizeof(ucc_slow_private_t));
+
+ /* Fill slow UCC structure */
+ uccs->us_info = us_info;
+ uccs->saved_uccm = 0;
+ uccs->p_rx_frame = 0;
+ uccs->us_regs = us_info->us_regs;
+ us_regs = uccs->us_regs;
+ uccs->p_ucce = (u16 *) & (us_regs->ucce);
+ uccs->p_uccm = (u16 *) & (us_regs->uccm);
+#ifdef STATISTICS
+ uccs->rx_frames = 0;
+ uccs->tx_frames = 0;
+ uccs->rx_discarded = 0;
+#endif /* STATISTICS */
+
+ /* Get PRAM base */
+ uccs->us_pram_offset =
+ qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
+ if (IS_MURAM_ERR(uccs->us_pram_offset)) {
+ uccs_err
+ ("ucc_slow_init: Can not allocate MURAM memory " \
+ "for Slow UCC.");
+ ucc_slow_free(uccs);
+ return -ENOMEM;
+ }
+ id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+ qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, QE_CR_PROTOCOL_UNSPECIFIED,
+ (u32) uccs->us_pram_offset);
+
+ uccs->us_pram = qe_muram_addr(uccs->us_pram_offset);
+
+ /* Init Guemr register */
+ if ((ret = ucc_init_guemr((ucc_common_t *) (us_info->us_regs)))) {
+ uccs_err("ucc_slow_init: Could not init the guemr register.");
+ ucc_slow_free(uccs);
+ return ret;
+ }
+
+ /* Set UCC to slow type */
+ if ((ret = ucc_set_type(us_info->ucc_num,
+ (ucc_common_t *) (us_info->us_regs),
+ UCC_SPEED_TYPE_SLOW))) {
+ uccs_err("ucc_slow_init: Could not init the guemr register.");
+ ucc_slow_free(uccs);
+ return ret;
+ }
+
+ out_be16(&uccs->us_pram->mrblr, us_info->max_rx_buf_length);
+
+ INIT_LIST_HEAD(&uccs->confQ);
+
+ /* Allocate BDs. */
+ uccs->rx_base_offset =
+ qe_muram_alloc(us_info->rx_bd_ring_len * UCC_SLOW_SIZE_OF_BD,
+ QE_ALIGNMENT_OF_BD);
+ if (IS_MURAM_ERR(uccs->rx_base_offset)) {
+ uccs_err("ucc_slow_init: No memory for Rx BD's.");
+ uccs->rx_base_offset = 0;
+ ucc_slow_free(uccs);
+ return -ENOMEM;
+ }
+
+ uccs->tx_base_offset =
+ qe_muram_alloc(us_info->tx_bd_ring_len * UCC_SLOW_SIZE_OF_BD,
+ QE_ALIGNMENT_OF_BD);
+ if (IS_MURAM_ERR(uccs->tx_base_offset)) {
+ uccs_err("ucc_slow_init: No memory for Tx BD's.");
+ uccs->tx_base_offset = 0;
+ ucc_slow_free(uccs);
+ return -ENOMEM;
+ }
+
+ /* Init Tx bds */
+ bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
+ for (i = 0; i < us_info->tx_bd_ring_len; i++) {
+ BD_BUFFER_CLEAR(bd);
+ BD_STATUS_AND_LENGTH_SET(bd, 0);
+ bd += QE_SIZEOF_BD;
+ }
+ bd -= QE_SIZEOF_BD;
+ BD_STATUS_AND_LENGTH_SET(bd, T_W); /* for last BD set Wrap bit */
+
+ /* Init Rx bds */
+ bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
+ for (i = 0; i < us_info->rx_bd_ring_len; i++) {
+ BD_STATUS_AND_LENGTH_SET(bd, 0);
+ BD_BUFFER_CLEAR(bd);
+ bd += QE_SIZEOF_BD;
+ }
+ bd -= QE_SIZEOF_BD;
+ BD_STATUS_AND_LENGTH_SET(bd, R_W); /* for last BD set Wrap bit */
+
+ /* Set GUMR (For more details see the hardware spec.). */
+ /* gumr_h */
+ gumr = 0;
+ gumr |= us_info->tcrc;
+ if (us_info->cdp)
+ gumr |= UCC_SLOW_GUMR_H_CDP;
+ if (us_info->ctsp)
+ gumr |= UCC_SLOW_GUMR_H_CTSP;
+ if (us_info->cds)
+ gumr |= UCC_SLOW_GUMR_H_CDS;
+ if (us_info->ctss)
+ gumr |= UCC_SLOW_GUMR_H_CTSS;
+ if (us_info->tfl)
+ gumr |= UCC_SLOW_GUMR_H_TFL;
+ if (us_info->rfw)
+ gumr |= UCC_SLOW_GUMR_H_RFW;
+ if (us_info->txsy)
+ gumr |= UCC_SLOW_GUMR_H_TXSY;
+ if (us_info->rtsm)
+ gumr |= UCC_SLOW_GUMR_H_RTSM;
+ out_be32(&us_regs->gumr_h, gumr);
+
+ /* gumr_l */
+ gumr = 0;
+ if (us_info->tci)
+ gumr |= UCC_SLOW_GUMR_L_TCI;
+ if (us_info->rinv)
+ gumr |= UCC_SLOW_GUMR_L_RINV;
+ if (us_info->tinv)
+ gumr |= UCC_SLOW_GUMR_L_TINV;
+ if (us_info->tend)
+ gumr |= UCC_SLOW_GUMR_L_TEND;
+ gumr |= us_info->tdcr;
+ gumr |= us_info->rdcr;
+ gumr |= us_info->tenc;
+ gumr |= us_info->renc;
+ gumr |= us_info->diag;
+ gumr |= us_info->mode;
+ out_be32(&us_regs->gumr_l, gumr);
+
+ /* Function code registers */
+ /* function_code has initial value 0 */
+
+ /* if the data is in cachable memory, the 'global' */
+ /* in the function code should be set. */
+ function_code |= us_info->data_mem_part;
+ function_code |= QE_BMR_BYTE_ORDER_BO_MOT; /* Required for QE */
+ uccs->us_pram->tfcr = function_code;
+ uccs->us_pram->rfcr = function_code;
+
+ /* rbase, tbase are offsets from MURAM base */
+ out_be16(&uccs->us_pram->rbase, uccs->us_pram_offset);
+ out_be16(&uccs->us_pram->tbase, uccs->us_pram_offset);
+
+ /* Mux clocking */
+ /* Grant Support */
+ ucc_set_qe_mux_grant(us_info->ucc_num, us_info->grant_support);
+ /* Breakpoint Support */
+ ucc_set_qe_mux_bkpt(us_info->ucc_num, us_info->brkpt_support);
+ /* Set Tsa or NMSI mode. */
+ ucc_set_qe_mux_tsa(us_info->ucc_num, us_info->tsa);
+ /* If NMSI (not Tsa), set Tx and Rx clock. */
+ if (!us_info->tsa) {
+ /* Rx clock routing */
+ if (ucc_set_qe_mux_rxtx
+ (us_info->ucc_num, us_info->rx_clock, COMM_DIR_RX)) {
+ uccs_err
+ ("ucc_slow_init: Illegal value for parameter" \
+ " 'RxClock'.");
+ ucc_slow_free(uccs);
+ return -EINVAL;
+ }
+ /* Tx clock routing */
+ if (ucc_set_qe_mux_rxtx
+ (us_info->ucc_num, us_info->tx_clock, COMM_DIR_TX)) {
+ uccs_err
+ ("ucc_slow_init: Illegal value for parameter " \
+ "'TxClock'.");
+ ucc_slow_free(uccs);
+ return -EINVAL;
+ }
+ }
+
+ /*
+ * INTERRUPTS
+ */
+ /* Set interrupt mask register at UCC level. */
+ out_be16(&us_regs->uccm, us_info->uccm_mask);
+
+ /* First, clear anything pending at UCC level, */
+ /* otherwise, old garbage may come through */
+ /* as soon as the dam is opened. */
+
+ /* Writing '1' clears */
+ out_be16(&us_regs->ucce, 0xffff);
+
+ /* Issue QE Init command */
+ if (us_info->init_tx && us_info->init_rx)
+ command = QE_INIT_TX_RX;
+ else if (us_info->init_tx)
+ command = QE_INIT_TX;
+ else
+ command = QE_INIT_RX; /* We know at least one is TRUE */
+ id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
+ qe_issue_cmd(command, id, (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
+
+ *uccs_ret = uccs;
+ return 0;
+}
+
+void ucc_slow_free(ucc_slow_private_t * uccs)
+{
+ if (!uccs)
+ return;
+
+ if (uccs->rx_base_offset)
+ qe_muram_free(uccs->rx_base_offset);
+
+ if (uccs->tx_base_offset)
+ qe_muram_free(uccs->tx_base_offset);
+
+ if (uccs->us_pram) {
+ qe_muram_free(uccs->us_pram_offset);
+ uccs->us_pram = NULL;
+ }
+
+ kfree(uccs);
+}
diff --git a/include/asm-powerpc/ucc.h b/include/asm-powerpc/ucc.h
new file mode 100644
index 0000000..5c09df6
--- /dev/null
+++ b/include/asm-powerpc/ucc.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors: Shlomi Gridish <gridish@freescale.com>
+ * Li Yang <leoli@freescale.com>
+ *
+ * Description:
+ * Internal header file for UCC unit routines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __UCC_H__
+#define __UCC_H__
+
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#define STATISTICS
+
+#define UCC_MAX_NUM 8
+
+/* Slow or fast type for UCCs.
+*/
+typedef enum ucc_speed_type {
+ UCC_SPEED_TYPE_FAST, UCC_SPEED_TYPE_SLOW
+} ucc_speed_type_e;
+
+/* Initial UCCs Parameter RAM address relative to: MEM_MAP_BASE (IMMR).
+*/
+typedef enum ucc_pram_initial_offset {
+ UCC_PRAM_OFFSET_UCC1 = 0x8400,
+ UCC_PRAM_OFFSET_UCC2 = 0x8500,
+ UCC_PRAM_OFFSET_UCC3 = 0x8600,
+ UCC_PRAM_OFFSET_UCC4 = 0x9000,
+ UCC_PRAM_OFFSET_UCC5 = 0x8000,
+ UCC_PRAM_OFFSET_UCC6 = 0x8100,
+ UCC_PRAM_OFFSET_UCC7 = 0x8200,
+ UCC_PRAM_OFFSET_UCC8 = 0x8300
+} ucc_pram_initial_offset_e;
+
+/* ucc_set_type
+ * Sets UCC to slow or fast mode.
+ *
+ * ucc_num - (In) number of UCC (0-7).
+ * regs - (In) pointer to registers base for the UCC.
+ * speed - (In) slow or fast mode for UCC.
+ */
+int ucc_set_type(int ucc_num, struct ucc_common *regs,
+ enum ucc_speed_type speed);
+
+/* ucc_init_guemr
+ * Init the Guemr register.
+ *
+ * regs - (In) pointer to registers base for the UCC.
+ */
+int ucc_init_guemr(struct ucc_common *regs);
+
+int ucc_set_qe_mux_mii_mng(int ucc_num);
+
+int ucc_set_qe_mux_rxtx(int ucc_num, qe_clock_e clock, comm_dir_e mode);
+
+int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask);
+
+/* QE MUX clock routing for UCC
+*/
+static inline int ucc_set_qe_mux_grant(int ucc_num, int set)
+{
+ return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
+}
+
+static inline int ucc_set_qe_mux_tsa(int ucc_num, int set)
+{
+ return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
+}
+
+static inline int ucc_set_qe_mux_bkpt(int ucc_num, int set)
+{
+ return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
+}
+
+#endif /* __UCC_H__ */
diff --git a/include/asm-powerpc/ucc_fast.h b/include/asm-powerpc/ucc_fast.h
new file mode 100644
index 0000000..b1cfd00
--- /dev/null
+++ b/include/asm-powerpc/ucc_fast.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors: Shlomi Gridish <gridish@freescale.com>
+ * Li Yang <leoli@freescale.com>
+ *
+ * Description:
+ * Internal header file for UCC FAST unit routines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __UCC_FAST_H__
+#define __UCC_FAST_H__
+
+#include <linux/kernel.h>
+
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#include "ucc.h"
+
+/* Receive BD's status.
+*/
+#define R_E 0x80000000 /* buffer empty */
+#define R_W 0x20000000 /* wrap bit */
+#define R_I 0x10000000 /* interrupt on reception */
+#define R_L 0x08000000 /* last */
+#define R_F 0x04000000 /* first */
+
+/* transmit BD's status.
+*/
+#define T_R 0x80000000 /* ready bit */
+#define T_W 0x20000000 /* wrap bit */
+#define T_I 0x10000000 /* interrupt on completion */
+#define T_L 0x08000000 /* last */
+
+/* Rx Data buffer must be 4 bytes aligned in most cases.*/
+#define UCC_FAST_RX_ALIGN 4
+#define UCC_FAST_MRBLR_ALIGNMENT 4
+#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
+
+/* Sizes
+*/
+#define UCC_FAST_URFS_MIN_VAL 0x88
+#define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR 8
+
+/* ucc_fast_channel_protocol_mode - UCC FAST mode.
+*/
+typedef enum ucc_fast_channel_protocol_mode {
+ UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000,
+ UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001,
+ UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002,
+ UCC_FAST_PROTOCOL_MODE_RESERVED02 = 0x00000003,
+ UCC_FAST_PROTOCOL_MODE_RESERVED_UART = 0x00000004,
+ UCC_FAST_PROTOCOL_MODE_RESERVED03 = 0x00000005,
+ UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1 = 0x00000006,
+ UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2 = 0x00000007,
+ UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC = 0x00000008,
+ UCC_FAST_PROTOCOL_MODE_RESERVED04 = 0x00000009,
+ UCC_FAST_PROTOCOL_MODE_ATM = 0x0000000A,
+ UCC_FAST_PROTOCOL_MODE_RESERVED05 = 0x0000000B,
+ UCC_FAST_PROTOCOL_MODE_ETHERNET = 0x0000000C,
+ UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D,
+ UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E,
+ UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F
+} ucc_fast_channel_protocol_mode_e;
+
+/* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX
+*/
+typedef enum ucc_fast_transparent_txrx {
+ UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000,
+ UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000
+} ucc_fast_transparent_txrx_e;
+
+/* UCC fast diagnostic mode
+*/
+typedef enum ucc_fast_diag_mode {
+ UCC_FAST_DIAGNOSTIC_NORMAL = 0x0,
+ UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000,
+ UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000,
+ UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000
+} ucc_fast_diag_mode_e;
+
+/* UCC fast Sync length (transparent mode only)
+*/
+typedef enum ucc_fast_sync_len {
+ UCC_FAST_SYNC_LEN_NOT_USED = 0x0,
+ UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000,
+ UCC_FAST_SYNC_LEN_8_BIT = 0x00008000,
+ UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000
+} ucc_fast_sync_len_e;
+
+/* UCC fast RTS mode
+*/
+typedef enum ucc_fast_ready_to_send {
+ UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000,
+ UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000
+} ucc_fast_ready_to_send_e;
+
+/* UCC fast receiver decoding mode
+*/
+typedef enum ucc_fast_rx_decoding_method {
+ UCC_FAST_RX_ENCODING_NRZ = 0x00000000,
+ UCC_FAST_RX_ENCODING_NRZI = 0x00000800,
+ UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000,
+ UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800
+} ucc_fast_rx_decoding_method_e;
+
+/* UCC fast transmitter encoding mode
+*/
+typedef enum ucc_fast_tx_encoding_method {
+ UCC_FAST_TX_ENCODING_NRZ = 0x00000000,
+ UCC_FAST_TX_ENCODING_NRZI = 0x00000100,
+ UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200,
+ UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300
+} ucc_fast_tx_encoding_method_e;
+
+/* UCC fast CRC length
+*/
+typedef enum ucc_fast_transparent_tcrc {
+ UCC_FAST_16_BIT_CRC = 0x00000000,
+ UCC_FAST_CRC_RESERVED0 = 0x00000040,
+ UCC_FAST_32_BIT_CRC = 0x00000080,
+ UCC_FAST_CRC_RESERVED1 = 0x000000C0
+} ucc_fast_transparent_tcrc_e;
+
+/* Fast UCC initialization structure.
+*/
+typedef struct ucc_fast_info {
+ int ucc_num;
+ qe_clock_e rx_clock;
+ qe_clock_e tx_clock;
+ u32 regs;
+ int irq;
+ u32 uccm_mask;
+ int bd_mem_part;
+ int brkpt_support;
+ int grant_support;
+ int tsa;
+ int cdp;
+ int cds;
+ int ctsp;
+ int ctss;
+ int tci;
+ int txsy;
+ int rtsm;
+ int revd;
+ int rsyn;
+ u16 max_rx_buf_length;
+ u16 urfs;
+ u16 urfet;
+ u16 urfset;
+ u16 utfs;
+ u16 utfet;
+ u16 utftt;
+ u16 ufpt;
+ ucc_fast_channel_protocol_mode_e mode;
+ ucc_fast_transparent_txrx_e ttx_trx;
+ ucc_fast_tx_encoding_method_e tenc;
+ ucc_fast_rx_decoding_method_e renc;
+ ucc_fast_transparent_tcrc_e tcrc;
+ ucc_fast_sync_len_e synl;
+} ucc_fast_info_t;
+
+typedef struct ucc_fast_private {
+ ucc_fast_info_t *uf_info;
+ ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs. */
+ u32 *p_ucce; /* a pointer to the event register in memory. */
+ u32 *p_uccm; /* a pointer to the mask register in memory. */
+ int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
+ int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
+ int stopped_tx; /* Whether channel has been stopped for Tx
+ (STOP_TX, etc.) */
+ int stopped_rx; /* Whether channel has been stopped for Rx */
+ u32 ucc_fast_tx_virtual_fifo_base_offset;/* pointer to base of Tx
+ virtual fifo */
+ u32 ucc_fast_rx_virtual_fifo_base_offset;/* pointer to base of Rx
+ virtual fifo */
+#ifdef STATISTICS
+ u32 tx_frames; /* Transmitted frames counter. */
+ u32 rx_frames; /* Received frames counter (only frames
+ passed to application). */
+ u32 tx_discarded; /* Discarded tx frames counter (frames that
+ were discarded by the driver due to errors).
+ */
+ u32 rx_discarded; /* Discarded rx frames counter (frames that
+ were discarded by the driver due to errors).
+ */
+#endif /* STATISTICS */
+ u16 mrblr; /* maximum receive buffer length */
+} ucc_fast_private_t;
+
+/* ucc_fast_init
+ * Initializes Fast UCC according to user provided parameters.
+ *
+ * uf_info - (In) pointer to the fast UCC info structure.
+ * uccf_ret - (Out) pointer to the fast UCC structure.
+ */
+int ucc_fast_init(ucc_fast_info_t * uf_info, ucc_fast_private_t ** uccf_ret);
+
+/* ucc_fast_free
+ * Frees all resources for fast UCC.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ */
+void ucc_fast_free(ucc_fast_private_t * uccf);
+
+/* ucc_fast_enable
+ * Enables a fast UCC port.
+ * This routine enables Tx and/or Rx through the General UCC Mode Register.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ * mode - (In) TX, RX, or both.
+ */
+void ucc_fast_enable(ucc_fast_private_t * uccf, comm_dir_e mode);
+
+/* ucc_fast_disable
+ * Disables a fast UCC port.
+ * This routine disables Tx and/or Rx through the General UCC Mode Register.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ * mode - (In) TX, RX, or both.
+ */
+void ucc_fast_disable(ucc_fast_private_t * uccf, comm_dir_e mode);
+
+/* ucc_fast_irq
+ * Handles interrupts on fast UCC.
+ * Called from the general interrupt routine to handle interrupts on fast UCC.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ */
+void ucc_fast_irq(ucc_fast_private_t * uccf);
+
+/* ucc_fast_transmit_on_demand
+ * Immediately forces a poll of the transmitter for data to be sent.
+ * Typically, the hardware performs a periodic poll for data that the
+ * transmit routine has set up to be transmitted. In cases where
+ * this polling cycle is not soon enough, this optional routine can
+ * be invoked to force a poll right away, instead. Proper use for
+ * each transmission for which this functionality is desired is to
+ * call the transmit routine and then this routine right after.
+ *
+ * uccf - (In) pointer to the fast UCC structure.
+ */
+void ucc_fast_transmit_on_demand(ucc_fast_private_t * uccf);
+
+u32 ucc_fast_get_qe_cr_subblock(int uccf_num);
+
+void ucc_fast_dump_regs(ucc_fast_private_t * uccf);
+
+#endif /* __UCC_FAST_H__ */
diff --git a/include/asm-powerpc/ucc_slow.h b/include/asm-powerpc/ucc_slow.h
new file mode 100644
index 0000000..07db339
--- /dev/null
+++ b/include/asm-powerpc/ucc_slow.h
@@ -0,0 +1,304 @@
+/*
+ * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors: Shlomi Gridish <gridish@freescale.com>
+ * Li Yang <leoli@freescale.com>
+ *
+ * Description:
+ * Internal header file for UCC SLOW unit routines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef __UCC_SLOW_H__
+#define __UCC_SLOW_H__
+
+#include <linux/kernel.h>
+
+#include <asm/immap_qe.h>
+#include <asm/qe.h>
+
+#include "ucc.h"
+
+#define UCC_SLOW_SIZE_OF_BD QE_SIZEOF_BD
+
+/* transmit BD's status.
+*/
+#define T_R 0x80000000 /* ready bit */
+#define T_PAD 0x40000000 /* add pads to short frames */
+#define T_W 0x20000000 /* wrap bit */
+#define T_I 0x10000000 /* interrupt on completion */
+#define T_L 0x08000000 /* last */
+
+#define T_A 0x04000000 /* Address - the data transmitted as address
+ chars */
+#define T_TC 0x04000000 /* transmit CRC */
+#define T_CM 0x02000000 /* continuous mode */
+#define T_DEF 0x02000000 /* collision on previous attempt to transmit. */
+#define T_P 0x01000000 /* Preamble - send Preamble sequence before
+ data */
+#define T_HB 0x01000000 /* heartbeat. */
+#define T_NS 0x00800000 /* No Stop */
+#define T_LC 0x00800000 /* late collision. */
+#define T_RL 0x00400000 /* retransmission limit. */
+#define T_UN 0x00020000 /* underrun */
+#define T_CT 0x00010000 /* CTS lost */
+#define T_CSL 0x00010000 /* carrier sense lost. */
+#define T_RC 0x003c0000 /* retry count. */
+
+/* Receive BD's status.
+*/
+#define R_E 0x80000000 /* buffer empty */
+#define R_W 0x20000000 /* wrap bit */
+#define R_I 0x10000000 /* interrupt on reception */
+#define R_L 0x08000000 /* last */
+#define R_C 0x08000000 /* the last byte in this buffer is a cntl
+ char */
+#define R_F 0x04000000 /* first */
+#define R_A 0x04000000 /* the first byte in this buffer is address
+ byte */
+#define R_CM 0x02000000 /* continuous mode */
+#define R_ID 0x01000000 /* buffer close on reception of idles */
+#define R_M 0x01000000 /* Frame received because of promiscuous
+ mode. */
+#define R_AM 0x00800000 /* Address match */
+#define R_DE 0x00800000 /* Address match */
+#define R_LG 0x00200000 /* Break received */
+#define R_BR 0x00200000 /* Frame length violation */
+#define R_NO 0x00100000 /* Rx Non Octet Aligned Packet */
+#define R_FR 0x00100000 /* Framing Error (no stop bit) character
+ received */
+#define R_PR 0x00080000 /* Parity Error character received */
+#define R_AB 0x00080000 /* Frame Aborted */
+#define R_SH 0x00080000 /* frame is too short. */
+#define R_CR 0x00040000 /* CRC Error */
+#define R_OV 0x00020000 /* Overrun */
+#define R_CD 0x00010000 /* CD lost */
+#define R_CL 0x00010000 /* this frame is closed because of a
+ collision */
+
+/* Rx Data buffer must be 4 bytes aligned in most cases.*/
+#define UCC_SLOW_RX_ALIGN 4
+#define UCC_SLOW_MRBLR_ALIGNMENT 4
+#define UCC_SLOW_PRAM_SIZE 0x100
+#define ALIGNMENT_OF_UCC_SLOW_PRAM 64
+
+/* UCC Slow Channel Protocol Mode
+*/
+typedef enum ucc_slow_channel_protocol_mode {
+ UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC = 0x00000002, /* QMC */
+ UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART = 0x00000004, /* UART */
+ UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC = 0x00000008 /* BISYNC */
+} ucc_slow_channel_protocol_mode_e;
+
+/* UCC Slow Transparent Transmit CRC (TCRC)
+*/
+typedef enum ucc_slow_transparent_tcrc {
+ UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16 = 0x00000000, /* 16-bit
+ CCITT CRC
+ (HDLC).
+ (X16 + X12
+ + X5 + 1) */
+ UCC_SLOW_TRANSPARENT_TCRC_CRC16 = 0x00004000, /* CRC16 (BISYNC).
+ (X16 + X15 + X2 +
+ 1) */
+ UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32 = 0x00008000 /* 32-bit
+ CCITT CRC
+ (Ethernet
+ and HDLC).
+ */
+} ucc_slow_transparent_tcrc_e;
+
+/* UCC Slow oversampling rate for transmitter (TDCR)
+*/
+typedef enum ucc_slow_tx_oversampling_rate {
+ UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1 = 0x00000000, /* 1x clock
+ mode */
+ UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8 = 0x00010000, /* 8x clock
+ mode */
+ UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16 = 0x00020000, /* 16x clock
+ mode */
+ UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32 = 0x00030000 /* 32x clock
+ mode */
+} ucc_slow_tx_oversampling_rate_e;
+
+/* UCC Slow Oversampling rate for receiver (RDCR)
+*/
+typedef enum ucc_slow_rx_oversampling_rate {
+ UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1 = 0x00000000, /* 1x clock
+ mode */
+ UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8 = 0x00004000, /* 8x clock
+ mode */
+ UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16 = 0x00008000, /* 16x clock
+ mode */
+ UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32 = 0x0000c000 /* 32x clock
+ mode */
+} ucc_slow_rx_oversampling_rate_e;
+
+/* UCC Slow Transmitter encoding method (TENC)
+*/
+typedef enum ucc_slow_tx_encoding_method {
+ UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ = 0x00000000,
+ UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI = 0x00000100
+} ucc_slow_tx_encoding_method_e;
+
+/* UCC Slow Receiver decoding method (RENC)
+*/
+typedef enum ucc_slow_rx_decoding_method {
+ UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ = 0x00000000,
+ UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI = 0x00000800
+} ucc_slow_rx_decoding_method_e;
+
+/* UCC Slow Diagnostic mode (DIAG)
+*/
+typedef enum ucc_slow_diag_mode {
+ UCC_SLOW_DIAG_MODE_NORMAL = 0x00000000,
+ UCC_SLOW_DIAG_MODE_LOOPBACK = 0x00000040,
+ UCC_SLOW_DIAG_MODE_ECHO = 0x00000080,
+ UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO = 0x000000c0
+} ucc_slow_diag_mode_e;
+
+typedef struct ucc_slow_info {
+ int ucc_num;
+ qe_clock_e rx_clock;
+ qe_clock_e tx_clock;
+ ucc_slow_t *us_regs;
+ int irq;
+ u16 uccm_mask;
+ int data_mem_part;
+ int init_tx;
+ int init_rx;
+ u32 tx_bd_ring_len;
+ u32 rx_bd_ring_len;
+ int rx_interrupts;
+ int brkpt_support;
+ int grant_support;
+ int tsa;
+ int cdp;
+ int cds;
+ int ctsp;
+ int ctss;
+ int rinv;
+ int tinv;
+ int rtsm;
+ int rfw;
+ int tci;
+ int tend;
+ int tfl;
+ int txsy;
+ u16 max_rx_buf_length;
+ ucc_slow_transparent_tcrc_e tcrc;
+ ucc_slow_channel_protocol_mode_e mode;
+ ucc_slow_diag_mode_e diag;
+ ucc_slow_tx_oversampling_rate_e tdcr;
+ ucc_slow_rx_oversampling_rate_e rdcr;
+ ucc_slow_tx_encoding_method_e tenc;
+ ucc_slow_rx_decoding_method_e renc;
+} ucc_slow_info_t;
+
+typedef struct ucc_slow_private {
+ ucc_slow_info_t *us_info;
+ ucc_slow_t *us_regs; /* a pointer to memory map of UCC regs. */
+ ucc_slow_pram_t *us_pram; /* a pointer to the parameter RAM. */
+ uint us_pram_offset;
+ int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
+ int enabled_rx; /* Whether channel is enabled for Rx (ENR) */
+ int stopped_tx; /* Whether channel has been stopped for Tx
+ (STOP_TX, etc.) */
+ int stopped_rx; /* Whether channel has been stopped for Rx */
+ struct list_head confQ; /* frames passed to chip waiting for tx */
+ u32 first_tx_bd_mask; /* mask is used in Tx routine to save status
+ and length for first BD in a frame. */
+ uint tx_base_offset; /* first BD in Tx BD table offset (In MURAM) */
+ uint rx_base_offset; /* first BD in Rx BD table offset (In MURAM) */
+ u8 *confBd; /* next BD for confirm after Tx */
+ u8 *tx_bd; /* next BD for new Tx request */
+ u8 *rx_bd; /* next BD to collect after Rx */
+ void *p_rx_frame; /* accumulating receive frame */
+ u16 *p_ucce; /* a pointer to the event register in memory.
+ */
+ u16 *p_uccm; /* a pointer to the mask register in memory.
+ */
+ u16 saved_uccm; /* a saved mask for the RX Interrupt bits. */
+#ifdef STATISTICS
+ u32 tx_frames; /* Transmitted frames counters. */
+ u32 rx_frames; /* Received frames counters (only frames
+ passed to application). */
+ u32 rx_discarded; /* Discarded frames counters (frames that
+ were discarded by the driver due to
+ errors). */
+#endif /* STATISTICS */
+} ucc_slow_private_t;
+
+/* ucc_slow_init
+ * Initializes Slow UCC according to provided parameters.
+ *
+ * us_info - (In) pointer to the slow UCC info structure.
+ * uccs_ret - (Out) pointer to the slow UCC structure.
+ */
+int ucc_slow_init(ucc_slow_info_t * us_info, ucc_slow_private_t ** uccs_ret);
+
+/* ucc_slow_free
+ * Frees all resources for slow UCC.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_free(ucc_slow_private_t * uccs);
+
+/* ucc_slow_enable
+ * Enables a fast UCC port.
+ * This routine enables Tx and/or Rx through the General UCC Mode Register.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ * mode - (In) TX, RX, or both.
+ */
+void ucc_slow_enable(ucc_slow_private_t * uccs, comm_dir_e mode);
+
+/* ucc_slow_disable
+ * Disables a fast UCC port.
+ * This routine disables Tx and/or Rx through the General UCC Mode Register.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ * mode - (In) TX, RX, or both.
+ */
+void ucc_slow_disable(ucc_slow_private_t * uccs, comm_dir_e mode);
+
+/* ucc_slow_poll_transmitter_now
+ * Immediately forces a poll of the transmitter for data to be sent.
+ * Typically, the hardware performs a periodic poll for data that the
+ * transmit routine has set up to be transmitted. In cases where
+ * this polling cycle is not soon enough, this optional routine can
+ * be invoked to force a poll right away, instead. Proper use for
+ * each transmission for which this functionality is desired is to
+ * call the transmit routine and then this routine right after.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_poll_transmitter_now(ucc_slow_private_t * uccs);
+
+/* ucc_slow_graceful_stop_tx
+ * Smoothly stops transmission on a specified slow UCC.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_graceful_stop_tx(ucc_slow_private_t * uccs);
+
+/* ucc_slow_stop_tx
+ * Stops transmission on a specified slow UCC.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_stop_tx(ucc_slow_private_t * uccs);
+
+/* ucc_slow_restart_x
+ * Restarts transmitting on a specified slow UCC.
+ *
+ * uccs - (In) pointer to the slow UCC structure.
+ */
+void ucc_slow_restart_x(ucc_slow_private_t * uccs);
+
+u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
+
+#endif /* __UCC_SLOW_H__ */
--
1.4.2.1
^ permalink raw reply related
* [PATCH 7/15] qe_lib: Add QE memory map definition
From: Kim Phillips @ 2006-09-30 23:34 UTC (permalink / raw)
To: linuxppc-dev
qe_lib: Add QE memory map definition
Signed-off-by: Shlomi Gridish <gridish@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
include/asm-powerpc/immap_qe.h | 506 ++++++++++++++++++++++++++++++++++++++++
1 files changed, 506 insertions(+), 0 deletions(-)
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
new file mode 100644
index 0000000..754df2d
--- /dev/null
+++ b/include/asm-powerpc/immap_qe.h
@@ -0,0 +1,506 @@
+/*
+ * Copyright (C) 2006. Freescale Semicondutor, Inc. All rights reserved.
+ *
+ * Authors: Shlomi Gridish <gridish@freescale.com>
+ * Li Yang <leoli@freescale.com>
+ *
+ * Description:
+ * QUICC Engine (QE) Internal Memory Map.
+ * The Internal Memory Map for devices with QE on them. This
+ * is the superset of all QE devices (8360, etc.).
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifdef CONFIG_QUICC_ENGINE
+#ifdef __KERNEL__
+#ifndef __IMMAP_QE_H__
+#define __IMMAP_QE_H__
+
+#include <linux/kernel.h>
+
+#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
+
+/* QE I-RAM
+*/
+typedef struct qe_iram {
+ u32 iadd; /* I-RAM Address Register */
+ u32 idata; /* I-RAM Data Register */
+ u8 res0[0x78];
+} __attribute__ ((packed)) qe_iram_t;
+
+/* QE Interrupt Controller
+*/
+typedef struct qe_ic_regs {
+ u32 qicr;
+ u32 qivec;
+ u32 qripnr;
+ u32 qipnr;
+ u32 qipxcc;
+ u32 qipycc;
+ u32 qipwcc;
+ u32 qipzcc;
+ u32 qimr;
+ u32 qrimr;
+ u32 qicnr;
+ u8 res0[0x4];
+ u32 qiprta;
+ u32 qiprtb;
+ u8 res1[0x4];
+ u32 qricr;
+ u8 res2[0x20];
+ u32 qhivec;
+ u8 res3[0x1C];
+} __attribute__ ((packed)) qe_ic_t;
+
+/* Communications Processor
+*/
+typedef struct cp_qe {
+ u32 cecr; /* QE command register */
+ u32 ceccr; /* QE controller configuration register */
+ u32 cecdr; /* QE command data register */
+ u8 res0[0xA];
+ u16 ceter; /* QE timer event register */
+ u8 res1[0x2];
+ u16 cetmr; /* QE timers mask register */
+ u32 cetscr; /* QE time-stamp timer control register */
+ u32 cetsr1; /* QE time-stamp register 1 */
+ u32 cetsr2; /* QE time-stamp register 2 */
+ u8 res2[0x8];
+ u32 cevter; /* QE virtual tasks event register */
+ u32 cevtmr; /* QE virtual tasks mask register */
+ u16 cercr; /* QE RAM control register */
+ u8 res3[0x2];
+ u8 res4[0x24];
+ u16 ceexe1; /* QE external request 1 event register */
+ u8 res5[0x2];
+ u16 ceexm1; /* QE external request 1 mask register */
+ u8 res6[0x2];
+ u16 ceexe2; /* QE external request 2 event register */
+ u8 res7[0x2];
+ u16 ceexm2; /* QE external request 2 mask register */
+ u8 res8[0x2];
+ u16 ceexe3; /* QE external request 3 event register */
+ u8 res9[0x2];
+ u16 ceexm3; /* QE external request 3 mask register */
+ u8 res10[0x2];
+ u16 ceexe4; /* QE external request 4 event register */
+ u8 res11[0x2];
+ u16 ceexm4; /* QE external request 4 mask register */
+ u8 res12[0x2];
+ u8 res13[0x280];
+} __attribute__ ((packed)) cp_qe_t;
+
+/* QE Multiplexer
+*/
+typedef struct qe_mux {
+ u32 cmxgcr; /* CMX general clock route register */
+ u32 cmxsi1cr_l; /* CMX SI1 clock route low register */
+ u32 cmxsi1cr_h; /* CMX SI1 clock route high register */
+ u32 cmxsi1syr; /* CMX SI1 SYNC route register */
+ u32 cmxucr1; /* CMX UCC1, UCC3 clock route register */
+ u32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
+ u32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
+ u32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
+ u32 cmxupcr; /* CMX UPC clock route register */
+ u8 res0[0x1C];
+} __attribute__ ((packed)) qe_mux_t;
+
+/* QE Timers
+*/
+typedef struct qe_timers {
+ u8 gtcfr1; /* Timer 1 and Timer 2 global configuration
+ register */
+ u8 res0[0x3];
+ u8 gtcfr2; /* Timer 3 and timer 4 global configuration
+ register */
+ u8 res1[0xB];
+ u16 gtmdr1; /* Timer 1 mode register */
+ u16 gtmdr2; /* Timer 2 mode register */
+ u16 gtrfr1; /* Timer 1 reference register */
+ u16 gtrfr2; /* Timer 2 reference register */
+ u16 gtcpr1; /* Timer 1 capture register */
+ u16 gtcpr2; /* Timer 2 capture register */
+ u16 gtcnr1; /* Timer 1 counter */
+ u16 gtcnr2; /* Timer 2 counter */
+ u16 gtmdr3; /* Timer 3 mode register */
+ u16 gtmdr4; /* Timer 4 mode register */
+ u16 gtrfr3; /* Timer 3 reference register */
+ u16 gtrfr4; /* Timer 4 reference register */
+ u16 gtcpr3; /* Timer 3 capture register */
+ u16 gtcpr4; /* Timer 4 capture register */
+ u16 gtcnr3; /* Timer 3 counter */
+ u16 gtcnr4; /* Timer 4 counter */
+ u16 gtevr1; /* Timer 1 event register */
+ u16 gtevr2; /* Timer 2 event register */
+ u16 gtevr3; /* Timer 3 event register */
+ u16 gtevr4; /* Timer 4 event register */
+ u16 gtps; /* Timer 1 prescale register */
+ u8 res2[0x46];
+} __attribute__ ((packed)) qe_timers_t;
+
+/* BRG
+*/
+typedef struct qe_brg {
+ u32 brgc1; /* BRG1 configuration register */
+ u32 brgc2; /* BRG2 configuration register */
+ u32 brgc3; /* BRG3 configuration register */
+ u32 brgc4; /* BRG4 configuration register */
+ u32 brgc5; /* BRG5 configuration register */
+ u32 brgc6; /* BRG6 configuration register */
+ u32 brgc7; /* BRG7 configuration register */
+ u32 brgc8; /* BRG8 configuration register */
+ u32 brgc9; /* BRG9 configuration register */
+ u32 brgc10; /* BRG10 configuration register */
+ u32 brgc11; /* BRG11 configuration register */
+ u32 brgc12; /* BRG12 configuration register */
+ u32 brgc13; /* BRG13 configuration register */
+ u32 brgc14; /* BRG14 configuration register */
+ u32 brgc15; /* BRG15 configuration register */
+ u32 brgc16; /* BRG16 configuration register */
+ u8 res0[0x40];
+} __attribute__ ((packed)) qe_brg_t;
+
+/* SPI
+*/
+typedef struct spi {
+ u8 res0[0x20];
+ u32 spmode; /* SPI mode register */
+ u8 res1[0x2];
+ u8 spie; /* SPI event register */
+ u8 res2[0x1];
+ u8 res3[0x2];
+ u8 spim; /* SPI mask register */
+ u8 res4[0x1];
+ u8 res5[0x1];
+ u8 spcom; /* SPI command register */
+ u8 res6[0x2];
+ u32 spitd; /* SPI transmit data register (cpu mode) */
+ u32 spird; /* SPI receive data register (cpu mode) */
+ u8 res7[0x8];
+} __attribute__ ((packed)) spi_t;
+
+/* SI
+*/
+typedef struct si1 {
+ u16 siamr1; /* SI1 TDMA mode register */
+ u16 sibmr1; /* SI1 TDMB mode register */
+ u16 sicmr1; /* SI1 TDMC mode register */
+ u16 sidmr1; /* SI1 TDMD mode register */
+ u8 siglmr1_h; /* SI1 global mode register high */
+ u8 res0[0x1];
+ u8 sicmdr1_h; /* SI1 command register high */
+ u8 res2[0x1];
+ u8 sistr1_h; /* SI1 status register high */
+ u8 res3[0x1];
+ u16 sirsr1_h; /* SI1 RAM shadow address register high */
+ u8 sitarc1; /* SI1 RAM counter Tx TDMA */
+ u8 sitbrc1; /* SI1 RAM counter Tx TDMB */
+ u8 sitcrc1; /* SI1 RAM counter Tx TDMC */
+ u8 sitdrc1; /* SI1 RAM counter Tx TDMD */
+ u8 sirarc1; /* SI1 RAM counter Rx TDMA */
+ u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
+ u8 sircrc1; /* SI1 RAM counter Rx TDMC */
+ u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
+ u8 res4[0x8];
+ u16 siemr1; /* SI1 TDME mode register 16 bits */
+ u16 sifmr1; /* SI1 TDMF mode register 16 bits */
+ u16 sigmr1; /* SI1 TDMG mode register 16 bits */
+ u16 sihmr1; /* SI1 TDMH mode register 16 bits */
+ u8 siglmg1_l; /* SI1 global mode register low 8 bits */
+ u8 res5[0x1];
+ u8 sicmdr1_l; /* SI1 command register low 8 bits */
+ u8 res6[0x1];
+ u8 sistr1_l; /* SI1 status register low 8 bits */
+ u8 res7[0x1];
+ u16 sirsr1_l; /* SI1 RAM shadow address register low 16
+ bits */
+ u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */
+ u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */
+ u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */
+ u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */
+ u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
+ u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
+ u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
+ u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
+ u8 res8[0x8];
+ u32 siml1; /* SI1 multiframe limit register */
+ u8 siedm1; /* SI1 extended diagnostic mode register */
+ u8 res9[0xBB];
+} __attribute__ ((packed)) si1_t;
+
+/* SI Routing Tables
+*/
+typedef struct sir {
+ u8 tx[0x400];
+ u8 rx[0x400];
+ u8 res0[0x800];
+} __attribute__ ((packed)) sir_t;
+
+/* USB Controller.
+*/
+typedef struct usb_ctlr {
+ u8 usb_usmod;
+ u8 usb_usadr;
+ u8 usb_uscom;
+ u8 res1[1];
+ u16 usb_usep1;
+ u16 usb_usep2;
+ u16 usb_usep3;
+ u16 usb_usep4;
+ u8 res2[4];
+ u16 usb_usber;
+ u8 res3[2];
+ u16 usb_usbmr;
+ u8 res4[1];
+ u8 usb_usbs;
+ u16 usb_ussft;
+ u8 res5[2];
+ u16 usb_usfrn;
+ u8 res6[0x22];
+} __attribute__ ((packed)) usb_t;
+
+/* MCC
+*/
+typedef struct mcc {
+ u32 mcce; /* MCC event register */
+ u32 mccm; /* MCC mask register */
+ u32 mccf; /* MCC configuration register */
+ u32 merl; /* MCC emergency request level register */
+ u8 res0[0xF0];
+} __attribute__ ((packed)) mcc_t;
+
+/* QE UCC Slow
+*/
+typedef struct ucc_slow {
+ u32 gumr_l; /* UCCx general mode register (low) */
+ u32 gumr_h; /* UCCx general mode register (high) */
+ u16 upsmr; /* UCCx protocol-specific mode register */
+ u8 res0[0x2];
+ u16 utodr; /* UCCx transmit on demand register */
+ u16 udsr; /* UCCx data synchronization register */
+ u16 ucce; /* UCCx event register */
+ u8 res1[0x2];
+ u16 uccm; /* UCCx mask register */
+ u8 res2[0x1];
+ u8 uccs; /* UCCx status register */
+ u8 res3[0x24];
+ u16 utpt;
+ u8 guemr; /* UCC general extended mode register */
+ u8 res4[0x200 - 0x091];
+} __attribute__ ((packed)) ucc_slow_t;
+
+/* QE UCC Fast
+*/
+typedef struct ucc_fast {
+ u32 gumr; /* UCCx general mode register */
+ u32 upsmr; /* UCCx protocol-specific mode register */
+ u16 utodr; /* UCCx transmit on demand register */
+ u8 res0[0x2];
+ u16 udsr; /* UCCx data synchronization register */
+ u8 res1[0x2];
+ u32 ucce; /* UCCx event register */
+ u32 uccm; /* UCCx mask register. */
+ u8 uccs; /* UCCx status register */
+ u8 res2[0x7];
+ u32 urfb; /* UCC receive FIFO base */
+ u16 urfs; /* UCC receive FIFO size */
+ u8 res3[0x2];
+ u16 urfet; /* UCC receive FIFO emergency threshold */
+ u16 urfset; /* UCC receive FIFO special emergency
+ threshold */
+ u32 utfb; /* UCC transmit FIFO base */
+ u16 utfs; /* UCC transmit FIFO size */
+ u8 res4[0x2];
+ u16 utfet; /* UCC transmit FIFO emergency threshold */
+ u8 res5[0x2];
+ u16 utftt; /* UCC transmit FIFO transmit threshold */
+ u8 res6[0x2];
+ u16 utpt; /* UCC transmit polling timer */
+ u8 res7[0x2];
+ u32 urtry; /* UCC retry counter register */
+ u8 res8[0x4C];
+ u8 guemr; /* UCC general extended mode register */
+ u8 res9[0x100 - 0x091];
+} __attribute__ ((packed)) ucc_fast_t;
+
+/* QE UCC
+*/
+typedef struct ucc_common {
+ u8 res1[0x90];
+ u8 guemr;
+ u8 res2[0x200 - 0x091];
+} __attribute__ ((packed)) ucc_common_t;
+
+typedef struct ucc {
+ union {
+ ucc_slow_t slow;
+ ucc_fast_t fast;
+ ucc_common_t common;
+ };
+} __attribute__ ((packed)) ucc_t;
+
+/* MultiPHY UTOPIA POS Controllers (UPC)
+*/
+typedef struct upc {
+ u32 upgcr; /* UTOPIA/POS general configuration register */
+ u32 uplpa; /* UTOPIA/POS last PHY address */
+ u32 uphec; /* ATM HEC register */
+ u32 upuc; /* UTOPIA/POS UCC configuration */
+ u32 updc1; /* UTOPIA/POS device 1 configuration */
+ u32 updc2; /* UTOPIA/POS device 2 configuration */
+ u32 updc3; /* UTOPIA/POS device 3 configuration */
+ u32 updc4; /* UTOPIA/POS device 4 configuration */
+ u32 upstpa; /* UTOPIA/POS STPA threshold */
+ u8 res0[0xC];
+ u32 updrs1_h; /* UTOPIA/POS device 1 rate select */
+ u32 updrs1_l; /* UTOPIA/POS device 1 rate select */
+ u32 updrs2_h; /* UTOPIA/POS device 2 rate select */
+ u32 updrs2_l; /* UTOPIA/POS device 2 rate select */
+ u32 updrs3_h; /* UTOPIA/POS device 3 rate select */
+ u32 updrs3_l; /* UTOPIA/POS device 3 rate select */
+ u32 updrs4_h; /* UTOPIA/POS device 4 rate select */
+ u32 updrs4_l; /* UTOPIA/POS device 4 rate select */
+ u32 updrp1; /* UTOPIA/POS device 1 receive priority low */
+ u32 updrp2; /* UTOPIA/POS device 2 receive priority low */
+ u32 updrp3; /* UTOPIA/POS device 3 receive priority low */
+ u32 updrp4; /* UTOPIA/POS device 4 receive priority low */
+ u32 upde1; /* UTOPIA/POS device 1 event */
+ u32 upde2; /* UTOPIA/POS device 2 event */
+ u32 upde3; /* UTOPIA/POS device 3 event */
+ u32 upde4; /* UTOPIA/POS device 4 event */
+ u16 uprp1;
+ u16 uprp2;
+ u16 uprp3;
+ u16 uprp4;
+ u8 res1[0x8];
+ u16 uptirr1_0; /* Device 1 transmit internal rate 0 */
+ u16 uptirr1_1; /* Device 1 transmit internal rate 1 */
+ u16 uptirr1_2; /* Device 1 transmit internal rate 2 */
+ u16 uptirr1_3; /* Device 1 transmit internal rate 3 */
+ u16 uptirr2_0; /* Device 2 transmit internal rate 0 */
+ u16 uptirr2_1; /* Device 2 transmit internal rate 1 */
+ u16 uptirr2_2; /* Device 2 transmit internal rate 2 */
+ u16 uptirr2_3; /* Device 2 transmit internal rate 3 */
+ u16 uptirr3_0; /* Device 3 transmit internal rate 0 */
+ u16 uptirr3_1; /* Device 3 transmit internal rate 1 */
+ u16 uptirr3_2; /* Device 3 transmit internal rate 2 */
+ u16 uptirr3_3; /* Device 3 transmit internal rate 3 */
+ u16 uptirr4_0; /* Device 4 transmit internal rate 0 */
+ u16 uptirr4_1; /* Device 4 transmit internal rate 1 */
+ u16 uptirr4_2; /* Device 4 transmit internal rate 2 */
+ u16 uptirr4_3; /* Device 4 transmit internal rate 3 */
+ u32 uper1; /* Device 1 port enable register */
+ u32 uper2; /* Device 2 port enable register */
+ u32 uper3; /* Device 3 port enable register */
+ u32 uper4; /* Device 4 port enable register */
+ u8 res2[0x150];
+} __attribute__ ((packed)) upc_t;
+
+/* SDMA
+*/
+typedef struct sdma {
+ u32 sdsr; /* Serial DMA status register */
+ u32 sdmr; /* Serial DMA mode register */
+ u32 sdtr1; /* SDMA system bus threshold register */
+ u32 sdtr2; /* SDMA secondary bus threshold register */
+ u32 sdhy1; /* SDMA system bus hysteresis register */
+ u32 sdhy2; /* SDMA secondary bus hysteresis register */
+ u32 sdta1; /* SDMA system bus address register */
+ u32 sdta2; /* SDMA secondary bus address register */
+ u32 sdtm1; /* SDMA system bus MSNUM register */
+ u32 sdtm2; /* SDMA secondary bus MSNUM register */
+ u8 res0[0x10];
+ u32 sdaqr; /* SDMA address bus qualify register */
+ u32 sdaqmr; /* SDMA address bus qualify mask register */
+ u8 res1[0x4];
+ u32 sdebcr; /* SDMA CAM entries base register */
+ u8 res2[0x38];
+} __attribute__ ((packed)) sdma_t;
+
+/* Debug Space
+*/
+typedef struct dbg {
+ u32 bpdcr; /* Breakpoint debug command register */
+ u32 bpdsr; /* Breakpoint debug status register */
+ u32 bpdmr; /* Breakpoint debug mask register */
+ u32 bprmrr0; /* Breakpoint request mode risc register 0 */
+ u32 bprmrr1; /* Breakpoint request mode risc register 1 */
+ u8 res0[0x8];
+ u32 bprmtr0; /* Breakpoint request mode trb register 0 */
+ u32 bprmtr1; /* Breakpoint request mode trb register 1 */
+ u8 res1[0x8];
+ u32 bprmir; /* Breakpoint request mode immediate register */
+ u32 bprmsr; /* Breakpoint request mode serial register */
+ u32 bpemr; /* Breakpoint exit mode register */
+ u8 res2[0x48];
+} __attribute__ ((packed)) dbg_t;
+
+/* RISC Special Registers (Trap and Breakpoint)
+*/
+typedef struct rsp {
+ u8 fixme[0x100];
+} __attribute__ ((packed)) rsp_t;
+
+typedef struct qe_immap {
+ qe_iram_t iram; /* I-RAM */
+ qe_ic_t ic; /* Interrupt Controller */
+ cp_qe_t cp; /* Communications Processor */
+ qe_mux_t qmx; /* QE Multiplexer */
+ qe_timers_t qet; /* QE Timers */
+ spi_t spi[0x2]; /* spi */
+ mcc_t mcc; /* mcc */
+ qe_brg_t brg; /* brg */
+ usb_t usb; /* USB */
+ si1_t si1; /* SI */
+ u8 res11[0x800];
+ sir_t sir; /* SI Routing Tables */
+ ucc_t ucc1; /* ucc1 */
+ ucc_t ucc3; /* ucc3 */
+ ucc_t ucc5; /* ucc5 */
+ ucc_t ucc7; /* ucc7 */
+ u8 res12[0x600];
+ upc_t upc1; /* MultiPHY UTOPIA POS Controller 1 */
+ ucc_t ucc2; /* ucc2 */
+ ucc_t ucc4; /* ucc4 */
+ ucc_t ucc6; /* ucc6 */
+ ucc_t ucc8; /* ucc8 */
+ u8 res13[0x600];
+ upc_t upc2; /* MultiPHY UTOPIA POS Controller 2 */
+ sdma_t sdma; /* SDMA */
+ dbg_t dbg; /* Debug Space */
+ rsp_t rsp[0x2]; /* RISC Special Registers (Trap and Breakpoint)
+ */
+ u8 res14[0x300];
+ u8 res15[0x3A00];
+ u8 res16[0x8000]; /* 0x108000 - 0x110000 */
+ u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
+ u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
+ u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
+} __attribute__ ((packed)) qe_map_t;
+
+extern qe_map_t *qe_immr;
+extern phys_addr_t get_qe_base(void);
+
+static inline unsigned long immrbar_virt_to_phys(volatile void * address)
+{
+ if ( ((uint)address >= (uint)qe_immr) &&
+ ((uint)address < ((uint)qe_immr + QE_IMMAP_SIZE)) )
+ return (unsigned long)(address - (uint)qe_immr +
+ (uint)get_qe_base());
+ return (unsigned long)virt_to_phys(address);
+}
+
+static inline void * immrbar_phys_to_virt(unsigned long address)
+{
+ if ( (address >= (uint)get_qe_base()) &&
+ (address < ((uint)get_qe_base() + QE_IMMAP_SIZE)) )
+ return (void *)(address - (uint)get_qe_base() + (uint)qe_immr);
+ return (void *)phys_to_virt(address);
+}
+
+#endif /* __IMMAP_QE_H__ */
+#endif /* __KERNEL__ */
+#endif /* CONFIG_QUICC_ENGINE */
--
1.4.2.1
^ permalink raw reply related
* [PATCH 5/15] qe_lib: Add QE I/O ports API
From: Kim Phillips @ 2006-09-30 23:33 UTC (permalink / raw)
To: linuxppc-dev
qe_lib: Add QE I/O ports API
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Shlomi Gridish <gridish@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
arch/powerpc/sysdev/qe_lib/qe_io.c | 230 ++++++++++++++++++++++++++++++++++++
1 files changed, 230 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
new file mode 100644
index 0000000..265b464
--- /dev/null
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
+ *
+ * Author: Li Yang <LeoLi@freescale.com>
+ *
+ * Description:
+ * QE Parallel I/O ports configuration routines. Based on code from
+ * Shlomi Gridish <gridish@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/config.h>
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/ioport.h>
+
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <sysdev/fsl_soc.h>
+#undef DEBUG
+
+#define NUM_OF_PINS 32
+
+struct port_regs {
+ u32 cpodr; /* Open drain register */
+ u32 cpdata; /* Data register */
+ u32 cpdir1; /* Direction register */
+ u32 cpdir2; /* Direction register */
+ u32 cppar1; /* Pin assignment register */
+ u32 cppar2; /* Pin assignment register */
+};
+
+static struct port_regs *par_io = NULL;
+static int num_par_io_ports = 0;
+
+int par_io_init(struct device_node *np)
+{
+ struct resource res;
+ int ret;
+ u32 *num_ports;
+
+ /* Map Parallel I/O ports registers */
+ ret = of_address_to_resource(np, 0, &res);
+ if (ret)
+ return ret;
+ par_io = (struct port_regs *)ioremap(res.start, res.end - res.start + 1);
+
+ num_ports = get_property(np, "num-ports", NULL);
+ if (num_ports)
+ num_par_io_ports = *num_ports;
+
+ return 0;
+}
+
+int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
+ int assignment, int has_irq)
+{
+ u32 pinMask1bit, pinMask2bits, newMask2bits, tmp_val;
+
+ if (!par_io)
+ return -1;
+
+ /* calculate pin location for single and 2 bits information */
+ pinMask1bit = (u32) (1 << (NUM_OF_PINS - (pin + 1)));
+
+ /* Set open drain, if required */
+ tmp_val = in_be32(&par_io[port].cpodr);
+ if (open_drain)
+ out_be32(&par_io[port].cpodr, pinMask1bit | tmp_val);
+ else
+ out_be32(&par_io[port].cpodr, ~pinMask1bit & tmp_val);
+
+ /* define direction */
+ tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
+ in_be32(&par_io[port].cpdir2) :
+ in_be32(&par_io[port].cpdir1);
+
+ /* get all bits mask for 2 bit per port */
+ pinMask2bits = (u32) (0x3 <<
+ (NUM_OF_PINS -
+ (pin % (NUM_OF_PINS / 2) + 1) * 2));
+
+ /* Get the final mask we need for the right definition */
+ newMask2bits = (u32) (dir <<
+ (NUM_OF_PINS -
+ (pin % (NUM_OF_PINS / 2) + 1) * 2));
+
+ /* clear and set 2 bits mask */
+ if (pin > (NUM_OF_PINS / 2) - 1) {
+ out_be32(&par_io[port].cpdir2,
+ ~pinMask2bits & tmp_val);
+ tmp_val &= ~pinMask2bits;
+ out_be32(&par_io[port].cpdir2, newMask2bits | tmp_val);
+ } else {
+ out_be32(&par_io[port].cpdir1,
+ ~pinMask2bits & tmp_val);
+ tmp_val &= ~pinMask2bits;
+ out_be32(&par_io[port].cpdir1, newMask2bits | tmp_val);
+ }
+ /* define pin assignment */
+ tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
+ in_be32(&par_io[port].cppar2) :
+ in_be32(&par_io[port].cppar1);
+
+ newMask2bits = (u32) (assignment << (NUM_OF_PINS -
+ (pin % (NUM_OF_PINS / 2) + 1) * 2));
+ /* clear and set 2 bits mask */
+ if (pin > (NUM_OF_PINS / 2) - 1) {
+ out_be32(&par_io[port].cppar2,
+ ~pinMask2bits & tmp_val);
+ tmp_val &= ~pinMask2bits;
+ out_be32(&par_io[port].cppar2, newMask2bits | tmp_val);
+ } else {
+ out_be32(&par_io[port].cppar1,
+ ~pinMask2bits & tmp_val);
+ tmp_val &= ~pinMask2bits;
+ out_be32(&par_io[port].cppar1, newMask2bits | tmp_val);
+ }
+
+ return 0;
+}
+
+EXPORT_SYMBOL(par_io_config_pin);
+
+int par_io_data_set(u8 port, u8 pin, u8 val)
+{
+ u32 pin_mask, tmp_val;
+
+ if (port >= num_par_io_ports)
+ return -EINVAL;
+ if (pin >= NUM_OF_PINS)
+ return -EINVAL;
+ /* calculate pin location */
+ pin_mask = (u32) (1 << (NUM_OF_PINS - 1 - pin));
+
+ tmp_val = in_be32(&par_io[port].cpdata);
+
+ if (val == 0) /* clear */
+ out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val);
+ else /* set */
+ out_be32(&par_io[port].cpdata, pin_mask | tmp_val);
+
+ return 0;
+}
+
+EXPORT_SYMBOL(par_io_data_set);
+
+int par_io_of_config(struct device_node *np)
+{
+ struct device_node *pio;
+ phandle *ph;
+ int pio_map_len;
+ unsigned int *pio_map;
+
+ if (par_io == NULL) {
+ printk(KERN_ERR "par_io not initialized \n");
+ return -1;
+ }
+
+ ph = (phandle *) get_property(np, "pio-handle", NULL);
+ if (ph == 0) {
+ printk(KERN_ERR "pio-handle not available \n");
+ return -1;
+ }
+
+ pio = of_find_node_by_phandle(*ph);
+
+ pio_map = (unsigned int *)
+ get_property(pio, "pio-map", &pio_map_len);
+ if (pio_map == NULL) {
+ printk(KERN_ERR "pio-map is not set! \n");
+ return -1;
+ }
+ pio_map_len /= sizeof(unsigned int);
+ if ((pio_map_len % 6) != 0) {
+ printk(KERN_ERR "pio-map format wrong! \n");
+ return -1;
+ }
+
+ while (pio_map_len > 0) {
+ par_io_config_pin((u8) pio_map[0], (u8) pio_map[1],
+ (int) pio_map[2], (int) pio_map[3],
+ (int) pio_map[4], (int) pio_map[5]);
+ pio_map += 6;
+ pio_map_len -= 6;
+ }
+ of_node_put(pio);
+ return 0;
+}
+EXPORT_SYMBOL(par_io_of_config);
+
+#ifdef DEBUG
+static void dump_par_io(void)
+{
+ int i;
+
+ printk(KERN_INFO "PAR IO registars:\n");
+ printk(KERN_INFO "Base address: 0x%08x\n", (u32) par_io);
+ for (i = 0; i < num_par_io_ports; i++) {
+ printk(KERN_INFO "cpodr[%d] : addr - 0x%08x, val - 0x%08x\n",
+ i, (u32) & par_io[i].cpodr,
+ in_be32(&par_io[i].cpodr));
+ printk(KERN_INFO "cpdata[%d]: addr - 0x%08x, val - 0x%08x\n",
+ i, (u32) & par_io[i].cpdata,
+ in_be32(&par_io[i].cpdata));
+ printk(KERN_INFO "cpdir1[%d]: addr - 0x%08x, val - 0x%08x\n",
+ i, (u32) & par_io[i].cpdir1,
+ in_be32(&par_io[i].cpdir1));
+ printk(KERN_INFO "cpdir2[%d]: addr - 0x%08x, val - 0x%08x\n",
+ i, (u32) & par_io[i].cpdir2,
+ in_be32(&par_io[i].cpdir2));
+ printk(KERN_INFO "cppar1[%d]: addr - 0x%08x, val - 0x%08x\n",
+ i, (u32) & par_io[i].cppar1,
+ in_be32(&par_io[i].cppar1));
+ printk(KERN_INFO "cppar2[%d]: addr - 0x%08x, val - 0x%08x\n",
+ i, (u32) & par_io[i].cppar2,
+ in_be32(&par_io[i].cppar2));
+ }
+
+}
+
+EXPORT_SYMBOL(dump_par_io);
+#endif
--
1.4.2.1
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