* Re: Device tree and external RTC
From: Bruce_Leonard @ 2007-10-04 18:17 UTC (permalink / raw)
To: Guennadi Liakhovetski; +Cc: linuxppc-embedded
In-Reply-To: <Pine.LNX.4.60.0710041046040.4537@poirot.grange>
Guennadi Liakhovetski <g.liakhovetski@gmx.de> wrote on 10/04/2007 02:29:06
AM:
> > CONFIG_SENSORS_M41T00=y
>
> It shall not hurt, but do you really have this one?
I turned this on because my clock is a SMT M41T00. Not sure why it's
called a sensor in the .config.
> First, this might be either a userspace or a kernel problem. Do you have
> the correct device nodes? Are you using udev? Should be something like
Ultimatly it was my own stupididty that did me in. You are absolutly
correct, I didn't have the right device nodes and because we're limited on
space we don't want to use udev. Once I created the rtc0 device and
linked rtc to it, hwclock started working correctly.
> > When I dump out ppc_md, all the RTC functions (i.e., get_rtc_time,
> > read_rtc_val, etc.) are all NULL.
>
> Don't think you need those. Those are for powerpc platforms not using
> the generic rtc driver.
Right.
> you need suitable entries in arch/powerpc/sysdev/fsl_soc.c in the
> i2c_devices array. I think, patch at
> http://patchwork.ozlabs.org/linuxppc/patch?id=13624 is exactly what you
> need.
I'll give this a try. I'd really prefer to be using the device tree for
this, but I guess as long as I have it working using configuration options
in the kernel it doesn't really matter. Either way I don't have to write
any special board support code for the kernel.
Thanks for all the information and pointers. It's been a big help!
Bruce
^ permalink raw reply
* Re: Stdout console clogging => 300ms blocked
From: Linas Vepstas @ 2007-10-04 17:21 UTC (permalink / raw)
To: Hollis Blanchard; +Cc: linuxppc-dev
In-Reply-To: <fe0v88$dt5$1@sea.gmane.org>
Hi Bernard,
On Wed, Oct 03, 2007 at 08:49:12PM +0000, Hollis Blanchard wrote:
> On Tue, 02 Oct 2007 09:41:28 +0200, Willaert, Bernard wrote:
>
> > Problem:
> > When we log debug output via the serial console on a multithreaded
> > application, the console throughput may get clogged and then we
> > experience a >300ms deadlock.
> >
> > #define THREAD_DELAY 1000
> > usleep(THREAD_DELAY);
> > fprintf(stdout," <----- thread 1\n");
[...]
> >
> > usleep(THREAD_DELAY);
> > fprintf(stdout," <----- thread 2\n");
> >
> > baudrate=115200
OK, lets do the math. 115200 baud == approx 115200 bits per second
assuming 8N1 for stop & parity bits, I get approx 9 bits per byte
so your serial port is capable of 115.2/9 = 12.8KBytes per second.
Now, every millisecond, you are attempting to print
" <----- thread 1\n"
Lets see, thats 17 bytes. And also " <----- thread 2\n" for
a grand total of 34 bytes per millisecond.
And you are attempting to jam this through a serial line capable
of 12.8 Bytes per millisecond? Well, of course it won't fit!
> > Real output on the console:
> >
> > .... /\ ........
> > <----- thread 1
> > <----- thread 2
> > <----- thread 1
> > <----- thread 2
> > <----- thread 1
> > <----- thread 2
> > !!!!!!!!!!! thread2 interval timeout = 335 ms
Well, thread 1 clearly also had a delay of 335 milliseconds
for a total of 670 milliseconds delay.
Now, theoretically, we should have seen a delay equal to
(34 - 12.8)/34 = 0.623 seconds
I'd say that theory and practice match up pretty damned well;
I see no evidence of any problem at all.
> Could you not post HTML please? Thanks.
Agreed.
--linas
^ permalink raw reply
* Re: Is it safe to use these Linux function (test_bit(), set_bit(), clear_bit()) in character device driver for 2.6.10 ppc kernel.
From: Grant Likely @ 2007-10-04 16:42 UTC (permalink / raw)
To: Misbah khan; +Cc: linuxppc-embedded
In-Reply-To: <13039401.post@talk.nabble.com>
On 10/4/07, Misbah khan <misbah_khan@engineer.com> wrote:
>
> Hi ...
> I did followed you and it worked as well. I really Thank you for it.
>
> At one Place i am doing memcpy() of floating point data to the memory mapped
> registers, what could be the substitute of it like "memcpy_toio() " which is
> suggested in the Book. I am working BE architecture.
>
> I would really appreaciate if you would let me know the defineation of these
> wrapper functions (in_be32,out_be32(),ioread32(),iowrite32(),etc) so that i
> could have the clear idea of the reason for not directly dreferencing the
> Pointer.
You don't want to directly dereference pointers to device registers
because you don't want the processor or compiler to reorder your
register accesses. The in/out_* wrappers keeps the compiler from
reordering things, and the wrappers contain the 'sync' instruction
which prevents the processor from reordering operations at runtime.
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
grant.likely@secretlab.ca
(403) 399-0195
^ permalink raw reply
* Re: [PATCH] Don't build arch/powerpc/sysdev/dcr.c for ARCH=ppc kernels
From: Josh Boyer @ 2007-10-04 14:42 UTC (permalink / raw)
To: michael; +Cc: linuxppc-dev, paulus
In-Reply-To: <1191508485.7014.7.camel@concordia>
On Fri, 05 Oct 2007 00:34:45 +1000
Michael Ellerman <michael@ellerman.id.au> wrote:
> On Thu, 2007-10-04 at 05:56 -0500, Josh Boyer wrote:
> > On Wed, 2007-10-03 at 22:50 -0600, Grant Likely wrote:
> > > From: Grant Likely <grant.likely@secretlab.ca>
> > >
> > > dcr.c is an arch/powerpc only thing.
> > >
> > > Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> > > ---
> > >
> > > Ben/Paulus,
> > >
> > > As far as I can tell this is correct. Having sysdev/dcr.c in the arch/ppc
> > > build spits out warnings. Grep doesn't show anything in arch/ppc that
> > > is using it.
> >
> > Sorry, no. The ibm_emac driver uses it, which is arch/ppc. (Yes, the
> > old one.)
> >
> > If there are warnings, let's fix those up. Perhaps Michael's recent
> > patches in that area introduced something.
>
> Hmm, I picked a good time to be away :)
>
> I think it's OK. ibm_emac uses dcr_write() but it should always be using
> the native one from dcr-native.h. So I think this patch is good.
Agreed.
> Just another reason to get rid of arch/ppc :D
Agreed.
josh
^ permalink raw reply
* Re: [PATCH] Don't build arch/powerpc/sysdev/dcr.c for ARCH=ppc kernels
From: Michael Ellerman @ 2007-10-04 14:34 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev, paulus
In-Reply-To: <1191495405.3647.3.camel@localhost.localdomain>
[-- Attachment #1: Type: text/plain, Size: 1199 bytes --]
On Thu, 2007-10-04 at 05:56 -0500, Josh Boyer wrote:
> On Wed, 2007-10-03 at 22:50 -0600, Grant Likely wrote:
> > From: Grant Likely <grant.likely@secretlab.ca>
> >
> > dcr.c is an arch/powerpc only thing.
> >
> > Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> > ---
> >
> > Ben/Paulus,
> >
> > As far as I can tell this is correct. Having sysdev/dcr.c in the arch/ppc
> > build spits out warnings. Grep doesn't show anything in arch/ppc that
> > is using it.
>
> Sorry, no. The ibm_emac driver uses it, which is arch/ppc. (Yes, the
> old one.)
>
> If there are warnings, let's fix those up. Perhaps Michael's recent
> patches in that area introduced something.
Hmm, I picked a good time to be away :)
I think it's OK. ibm_emac uses dcr_write() but it should always be using
the native one from dcr-native.h. So I think this patch is good.
Just another reason to get rid of arch/ppc :D
cheers
--
Michael Ellerman
OzLabs, IBM Australia Development Lab
wwweb: http://michael.ellerman.id.au
phone: +61 2 6212 1183 (tie line 70 21183)
We do not inherit the earth from our ancestors,
we borrow it from our children. - S.M.A.R.T Person
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* [PATCH] [POWERPC] 85xx: Killed <asm/mpc85xx.h>
From: Kumar Gala @ 2007-10-04 13:54 UTC (permalink / raw)
To: linuxppc-dev
asm-powerpc/mpc85xx.h was really a hold over from arch/ppc. Now that
more decoupling has occurred we can remove <asm/mpc85xx.h> and some of
its legacy.
As part of this we moved the definition of CPM_MAP_ADDR into cpm2_common
for 85xx platforms. This is a stop gap until we switch them over to the
new device-tree based config.
---
arch/powerpc/platforms/85xx/mpc8540_ads.h | 35 -----------------
arch/powerpc/platforms/85xx/mpc85xx_ads.c | 1 -
arch/powerpc/platforms/85xx/mpc85xx_ads.h | 60 -----------------------------
arch/powerpc/platforms/85xx/mpc85xx_cds.c | 10 ++++-
arch/powerpc/platforms/85xx/mpc85xx_cds.h | 43 --------------------
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 1 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 -
arch/powerpc/sysdev/cpm2_common.c | 4 ++
include/asm-powerpc/cpm2.h | 20 ----------
include/asm-powerpc/fs_pd.h | 2 -
include/asm-powerpc/mpc85xx.h | 45 ---------------------
11 files changed, 13 insertions(+), 209 deletions(-)
delete mode 100644 arch/powerpc/platforms/85xx/mpc8540_ads.h
delete mode 100644 arch/powerpc/platforms/85xx/mpc85xx_ads.h
delete mode 100644 arch/powerpc/platforms/85xx/mpc85xx_cds.h
delete mode 100644 include/asm-powerpc/mpc85xx.h
Removing code is far more fun than adding it :)
diff --git a/arch/powerpc/platforms/85xx/mpc8540_ads.h b/arch/powerpc/platforms/85xx/mpc8540_ads.h
deleted file mode 100644
index da82f4c..0000000
--- a/arch/powerpc/platforms/85xx/mpc8540_ads.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * arch/powerpc/platforms/85xx/mpc8540_ads.h
- *
- * MPC8540ADS board definitions
- *
- * Maintainer: Kumar Gala <kumar.gala@freescale.com>
- *
- * Copyright 2004 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifndef __MACH_MPC8540ADS_H__
-#define __MACH_MPC8540ADS_H__
-
-#include <linux/initrd.h>
-
-#define BOARD_CCSRBAR ((uint)0xe0000000)
-#define BCSR_ADDR ((uint)0xf8000000)
-#define BCSR_SIZE ((uint)(32 * 1024))
-
-/* PCI interrupt controller */
-#define PIRQA MPC85xx_IRQ_EXT1
-#define PIRQB MPC85xx_IRQ_EXT2
-#define PIRQC MPC85xx_IRQ_EXT3
-#define PIRQD MPC85xx_IRQ_EXT4
-
-/* Offset of CPM register space */
-#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET)
-
-#endif /* __MACH_MPC8540ADS_H__ */
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 378a244..5bc9319 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -22,7 +22,6 @@
#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
-#include <asm/mpc85xx.h>
#include <asm/prom.h>
#include <asm/mpic.h>
#include <mm/mmu_decl.h>
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.h b/arch/powerpc/platforms/85xx/mpc85xx_ads.h
deleted file mode 100644
index 46c3532..0000000
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * MPC85xx ADS board definitions
- *
- * Maintainer: Kumar Gala <galak@kernel.crashing.org>
- *
- * Copyright 2004 Freescale Semiconductor Inc.
- *
- * 2006 (c) MontaVista Software, Inc.
- * Vitaly Bordug <vbordug@ru.mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifndef __MACH_MPC85XXADS_H
-#define __MACH_MPC85XXADS_H
-
-#include <linux/initrd.h>
-#include <sysdev/fsl_soc.h>
-
-#define BCSR_ADDR ((uint)0xf8000000)
-#define BCSR_SIZE ((uint)(32 * 1024))
-
-#ifdef CONFIG_CPM2
-
-#define MPC85xx_CPM_OFFSET (0x80000)
-
-#define CPM_MAP_ADDR (get_immrbase() + MPC85xx_CPM_OFFSET)
-#define CPM_IRQ_OFFSET 60
-
-#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
-#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
-#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
-#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
-#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
-#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
-
-/* FCC1 Clock Source Configuration. These can be
- * redefined in the board specific file.
- * Can only choose from CLK9-12 */
-#define F1_RXCLK 12
-#define F1_TXCLK 11
-
-/* FCC2 Clock Source Configuration. These can be
- * redefined in the board specific file.
- * Can only choose from CLK13-16 */
-#define F2_RXCLK 13
-#define F2_TXCLK 14
-
-/* FCC3 Clock Source Configuration. These can be
- * redefined in the board specific file.
- * Can only choose from CLK13-16 */
-#define F3_RXCLK 15
-#define F3_TXCLK 16
-
-#endif /* CONFIG_CPM2 */
-#endif /* __MACH_MPC85XXADS_H */
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index afe5868..4d063ee 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -36,7 +36,6 @@
#include <asm/machdep.h>
#include <asm/ipic.h>
#include <asm/pci-bridge.h>
-#include <asm/mpc85xx.h>
#include <asm/irq.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
@@ -47,6 +46,15 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
+/* CADMUS info */
+/* xxx - galak, move into device tree */
+#define CADMUS_BASE (0xf8004000)
+#define CADMUS_SIZE (256)
+#define CM_VER (0)
+#define CM_CSR (1)
+#define CM_RST (2)
+
+
static int cds_pci_slot = 2;
static volatile u8 *cadmus;
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.h b/arch/powerpc/platforms/85xx/mpc85xx_cds.h
deleted file mode 100644
index b251c9f..0000000
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * arch/powerpc/platforms/85xx/mpc85xx_cds.h
- *
- * MPC85xx CDS board definitions
- *
- * Maintainer: Kumar Gala <galak@kernel.crashing.org>
- *
- * Copyright 2004 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-#ifndef __MACH_MPC85XX_CDS_H__
-#define __MACH_MPC85XX_CDS_H__
-
-/* CADMUS info */
-#define CADMUS_BASE (0xf8004000)
-#define CADMUS_SIZE (256)
-#define CM_VER (0)
-#define CM_CSR (1)
-#define CM_RST (2)
-
-/* CDS NVRAM/RTC */
-#define CDS_RTC_ADDR (0xf8000000)
-#define CDS_RTC_SIZE (8 * 1024)
-
-/* PCI interrupt controller */
-#define PIRQ0A MPC85xx_IRQ_EXT0
-#define PIRQ0B MPC85xx_IRQ_EXT1
-#define PIRQ0C MPC85xx_IRQ_EXT2
-#define PIRQ0D MPC85xx_IRQ_EXT3
-#define PIRQ1A MPC85xx_IRQ_EXT11
-
-#define NR_8259_INTS 16
-#define CPM_IRQ_OFFSET NR_8259_INTS
-
-#define MPC85xx_OPENPIC_IRQ_OFFSET 80
-
-#endif /* __MACH_MPC85XX_CDS_H__ */
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 772e8de..59c121a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -24,7 +24,6 @@
#include <asm/time.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
-#include <asm/mpc85xx.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
#include <asm/udbg.h>
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 00f4c3a..2269d2e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -39,7 +39,6 @@
#include <asm/io.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
-#include <asm/mpc85xx.h>
#include <asm/irq.h>
#include <mm/mmu_decl.h>
#include <asm/prom.h>
diff --git a/arch/powerpc/sysdev/cpm2_common.c b/arch/powerpc/sysdev/cpm2_common.c
index 453f8a5..ea2ba84 100644
--- a/arch/powerpc/sysdev/cpm2_common.c
+++ b/arch/powerpc/sysdev/cpm2_common.c
@@ -330,6 +330,10 @@ static rh_block_t cpm_boot_dpmem_rh_block[16];
static rh_info_t cpm_dpmem_info;
static u8 __iomem *im_dprambase;
+#ifdef CONFIG_PPC_85xx
+#define CPM_MAP_ADDR (get_immrbase() + 0x80000)
+#endif
+
static void cpm2_dpinit(void)
{
spin_lock_init(&cpm_dpmem_lock);
diff --git a/include/asm-powerpc/cpm2.h b/include/asm-powerpc/cpm2.h
index e698b1d..111f45d 100644
--- a/include/asm-powerpc/cpm2.h
+++ b/include/asm-powerpc/cpm2.h
@@ -1120,26 +1120,6 @@ typedef struct im_idma {
#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
-#define PC_F1RXCLK PC_CLK(F1_RXCLK)
-#define PC_F1TXCLK PC_CLK(F1_TXCLK)
-#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
-#define CMX1_CLK_MASK ((uint)0xff000000)
-
-#define PC_F2RXCLK PC_CLK(F2_RXCLK)
-#define PC_F2TXCLK PC_CLK(F2_TXCLK)
-#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
-#define CMX2_CLK_MASK ((uint)0x00ff0000)
-
-#define PC_F3RXCLK PC_CLK(F3_RXCLK)
-#define PC_F3TXCLK PC_CLK(F3_TXCLK)
-#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
-#define CMX3_CLK_MASK ((uint)0x0000ff00)
-
-#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
-#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
-
-#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
-
/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
* but there is little variation among the choices.
*/
diff --git a/include/asm-powerpc/fs_pd.h b/include/asm-powerpc/fs_pd.h
index 64706a0..9361cd5 100644
--- a/include/asm-powerpc/fs_pd.h
+++ b/include/asm-powerpc/fs_pd.h
@@ -19,8 +19,6 @@
#if defined(CONFIG_8260)
#include <asm/mpc8260.h>
-#elif defined(CONFIG_85xx)
-#include <asm/mpc85xx.h>
#endif
#define cpm2_map(member) (&cpm2_immr->member)
diff --git a/include/asm-powerpc/mpc85xx.h b/include/asm-powerpc/mpc85xx.h
deleted file mode 100644
index 5414299..0000000
--- a/include/asm-powerpc/mpc85xx.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * include/asm-powerpc/mpc85xx.h
- *
- * MPC85xx definitions
- *
- * Maintainer: Kumar Gala <galak@kernel.crashing.org>
- *
- * Copyright 2004 Freescale Semiconductor, Inc
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_MPC85xx_H__
-#define __ASM_MPC85xx_H__
-
-#include <asm/mmu.h>
-
-#ifdef CONFIG_85xx
-
-#if defined(CONFIG_MPC8540_ADS) || defined(CONFIG_MPC8560_ADS)
-#include <platforms/85xx/mpc85xx_ads.h>
-#endif
-#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
-#include <platforms/85xx/mpc8555_cds.h>
-#endif
-#ifdef CONFIG_MPC85xx_CDS
-#include <platforms/85xx/mpc85xx_cds.h>
-#endif
-
-/* Let modules/drivers get at CCSRBAR */
-extern phys_addr_t get_ccsrbar(void);
-
-#ifdef MODULE
-#define CCSRBAR get_ccsrbar()
-#else
-#define CCSRBAR BOARD_CCSRBAR
-#endif
-
-#endif /* CONFIG_85xx */
-#endif /* __ASM_MPC85xx_H__ */
-#endif /* __KERNEL__ */
--
1.5.2.4
^ permalink raw reply related
* Re: [PATCH 2/5] Add initial MPC8610 HPCD Platform files.
From: Kumar Gala @ 2007-10-04 13:43 UTC (permalink / raw)
To: Jon Loeliger; +Cc: Stephen Rothwell, Xianghua Xiao, linuxppc-dev@ozlabs.org
In-Reply-To: <E1IdQ7s-0006DC-8I@jdl.com>
On Oct 4, 2007, at 7:48 AM, Jon Loeliger wrote:
> So, like, the other day Kumar Gala mumbled:
>>
>> On Oct 3, 2007, at 10:41 PM, Stephen Rothwell wrote:
>>
>>> On Wed, 03 Oct 2007 15:09:33 -0500 Jon Loeliger <jdl@freescale.com>
>>> wrote:
>>>>
>>>> +++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
>>>> +#include <linux/stddef.h>
>>>> +#include <linux/kernel.h>
>>>> +#include <linux/pci.h>
>>>> +#include <linux/kdev_t.h>
>>>> +#include <linux/delay.h>
>>>> +#include <linux/seq_file.h>
>>>> +
>>>> +#include <asm/system.h>
>>>> +#include <asm/time.h>
>>>> +#include <asm/machdep.h>
>>>> +#include <asm/pci-bridge.h>
>>>> +#include <asm/mpc86xx.h>
>>>> +#include <asm/prom.h>
>>>
>>> You should include linux/of.h as well to use the of_ accessor
>>> functions.
>>
>> added.
>>
>> - k
>
> Thanks, Kumar.
np. I made a few other changes (like killing the cpuinfo code in the
platform).
this is on my for-2.6.24 branch now.
- k
^ permalink raw reply
* [RFC][PATCH][POWERPC] QEIC: Implement pluggable handlers, fix MPIC cascading
From: Anton Vorontsov @ 2007-10-04 13:04 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
In-Reply-To: <1191362562.22572.24.camel@pasglop>
On Wed, Oct 03, 2007 at 08:02:42AM +1000, Benjamin Herrenschmidt wrote:
>
> >
> > Exactly, this is what that patch is trying to do. QEIC cascade handler is
> > calling mpic's eoi() (end() actually, as it's flow level, but end == eoi.
> > Is it main objection? Ok, I can get rid of it, and use chip level eoi()
> > directly).
>
> Yes, use eoi() directly, don't add end()
Ok.
> > Yup, exactly. Actually, QEIC's cascade handlers do not really know
> > what needs to be done, but they're good at guessing (if (chip->eoi)).
> >
> > Sure, I can place board-specific QEIC handlers in the board file, but
> > that will be quite big code duplication for all machines using QEIC.
>
> Maybe you can provide a set of common ones, and then just pick the one
> you want from the board file ?
>
> Or have some board code call into a QEIC init routine specifying the
> type of cascade handler to use ... or whatevre you like here.
Ok, thanks. How about this patch?
- - - -
From: Anton Vorontsov <avorontsov@ru.mvista.com>
Subject: [PATCH] [POWERPC] QEIC: Implement pluggable handlers, fix MPIC cascading
set_irq_chained_handler overwrites MPIC's handle_irq function
(handle_fasteoi_irq) thus MPIC never gets eoi event from the
cascaded IRQ. This situation hangs MPIC on MPC8568E.
To solve this problem efficiently, QEIC needs pluggable handlers,
specific to the underlaying interrupt controller.
Patch extends qe_ic_init() function to accept low and high interrupt
handlers. To avoid #ifdefs, stack of interrupt handlers specified in
the header file and functions are marked 'static inline', thus
handlers are compiled-in only if actually used (in the board file).
Another option would be to lookup for parent controller and
automatically detect handlers, but this will waste text size because
of never used handlers.
qe_ic_init() also changed in regard to support multiplexed high/low
lines as found in MPC8568E-MDS, plus qe_ic_cascade_muxed_mpic()
handler implemented appropriately.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
arch/powerpc/platforms/83xx/mpc832x_mds.c | 2 +-
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 2 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +-
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 2 +-
arch/powerpc/sysdev/qe_lib/qe_ic.c | 29 +++---------
include/asm-powerpc/qe_ic.h | 68 ++++++++++++++++++++++++++++-
6 files changed, 78 insertions(+), 27 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index d494bc4..95f32ca 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -140,7 +140,7 @@ static void __init mpc832x_sys_init_IRQ(void)
if (!np)
return;
- qe_ic_init(np, 0);
+ qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
of_node_put(np);
#endif /* CONFIG_QUICC_ENGINE */
}
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index 24a790c..f842a1c 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -151,7 +151,7 @@ void __init mpc832x_rdb_init_IRQ(void)
if (!np)
return;
- qe_ic_init(np, 0);
+ qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
of_node_put(np);
#endif /* CONFIG_QUICC_ENGINE */
}
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index db69576..5971fe6 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -147,7 +147,7 @@ static void __init mpc836x_mds_init_IRQ(void)
if (!np)
return;
- qe_ic_init(np, 0);
+ qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
of_node_put(np);
#endif /* CONFIG_QUICC_ENGINE */
}
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index c379286..69c177b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -174,7 +174,7 @@ static void __init mpc85xx_mds_pic_init(void)
if (!np)
return;
- qe_ic_init(np, 0);
+ qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
of_node_put(np);
#endif /* CONFIG_QUICC_ENGINE */
}
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index 9a2d1ed..e1c0fd6 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -321,25 +321,9 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-void qe_ic_cascade_low(unsigned int irq, struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = desc->handler_data;
- unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-}
-
-void qe_ic_cascade_high(unsigned int irq, struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = desc->handler_data;
- unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-}
-
-void __init qe_ic_init(struct device_node *node, unsigned int flags)
+void __init qe_ic_init(struct device_node *node, unsigned int flags,
+ void (*low_handler)(unsigned int irq, struct irq_desc *desc),
+ void (*high_handler)(unsigned int irq, struct irq_desc *desc))
{
struct qe_ic *qe_ic;
struct resource res;
@@ -399,11 +383,12 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags)
qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
set_irq_data(qe_ic->virq_low, qe_ic);
- set_irq_chained_handler(qe_ic->virq_low, qe_ic_cascade_low);
+ set_irq_chained_handler(qe_ic->virq_low, low_handler);
- if (qe_ic->virq_high != NO_IRQ) {
+ if (qe_ic->virq_high != NO_IRQ &&
+ qe_ic->virq_high != qe_ic->virq_low) {
set_irq_data(qe_ic->virq_high, qe_ic);
- set_irq_chained_handler(qe_ic->virq_high, qe_ic_cascade_high);
+ set_irq_chained_handler(qe_ic->virq_high, high_handler);
}
}
diff --git a/include/asm-powerpc/qe_ic.h b/include/asm-powerpc/qe_ic.h
index e386fb7..a779b2c 100644
--- a/include/asm-powerpc/qe_ic.h
+++ b/include/asm-powerpc/qe_ic.h
@@ -56,9 +56,75 @@ enum qe_ic_grp_id {
QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
};
-void qe_ic_init(struct device_node *node, unsigned int flags);
+void qe_ic_init(struct device_node *node, unsigned int flags,
+ void (*low_handler)(unsigned int irq, struct irq_desc *desc),
+ void (*high_handler)(unsigned int irq, struct irq_desc *desc));
void qe_ic_set_highest_priority(unsigned int virq, int high);
int qe_ic_set_priority(unsigned int virq, unsigned int priority);
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
+struct qe_ic;
+unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
+unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
+
+static inline void qe_ic_cascade_low_ipic(unsigned int irq,
+ struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = desc->handler_data;
+ unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+}
+
+static inline void qe_ic_cascade_high_ipic(unsigned int irq,
+ struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = desc->handler_data;
+ unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+}
+
+static inline void qe_ic_cascade_low_mpic(unsigned int irq,
+ struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = desc->handler_data;
+ unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+
+ desc->chip->eoi(irq);
+}
+
+static inline void qe_ic_cascade_high_mpic(unsigned int irq,
+ struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = desc->handler_data;
+ unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+
+ desc->chip->eoi(irq);
+}
+
+static inline void qe_ic_cascade_muxed_mpic(unsigned int irq,
+ struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = desc->handler_data;
+ unsigned int cascade_irq;
+
+ cascade_irq = qe_ic_get_high_irq(qe_ic);
+ if (cascade_irq == NO_IRQ)
+ cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+
+ desc->chip->eoi(irq);
+}
+
#endif /* _ASM_POWERPC_QE_IC_H */
--
1.5.0.6
^ permalink raw reply related
* Re: Is it safe to use these Linux function (test_bit(), set_bit(), clear_bit()) in character device driver for 2.6.10 ppc kernel.
From: Misbah khan @ 2007-10-04 13:02 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <20071001135516.GA8572@lixom.net>
Hi ...
I did followed you and it worked as well. I really Thank you for it.
At one Place i am doing memcpy() of floating point data to the memory mapped
registers, what could be the substitute of it like "memcpy_toio() " which is
suggested in the Book. I am working BE architecture.
I would really appreaciate if you would let me know the defineation of these
wrapper functions (in_be32,out_be32(),ioread32(),iowrite32(),etc) so that i
could have the clear idea of the reason for not directly dreferencing the
Pointer.
Misbah
Olof Johansson-2 wrote:
>
> On Sun, Sep 30, 2007 at 10:38:32PM -0700, Misbah khan wrote:
>
>> Olof Johansson-2 wrote:
>> >
>> > First, PLEASE stop quoting your own text. Do not append > in front of
>> > the lines you write yourself in the reply. It makes it impossible to
>> > tell what parts are new and what are old.
>
> Please read the above again, since you didn't fix your mailer.
>
> Also, make sure it doesn't prepend spaces in front of the lines you are
> writing.
>
>> > I am confused that some people tells me to map the memory noncacheble
>> and
>> > some tells me not. could you tell me which is the best approach and
>> please
>> > elaborate the reason as well. The part of the code is mentioned above
>> is a
>> > reference and my concern are as follows:-
>
> It depends on your application and how the FPGA is attached. Buf if it is
> attached outside of the coherence domain (for example on PCI), then you
> should map it uncacheable. Otherwise you will have to do manual flushing
> of caches to make sure writes make it out to the device, and also flush
> any copy in cache before you read any register. In other words, it makes
> things considerably more complicated and error-prone.
>
>> > 1. I am mapping 32 KB of memory for which i am using _nocasheble. Is it
>> > absolutely fine????
>
> Just use ioremap().
>
>> > 2. I am directly dereferencing the pointer to the mapped region insted
>> of
>> > using a wrapper function due to (1) Aready used in the past and have
>> faith
>> > in it .
>
> I don't care if you have faith in it or not, it's still not the correct
> way to do it. It might work right some of the time by pure luck but it
> is the incorrect way of accessing device memory.
>
>> > (2) I had used functions like ioread32() iowrite32() in the past
>> which
>> > is suggested by rubini in his book on Linux device Driver but the
>> output i
>> > got was bitswapped .
>
> I assume you mean byte swapped and not bit swapped.
>
> Are your registers on the device big- or little endian?
>
> If they are big endian, use in_be32/out_be32. If they're little endian,
> use
> in_le32/out_le32. That will take care of any swapping for you.
>
>> > 3. test_bit()/clear_bit() are the functions which i am using in my
>> driver
>> > and in the way i described above , please let me know that is looks
>> fine
>> > in the Implimention
>
> No it is not fine. You cannot use set_bit/clear_bit against noncacheable
> memory. EVER.
>
>> > or shall i read the value and mask the bits rather
>> > than beliving in these functions for eg :-
>> >
>> > dfr_data_ret=*(volatile UINT32 *)((volatile UINT32
>> > *)mmap_reg_ptr+DATA_STATUS_REG);
>> >
>> > dfr_data_ret&=STATUS_MASK;
>> >
>> > Please reply to clear my doubts.
>
> Just do what I told you earlier:
>
> To read the status register, mask out the STATUS_MASK and write it
> back, do:
>
> val = in_be32(mmap_reg_ptr + DATA_STATUS_REG);
> val &= STATUS_MASK;
> out_be32(MMAP_REG_PTR + DATA_STATUS_REG, val);
>
>
> -Olof
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
>
>
--
View this message in context: http://www.nabble.com/Is-it-safe-to-use-these-Linux-function-%28test_bit%28%29%2Cset_bit%28%29%2Cclear_bit%28%29%29-in-character-device-driver-for-2.6.10-ppc-kernel.-tf4527008.html#a13039401
Sent from the linuxppc-embedded mailing list archive at Nabble.com.
^ permalink raw reply
* Re: [PATCH 2/5] Add initial MPC8610 HPCD Platform files.
From: Jon Loeliger @ 2007-10-04 12:48 UTC (permalink / raw)
To: Kumar Gala; +Cc: Stephen Rothwell, Xianghua Xiao, linuxppc-dev@ozlabs.org
In-Reply-To: <44FE7AFC-1883-49A1-A781-6D966653EDF4@kernel.crashing.org>
So, like, the other day Kumar Gala mumbled:
>
> On Oct 3, 2007, at 10:41 PM, Stephen Rothwell wrote:
>
> > On Wed, 03 Oct 2007 15:09:33 -0500 Jon Loeliger <jdl@freescale.com>
> > wrote:
> >>
> >> +++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
> >> +#include <linux/stddef.h>
> >> +#include <linux/kernel.h>
> >> +#include <linux/pci.h>
> >> +#include <linux/kdev_t.h>
> >> +#include <linux/delay.h>
> >> +#include <linux/seq_file.h>
> >> +
> >> +#include <asm/system.h>
> >> +#include <asm/time.h>
> >> +#include <asm/machdep.h>
> >> +#include <asm/pci-bridge.h>
> >> +#include <asm/mpc86xx.h>
> >> +#include <asm/prom.h>
> >
> > You should include linux/of.h as well to use the of_ accessor
> > functions.
>
> added.
>
> - k
Thanks, Kumar.
jdl
^ permalink raw reply
* Re: [PATCH] Don't build arch/powerpc/sysdev/dcr.c for ARCH=ppc kernels
From: Josh Boyer @ 2007-10-04 12:16 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev, paulus
In-Reply-To: <1191496084.6245.0.camel@pasglop>
On Thu, 04 Oct 2007 21:08:04 +1000
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
>
> On Thu, 2007-10-04 at 05:56 -0500, Josh Boyer wrote:
> > On Wed, 2007-10-03 at 22:50 -0600, Grant Likely wrote:
> > > From: Grant Likely <grant.likely@secretlab.ca>
> > >
> > > dcr.c is an arch/powerpc only thing.
> > >
> > > Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> > > ---
> > >
> > > Ben/Paulus,
> > >
> > > As far as I can tell this is correct. Having sysdev/dcr.c in the arch/ppc
> > > build spits out warnings. Grep doesn't show anything in arch/ppc that
> > > is using it.
> >
> > Sorry, no. The ibm_emac driver uses it, which is arch/ppc. (Yes, the
> > old one.)
> >
> > If there are warnings, let's fix those up. Perhaps Michael's recent
> > patches in that area introduced something.
>
> What does it use of dcr.c ? Initially, the 4xx bits where totally
> inline, but maybe Michael's patches is changing that ?
Gah. Sorry, I was thinking of dcr-low.S, not dcr.c. And poor Michael
has nothing to do with it.
Drink coffee. Then think.
josh
^ permalink raw reply
* Re: linux ethernet problem
From: Valentine Barshak @ 2007-10-04 11:45 UTC (permalink / raw)
To: jxnuxdy; +Cc: linuxppc-embedded
In-Reply-To: <4418074.198781191459542009.JavaMail.coremail@bj163app58.163.com>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=x-gbk; format=flowed, Size: 976 bytes --]
jxnuxdy wrote:
> Hi,
>
> I use the 440epx CPU and bcm5241 PHY in my system, the ehternet works
> fine in u-boot, however I can't use the ethernet in linux if I didn't
> active the ehernet in u-boot(such as 'ping'... or 'tftp'...).
>
> Is there anyone even encounter such problem? is the issue due to my
> u-boot or linux?
What kernel version do you use?
Please, make sure that phy is initialized by linux and the phy mode is
correct.
IIRC, bcm5241 is connected to the ZMII bridge and works in SMII mode.
Thanks,
Valentine.
>
>
> ,Regards
> - Denny
>
>
> Íø Ò× Yeah.net Ãâ ·Ñ ÓÊ Ïä È« Р¸Ä °æ£¬Õä ²Ø ÕÊ ºÅ ¿ª ·Å£¬¿ì À´ ÇÀ ×¢
> >> < http://event.mail.163.com/chanel/click.htm?from=NO_16&domain=163>
>
>
> ------------------------------------------------------------------------
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: Device tree and external RTC
From: Peter Korsgaard @ 2007-10-04 11:21 UTC (permalink / raw)
To: Bruce_Leonard; +Cc: linuxppc-embedded
In-Reply-To: <OFFFD4BE8F.17F6E427-ON88257369.006D8651-88257369.00736D96@selinc.com>
>>>>> "Bruce" == Bruce Leonard <Bruce_Leonard@selinc.com> writes:
Hi,
Bruce> I'm seriously confused by how things are supposed to work now
Bruce> with device trees on the PowerPC arch. I'm bringing up our
Bruce> custom HW which is bassed on the mpc8347e, with an m41t00 RTC
Bruce> hanging off the i2c bus, U-boot is 1.2.0, kernel is 2.6.22.
Bruce> My problem is I can't get the kernel to access the RTC. It
Bruce> works fine in U-boot, but nothing in the kernel.
Bruce> I've searched through all the device tree files that come with
Bruce> the kernel
Bruce> and I can't find any that explicitly show an external device
Bruce> as a child node to a SoC I2C controller but it sure seems to
Bruce> me that the purpose of the device tree is to describe to the
Bruce> kernel all the hardware in the system. Therefore it seems to
Bruce> me that there should be something like the following in the
Bruce> device tree:
Bruce> <snip>
Bruce> i2c@3000 {
Bruce> device_type = "i2c";
Bruce> compatible = "fsl-i2c";
Bruce> reg = <3000 100>;
Bruce> interrupts = <e 8>;
Bruce> interrupt-parent = < &ipic >;
Bruce> dfsrr;
You need to add #address/size-cells to the I2C node, E.G.:
+ #address-cells = <1>;
+ #size-cells = <0>;
Bruce> rtc@54 {
Bruce> device_type = "rtc";
Bruce> something;
Bruce> something;
Bruce> something;
Bruce> }
Bruce> }
Bruce> <snip>
You need to set compatible and reg, E.G.
rtc@54 {
device_type = "rtc";
compatible = "stm,m41t00";
reg = <54>;
};
And it should get picked up automatically by
fsl_soc.c:of_find_i2c_driver().
Notice that you will need to use galak's git tree
(git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git) or
apply the following patch:
http://ozlabs.org/pipermail/linuxppc-dev/2007-September/042896.html
As it isn't in mainline yet.
--
Bye, Peter Korsgaard
^ permalink raw reply
* Re: [PATCH] Don't build arch/powerpc/sysdev/dcr.c for ARCH=ppc kernels
From: Benjamin Herrenschmidt @ 2007-10-04 11:08 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev, paulus
In-Reply-To: <1191495405.3647.3.camel@localhost.localdomain>
On Thu, 2007-10-04 at 05:56 -0500, Josh Boyer wrote:
> On Wed, 2007-10-03 at 22:50 -0600, Grant Likely wrote:
> > From: Grant Likely <grant.likely@secretlab.ca>
> >
> > dcr.c is an arch/powerpc only thing.
> >
> > Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> > ---
> >
> > Ben/Paulus,
> >
> > As far as I can tell this is correct. Having sysdev/dcr.c in the arch/ppc
> > build spits out warnings. Grep doesn't show anything in arch/ppc that
> > is using it.
>
> Sorry, no. The ibm_emac driver uses it, which is arch/ppc. (Yes, the
> old one.)
>
> If there are warnings, let's fix those up. Perhaps Michael's recent
> patches in that area introduced something.
What does it use of dcr.c ? Initially, the 4xx bits where totally
inline, but maybe Michael's patches is changing that ?
Ben.
^ permalink raw reply
* Re: [PATCH] Don't build arch/powerpc/sysdev/dcr.c for ARCH=ppc kernels
From: Josh Boyer @ 2007-10-04 10:56 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev, paulus
In-Reply-To: <20071004044911.30154.23109.stgit@trillian.cg.shawcable.net>
On Wed, 2007-10-03 at 22:50 -0600, Grant Likely wrote:
> From: Grant Likely <grant.likely@secretlab.ca>
>
> dcr.c is an arch/powerpc only thing.
>
> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> ---
>
> Ben/Paulus,
>
> As far as I can tell this is correct. Having sysdev/dcr.c in the arch/ppc
> build spits out warnings. Grep doesn't show anything in arch/ppc that
> is using it.
Sorry, no. The ibm_emac driver uses it, which is arch/ppc. (Yes, the
old one.)
If there are warnings, let's fix those up. Perhaps Michael's recent
patches in that area introduced something.
josh
^ permalink raw reply
* Re: Device tree and external RTC
From: Guennadi Liakhovetski @ 2007-10-04 9:29 UTC (permalink / raw)
To: Bruce_Leonard; +Cc: linuxppc-embedded
In-Reply-To: <OF5A3A8901.AAC62E29-ON88257369.007F3E0B-88257369.007FC5D0@selinc.com>
On Wed, 3 Oct 2007 Bruce_Leonard@selinc.com wrote:
> I'm seriously confused by how things are supposed to work now with device
> trees on the PowerPC arch. I'm bringing up our custom HW which is bassed
> on the mpc8347e, with an m41t00 RTC hanging off the i2c bus, U-boot is
> 1.2.0, kernel is 2.6.22. My problem is I can't get the kernel to access
> the RTC. It works fine in U-boot, but nothing in the kernel.
>
> Where I get confused is I'm not sure if this is something that the device
> tree is supposed to be telling the kernel about or if it's something that
> the kernel should probe for.
i2c probing is not perfectly reliable, so, yes, you have to tell the i2c
subsystem what i2c devices you have. There are several possibilities to do
this currently in the kernel, one of which is using the device-tree, which
is also the way I personally prefer:-)
> I've turned on everything in Kconfig I can
> find for I2C and RTC. Here's what I think are the relavant parts of
> .config:
Let's see
...
> CONFIG_I2C_BOARDINFO=y
This is good.
> #
> # I2C Algorithms
> #
> CONFIG_I2C_ALGOBIT=y
> CONFIG_I2C_ALGOPCF=y
> CONFIG_I2C_ALGOPCA=y
You don't need any of these.
> #
> # I2C Hardware Bus support
> #
> CONFIG_I2C_ALI1535=y
> # CONFIG_I2C_ALI1563 is not set
> CONFIG_I2C_ALI15X3=y
> CONFIG_I2C_AMD756=y
> # CONFIG_I2C_AMD756_S4882 is not set
> CONFIG_I2C_AMD8111=y
> CONFIG_I2C_I801=y
> CONFIG_I2C_I810=y
> CONFIG_I2C_PIIX4=y
> CONFIG_I2C_MPC=y
You only have one i2c bus, I guess, and it is the one above: "I2C_MPC".
> CONFIG_I2C_NFORCE2=y
> # CONFIG_I2C_OCORES is not set
> CONFIG_I2C_PARPORT_LIGHT=y
> CONFIG_I2C_PROSAVAGE=y
> # CONFIG_I2C_SAVAGE4 is not set
> CONFIG_I2C_SIMTEC=y
> CONFIG_I2C_SIS5595=y
> CONFIG_I2C_SIS630=y
> CONFIG_I2C_SIS96X=y
> # CONFIG_I2C_STUB is not set
> # CONFIG_I2C_VIA is not set
> CONFIG_I2C_VIAPRO=y
> CONFIG_I2C_VOODOO3=y
>
> #
> # Miscellaneous I2C Chip support
> #
> # CONFIG_SENSORS_DS1337 is not set
> # CONFIG_SENSORS_DS1374 is not set
> # CONFIG_SENSORS_EEPROM is not set
> # CONFIG_SENSORS_PCF8574 is not set
> # CONFIG_SENSORS_PCA9539 is not set
> # CONFIG_SENSORS_PCF8591 is not set
> CONFIG_SENSORS_M41T00=y
It shall not hurt, but do you really have this one?
> # CONFIG_SENSORS_MAX6875 is not set
> CONFIG_I2C_DEBUG_CORE=y
> CONFIG_I2C_DEBUG_ALGO=y
> CONFIG_I2C_DEBUG_BUS=y
> CONFIG_I2C_DEBUG_CHIP=y
>
> <snip>
>
> #
> # Real Time Clock
> #
> CONFIG_RTC_LIB=y
> CONFIG_RTC_CLASS=y
> CONFIG_RTC_HCTOSYS=y
> CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
> CONFIG_RTC_DEBUG=y
>
> #
> # RTC interfaces
> #
> CONFIG_RTC_INTF_SYSFS=y
> CONFIG_RTC_INTF_PROC=y
> CONFIG_RTC_INTF_DEV=y
> # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> # CONFIG_RTC_DRV_TEST is not set
>
> #
> # I2C RTC drivers
> #
> CONFIG_RTC_DRV_DS1307=y
Ok, so, this is your rtc.
> However, I get the following error when I run hwclock --debug:
> hwclock from util-linux-2.12r
> hwclock: Open of /dev/rtc failed, errno=19: No such device. (note that
> the device is present with a major of 10 and a minor of 135)
> No usable clock interface found.
> Cannot access the Hardware Clock via any known method.
First, this might be either a userspace or a kernel problem. Do you have
the correct device nodes? Are you using udev? Should be something like
$ ls -l /dev/rtc*
lrwxrwxrwx 1 root root 4 Oct 4 10:44 /dev/rtc -> rtc0
crw-rw---- 1 root root 254, 0 Oct 4 10:44 /dev/rtc0
> When I dump out ppc_md, all the RTC functions (i.e., get_rtc_time,
> read_rtc_val, etc.) are all NULL.
Don't think you need those. Those are for powerpc platforms not using
the generic rtc driver.
> I've searched through all the device tree files that come with the kernel
> and I can't find any that explicitly show an external device as a child
> node to a SoC I2C controller but it sure seems to me that the purpose of
> the device tree is to describe to the kernel all the hardware in the
> system. Therefore it seems to me that there should be something like the
> following in the device tree:
>
> <snip>
> i2c@3000 {
> device_type = "i2c";
> compatible = "fsl-i2c";
> reg = <3000 100>;
> interrupts = <e 8>;
> interrupt-parent = < &ipic >;
> dfsrr;
>
> rtc@54 {
> device_type = "rtc";
> something;
> something;
> something;
> }
> }
> <snip>
Yes, this is exactly what you need, if you don't want to hard code your
rtc in the kernel board-specific code. I'm gessing, examples you were
looking at are in arch/powerpc/boot/dts/kuroboxH[DG].dts. For this to work
you need suitable entries in arch/powerpc/sysdev/fsl_soc.c in the
i2c_devices array. I think, patch at
http://patchwork.ozlabs.org/linuxppc/patch?id=13624 is exactly what you
need.
Having applied the above patch and booted with the new kernel and
device-tree, after "cd /proc/device-tree" and calling lsprop you should
see something like
soc10x/i2c@80003000:
name "i2c"
interrupt-parent 00000001
interrupts 00000005 00000002
reg 80003000 00001000
compatible "fsl-i2c"
device_type "i2c"
#size-cells 00000000
#address-cells 00000001
soc10x/i2c@80003000/rtc@32:
name "rtc"
reg 00000032 (50)
compatible "ricoh,rs5c372a"
device_type "rtc"
Then you should have a directory like
/sys/devices/platform/fsl-i2c.0/i2c-adapter/i2c-0/0-0032
with a link in it like
lrwxrwxrwx 1 root root 0 Oct 4 11:00 driver -> ../../../../../../bus/i2c/drivers/rtc-rs5c372
dmesg should report something like
rtc-rs5c372 0-0032: rtc core: registered rtc-rs5c372 as rtc0
and
rtc-rs5c372 0-0032: setting the system clock to 2007-10-04 08:44:26 (1191487466)
Don't know what other messages ds1307 prints out.
> Okay, I figured out that I was indeed reading the clock (should have been
> using date command rather than hwclock command), so sorry for the noise.
> So what is is that hwclock is trying to do that it's unhappy about?
No, date is just giving you the system time, set either from rtc, or from
an ntp server, or to 1.1.1970 on startup.
Thanks
Guennadi
---
Guennadi Liakhovetski
^ permalink raw reply
* Re: [PATCH 4/4] edac: Add Cell memory controller
From: Benjamin Herrenschmidt @ 2007-10-04 7:07 UTC (permalink / raw)
To: Stephen Rothwell
Cc: Arnd Bergmann, linuxppc-dev, Paul Mackerras, bluesmoke-devel,
cbe-oss-dev
In-Reply-To: <20071004170047.30883e02.sfr@canb.auug.org.au>
On Thu, 2007-10-04 at 17:00 +1000, Stephen Rothwell wrote:
> On Thu, 04 Oct 2007 15:40:44 +1000 Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
> >
> > +++ linux-work/drivers/edac/cell-edac.c 2007-10-04 15:34:46.000000000 +1000
> > @@ -0,0 +1,258 @@
> > +#include <linux/module.h>
> > +#include <linux/init.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/stop_machine.h>
> > +#include <asm/io.h>
> > +#include <asm/machdep.h>
> > +#include <asm/cell-regs.h>
>
> Since you use the of_ accessors, you should include linux/of.h
Looks like it gets pulled in by somebody on my behalf, I suppose I can
respin the patch though or just send a corrective add-on (I prefer the
later as I have to go home now :-)
Ben.
^ permalink raw reply
* Re: [PATCH 4/4] edac: Add Cell memory controller
From: Stephen Rothwell @ 2007-10-04 7:00 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: Arnd Bergmann, cbe-oss-dev, linuxppc-dev, Mackerras, Paul,
bluesmoke-devel
In-Reply-To: <20071004054106.E5329DDE3C@ozlabs.org>
[-- Attachment #1: Type: text/plain, Size: 588 bytes --]
On Thu, 04 Oct 2007 15:40:44 +1000 Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
>
> +++ linux-work/drivers/edac/cell-edac.c 2007-10-04 15:34:46.000000000 +1000
> @@ -0,0 +1,258 @@
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/platform_device.h>
> +#include <linux/stop_machine.h>
> +#include <asm/io.h>
> +#include <asm/machdep.h>
> +#include <asm/cell-regs.h>
Since you use the of_ accessors, you should include linux/of.h
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH 0/3] Fixups to SystemACE driver
From: Jens Axboe @ 2007-10-04 6:53 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <20071004041114.20868.34605.stgit@trillian.cg.shawcable.net>
On Wed, Oct 03 2007, Grant Likely wrote:
> Jens,
>
> Here are some more Sysace patches based on comments received on the
> first series and a run through sparse. Can you please queue them up
> for 2.6.24?
Applied all 3, looked fine to me.
--
Jens Axboe
^ permalink raw reply
* [PATCH] [POWERPC] 85xx/86xx: refactor RSTCR reset code
From: Kumar Gala @ 2007-10-04 6:05 UTC (permalink / raw)
To: linuxppc-dev
On the majority of 85xx & 86xx we have a register that's ability to
assert HRESET_REQ to reset the board. We refactored that code so it
can be shared between both platforms into fsl_soc.c and removed all
the duplication in each platform directory.
---
arch/powerpc/boot/dts/mpc8641_hpcn.dts | 6 +++
arch/powerpc/platforms/85xx/Makefile | 1 -
arch/powerpc/platforms/85xx/misc.c | 55 ----------------------------
arch/powerpc/platforms/85xx/mpc85xx.h | 17 ---------
arch/powerpc/platforms/85xx/mpc85xx_ads.c | 3 +-
arch/powerpc/platforms/85xx/mpc85xx_cds.c | 5 +--
arch/powerpc/platforms/85xx/mpc85xx_ds.c | 5 +--
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 4 +--
arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 19 +---------
arch/powerpc/platforms/86xx/mpc8641_hpcn.h | 21 -----------
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c | 20 +----------
arch/powerpc/sysdev/fsl_soc.c | 38 +++++++++++++++++++
arch/powerpc/sysdev/fsl_soc.h | 1 +
13 files changed, 53 insertions(+), 142 deletions(-)
delete mode 100644 arch/powerpc/platforms/85xx/misc.c
delete mode 100644 arch/powerpc/platforms/85xx/mpc85xx.h
delete mode 100644 arch/powerpc/platforms/86xx/mpc8641_hpcn.h
Some code reduction for once :)
diff --git a/arch/powerpc/boot/dts/mpc8641_hpcn.dts b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
index f797662..3677659 100644
--- a/arch/powerpc/boot/dts/mpc8641_hpcn.dts
+++ b/arch/powerpc/boot/dts/mpc8641_hpcn.dts
@@ -214,6 +214,12 @@
device_type = "open-pic";
big-endian;
};
+
+ global-utilities@e0000 {
+ compatible = "fsl,mpc8641-guts";
+ reg = <e0000 1000>;
+ fsl,has-rstcr;
+ };
};
pcie@f8008000 {
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 25bd9e2..5eca920 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -1,7 +1,6 @@
#
# Makefile for the PowerPC 85xx linux kernel.
#
-obj-$(CONFIG_PPC_85xx) += misc.o
obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
diff --git a/arch/powerpc/platforms/85xx/misc.c b/arch/powerpc/platforms/85xx/misc.c
deleted file mode 100644
index 4fe376e..0000000
--- a/arch/powerpc/platforms/85xx/misc.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * MPC85xx generic code.
- *
- * Maintained by Kumar Gala (see MAINTAINERS for contact information)
- *
- * Copyright 2005 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <linux/irq.h>
-#include <linux/module.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-#include <asm/prom.h>
-#include <sysdev/fsl_soc.h>
-
-static __be32 __iomem *rstcr;
-
-extern void abort(void);
-
-static int __init mpc85xx_rstcr(void)
-{
- struct device_node *np;
- np = of_find_node_by_name(NULL, "global-utilities");
- if ((np && of_get_property(np, "fsl,has-rstcr", NULL))) {
- const u32 *prop = of_get_property(np, "reg", NULL);
- if (prop) {
- /* map reset control register
- * 0xE00B0 is offset of reset control register
- */
- rstcr = ioremap(get_immrbase() + *prop + 0xB0, 0xff);
- if (!rstcr)
- printk (KERN_EMERG "Error: reset control "
- "register not mapped!\n");
- }
- } else
- printk (KERN_INFO "rstcr compatible register does not exist!\n");
- if (np)
- of_node_put(np);
- return 0;
-}
-
-arch_initcall(mpc85xx_rstcr);
-
-void mpc85xx_restart(char *cmd)
-{
- local_irq_disable();
- if (rstcr)
- /* set reset control register */
- out_be32(rstcr, 0x2); /* HRESET_REQ */
- abort();
-}
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h
deleted file mode 100644
index 5b34dee..0000000
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/powerpc/platforms/85xx/mpc85xx.h
- *
- * MPC85xx soc definitions/function decls
- *
- * Maintainer: Kumar Gala <kumar.gala@freescale.com>
- *
- * Copyright 2005 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- */
-
-extern void mpc85xx_restart(char *);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index acb1ef9..378a244 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -30,7 +30,6 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
-#include "mpc85xx.h"
#ifdef CONFIG_CPM2
#include <linux/fs_enet_pd.h>
@@ -249,7 +248,7 @@ define_machine(mpc85xx_ads) {
.init_IRQ = mpc85xx_ads_pic_init,
.show_cpuinfo = mpc85xx_ads_show_cpuinfo,
.get_irq = mpic_get_irq,
- .restart = mpc85xx_restart,
+ .restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index abc85b8..afe5868 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -46,7 +46,6 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
-#include "mpc85xx.h"
static int cds_pci_slot = 2;
static volatile u8 *cadmus;
@@ -96,7 +95,7 @@ static void mpc85xx_cds_restart(char *cmd)
* If we can't find the VIA chip (maybe the P2P bridge is disabled)
* or the VIA chip reset didn't work, just use the default reset.
*/
- mpc85xx_restart(NULL);
+ fsl_rstcr_restart(NULL);
}
static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
@@ -343,7 +342,7 @@ define_machine(mpc85xx_cds) {
.restart = mpc85xx_cds_restart,
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#else
- .restart = mpc85xx_restart,
+ .restart = fsl_rstcr_restart,
#endif
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index d60bb2b..772e8de 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -33,7 +33,6 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
-#include "mpc85xx.h"
#undef DEBUG
@@ -211,7 +210,7 @@ define_machine(mpc8544_ds) {
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif
.get_irq = mpic_get_irq,
- .restart = mpc85xx_restart,
+ .restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
@@ -225,7 +224,7 @@ define_machine(mpc8572_ds) {
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
#endif
.get_irq = mpic_get_irq,
- .restart = mpc85xx_restart,
+ .restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index f8b6b08..00f4c3a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -50,8 +50,6 @@
#include <asm/qe_ic.h>
#include <asm/mpic.h>
-#include "mpc85xx.h"
-
#undef DEBUG
#ifdef DEBUG
#define DBG(fmt...) udbg_printf(fmt)
@@ -200,7 +198,7 @@ define_machine(mpc85xx_mds) {
.setup_arch = mpc85xx_mds_setup_arch,
.init_IRQ = mpc85xx_mds_pic_init,
.get_irq = mpic_get_irq,
- .restart = mpc85xx_restart,
+ .restart = fsl_rstcr_restart,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
#ifdef CONFIG_PCI
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index c794d88..6390895 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -37,8 +37,6 @@
#include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h>
-#define MPC86XX_RSTCR_OFFSET (0xe00b0) /* Reset Control Register */
-
void __init
mpc86xx_hpcd_init_irq(void)
{
@@ -187,21 +185,6 @@ static int __init mpc86xx_hpcd_probe(void)
return 0;
}
-void
-mpc86xx_restart(char *cmd)
-{
- void __iomem *rstcr;
-
- rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
-
- local_irq_disable();
-
- /* Assert reset request to Reset Control Register */
- out_be32(rstcr, 0x2);
-
- /* not reached */
-}
-
long __init
mpc86xx_time_init(void)
{
@@ -225,7 +208,7 @@ define_machine(mpc86xx_hpcd) {
.setup_arch = mpc86xx_hpcd_setup_arch,
.init_IRQ = mpc86xx_hpcd_init_irq,
.get_irq = mpic_get_irq,
- .restart = mpc86xx_restart,
+ .restart = fsl_rstcr_restart,
.time_init = mpc86xx_time_init,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
diff --git a/arch/powerpc/platforms/86xx/mpc8641_hpcn.h b/arch/powerpc/platforms/86xx/mpc8641_hpcn.h
deleted file mode 100644
index 41e554c..0000000
--- a/arch/powerpc/platforms/86xx/mpc8641_hpcn.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * MPC8641 HPCN board definitions
- *
- * Copyright 2006 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * Author: Xianghua Xiao <x.xiao@freescale.com>
- */
-
-#ifndef __MPC8641_HPCN_H__
-#define __MPC8641_HPCN_H__
-
-#include <linux/init.h>
-
-#define MPC86XX_RSTCR_OFFSET (0xe00b0) /* Reset Control Register */
-
-#endif /* __MPC8641_HPCN_H__ */
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index 6879b83..32a531a 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -35,7 +35,6 @@
#include <sysdev/fsl_soc.h>
#include "mpc86xx.h"
-#include "mpc8641_hpcn.h"
#undef DEBUG
@@ -196,23 +195,6 @@ static int __init mpc86xx_hpcn_probe(void)
return 0;
}
-
-void
-mpc86xx_restart(char *cmd)
-{
- void __iomem *rstcr;
-
- rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
-
- local_irq_disable();
-
- /* Assert reset request to Reset Control Register */
- out_be32(rstcr, 0x2);
-
- /* not reached */
-}
-
-
long __init
mpc86xx_time_init(void)
{
@@ -237,7 +219,7 @@ define_machine(mpc86xx_hpcn) {
.init_IRQ = mpc86xx_hpcn_init_irq,
.show_cpuinfo = mpc86xx_hpcn_show_cpuinfo,
.get_irq = mpic_get_irq,
- .restart = mpc86xx_restart,
+ .restart = fsl_rstcr_restart,
.time_init = mpc86xx_time_init,
.calibrate_decr = generic_calibrate_decr,
.progress = udbg_progress,
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index c765d7a..f16d432 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -1298,3 +1298,41 @@ err:
return spi_register_board_info(board_infos, num_board_infos);
}
+
+#if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
+static __be32 __iomem *rstcr;
+
+static int __init setup_rstcr(void)
+{
+ struct device_node *np;
+ np = of_find_node_by_name(NULL, "global-utilities");
+ if ((np && of_get_property(np, "fsl,has-rstcr", NULL))) {
+ const u32 *prop = of_get_property(np, "reg", NULL);
+ if (prop) {
+ /* map reset control register
+ * 0xE00B0 is offset of reset control register
+ */
+ rstcr = ioremap(get_immrbase() + *prop + 0xB0, 0xff);
+ if (!rstcr)
+ printk (KERN_EMERG "Error: reset control "
+ "register not mapped!\n");
+ }
+ } else
+ printk (KERN_INFO "rstcr compatible register does not exist!\n");
+ if (np)
+ of_node_put(np);
+ return 0;
+}
+
+arch_initcall(setup_rstcr);
+
+void fsl_rstcr_restart(char *cmd)
+{
+ local_irq_disable();
+ if (rstcr)
+ /* set reset control register */
+ out_be32(rstcr, 0x2); /* HRESET_REQ */
+
+ while (1) ;
+}
+#endif
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 618d91d..63e7db3 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -15,5 +15,6 @@ extern int fsl_spi_init(struct spi_board_info *board_infos,
void (*activate_cs)(u8 cs, u8 polarity),
void (*deactivate_cs)(u8 cs, u8 polarity));
+extern void fsl_rstcr_restart(char *cmd);
#endif
#endif
--
1.5.2.4
^ permalink raw reply related
* [PATCH 4/4] edac: Add Cell memory controller
From: Benjamin Herrenschmidt @ 2007-10-04 5:40 UTC (permalink / raw)
To: bluesmoke-devel, linuxppc-dev; +Cc: Paul Mackerras, cbe-oss-dev, Arnd Bergmann
In-Reply-To: <1191476442.154524.519055590678.qpush@grosgo>
Adds driver for the Cell memory controller when used without a
Hypervisor such as on the IBM Cell blades. There might still
be some improvements to do to this such as finding if it's
possible to properly obtain more details about the address
of the error but it's good enough already to report CE counts
which is our main priority at the moment.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
device_initcall(cell_publish_devices);
drivers/edac/Kconfig | 7 +
drivers/edac/Makefile | 1
drivers/edac/cell-edac.c | 258 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 266 insertions(+)
Index: linux-work/drivers/edac/Kconfig
===================================================================
--- linux-work.orig/drivers/edac/Kconfig 2007-10-04 15:00:11.000000000 +1000
+++ linux-work/drivers/edac/Kconfig 2007-10-04 15:34:32.000000000 +1000
@@ -131,5 +131,12 @@ config EDAC_PASEMI
Support for error detection and correction on PA Semi
PWRficient.
+config EDAC_CELL
+ tristate "Cell Broadband Engine memory controller"
+ depends on EDAC_MM_EDAC && PPC_CELL_NATIVE
+ help
+ Support for error detection and correction on the
+ Cell Broadband Engine internal memory controller
+ on platform without a hypervisor
endif # EDAC
Index: linux-work/drivers/edac/Makefile
===================================================================
--- linux-work.orig/drivers/edac/Makefile 2007-10-04 15:00:11.000000000 +1000
+++ linux-work/drivers/edac/Makefile 2007-10-04 15:34:32.000000000 +1000
@@ -28,4 +28,5 @@ obj-$(CONFIG_EDAC_I3000) += i3000_edac.
obj-$(CONFIG_EDAC_I82860) += i82860_edac.o
obj-$(CONFIG_EDAC_R82600) += r82600_edac.o
obj-$(CONFIG_EDAC_PASEMI) += pasemi_edac.o
+obj-$(CONFIG_EDAC_CELL) += cell-edac.o
Index: linux-work/drivers/edac/cell-edac.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/drivers/edac/cell-edac.c 2007-10-04 15:34:46.000000000 +1000
@@ -0,0 +1,258 @@
+/*
+ * Cell MIC driver for ECC counting
+ *
+ * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
+ * <benh@kernel.crashing.org>
+ *
+ * This file may be distributed under the terms of the
+ * GNU General Public License.
+ */
+#undef DEBUG
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/stop_machine.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/cell-regs.h>
+
+#include "edac_core.h"
+
+struct cell_edac_priv
+{
+ struct cbe_mic_tm_regs __iomem *regs;
+ int node;
+ int chanmask;
+#ifdef DEBUG
+ u64 prev_fir;
+#endif
+};
+
+static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar)
+{
+ struct cell_edac_priv *priv = mci->pvt_info;
+ struct csrow_info *csrow = &mci->csrows[0];
+ unsigned long address, pfn, offset;
+
+ dev_dbg(mci->dev, "ECC CE err on node %d, channel %d, ar = 0x%016lx\n",
+ priv->node, chan, ar);
+
+ /* Address decoding is likely a bit bogus, to dbl check */
+ address = (ar & 0xffffffffe0000000ul) >> 29;
+ if (priv->chanmask == 0x3)
+ address = (address << 1) | chan;
+ pfn = address >> PAGE_SHIFT;
+ offset = address & ~PAGE_MASK;
+
+ /* TODO: Decoding of the error addresss */
+ edac_mc_handle_ce(mci, csrow->first_page + pfn, offset,
+ 0, 0, chan, "");
+}
+
+static void cell_edac_count_ue(struct mem_ctl_info *mci, int chan, u64 ar)
+{
+ struct cell_edac_priv *priv = mci->pvt_info;
+ struct csrow_info *csrow = &mci->csrows[0];
+ unsigned long address, pfn, offset;
+
+ dev_dbg(mci->dev, "ECC UE err on node %d, channel %d, ar = 0x%016lx\n",
+ priv->node, chan, ar);
+
+ /* Address decoding is likely a bit bogus, to dbl check */
+ address = (ar & 0xffffffffe0000000ul) >> 29;
+ if (priv->chanmask == 0x3)
+ address = (address << 1) | chan;
+ pfn = address >> PAGE_SHIFT;
+ offset = address & ~PAGE_MASK;
+
+ /* TODO: Decoding of the error addresss */
+ edac_mc_handle_ue(mci, csrow->first_page + pfn, offset, 0, "");
+}
+
+static void cell_edac_check(struct mem_ctl_info *mci)
+{
+ struct cell_edac_priv *priv = mci->pvt_info;
+ u64 fir, addreg, clear = 0;
+
+ fir = in_be64(&priv->regs->mic_fir);
+#ifdef DEBUG
+ if (fir != priv->prev_fir) {
+ dev_dbg(mci->dev, "fir change : 0x%016lx\n", fir);
+ priv->prev_fir = fir;
+ }
+#endif
+ if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_SINGLE_0_ERR)) {
+ addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
+ clear |= CBE_MIC_FIR_ECC_SINGLE_0_RESET;
+ cell_edac_count_ce(mci, 0, addreg);
+ }
+ if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_SINGLE_1_ERR)) {
+ addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
+ clear |= CBE_MIC_FIR_ECC_SINGLE_1_RESET;
+ cell_edac_count_ce(mci, 1, addreg);
+ }
+ if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_MULTI_0_ERR)) {
+ addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
+ clear |= CBE_MIC_FIR_ECC_MULTI_0_RESET;
+ cell_edac_count_ue(mci, 0, addreg);
+ }
+ if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_MULTI_1_ERR)) {
+ addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
+ clear |= CBE_MIC_FIR_ECC_MULTI_1_RESET;
+ cell_edac_count_ue(mci, 1, addreg);
+ }
+
+ /* The procedure for clearing FIR bits is a bit ... weird */
+ if (clear) {
+ fir &= ~(CBE_MIC_FIR_ECC_ERR_MASK | CBE_MIC_FIR_ECC_SET_MASK);
+ fir |= CBE_MIC_FIR_ECC_RESET_MASK;
+ fir &= ~clear;
+ out_be64(&priv->regs->mic_fir, fir);
+ (void)in_be64(&priv->regs->mic_fir);
+ mb();
+#ifdef DEBUG
+ fir = in_be64(&priv->regs->mic_fir);
+ dev_dbg(mci->dev, "fir clear : 0x%016lx\n", fir);
+#endif
+ }
+}
+
+static void __devinit cell_edac_init_csrows(struct mem_ctl_info *mci)
+{
+ struct csrow_info *csrow = &mci->csrows[0];
+ struct cell_edac_priv *priv = mci->pvt_info;
+ struct device_node *np;
+
+ for (np = NULL;
+ (np = of_find_node_by_name(np, "memory")) != NULL;) {
+ struct resource r;
+
+ /* We "know" that the Cell firmware only creates one entry
+ * in the "memory" nodes. If that changes, this code will
+ * need to be adapted.
+ */
+ if (of_address_to_resource(np, 0, &r))
+ continue;
+ if (of_node_to_nid(np) != priv->node)
+ continue;
+ csrow->first_page = r.start >> PAGE_SHIFT;
+ csrow->nr_pages = (r.end - r.start + 1) >> PAGE_SHIFT;
+ csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
+ csrow->mtype = MEM_XDR;
+ csrow->edac_mode = EDAC_FLAG_EC | EDAC_FLAG_SECDED;
+ dev_dbg(mci->dev,
+ "Initialized on node %d, chanmask=0x%x,"
+ " first_page=0x%lx, nr_pages=0x%x\n",
+ priv->node, priv->chanmask,
+ csrow->first_page, csrow->nr_pages);
+ break;
+ }
+}
+
+static int __devinit cell_edac_probe(struct platform_device *pdev)
+{
+ struct cbe_mic_tm_regs __iomem *regs;
+ struct mem_ctl_info *mci;
+ struct cell_edac_priv *priv;
+ u64 reg;
+ int rc, chanmask;
+
+ regs = cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(pdev->id));
+ if (regs == NULL)
+ return -ENODEV;
+
+ /* Get channel population */
+ reg = in_be64(®s->mic_mnt_cfg);
+ dev_dbg(&pdev->dev, "MIC_MNT_CFG = 0x%016lx\n", reg);
+ chanmask = 0;
+ if (reg & CBE_MIC_MNT_CFG_CHAN_0_POP)
+ chanmask |= 0x1;
+ if (reg & CBE_MIC_MNT_CFG_CHAN_1_POP)
+ chanmask |= 0x2;
+ if (chanmask == 0) {
+ dev_warn(&pdev->dev,
+ "Yuck ! No channel populated ? Aborting !\n");
+ return -ENODEV;
+ }
+ dev_dbg(&pdev->dev, "Initial FIR = 0x%016lx\n",
+ in_be64(®s->mic_fir));
+
+ /* Allocate & init EDAC MC data structure */
+ mci = edac_mc_alloc(sizeof(struct cell_edac_priv), 1,
+ chanmask == 3 ? 2 : 1, pdev->id);
+ if (mci == NULL)
+ return -ENOMEM;
+ priv = mci->pvt_info;
+ priv->regs = regs;
+ priv->node = pdev->id;
+ priv->chanmask = chanmask;
+ mci->dev = &pdev->dev;
+ mci->mtype_cap = MEM_FLAG_XDR;
+ mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
+ mci->edac_cap = EDAC_FLAG_EC | EDAC_FLAG_SECDED;
+ mci->mod_name = "cell-edac";
+ mci->ctl_name = "MIC";
+ mci->dev_name = pdev->dev.bus_id;
+ mci->edac_check = cell_edac_check;
+ cell_edac_init_csrows(mci);
+
+ /* Register with EDAC core */
+ rc = edac_mc_add_mc(mci);
+ if (rc) {
+ dev_err(&pdev->dev, "failed to register with EDAC core\n");
+ edac_mc_free(mci);
+ return rc;
+ }
+
+ return 0;
+}
+
+static int __devexit cell_edac_remove(struct platform_device *pdev)
+{
+ struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev);
+ if (mci)
+ edac_mc_free(mci);
+ return 0;
+}
+
+static struct platform_driver cell_edac_driver =
+{
+ .driver = {
+ .name = "cbe-mic",
+ .owner = THIS_MODULE,
+ },
+ .probe = cell_edac_probe,
+ .remove = cell_edac_remove,
+};
+
+static int __init cell_edac_init(void)
+{
+ /* Sanity check registers data structure */
+ BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
+ mic_df_ecc_address_0) != 0xf8);
+ BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
+ mic_df_ecc_address_1) != 0x1b8);
+ BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
+ mic_df_config) != 0x218);
+ BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
+ mic_fir) != 0x230);
+ BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
+ mic_mnt_cfg) != 0x210);
+ BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
+ mic_exc) != 0x208);
+
+ return platform_driver_register(&cell_edac_driver);
+}
+
+static void __exit cell_edac_exit(void)
+{
+ platform_driver_unregister(&cell_edac_driver);
+}
+
+module_init(cell_edac_init);
+module_exit(cell_edac_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
+MODULE_DESCRIPTION("ECC counting for Cell MIC");
^ permalink raw reply
* [PATCH 3/4] edac: Add Cell XDR memory definition
From: Benjamin Herrenschmidt @ 2007-10-04 5:40 UTC (permalink / raw)
To: bluesmoke-devel, linuxppc-dev; +Cc: Paul Mackerras, cbe-oss-dev, Arnd Bergmann
In-Reply-To: <1191476442.154524.519055590678.qpush@grosgo>
This patch adds the definitions for the Rambus XDR memory type
used by the Cell processor. It's a pre-requisite for the followup
Cell EDAC patch.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
drivers/edac/edac_core.h | 2 ++
drivers/edac/edac_mc_sysfs.c | 3 ++-
2 files changed, 4 insertions(+), 1 deletion(-)
Index: linux-work/drivers/edac/edac_core.h
===================================================================
--- linux-work.orig/drivers/edac/edac_core.h 2007-10-04 15:00:16.000000000 +1000
+++ linux-work/drivers/edac/edac_core.h 2007-10-04 15:34:20.000000000 +1000
@@ -138,6 +138,7 @@ enum mem_type {
MEM_DDR2, /* DDR2 RAM */
MEM_FB_DDR2, /* fully buffered DDR2 */
MEM_RDDR2, /* Registered DDR2 RAM */
+ MEM_XDR, /* Rambus XDR */
};
#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
@@ -154,6 +155,7 @@ enum mem_type {
#define MEM_FLAG_DDR2 BIT(MEM_DDR2)
#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
+#define MEM_FLAG_XDR BIT(MEM_XDR)
/* chipset Error Detection and Correction capabilities and mode */
enum edac_type {
Index: linux-work/drivers/edac/edac_mc_sysfs.c
===================================================================
--- linux-work.orig/drivers/edac/edac_mc_sysfs.c 2007-10-04 15:00:16.000000000 +1000
+++ linux-work/drivers/edac/edac_mc_sysfs.c 2007-10-04 15:34:26.000000000 +1000
@@ -73,7 +73,8 @@ static const char *mem_types[] = {
[MEM_RMBS] = "RMBS",
[MEM_DDR2] = "Unbuffered-DDR2",
[MEM_FB_DDR2] = "FullyBuffered-DDR2",
- [MEM_RDDR2] = "Registered-DDR2"
+ [MEM_RDDR2] = "Registered-DDR2",
+ [MEM_XDR] = "XDR"
};
static const char *dev_types[] = {
^ permalink raw reply
* [PATCH 2/4] powerpc: Add Cell memory controller register defs and expose it
From: Benjamin Herrenschmidt @ 2007-10-04 5:40 UTC (permalink / raw)
To: bluesmoke-devel, linuxppc-dev; +Cc: Paul Mackerras, cbe-oss-dev, Arnd Bergmann
In-Reply-To: <1191476442.154524.519055590678.qpush@grosgo>
This adds definitions for the Cell memory controller registers (at
least some of them) for use by the EDAC driver for ECC error reporting.
It also expose the said MIC as a platform device that can be used
by the EDAC driver to match on.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/platforms/cell/setup.c | 10 +++++++
include/asm-powerpc/cell-regs.h | 48 ++++++++++++++++++++++++++++++++++--
2 files changed, 56 insertions(+), 2 deletions(-)
Index: linux-work/include/asm-powerpc/cell-regs.h
===================================================================
--- linux-work.orig/include/asm-powerpc/cell-regs.h 2007-10-04 15:15:23.000000000 +1000
+++ linux-work/include/asm-powerpc/cell-regs.h 2007-10-04 15:33:06.000000000 +1000
@@ -244,16 +244,60 @@ struct cbe_mic_tm_regs {
u64 slow_fast_timer_0; /* 0x0090 */
u64 slow_next_timer_0; /* 0x0098 */
- u8 pad_0x00a0_0x01c0[0x01c0 - 0x0a0]; /* 0x00a0 */
+ u8 pad_0x00a0_0x00f8[0x00f8 - 0x00a0]; /* 0x00a0 */
+ u64 mic_df_ecc_address_0; /* 0x00f8 */
+
+ u8 pad_0x0100_0x01b8[0x01b8 - 0x0100]; /* 0x0100 */
+ u64 mic_df_ecc_address_1; /* 0x01b8 */
u64 mic_ctl_cnfg_1; /* 0x01c0 */
#define CBE_MIC_DISABLE_PWR_SAV_1 0x8000000000000000LL
+
u64 pad_0x01c8; /* 0x01c8 */
u64 slow_fast_timer_1; /* 0x01d0 */
u64 slow_next_timer_1; /* 0x01d8 */
- u8 pad_0x01e0_0x1000[0x1000 - 0x01e0]; /* 0x01e0 */
+ u8 pad_0x01e0_0x0208[0x0208 - 0x01e0]; /* 0x01e0 */
+ u64 mic_exc; /* 0x0208 */
+#define CBE_MIC_EXC_BLOCK_SCRUB 0x0800000000000000ULL
+#define CBE_MIC_EXC_FAST_SCRUB 0x0100000000000000ULL
+
+ u64 mic_mnt_cfg; /* 0x0210 */
+#define CBE_MIC_MNT_CFG_CHAN_0_POP 0x0002000000000000ULL
+#define CBE_MIC_MNT_CFG_CHAN_1_POP 0x0004000000000000ULL
+
+ u64 mic_df_config; /* 0x0218 */
+#define CBE_MIC_ECC_DISABLE_0 0x4000000000000000ULL
+#define CBE_MIC_ECC_REP_SINGLE_0 0x2000000000000000ULL
+#define CBE_MIC_ECC_DISABLE_1 0x0080000000000000ULL
+#define CBE_MIC_ECC_REP_SINGLE_1 0x0040000000000000ULL
+
+ u8 pad_0x0220_0x0230[0x0230 - 0x0220]; /* 0x0220 */
+ u64 mic_fir; /* 0x0230 */
+#define CBE_MIC_FIR_ECC_SINGLE_0_ERR 0x0200000000000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_0_ERR 0x0100000000000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_1_ERR 0x0080000000000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_1_ERR 0x0040000000000000ULL
+#define CBE_MIC_FIR_ECC_ERR_MASK 0xffff000000000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_0_CTE 0x0000020000000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_0_CTE 0x0000010000000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_1_CTE 0x0000008000000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_1_CTE 0x0000004000000000ULL
+#define CBE_MIC_FIR_ECC_CTE_MASK 0x0000ffff00000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_0_RESET 0x0000000002000000ULL
+#define CBE_MIC_FIR_ECC_MULTI_0_RESET 0x0000000001000000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_1_RESET 0x0000000000800000ULL
+#define CBE_MIC_FIR_ECC_MULTI_1_RESET 0x0000000000400000ULL
+#define CBE_MIC_FIR_ECC_RESET_MASK 0x00000000ffff0000ULL
+#define CBE_MIC_FIR_ECC_SINGLE_0_SET 0x0000000000000200ULL
+#define CBE_MIC_FIR_ECC_MULTI_0_SET 0x0000000000000100ULL
+#define CBE_MIC_FIR_ECC_SINGLE_1_SET 0x0000000000000080ULL
+#define CBE_MIC_FIR_ECC_MULTI_1_SET 0x0000000000000040ULL
+#define CBE_MIC_FIR_ECC_SET_MASK 0x000000000000ffffULL
+ u64 mic_fir_debug; /* 0x0238 */
+
+ u8 pad_0x0240_0x1000[0x1000 - 0x0240]; /* 0x0240 */
};
extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
Index: linux-work/arch/powerpc/platforms/cell/setup.c
===================================================================
--- linux-work.orig/arch/powerpc/platforms/cell/setup.c 2007-10-04 15:15:23.000000000 +1000
+++ linux-work/arch/powerpc/platforms/cell/setup.c 2007-10-04 15:33:06.000000000 +1000
@@ -83,12 +83,22 @@ static void cell_progress(char *s, unsig
static int __init cell_publish_devices(void)
{
+ int node;
+
if (!machine_is(cell))
return 0;
/* Publish OF platform devices for southbridge IOs */
of_platform_bus_probe(NULL, NULL, NULL);
+ /* There is no device for the MIC memory controller, thus we create
+ * a platform device for it to attach the EDAC driver to.
+ */
+ for_each_online_node(node) {
+ if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
+ continue;
+ platform_device_register_simple("cbe-mic", node, NULL, 0);
+ }
return 0;
}
device_initcall(cell_publish_devices);
^ permalink raw reply
* [PATCH 1/4] powerpc: Move cbe_regs.h to include/asm-powerpc/cell-regs.h
From: Benjamin Herrenschmidt @ 2007-10-04 5:40 UTC (permalink / raw)
To: bluesmoke-devel, linuxppc-dev; +Cc: Paul Mackerras, cbe-oss-dev, Arnd Bergmann
In-Reply-To: <1191476442.154524.519055590678.qpush@grosgo>
The new Cell EDAC driver needs that file, oprofile also does ugly
path tricks to get to it, it's time to move it to asm-powerpc. While
at it, rename it to be consistent with cell-pmu.h (and dashes look
nicer than underscores anyway).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/powerpc/oprofile/cell/pr_util.h | 3
arch/powerpc/oprofile/op_model_cell.c | 2
arch/powerpc/platforms/cell/cbe_cpufreq.c | 2
arch/powerpc/platforms/cell/cbe_cpufreq_pervasive.c | 2
arch/powerpc/platforms/cell/cbe_cpufreq_pmi.c | 2
arch/powerpc/platforms/cell/cbe_regs.c | 3
arch/powerpc/platforms/cell/cbe_regs.h | 271 --------------------
arch/powerpc/platforms/cell/cbe_thermal.c | 2
arch/powerpc/platforms/cell/interrupt.c | 2
arch/powerpc/platforms/cell/iommu.c | 2
arch/powerpc/platforms/cell/pervasive.c | 2
arch/powerpc/platforms/cell/pmu.c | 2
arch/powerpc/platforms/cell/ras.c | 2
arch/powerpc/platforms/cell/setup.c | 2
include/asm-powerpc/cell-regs.h | 271 ++++++++++++++++++++
15 files changed, 284 insertions(+), 286 deletions(-)
Index: linux-work/arch/powerpc/platforms/cell/cbe_regs.h
===================================================================
--- linux-work.orig/arch/powerpc/platforms/cell/cbe_regs.h 2007-10-04 15:15:21.000000000 +1000
+++ /dev/null 1970-01-01 00:00:00.000000000 +0000
@@ -1,271 +0,0 @@
-/*
- * cbe_regs.h
- *
- * This file is intended to hold the various register definitions for CBE
- * on-chip system devices (memory controller, IO controller, etc...)
- *
- * (C) Copyright IBM Corporation 2001,2006
- *
- * Authors: Maximino Aguilar (maguilar@us.ibm.com)
- * David J. Erb (djerb@us.ibm.com)
- *
- * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
- */
-
-#ifndef CBE_REGS_H
-#define CBE_REGS_H
-
-#include <asm/cell-pmu.h>
-
-/*
- *
- * Some HID register definitions
- *
- */
-
-/* CBE specific HID0 bits */
-#define HID0_CBE_THERM_WAKEUP 0x0000020000000000ul
-#define HID0_CBE_SYSERR_WAKEUP 0x0000008000000000ul
-#define HID0_CBE_THERM_INT_EN 0x0000000400000000ul
-#define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul
-
-#define MAX_CBE 2
-
-/*
- *
- * Pervasive unit register definitions
- *
- */
-
-union spe_reg {
- u64 val;
- u8 spe[8];
-};
-
-union ppe_spe_reg {
- u64 val;
- struct {
- u32 ppe;
- u32 spe;
- };
-};
-
-
-struct cbe_pmd_regs {
- /* Debug Bus Control */
- u64 pad_0x0000; /* 0x0000 */
-
- u64 group_control; /* 0x0008 */
-
- u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
-
- u64 debug_bus_control; /* 0x00a8 */
-
- u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
-
- u64 trace_aux_data; /* 0x0100 */
- u64 trace_buffer_0_63; /* 0x0108 */
- u64 trace_buffer_64_127; /* 0x0110 */
- u64 trace_address; /* 0x0118 */
- u64 ext_tr_timer; /* 0x0120 */
-
- u8 pad_0x0128_0x0400 [0x0400 - 0x0128]; /* 0x0128 */
-
- /* Performance Monitor */
- u64 pm_status; /* 0x0400 */
- u64 pm_control; /* 0x0408 */
- u64 pm_interval; /* 0x0410 */
- u64 pm_ctr[4]; /* 0x0418 */
- u64 pm_start_stop; /* 0x0438 */
- u64 pm07_control[8]; /* 0x0440 */
-
- u8 pad_0x0480_0x0800 [0x0800 - 0x0480]; /* 0x0480 */
-
- /* Thermal Sensor Registers */
- union spe_reg ts_ctsr1; /* 0x0800 */
- u64 ts_ctsr2; /* 0x0808 */
- union spe_reg ts_mtsr1; /* 0x0810 */
- u64 ts_mtsr2; /* 0x0818 */
- union spe_reg ts_itr1; /* 0x0820 */
- u64 ts_itr2; /* 0x0828 */
- u64 ts_gitr; /* 0x0830 */
- u64 ts_isr; /* 0x0838 */
- u64 ts_imr; /* 0x0840 */
- union spe_reg tm_cr1; /* 0x0848 */
- u64 tm_cr2; /* 0x0850 */
- u64 tm_simr; /* 0x0858 */
- union ppe_spe_reg tm_tpr; /* 0x0860 */
- union spe_reg tm_str1; /* 0x0868 */
- u64 tm_str2; /* 0x0870 */
- union ppe_spe_reg tm_tsr; /* 0x0878 */
-
- /* Power Management */
- u64 pmcr; /* 0x0880 */
-#define CBE_PMD_PAUSE_ZERO_CONTROL 0x10000
- u64 pmsr; /* 0x0888 */
-
- /* Time Base Register */
- u64 tbr; /* 0x0890 */
-
- u8 pad_0x0898_0x0c00 [0x0c00 - 0x0898]; /* 0x0898 */
-
- /* Fault Isolation Registers */
- u64 checkstop_fir; /* 0x0c00 */
- u64 recoverable_fir; /* 0x0c08 */
- u64 spec_att_mchk_fir; /* 0x0c10 */
- u32 fir_mode_reg; /* 0x0c18 */
- u8 pad_0x0c1c_0x0c20 [4]; /* 0x0c1c */
-#define CBE_PMD_FIR_MODE_M8 0x00800
- u64 fir_enable_mask; /* 0x0c20 */
-
- u8 pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28]; /* 0x0c28 */
- u64 ras_esc_0; /* 0x0ca8 */
- u8 pad_0x0cb0_0x1000 [0x1000 - 0x0cb0]; /* 0x0cb0 */
-};
-
-extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
-extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
-
-/*
- * PMU shadow registers
- *
- * Many of the registers in the performance monitoring unit are write-only,
- * so we need to save a copy of what we write to those registers.
- *
- * The actual data counters are read/write. However, writing to the counters
- * only takes effect if the PMU is enabled. Otherwise the value is stored in
- * a hardware latch until the next time the PMU is enabled. So we save a copy
- * of the counter values if we need to read them back while the PMU is
- * disabled. The counter_value_in_latch field is a bitmap indicating which
- * counters currently have a value waiting to be written.
- */
-
-struct cbe_pmd_shadow_regs {
- u32 group_control;
- u32 debug_bus_control;
- u32 trace_address;
- u32 ext_tr_timer;
- u32 pm_status;
- u32 pm_control;
- u32 pm_interval;
- u32 pm_start_stop;
- u32 pm07_control[NR_CTRS];
-
- u32 pm_ctr[NR_PHYS_CTRS];
- u32 counter_value_in_latch;
-};
-
-extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np);
-extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu);
-
-/*
- *
- * IIC unit register definitions
- *
- */
-
-struct cbe_iic_pending_bits {
- u32 data;
- u8 flags;
- u8 class;
- u8 source;
- u8 prio;
-};
-
-#define CBE_IIC_IRQ_VALID 0x80
-#define CBE_IIC_IRQ_IPI 0x40
-
-struct cbe_iic_thread_regs {
- struct cbe_iic_pending_bits pending;
- struct cbe_iic_pending_bits pending_destr;
- u64 generate;
- u64 prio;
-};
-
-struct cbe_iic_regs {
- u8 pad_0x0000_0x0400[0x0400 - 0x0000]; /* 0x0000 */
-
- /* IIC interrupt registers */
- struct cbe_iic_thread_regs thread[2]; /* 0x0400 */
-
- u64 iic_ir; /* 0x0440 */
-#define CBE_IIC_IR_PRIO(x) (((x) & 0xf) << 12)
-#define CBE_IIC_IR_DEST_NODE(x) (((x) & 0xf) << 4)
-#define CBE_IIC_IR_DEST_UNIT(x) ((x) & 0xf)
-#define CBE_IIC_IR_IOC_0 0x0
-#define CBE_IIC_IR_IOC_1S 0xb
-#define CBE_IIC_IR_PT_0 0xe
-#define CBE_IIC_IR_PT_1 0xf
-
- u64 iic_is; /* 0x0448 */
-#define CBE_IIC_IS_PMI 0x2
-
- u8 pad_0x0450_0x0500[0x0500 - 0x0450]; /* 0x0450 */
-
- /* IOC FIR */
- u64 ioc_fir_reset; /* 0x0500 */
- u64 ioc_fir_set; /* 0x0508 */
- u64 ioc_checkstop_enable; /* 0x0510 */
- u64 ioc_fir_error_mask; /* 0x0518 */
- u64 ioc_syserr_enable; /* 0x0520 */
- u64 ioc_fir; /* 0x0528 */
-
- u8 pad_0x0530_0x1000[0x1000 - 0x0530]; /* 0x0530 */
-};
-
-extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
-extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
-
-
-struct cbe_mic_tm_regs {
- u8 pad_0x0000_0x0040[0x0040 - 0x0000]; /* 0x0000 */
-
- u64 mic_ctl_cnfg2; /* 0x0040 */
-#define CBE_MIC_ENABLE_AUX_TRC 0x8000000000000000LL
-#define CBE_MIC_DISABLE_PWR_SAV_2 0x0200000000000000LL
-#define CBE_MIC_DISABLE_AUX_TRC_WRAP 0x0100000000000000LL
-#define CBE_MIC_ENABLE_AUX_TRC_INT 0x0080000000000000LL
-
- u64 pad_0x0048; /* 0x0048 */
-
- u64 mic_aux_trc_base; /* 0x0050 */
- u64 mic_aux_trc_max_addr; /* 0x0058 */
- u64 mic_aux_trc_cur_addr; /* 0x0060 */
- u64 mic_aux_trc_grf_addr; /* 0x0068 */
- u64 mic_aux_trc_grf_data; /* 0x0070 */
-
- u64 pad_0x0078; /* 0x0078 */
-
- u64 mic_ctl_cnfg_0; /* 0x0080 */
-#define CBE_MIC_DISABLE_PWR_SAV_0 0x8000000000000000LL
-
- u64 pad_0x0088; /* 0x0088 */
-
- u64 slow_fast_timer_0; /* 0x0090 */
- u64 slow_next_timer_0; /* 0x0098 */
-
- u8 pad_0x00a0_0x01c0[0x01c0 - 0x0a0]; /* 0x00a0 */
-
- u64 mic_ctl_cnfg_1; /* 0x01c0 */
-#define CBE_MIC_DISABLE_PWR_SAV_1 0x8000000000000000LL
- u64 pad_0x01c8; /* 0x01c8 */
-
- u64 slow_fast_timer_1; /* 0x01d0 */
- u64 slow_next_timer_1; /* 0x01d8 */
-
- u8 pad_0x01e0_0x1000[0x1000 - 0x01e0]; /* 0x01e0 */
-};
-
-extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
-extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
-
-/* some utility functions to deal with SMT */
-extern u32 cbe_get_hw_thread_id(int cpu);
-extern u32 cbe_cpu_to_node(int cpu);
-extern u32 cbe_node_to_cpu(int node);
-
-/* Init this module early */
-extern void cbe_regs_init(void);
-
-
-#endif /* CBE_REGS_H */
Index: linux-work/arch/powerpc/oprofile/cell/pr_util.h
===================================================================
--- linux-work.orig/arch/powerpc/oprofile/cell/pr_util.h 2007-10-04 15:15:22.000000000 +1000
+++ linux-work/arch/powerpc/oprofile/cell/pr_util.h 2007-10-04 15:15:23.000000000 +1000
@@ -17,10 +17,9 @@
#include <linux/cpumask.h>
#include <linux/oprofile.h>
#include <asm/cell-pmu.h>
+#include <asm/cell-regs.h>
#include <asm/spu.h>
-#include "../../platforms/cell/cbe_regs.h"
-
/* Defines used for sync_start */
#define SKIP_GENERIC_SYNC 0
#define SYNC_START_ERROR -1
Index: linux-work/arch/powerpc/oprofile/op_model_cell.c
===================================================================
--- linux-work.orig/arch/powerpc/oprofile/op_model_cell.c 2007-10-04 15:15:22.000000000 +1000
+++ linux-work/arch/powerpc/oprofile/op_model_cell.c 2007-10-04 15:15:23.000000000 +1000
@@ -35,9 +35,9 @@
#include <asm/reg.h>
#include <asm/rtas.h>
#include <asm/system.h>
+#include <asm/cell-regs.h>
#include "../platforms/cell/interrupt.h"
-#include "../platforms/cell/cbe_regs.h"
#include "cell/pr_util.h"
static void cell_global_stop_spu(void);
Index: linux-work/arch/powerpc/platforms/cell/cbe_cpufreq.c
===================================================================
--- linux-work.orig/arch/powerpc/platforms/cell/cbe_cpufreq.c 2007-10-04 15:15:21.000000000 +1000
+++ linux-work/arch/powerpc/platforms/cell/cbe_cpufreq.c 2007-10-04 15:15:23.000000000 +1000
@@ -24,7 +24,7 @@
#include <asm/machdep.h>
#include <asm/of_platform.h>
#include <asm/prom.h>
-#include "cbe_regs.h"
+#include <asm/cell-regs.h>
#include "cbe_cpufreq.h"
static DEFINE_MUTEX(cbe_switch_mutex);
Index: linux-work/arch/powerpc/platforms/cell/cbe_cpufreq_pervasive.c
===================================================================
--- linux-work.orig/arch/powerpc/platforms/cell/cbe_cpufreq_pervasive.c 2007-10-04 15:15:21.000000000 +1000
+++ linux-work/arch/powerpc/platforms/cell/cbe_cpufreq_pervasive.c 2007-10-04 15:15:23.000000000 +1000
@@ -28,8 +28,8 @@
#include <linux/time.h>
#include <asm/machdep.h>
#include <asm/hw_irq.h>
+#include <asm/cell-regs.h>
-#include "cbe_regs.h"
#include "cbe_cpufreq.h"
/* to write to MIC register */
Index: linux-work/arch/powerpc/platforms/cell/cbe_cpufreq_pmi.c
===================================================================
--- linux-work.orig/arch/powerpc/platforms/cell/cbe_cpufreq_pmi.c 2007-10-04 15:15:22.000000000 +1000
+++ linux-work/arch/powerpc/platforms/cell/cbe_cpufreq_pmi.c 2007-10-04 15:15:23.000000000 +1000
@@ -27,12 +27,12 @@
#include <asm/processor.h>
#include <asm/prom.h>
#include <asm/pmi.h>
+#include <asm/cell-regs.h>
#ifdef DEBUG
#include <asm/time.h>
#endif
-#include "cbe_regs.h"
#include "cbe_cpufreq.h"
static u8 pmi_slow_mode_limit[MAX_CBE];
Index: linux-work/arch/powerpc/platforms/cell/cbe_regs.c
===================================================================
--- linux-work.orig/arch/powerpc/platforms/cell/cbe_regs.c 2007-10-04 15:15:21.000000000 +1000
+++ linux-work/arch/powerpc/platforms/cell/cbe_regs.c 2007-10-04 15:15:23.000000000 +1000
@@ -16,8 +16,7 @@
#include <asm/ptrace.h>
#include <asm/of_device.h>
#include <asm/of_platform.h>
-
-#include "cbe_regs.h"
+#include <asm/cell-regs.h>
/*
* Current implementation uses "cpu" nodes. We build our own mapping
Index: linux-work/arch/powerpc/platforms/cell/cbe_thermal.c
===================================================================
--- linux-work.orig/arch/powerpc/platforms/cell/cbe_thermal.c 2007-10-04 15:15:21.000000000 +1000
+++ linux-work/arch/powerpc/platforms/cell/cbe_thermal.c 2007-10-04 15:15:23.000000000 +1000
@@ -52,8 +52,8 @@
#include <asm/spu.h>
#include <asm/io.h>
#include <asm/prom.h>
+#include <asm/cell-regs.h>
-#include "cbe_regs.h"
#include "spu_priv1_mmio.h"
#define TEMP_MIN 65
Index: linux-work/arch/powerpc/platforms/cell/interrupt.c
===================================================================
--- linux-work.orig/arch/powerpc/platforms/cell/interrupt.c 2007-10-04 15:15:21.000000000 +1000
+++ linux-work/arch/powerpc/platforms/cell/interrupt.c 2007-10-04 15:15:23.000000000 +1000
@@ -41,9 +41,9 @@
#include <asm/prom.h>
#include <asm/ptrace.h>
#include <asm/machdep.h>
+#include <asm/cell-regs.h>
#include "interrupt.h"
-#include "cbe_regs.h"
struct iic {
struct cbe_iic_thread_regs __iomem *regs;
Index: linux-work/arch/powerpc/platforms/cell/iommu.c
===================================================================
--- linux-work.orig/arch/powerpc/platforms/cell/iommu.c 2007-10-04 15:15:21.000000000 +1000
+++ linux-work/arch/powerpc/platforms/cell/iommu.c 2007-10-04 15:15:23.000000000 +1000
@@ -34,8 +34,8 @@
#include <asm/udbg.h>
#include <asm/of_platform.h>
#include <asm/lmb.h>
+#include <asm/cell-regs.h>
-#include "cbe_regs.h"
#include "interrupt.h"
/* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages
Index: linux-work/arch/powerpc/platforms/cell/pervasive.c
===================================================================
--- linux-work.orig/arch/powerpc/platforms/cell/pervasive.c 2007-10-04 15:15:21.000000000 +1000
+++ linux-work/arch/powerpc/platforms/cell/pervasive.c 2007-10-04 15:15:23.000000000 +1000
@@ -34,9 +34,9 @@
#include <asm/prom.h>
#include <asm/pgtable.h>
#include <asm/reg.h>
+#include <asm/cell-regs.h>
#include "pervasive.h"
-#include "cbe_regs.h"
static int sysreset_hack;
Index: linux-work/arch/powerpc/platforms/cell/pmu.c
===================================================================
--- linux-work.orig/arch/powerpc/platforms/cell/pmu.c 2007-10-04 15:15:21.000000000 +1000
+++ linux-work/arch/powerpc/platforms/cell/pmu.c 2007-10-04 15:15:23.000000000 +1000
@@ -30,8 +30,8 @@
#include <asm/pmc.h>
#include <asm/reg.h>
#include <asm/spu.h>
+#include <asm/cell-regs.h>
-#include "cbe_regs.h"
#include "interrupt.h"
/*
Index: linux-work/arch/powerpc/platforms/cell/ras.c
===================================================================
--- linux-work.orig/arch/powerpc/platforms/cell/ras.c 2007-10-04 15:15:21.000000000 +1000
+++ linux-work/arch/powerpc/platforms/cell/ras.c 2007-10-04 15:15:23.000000000 +1000
@@ -10,9 +10,9 @@
#include <asm/prom.h>
#include <asm/machdep.h>
#include <asm/rtas.h>
+#include <asm/cell-regs.h>
#include "ras.h"
-#include "cbe_regs.h"
static void dump_fir(int cpu)
Index: linux-work/arch/powerpc/platforms/cell/setup.c
===================================================================
--- linux-work.orig/arch/powerpc/platforms/cell/setup.c 2007-10-04 15:15:21.000000000 +1000
+++ linux-work/arch/powerpc/platforms/cell/setup.c 2007-10-04 15:15:23.000000000 +1000
@@ -52,9 +52,9 @@
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <asm/of_platform.h>
+#include <asm/cell-regs.h>
#include "interrupt.h"
-#include "cbe_regs.h"
#include "pervasive.h"
#include "ras.h"
Index: linux-work/include/asm-powerpc/cell-regs.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-work/include/asm-powerpc/cell-regs.h 2007-10-04 15:15:23.000000000 +1000
@@ -0,0 +1,271 @@
+/*
+ * cbe_regs.h
+ *
+ * This file is intended to hold the various register definitions for CBE
+ * on-chip system devices (memory controller, IO controller, etc...)
+ *
+ * (C) Copyright IBM Corporation 2001,2006
+ *
+ * Authors: Maximino Aguilar (maguilar@us.ibm.com)
+ * David J. Erb (djerb@us.ibm.com)
+ *
+ * (c) 2006 Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
+ */
+
+#ifndef CBE_REGS_H
+#define CBE_REGS_H
+
+#include <asm/cell-pmu.h>
+
+/*
+ *
+ * Some HID register definitions
+ *
+ */
+
+/* CBE specific HID0 bits */
+#define HID0_CBE_THERM_WAKEUP 0x0000020000000000ul
+#define HID0_CBE_SYSERR_WAKEUP 0x0000008000000000ul
+#define HID0_CBE_THERM_INT_EN 0x0000000400000000ul
+#define HID0_CBE_SYSERR_INT_EN 0x0000000200000000ul
+
+#define MAX_CBE 2
+
+/*
+ *
+ * Pervasive unit register definitions
+ *
+ */
+
+union spe_reg {
+ u64 val;
+ u8 spe[8];
+};
+
+union ppe_spe_reg {
+ u64 val;
+ struct {
+ u32 ppe;
+ u32 spe;
+ };
+};
+
+
+struct cbe_pmd_regs {
+ /* Debug Bus Control */
+ u64 pad_0x0000; /* 0x0000 */
+
+ u64 group_control; /* 0x0008 */
+
+ u8 pad_0x0010_0x00a8 [0x00a8 - 0x0010]; /* 0x0010 */
+
+ u64 debug_bus_control; /* 0x00a8 */
+
+ u8 pad_0x00b0_0x0100 [0x0100 - 0x00b0]; /* 0x00b0 */
+
+ u64 trace_aux_data; /* 0x0100 */
+ u64 trace_buffer_0_63; /* 0x0108 */
+ u64 trace_buffer_64_127; /* 0x0110 */
+ u64 trace_address; /* 0x0118 */
+ u64 ext_tr_timer; /* 0x0120 */
+
+ u8 pad_0x0128_0x0400 [0x0400 - 0x0128]; /* 0x0128 */
+
+ /* Performance Monitor */
+ u64 pm_status; /* 0x0400 */
+ u64 pm_control; /* 0x0408 */
+ u64 pm_interval; /* 0x0410 */
+ u64 pm_ctr[4]; /* 0x0418 */
+ u64 pm_start_stop; /* 0x0438 */
+ u64 pm07_control[8]; /* 0x0440 */
+
+ u8 pad_0x0480_0x0800 [0x0800 - 0x0480]; /* 0x0480 */
+
+ /* Thermal Sensor Registers */
+ union spe_reg ts_ctsr1; /* 0x0800 */
+ u64 ts_ctsr2; /* 0x0808 */
+ union spe_reg ts_mtsr1; /* 0x0810 */
+ u64 ts_mtsr2; /* 0x0818 */
+ union spe_reg ts_itr1; /* 0x0820 */
+ u64 ts_itr2; /* 0x0828 */
+ u64 ts_gitr; /* 0x0830 */
+ u64 ts_isr; /* 0x0838 */
+ u64 ts_imr; /* 0x0840 */
+ union spe_reg tm_cr1; /* 0x0848 */
+ u64 tm_cr2; /* 0x0850 */
+ u64 tm_simr; /* 0x0858 */
+ union ppe_spe_reg tm_tpr; /* 0x0860 */
+ union spe_reg tm_str1; /* 0x0868 */
+ u64 tm_str2; /* 0x0870 */
+ union ppe_spe_reg tm_tsr; /* 0x0878 */
+
+ /* Power Management */
+ u64 pmcr; /* 0x0880 */
+#define CBE_PMD_PAUSE_ZERO_CONTROL 0x10000
+ u64 pmsr; /* 0x0888 */
+
+ /* Time Base Register */
+ u64 tbr; /* 0x0890 */
+
+ u8 pad_0x0898_0x0c00 [0x0c00 - 0x0898]; /* 0x0898 */
+
+ /* Fault Isolation Registers */
+ u64 checkstop_fir; /* 0x0c00 */
+ u64 recoverable_fir; /* 0x0c08 */
+ u64 spec_att_mchk_fir; /* 0x0c10 */
+ u32 fir_mode_reg; /* 0x0c18 */
+ u8 pad_0x0c1c_0x0c20 [4]; /* 0x0c1c */
+#define CBE_PMD_FIR_MODE_M8 0x00800
+ u64 fir_enable_mask; /* 0x0c20 */
+
+ u8 pad_0x0c28_0x0ca8 [0x0ca8 - 0x0c28]; /* 0x0c28 */
+ u64 ras_esc_0; /* 0x0ca8 */
+ u8 pad_0x0cb0_0x1000 [0x1000 - 0x0cb0]; /* 0x0cb0 */
+};
+
+extern struct cbe_pmd_regs __iomem *cbe_get_pmd_regs(struct device_node *np);
+extern struct cbe_pmd_regs __iomem *cbe_get_cpu_pmd_regs(int cpu);
+
+/*
+ * PMU shadow registers
+ *
+ * Many of the registers in the performance monitoring unit are write-only,
+ * so we need to save a copy of what we write to those registers.
+ *
+ * The actual data counters are read/write. However, writing to the counters
+ * only takes effect if the PMU is enabled. Otherwise the value is stored in
+ * a hardware latch until the next time the PMU is enabled. So we save a copy
+ * of the counter values if we need to read them back while the PMU is
+ * disabled. The counter_value_in_latch field is a bitmap indicating which
+ * counters currently have a value waiting to be written.
+ */
+
+struct cbe_pmd_shadow_regs {
+ u32 group_control;
+ u32 debug_bus_control;
+ u32 trace_address;
+ u32 ext_tr_timer;
+ u32 pm_status;
+ u32 pm_control;
+ u32 pm_interval;
+ u32 pm_start_stop;
+ u32 pm07_control[NR_CTRS];
+
+ u32 pm_ctr[NR_PHYS_CTRS];
+ u32 counter_value_in_latch;
+};
+
+extern struct cbe_pmd_shadow_regs *cbe_get_pmd_shadow_regs(struct device_node *np);
+extern struct cbe_pmd_shadow_regs *cbe_get_cpu_pmd_shadow_regs(int cpu);
+
+/*
+ *
+ * IIC unit register definitions
+ *
+ */
+
+struct cbe_iic_pending_bits {
+ u32 data;
+ u8 flags;
+ u8 class;
+ u8 source;
+ u8 prio;
+};
+
+#define CBE_IIC_IRQ_VALID 0x80
+#define CBE_IIC_IRQ_IPI 0x40
+
+struct cbe_iic_thread_regs {
+ struct cbe_iic_pending_bits pending;
+ struct cbe_iic_pending_bits pending_destr;
+ u64 generate;
+ u64 prio;
+};
+
+struct cbe_iic_regs {
+ u8 pad_0x0000_0x0400[0x0400 - 0x0000]; /* 0x0000 */
+
+ /* IIC interrupt registers */
+ struct cbe_iic_thread_regs thread[2]; /* 0x0400 */
+
+ u64 iic_ir; /* 0x0440 */
+#define CBE_IIC_IR_PRIO(x) (((x) & 0xf) << 12)
+#define CBE_IIC_IR_DEST_NODE(x) (((x) & 0xf) << 4)
+#define CBE_IIC_IR_DEST_UNIT(x) ((x) & 0xf)
+#define CBE_IIC_IR_IOC_0 0x0
+#define CBE_IIC_IR_IOC_1S 0xb
+#define CBE_IIC_IR_PT_0 0xe
+#define CBE_IIC_IR_PT_1 0xf
+
+ u64 iic_is; /* 0x0448 */
+#define CBE_IIC_IS_PMI 0x2
+
+ u8 pad_0x0450_0x0500[0x0500 - 0x0450]; /* 0x0450 */
+
+ /* IOC FIR */
+ u64 ioc_fir_reset; /* 0x0500 */
+ u64 ioc_fir_set; /* 0x0508 */
+ u64 ioc_checkstop_enable; /* 0x0510 */
+ u64 ioc_fir_error_mask; /* 0x0518 */
+ u64 ioc_syserr_enable; /* 0x0520 */
+ u64 ioc_fir; /* 0x0528 */
+
+ u8 pad_0x0530_0x1000[0x1000 - 0x0530]; /* 0x0530 */
+};
+
+extern struct cbe_iic_regs __iomem *cbe_get_iic_regs(struct device_node *np);
+extern struct cbe_iic_regs __iomem *cbe_get_cpu_iic_regs(int cpu);
+
+
+struct cbe_mic_tm_regs {
+ u8 pad_0x0000_0x0040[0x0040 - 0x0000]; /* 0x0000 */
+
+ u64 mic_ctl_cnfg2; /* 0x0040 */
+#define CBE_MIC_ENABLE_AUX_TRC 0x8000000000000000LL
+#define CBE_MIC_DISABLE_PWR_SAV_2 0x0200000000000000LL
+#define CBE_MIC_DISABLE_AUX_TRC_WRAP 0x0100000000000000LL
+#define CBE_MIC_ENABLE_AUX_TRC_INT 0x0080000000000000LL
+
+ u64 pad_0x0048; /* 0x0048 */
+
+ u64 mic_aux_trc_base; /* 0x0050 */
+ u64 mic_aux_trc_max_addr; /* 0x0058 */
+ u64 mic_aux_trc_cur_addr; /* 0x0060 */
+ u64 mic_aux_trc_grf_addr; /* 0x0068 */
+ u64 mic_aux_trc_grf_data; /* 0x0070 */
+
+ u64 pad_0x0078; /* 0x0078 */
+
+ u64 mic_ctl_cnfg_0; /* 0x0080 */
+#define CBE_MIC_DISABLE_PWR_SAV_0 0x8000000000000000LL
+
+ u64 pad_0x0088; /* 0x0088 */
+
+ u64 slow_fast_timer_0; /* 0x0090 */
+ u64 slow_next_timer_0; /* 0x0098 */
+
+ u8 pad_0x00a0_0x01c0[0x01c0 - 0x0a0]; /* 0x00a0 */
+
+ u64 mic_ctl_cnfg_1; /* 0x01c0 */
+#define CBE_MIC_DISABLE_PWR_SAV_1 0x8000000000000000LL
+ u64 pad_0x01c8; /* 0x01c8 */
+
+ u64 slow_fast_timer_1; /* 0x01d0 */
+ u64 slow_next_timer_1; /* 0x01d8 */
+
+ u8 pad_0x01e0_0x1000[0x1000 - 0x01e0]; /* 0x01e0 */
+};
+
+extern struct cbe_mic_tm_regs __iomem *cbe_get_mic_tm_regs(struct device_node *np);
+extern struct cbe_mic_tm_regs __iomem *cbe_get_cpu_mic_tm_regs(int cpu);
+
+/* some utility functions to deal with SMT */
+extern u32 cbe_get_hw_thread_id(int cpu);
+extern u32 cbe_cpu_to_node(int cpu);
+extern u32 cbe_node_to_cpu(int node);
+
+/* Init this module early */
+extern void cbe_regs_init(void);
+
+
+#endif /* CBE_REGS_H */
^ permalink raw reply
* [PATCH 0/4] Cell EDAC driver and dependencies
From: Benjamin Herrenschmidt @ 2007-10-04 5:40 UTC (permalink / raw)
To: bluesmoke-devel, linuxppc-dev; +Cc: Paul Mackerras, cbe-oss-dev, Arnd Bergmann
This is a serie of 4 patches. The first two should be applied via
the powerpc tree and the second via the bluesmoke tree. The later
do depend on the former so the new driver won't compile until the
former has been merged in case bluesmoke is pulled first but that
shoudn't be a big issue.
^ permalink raw reply
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