* [RFC 09/10] alpha: vmlinux.lds cleanup - use THREAD_SIZE macro
From: gorcunov @ 2008-02-27 20:58 UTC (permalink / raw)
To: rth, chris, jdike, linuxppc-dev, paulus, dhowells, zippel, geert,
linux-m68k, takata, linux-m32r, linux-kernel
Cc: gorcunov, sam
In-Reply-To: <20080227205831.150784453@gmail.com>
This patch modifies thread_info.h header to be able to include it
into linker script and then we're able to use THREAD_SIZE in
vmlinux.lds
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Reviewed-by: Sam Ravnborg <sam@ravnborg.org>
---
arch/alpha/kernel/vmlinux.lds.S | 3 ++-
include/asm-alpha/thread_info.h | 9 ++++++---
2 files changed, 8 insertions(+), 4 deletions(-)
Index: linux-2.6.git/arch/alpha/kernel/vmlinux.lds.S
===================================================================
--- linux-2.6.git.orig/arch/alpha/kernel/vmlinux.lds.S 2008-02-27 21:48:19.000000000 +0300
+++ linux-2.6.git/arch/alpha/kernel/vmlinux.lds.S 2008-02-27 22:05:37.000000000 +0300
@@ -1,5 +1,6 @@
#include <asm-generic/vmlinux.lds.h>
#include <asm/page.h>
+#include <asm/thread_info.h>
OUTPUT_FORMAT("elf64-alpha")
OUTPUT_ARCH(alpha)
@@ -88,7 +89,7 @@ SECTIONS
PERCPU(PAGE_SIZE)
- . = ALIGN(2 * PAGE_SIZE);
+ . = ALIGN(THREAD_SIZE);
__init_end = .;
/* Freed after init ends here */
Index: linux-2.6.git/include/asm-alpha/thread_info.h
===================================================================
--- linux-2.6.git.orig/include/asm-alpha/thread_info.h 2008-02-27 21:48:28.000000000 +0300
+++ linux-2.6.git/include/asm-alpha/thread_info.h 2008-02-27 22:05:37.000000000 +0300
@@ -7,9 +7,7 @@
#include <asm/processor.h>
#include <asm/types.h>
#include <asm/hwrpb.h>
-#endif
-#ifndef __ASSEMBLY__
struct thread_info {
struct pcb_struct pcb; /* palcode state */
@@ -50,13 +48,14 @@ register struct thread_info *__current_t
#define current_thread_info() __current_thread_info
/* Thread information allocation. */
-#define THREAD_SIZE (2*PAGE_SIZE)
#define alloc_thread_info(tsk) \
((struct thread_info *) __get_free_pages(GFP_KERNEL,1))
#define free_thread_info(ti) free_pages((unsigned long) (ti), 1)
#endif /* __ASSEMBLY__ */
+#define THREAD_SIZE (2 * PAGE_SIZE)
+
#define PREEMPT_ACTIVE 0x40000000
/*
@@ -94,6 +93,8 @@ register struct thread_info *__current_t
#define ALPHA_UAC_MASK (1 << TIF_UAC_NOPRINT | 1 << TIF_UAC_NOFIX | \
1 << TIF_UAC_SIGBUS)
+#ifndef __ASSEMBLY__
+
#define SET_UNALIGN_CTL(task,value) ({ \
task_thread_info(task)->flags = ((task_thread_info(task)->flags & \
~ALPHA_UAC_MASK) \
@@ -112,5 +113,7 @@ register struct thread_info *__current_t
(int __user *)(value)); \
})
+#endif /* __ASSEMBLY__ */
+
#endif /* __KERNEL__ */
#endif /* _ALPHA_THREAD_INFO_H */
--
^ permalink raw reply
* [RFC 08/10] um: dyn/uml.lds.S cleanup - use PAGE_SIZE macro
From: gorcunov @ 2008-02-27 20:58 UTC (permalink / raw)
To: rth, chris, jdike, linuxppc-dev, paulus, dhowells, zippel, geert,
linux-m68k, takata, linux-m32r, linux-kernel
Cc: gorcunov, sam
In-Reply-To: <20080227205831.150784453@gmail.com>
This patch includes page.h header into liker scripts that
allow us to use PAGE_SIZE macro instead of numeric constant.
To be able to include page.h into linker scripts page.h is
needed for some modification - i.e. we need to use __ASSEMBLY__
and _AC macro
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
---
WARNING: COMPLETELY UNTESTED !!!
arch/um/kernel/dyn.lds.S | 7 ++++---
arch/um/kernel/uml.lds.S | 7 ++++---
include/asm-um/page.h | 17 +++++++++++------
3 files changed, 19 insertions(+), 12 deletions(-)
Index: linux-2.6.git/arch/um/kernel/dyn.lds.S
===================================================================
--- linux-2.6.git.orig/arch/um/kernel/dyn.lds.S 2008-01-29 18:03:46.000000000 +0300
+++ linux-2.6.git/arch/um/kernel/dyn.lds.S 2008-02-27 21:38:48.000000000 +0300
@@ -1,4 +1,5 @@
#include <asm-generic/vmlinux.lds.h>
+#include <asm/page.h>
OUTPUT_FORMAT(ELF_FORMAT)
OUTPUT_ARCH(ELF_ARCH)
@@ -21,7 +22,7 @@ SECTIONS
_einittext = .;
}
- . = ALIGN(4096);
+ . = ALIGN(PAGE_SIZE);
/* Read-only sections, merged into text segment: */
.hash : { *(.hash) }
@@ -68,9 +69,9 @@ SECTIONS
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
- . = ALIGN(4096);
+ . = ALIGN(PAGE_SIZE);
} =0x90909090
- . = ALIGN(4096);
+ . = ALIGN(PAGE_SIZE);
.syscall_stub : {
__syscall_stub_start = .;
*(.__syscall_stub*)
Index: linux-2.6.git/arch/um/kernel/uml.lds.S
===================================================================
--- linux-2.6.git.orig/arch/um/kernel/uml.lds.S 2008-01-29 18:03:46.000000000 +0300
+++ linux-2.6.git/arch/um/kernel/uml.lds.S 2008-02-27 21:38:53.000000000 +0300
@@ -1,4 +1,5 @@
#include <asm-generic/vmlinux.lds.h>
+#include <asm/page.h>
OUTPUT_FORMAT(ELF_FORMAT)
OUTPUT_ARCH(ELF_ARCH)
@@ -26,7 +27,7 @@ SECTIONS
INIT_TEXT
_einittext = .;
}
- . = ALIGN(4096);
+ . = ALIGN(PAGE_SIZE);
.text :
{
@@ -39,7 +40,7 @@ SECTIONS
*(.gnu.linkonce.t*)
}
- . = ALIGN(4096);
+ . = ALIGN(PAGE_SIZE);
.syscall_stub : {
__syscall_stub_start = .;
*(.__syscall_stub*)
@@ -79,7 +80,7 @@ SECTIONS
.sdata : { *(.sdata) }
_edata = .;
PROVIDE (edata = .);
- . = ALIGN(0x1000);
+ . = ALIGN(PAGE_SIZE);
.sbss :
{
__bss_start = .;
Index: linux-2.6.git/include/asm-um/page.h
===================================================================
--- linux-2.6.git.orig/include/asm-um/page.h 2008-02-09 12:09:29.000000000 +0300
+++ linux-2.6.git/include/asm-um/page.h 2008-02-27 21:42:17.000000000 +0300
@@ -7,16 +7,20 @@
#ifndef __UM_PAGE_H
#define __UM_PAGE_H
-struct page;
-
-#include <linux/types.h>
-#include <asm/vm-flags.h>
+#include <linux/const.h>
/* PAGE_SHIFT determines the page size */
#define PAGE_SHIFT 12
-#define PAGE_SIZE (1UL << PAGE_SHIFT)
+#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
+#ifndef __ASSEMBLY__
+
+struct page;
+
+#include <linux/types.h>
+#include <asm/vm-flags.h>
+
/*
* These are used to make use of C type-checking..
*/
@@ -120,4 +124,5 @@ extern struct page *arch_validate(struct
#include <asm-generic/memory_model.h>
#include <asm-generic/page.h>
-#endif
+#endif /* __ASSEMBLY__ */
+#endif /* __UM_PAGE_H */
--
^ permalink raw reply
* Re: [dtc] breaking out libfdt from dtc so other progs can use it
From: Jerone Young @ 2008-02-27 21:24 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev
In-Reply-To: <20080227143101.7a262aae@zod.rchland.ibm.com>
On Wed, 2008-02-27 at 14:31 -0600, Josh Boyer wrote:
> On Wed, 27 Feb 2008 13:40:43 -0600
> Jerone Young <jyoung5@us.ibm.com> wrote:
>
> > Currently the dtc source code has libfdt integrated in it. This seems to
> > have become place for upstream libfdt changes. Now we all know everyone
> > (linux kernel, cuboot) also have their own versions over libfdt. But if
> > another userspace app wants to use libfdt , it has to copy it from the
> > dtc source and try to maintain it's own copy.
> >
> > The question I have is can libfdt be split out from dtc source, and
> > become it's own thing. This way other userspace apps can easily download
> > it and link with it?
>
> Downloading isn't changed at all by splitting it out to it's own repo.
Well it is, as we could then point to libfdt repository. Right now we
need to download dtc ..the do make libfdt ... and then we are rollin. So
there are some steps required.
It would just be really really nice if it was more stand alone.
>
> > The reason I ask is I have added dynamic manipulation support of device
> > trees in memory into qemu for KVM. But the issue is keeping a copy of
> > libfdt in the KVM userspace repository, which is getting some opposition
> > (understandably). But this would be much easier if there was a libfdt
> > repo for the library so that we wouldn't need to keep our own copy.
>
> It seems the real crux of your issue is that you want distros to
> provide a libfdt package. That can be done by creating a subpackage
> off of the dtc package. The harder part for certain distros will be
> either convincing them to allow the static libfdt to exist, or creating
> a shared library for it instead.
Ultimately this would be the most optimal solution for the future. If
distros could distribute a library with headers that would be awesome.
Since this is something that qemu in general can take advantage of (not
just KVM qemu)...having libs in the distro would be easier for
distributing.
But for now I just need a way for users to easily get a hold of libary
and just point cflags and ldflags at the directory where it is
compiled.
>
> josh
^ permalink raw reply
* Re: patchwork missing patches?
From: Olof Johansson @ 2008-02-27 22:34 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev, jk
In-Reply-To: <20080227093950.11c8f4af@zod.rchland.ibm.com>
On Wed, Feb 27, 2008 at 09:39:50AM -0600, Josh Boyer wrote:
> I'm trying to find some patches that went to the list recently in
> patchwork and they seem to be missing. Here are a few:
>
> http://ozlabs.org/pipermail/linuxppc-dev/2008-February/052196.html
I looked up the first one:
http://patchwork.ozlabs.org/linuxppc/patch&id=17004
> There might be more. Maybe I'm just blind, but I can't find them at
> all in patchwork.
The above is marked "Awaiting Upstream", maybe that's filtering it out
from your default list?
-Olof
^ permalink raw reply
* Re: patchwork missing patches?
From: Paul Mackerras @ 2008-02-27 23:00 UTC (permalink / raw)
To: Josh Boyer; +Cc: linuxppc-dev, jk
In-Reply-To: <20080227093950.11c8f4af@zod.rchland.ibm.com>
Josh Boyer writes:
> I'm trying to find some patches that went to the list recently in
> patchwork and they seem to be missing. Here are a few:
>
> http://ozlabs.org/pipermail/linuxppc-dev/2008-February/052196.html
That one was in "awaiting upstream" state since I put it in the
bundle, then realized it should probably go through your tree, and
didn't apply it. I've put it back to "new" state now.
> http://ozlabs.org/pipermail/linuxppc-dev/2008-February/052164.html
I seem to recall putting that one in "changes requested" state, but
now I can't find it either. Strange...
> http://ozlabs.org/pipermail/linuxppc-dev/2008-February/052129.html
Not sure where that one has gone.
> http://ozlabs.org/pipermail/linuxppc-dev/2008-February/052050.html
I have been deleting patches that go through other maintainers to try
to keep the number of patches down to a manageable level, and that
includes ibm_newemac patches, since they go through Jeff Garzik.
That's probably what happened to this one. I'll leave ibm_newemac
patches alone if you promise to clean them up periodically. :)
Paul.
^ permalink raw reply
* FW: [PATCH] Xilinx: LL TEMAC/Bootstrap: Updated driver and bootstrap to pull mac addr from eeprom
From: John Linn @ 2008-02-27 23:14 UTC (permalink / raw)
To: linuxppc-dev, git-dev
The LL TEMAC driver was updated to use the mac address from the board
data,
to use the Marvell specific PHY code so that 10 Mbit works, and to use
the
dcr_host from the platform data rather than using conditional
compilation
for DCR with DMA. The bootstrap loader was changed to read the mac
address
from the eeprom into the board data.
Signed-off-by: John Linn <john.linn@xilinx.com>
---
arch/ppc/boot/simple/Makefile | 10 +-
arch/ppc/boot/simple/embed_config.c | 154 ++++-
drivers/i2c/algos/xilinx_iic/Makefile | 2 +-
drivers/i2c/algos/xilinx_iic/xiic_l.c | 967
++++++++++++++++++++++++++++
drivers/net/xilinx_lltemac/xlltemac_main.c | 58 +-
5 files changed, 1153 insertions(+), 38 deletions(-)
create mode 100755 drivers/i2c/algos/xilinx_iic/xiic_l.c
diff --git a/arch/ppc/boot/simple/Makefile
b/arch/ppc/boot/simple/Makefile
index 8581bea..2b0671e 100644
--- a/arch/ppc/boot/simple/Makefile
+++ b/arch/ppc/boot/simple/Makefile
@@ -21,6 +21,11 @@
# XXX_memory.o file for this to work, as well as editing the
# misc-$(CONFIG_MACHINE) variable.
=20
+ifeq ($(CONFIG_XILINX_EMBED_CONFIG),y)
+EXTRA_CFLAGS +=3D -Idrivers/i2c/algos/xilinx_iic
+EXTRA_CFLAGS +=3D -Idrivers/xilinx_common
+endif
+
boot :=3D arch/ppc/boot
common :=3D $(boot)/common
utils :=3D $(boot)/utils
@@ -128,6 +133,9 @@ zimageinitrd-$(CONFIG_WALNUT) :=3D
zImage.initrd-TREE
end-$(CONFIG_EV64360) :=3D ev64360
cacheflag-$(CONFIG_EV64360) :=3D -include $(clear_L2_L3)
=20
+ extra.o-$(CONFIG_XILINX_EMBED_CONFIG) :=3D
../../../../drivers/xilinx_common/xio.o \
+
../../../../drivers/i2c/algos/xilinx_iic/xiic_l.o=09
+
# kconfig 'feature', only one of these will ever be 'y' at a time.
# The rest will be unset.
motorola :=3D $(CONFIG_MVME5100)$(CONFIG_PRPMC750) \
@@ -187,7 +195,7 @@ boot-$(CONFIG_REDWOOD_6) +=3D embed_config.o
boot-$(CONFIG_8xx) +=3D embed_config.o
boot-$(CONFIG_8260) +=3D embed_config.o
boot-$(CONFIG_EP405) +=3D embed_config.o
-boot-$(CONFIG_XILINX_EMBED_CONFIG) +=3D embed_config.o
+boot-$(CONFIG_XILINX_EMBED_CONFIG) +=3D embed_config.o=20
boot-$(CONFIG_BSEIP) +=3D iic.o
boot-$(CONFIG_MBX) +=3D iic.o pci.o qspan_pci.o
boot-$(CONFIG_MV64X60) +=3D misc-mv64x60.o
diff --git a/arch/ppc/boot/simple/embed_config.c
b/arch/ppc/boot/simple/embed_config.c
index beb03db..45f1421 100644
--- a/arch/ppc/boot/simple/embed_config.c
+++ b/arch/ppc/boot/simple/embed_config.c
@@ -17,12 +17,14 @@
#include <asm/mpc8260.h>
#include <asm/immap_cpm2.h>
#endif
-#ifdef CONFIG_40x
+#if defined (CONFIG_40x) || defined (CONFIG_44x)
#include <asm/io.h>
#endif
+
#ifdef CONFIG_XILINX_VIRTEX
#include <platforms/4xx/xparameters/xparameters.h>
#endif
+
extern unsigned long timebase_period_ns;
=20
/* For those boards that don't provide one.
@@ -744,17 +746,134 @@ embed_config(bd_t **bdp)
}
#endif /* WILLOW */
=20
-#if defined(CONFIG_XILINX_EMBED_CONFIG)
+#if defined(CONFIG_XILINX_ML403) || defined(CONFIG_XILINX_ML405) ||
defined(CONFIG_XILINX_ML507)
+
+#if (!defined(XPAR_IIC_0_BASEADDR) ||
!defined(XPAR_PERSISTENT_0_IIC_0_BASEADDR))
+int get_cfg_data(unsigned char **cfg_data)
+{
+ /*
+ * The ML300, ML40x and ML50x uses an I2C SEEPROM to store the
Ethernet
+ * MAC address, but either an I2C interface or the SEEPROM
aren't
+ * configured in. If you are in this situation, you'll need to
define
+ * an alternative way of storing the Ethernet MAC address. For
now, a
+ * hard-coded MAC will be used. If this is sufficient, you may
simply
+ * comment out the followign #warning.
+ */
+#warning I2C needed for obtaining the Ethernet MAC address. Using
hard-coded MAC address
+ return 0; /* no cfg data found */
+}
+#else
+#include <xiic_l.h>
+
+#define CFG_DATA_SIZE \
+ (XPAR_PERSISTENT_0_IIC_0_HIGHADDR - XPAR_PERSISTENT_0_IIC_0_BASEADDR +
1)
+
+int get_cfg_data(unsigned char **cfg_data)
+{
+ static unsigned char sdata[CFG_DATA_SIZE]; /* 'static': get
sdata off the stack */
+ int i;
+
+ /*
+ * Fill our SEEPROM data array (sdata) from address
+ * XPAR_PERSISTENT_0_IIC_0_BASEADDR of the SEEPROM at slave
+ * address XPAR_PERSISTENT_0_IIC_0_EEPROMADDR. We'll then parse
+ * that data looking for a MAC address. */
+ sdata[0] =3D XPAR_PERSISTENT_0_IIC_0_BASEADDR >> 8;
+#if defined(XPAR_IIC_0_TEN_BIT_ADR) && (XPAR_IIC_0_TEN_BIT_ADR =3D=3D =
1)
+ sdata[1] =3D XPAR_PERSISTENT_0_IIC_0_BASEADDR & 0xFF;
+ i =3D XIic_Send(XPAR_IIC_0_BASEADDR,
+ XPAR_PERSISTENT_0_IIC_0_EEPROMADDR>>1, sdata, 2,
XIIC_STOP);
+ if (i !=3D 2)
+ return 0; /* Couldn't send the address. Return
error. */
+#else
+ i =3D XIic_Send(XPAR_IIC_0_BASEADDR,
+ XPAR_PERSISTENT_0_IIC_0_EEPROMADDR>>1, sdata, 1,
XIIC_STOP);
+ if (i !=3D 1) {
+ return 0; /* Couldn't send the address. Return
error. */
+ }
+#endif
+ i =3D XIic_Recv(XPAR_IIC_0_BASEADDR,
+ XPAR_PERSISTENT_0_IIC_0_EEPROMADDR>>1,
+ sdata, sizeof(sdata), XIIC_STOP);
+ if (i !=3D sizeof(sdata)) {
+ return 0; /* Didn't read all the data. Return
error. */
+ }
+ *cfg_data =3D sdata;
+ return CFG_DATA_SIZE;
+}
+#endif /* (!defined(XPAR_IIC_0_BASEADDR) ||
!defined(XPAR_PERSISTENT_0_IIC_0_BASEADDR)) */
+
+static int
+hexdigit(char c)
+{
+ if ('0' <=3D c && c <=3D '9')
+ return c - '0';
+ else if ('a' <=3D c && c <=3D 'f')
+ return c - 'a' + 10;
+ else if ('A' <=3D c && c <=3D 'F')
+ return c - 'A' + 10;
+ else
+ return -1;
+}
+
+typedef struct iic_eeprom_struct {
+ /* Generally used parameters */
+ char which_board[17]; /* 0x000 to 0x010 Plain text ID
of which board */
+ char board_rev[5]; /* 0x011 to 0x015 Plain text
Board Rev (A, B, C, etc) */
+ char minor_board_rev[5]; /* 0x016 to 0x01A Plain text
minor board rev (001, 002, etc) */
+ char which_FPGA[19]; /* 0x01B to 0x02E Plain text
which FPGA is on the board (main FPGA if multiple) */
+ char board_sn[9]; /* 0x02F to 0x037 Plain text
Serial Number of board */
+ char board_mac_id[13]; /* 0x038 to 0x044 Plain text MAC
Address for this board */
+ char last_test_date[12]; /* 0x045 to 0x050 Plain text last
date that tests were run (DD-MMM-YYYY) */
+ char manufacture_date[12]; /* 0x051 to 0x05C Plain text
Manufacture Date (DD-MMM-YYYY) */
+ char manufacture_id[17]; /* 0x05D to 0x06D Plain text
Manufacture ID (Name) */
+ char tested_before[19]; /* 0x06E to 0x080 Plain text set
to 'Xilinx Virtex-X Based MLxxx' (?19?) */
+} iic_eeprom_struct;
+
+static int get_mac_addr(unsigned char *mac)
+{
+ iic_eeprom_struct *eeprom;
+ int cfg_size;
+
+ cfg_size =3D get_cfg_data((unsigned char **)&eeprom);
+
+ if (cfg_size =3D=3D 0)
+ return 1; /* Failed to read configuration data */
+
+ /* check the manufacture date to make sure we've got the right
struct
+ * info */
+ if ((eeprom->board_mac_id[0] =3D=3D '0') &&
+ (eeprom->board_mac_id[1] =3D=3D '0') &&
+ (eeprom->board_mac_id[2] =3D=3D '0') && =09
+ (eeprom->board_mac_id[3] =3D=3D 'A') &&
+ (eeprom->board_mac_id[4] =3D=3D '3') &&
+ (eeprom->board_mac_id[5] =3D=3D '5')) {
+ mac[0] =3D (hexdigit(eeprom->board_mac_id[0]) << 4) |
(hexdigit(eeprom->board_mac_id[1]));
+ mac[1] =3D (hexdigit(eeprom->board_mac_id[2]) << 4) |
(hexdigit(eeprom->board_mac_id[3]));
+ mac[2] =3D (hexdigit(eeprom->board_mac_id[4]) << 4) |
(hexdigit(eeprom->board_mac_id[5]));
+ mac[3] =3D (hexdigit(eeprom->board_mac_id[6]) << 4) |
(hexdigit(eeprom->board_mac_id[7]));
+ mac[4] =3D (hexdigit(eeprom->board_mac_id[8]) << 4) |
(hexdigit(eeprom->board_mac_id[9]));
+ mac[5] =3D (hexdigit(eeprom->board_mac_id[10]) << 4) |
(hexdigit(eeprom->board_mac_id[11]));
+
+ /* Success */
+ return 0;
+
+ }=20
+
+ /* Data not recognized */
+ return 1;
+}
+
void
embed_config(bd_t ** bdp)
{
+#ifdef CONFIG_40x
static const unsigned long line_size =3D 32;
static const unsigned long congruence_classes =3D 256;
unsigned long addr;
unsigned long dccr;
- uint8_t* cp;
+#endif
bd_t *bd;
- int i;
=20
/*
* Invalidate the data cache if the data cache is turned off.
@@ -765,6 +884,7 @@ embed_config(bd_t ** bdp)
* a bootloader and we assume that the cache contents are
* valid.
*/
+#ifdef CONFIG_40x
__asm__("mfdccr %0": "=3Dr" (dccr));
if (dccr =3D=3D 0) {
for (addr =3D 0;
@@ -773,23 +893,37 @@ embed_config(bd_t ** bdp)
__asm__("dccci 0,%0": :"b"(addr));
}
}
+#endif
=20
bd =3D &bdinfo;
*bdp =3D bd;
bd->bi_memsize =3D XPAR_DDR_0_SIZE;
bd->bi_intfreq =3D XPAR_CORE_CLOCK_FREQ_HZ;
bd->bi_busfreq =3D XPAR_PLB_CLOCK_FREQ_HZ;
+#ifdef XPAR_PCI_0_CLOCK_FREQ_HZ
bd->bi_pci_busfreq =3D XPAR_PCI_0_CLOCK_FREQ_HZ;
+#endif
=20
- /* Copy the default ethernet address */
- cp =3D (u_char *)def_enet_addr;
- for (i=3D0; i<6; i++)
- bd->bi_enetaddr[i] =3D *cp++;
+ if (get_mac_addr(bd->bi_enetaddr)) {
+ /* The SEEPROM is corrupted. set the address to
+ * Xilinx's preferred default. However, first to
+ * eliminate a compiler warning because we don't really
+ * use def_enet_addr, we'll reference it. The compiler
+ * optimizes it away so no harm done. */
+ bd->bi_enetaddr[0] =3D def_enet_addr[0];
+ bd->bi_enetaddr[0] =3D 0x00;
+ bd->bi_enetaddr[1] =3D 0x0A;
+ bd->bi_enetaddr[2] =3D 0x35;
+ bd->bi_enetaddr[3] =3D 0x01;
+ bd->bi_enetaddr[4] =3D 0x02;
+ bd->bi_enetaddr[5] =3D 0x03;
+ }
=20
timebase_period_ns =3D 1000000000 / bd->bi_tbfreq;
- /* see bi_tbfreq definition in
arch/ppc/platforms/4xx/xilinx_ml300.h */
+ /* see bi_tbfreq definition in
arch/ppc/platforms/4xx/xilinx_mlxxx.h */
}
-#endif /* CONFIG_XILINX_EMBED_CONFIG */
+#endif /* defined(CONFIG_XILINX_ML403) || defined(CONFIG_XILINX_ML405)
||=20
+ defined(CONFIG_XILINX_ML507) */
=20
#ifdef CONFIG_IBM_OPENBIOS
/* This could possibly work for all treeboot roms.
diff --git a/drivers/i2c/algos/xilinx_iic/Makefile
b/drivers/i2c/algos/xilinx_iic/Makefile
index 78ff332..80e351a 100644
--- a/drivers/i2c/algos/xilinx_iic/Makefile
+++ b/drivers/i2c/algos/xilinx_iic/Makefile
@@ -11,4 +11,4 @@ xilinx_iic-objs :=3D i2c-algo-xilinx.o
=20
# The Xilinx OS independent code.
xilinx_iic-objs +=3D xiic.o xiic_options.o xiic_master.o \
- xiic_intr.o
+ xiic_intr.o xiic_l.o
diff --git a/drivers/i2c/algos/xilinx_iic/xiic_l.c
b/drivers/i2c/algos/xilinx_iic/xiic_l.c
new file mode 100755
index 0000000..e2e23e3
--- /dev/null
+++ b/drivers/i2c/algos/xilinx_iic/xiic_l.c
@@ -0,0 +1,967 @@
+/* $Id: xiic_l.c,v 1.3 2007/12/17 19:15:38 meinelte Exp $ */
+/**********************************************************************
********
+*
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
+* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
+* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
+* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
+* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF
INFRINGEMENT,
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
REQUIRE
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE.
+*
+* (c) Copyright 2002-2007 Xilinx Inc.
+* All rights reserved.
+* This program is free software; you can redistribute it and/or modify
it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2 of the License, or (at
your
+* option) any later version.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301
USA
+*
+***********************************************************************
*******/
+/**********************************************************************
*******/
+/**
+*
+* @file xiic_l.c
+*
+* This file contains low-level driver functions that can be used to
access the
+* device in normal and dynamic controller mode. The user should refer
to the
+* hardware device specification for more details of the device
operation.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver Who Date Changes
+* ----- --- ------- -----------------------------------------------
+* 1.01b jhl 05/13/02 First release
+* 1.01b jhl 10/14/02 Corrected bug in the receive function, the setup
of the
+* interrupt status mask was not being done in the
loop such
+* that a read would sometimes fail on the last byte
because
+* the transmit error which should have been ignored
was
+* being used. This would leave an extra byte in
the FIFO
+* and the bus throttled such that the next
operation would
+* also fail. Also updated the receive function to
not
+* disable the device after the last byte until
after the
+* bus transitions to not busy which is more
consistent
+* with the expected behavior.
+* 1.01c ecm 12/05/02 new rev
+* 1.02a mta 03/09/06 Implemented Repeated Start in the Low Level
Driver.
+* 1.03a mta 04/04/06 Implemented Dynamic IIC core routines.
+* 1.03a ecm 06/15/06 Fixed the hang in low_level_eeprom_test with -O0
+* Added polling loops for BNB to allow the slave to
+* respond correctly. Also added polling loop prior
+* to reset in _Recv.
+* 1.13a wgr 03/22/07 Converted to new coding style.
+* 1.13b ecm 11/29/07 added BB polling loops to the DynSend and DynRecv
+* routines to handle the race
condition with BNB in IISR.
+* </pre>
+*
+***********************************************************************
*****/
+
+/***************************** Include Files
*******************************/
+
+#include "xbasic_types.h"
+#include "xio.h"
+#include "xiic_l.h"
+
+/************************** Constant Definitions
***************************/
+
+/**************************** Type Definitions
*****************************/
+
+/***************** Macros (Inline Functions) Definitions
*******************/
+
+/************************** Function Prototypes
****************************/
+
+static unsigned RecvData(u32 BaseAddress, u8 *BufferPtr,
+ unsigned ByteCount, u8 Option);
+static unsigned SendData(u32 BaseAddress, u8 *BufferPtr,
+ unsigned ByteCount, u8 Option);
+
+static unsigned DynRecvData(u32 BaseAddress, u8 *BufferPtr, u8
ByteCount);
+static unsigned DynSendData(u32 BaseAddress, u8 *BufferPtr,
+ u8 ByteCount, u8 Option);
+
+/************************** Variable Definitions
**************************/
+
+/**********************************************************************
******/
+/**
+* Receive data as a master on the IIC bus. This function receives the
data
+* using polled I/O and blocks until the data has been received. It only
+* supports 7 bit addressing mode of operation. The user is responsible
for
+* ensuring the bus is not busy if multiple masters are present on the
bus.
+*
+* @param BaseAddress contains the base address of the IIC device.
+* @param Address contains the 7 bit IIC address of the device to
send the
+* specified data to.
+* @param BufferPtr points to the data to be sent.
+* @param ByteCount is the number of bytes to be sent.
+* @param Option indicates whether to hold or free the bus after
reception
+* of data, XIIC_STOP =3D end with STOP condition,
XIIC_REPEATED_START
+* =3D don't end with STOP condition.
+*
+* @return
+*
+* The number of bytes received.
+*
+* @note
+*
+* None
+*
+***********************************************************************
*******/
+unsigned XIic_Recv(u32 BaseAddress, u8 Address,
+ u8 *BufferPtr, unsigned ByteCount, u8 Option)
+{
+ u8 CntlReg;
+ unsigned RemainingByteCount;
+ volatile u8 StatusReg;
+
+ /* Tx error is enabled incase the address (7 or 10) has no
device to answer
+ * with Ack. When only one byte of data, must set NO ACK before
address goes
+ * out therefore Tx error must not be enabled as it will go off
immediately
+ * and the Rx full interrupt will be checked. If full, then the
one byte
+ * was received and the Tx error will be disabled without
sending an error
+ * callback msg.
+ */
+ XIic_mClearIisr(BaseAddress,
+ XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK
|
+ XIIC_INTR_ARB_LOST_MASK);
+
+ /* Set receive FIFO occupancy depth for 1 byte (zero based)
+ */
+ XIo_Out8(BaseAddress + XIIC_RFD_REG_OFFSET, 0);
+
+
+ /* Check to see if already Master on the Bus.
+ * If Repeated Start bit is not set send Start bit by setting
MSMS bit else
+ * Send the address.
+ */
+ CntlReg =3D XIo_In8(BaseAddress + XIIC_CR_REG_OFFSET);
+ if ((CntlReg & XIIC_CR_REPEATED_START_MASK) =3D=3D 0) {
+ /* 7 bit slave address, send the address for a read
operation
+ * and set the state to indicate the address has been
sent
+ */
+ XIic_mSend7BitAddress(BaseAddress, Address,
+ XIIC_READ_OPERATION);
+
+
+ /* MSMS gets set after putting data in FIFO. Start the
master receive
+ * operation by setting CR Bits MSMS to Master, if the
buffer is only one
+ * byte, then it should not be acknowledged to indicate
the end of data
+ */
+ CntlReg =3D XIIC_CR_MSMS_MASK |
XIIC_CR_ENABLE_DEVICE_MASK;
+ if (ByteCount =3D=3D 1) {
+ CntlReg |=3D XIIC_CR_NO_ACK_MASK;
+ }
+
+ /* Write out the control register to start receiving
data and call the
+ * function to receive each byte into the buffer
+ */
+ XIo_Out8(BaseAddress + XIIC_CR_REG_OFFSET, CntlReg);
+
+ /* Clear the latched interrupt status for the bus not
busy bit which must
+ * be done while the bus is busy
+ */
+ StatusReg =3D XIo_In8(BaseAddress + XIIC_SR_REG_OFFSET);
+
+ while ((StatusReg & XIIC_SR_BUS_BUSY_MASK) =3D=3D 0) {
+ StatusReg =3D XIo_In8(BaseAddress +
XIIC_SR_REG_OFFSET);
+
+ }
+
+ XIic_mClearIisr(BaseAddress, XIIC_INTR_BNB_MASK);
+ }
+ else {
+ /* Already owns the Bus indicating that its a Repeated
Start call.
+ * 7 bit slave address, send the address for a read
operation
+ * and set the state to indicate the address has been
sent
+ */
+ XIic_mSend7BitAddress(BaseAddress, Address,
+ XIIC_READ_OPERATION);
+ }
+ /* Try to receive the data from the IIC bus */
+
+ RemainingByteCount =3D
+ RecvData(BaseAddress, BufferPtr, ByteCount, Option);
+
+ CntlReg =3D XIo_In8(BaseAddress + XIIC_CR_REG_OFFSET);
+ if ((CntlReg & XIIC_CR_REPEATED_START_MASK) =3D=3D 0) {
+ /* The receive is complete, disable the IIC device if
the Option is
+ * to release the Bus after Reception of data and return
the number of
+ * bytes that was received
+ */
+ XIo_Out8(BaseAddress + XIIC_CR_REG_OFFSET, 0);
+ }
+
+ /* Return the number of bytes that was received */
+
+ return ByteCount - RemainingByteCount;
+}
+
+/**********************************************************************
********
+*
+* Receive the specified data from the device that has been previously
addressed
+* on the IIC bus. This function assumes that the 7 bit address has
been sent
+* and it should wait for the transmit of the address to complete.
+*
+* @param BaseAddress contains the base address of the IIC device.
+* @param BufferPtr points to the buffer to hold the data that is
received.
+* @param ByteCount is the number of bytes to be received.
+* @param Option indicates whether to hold or free the bus after
reception
+* of data, XIIC_STOP =3D end with STOP condition,
XIIC_REPEATED_START
+* =3D don't end with STOP condition.
+*
+* @return
+*
+* The number of bytes remaining to be received.
+*
+* @note
+*
+* This function does not take advantage of the receive FIFO because it
is
+* designed for minimal code space and complexity. It contains loops
that
+* that could cause the function not to return if the hardware is not
working.
+*
+* This function assumes that the calling function will disable the IIC
device
+* after this function returns.
+*
+***********************************************************************
*******/
+static unsigned RecvData(u32 BaseAddress, u8 *BufferPtr,
+ unsigned ByteCount, u8 Option)
+{
+ u8 CntlReg;
+ u32 IntrStatusMask;
+ u32 IntrStatus;
+
+ /* Attempt to receive the specified number of bytes on the IIC
bus */
+
+ while (ByteCount > 0) {
+ /* Setup the mask to use for checking errors because
when receiving one
+ * byte OR the last byte of a multibyte message an error
naturally
+ * occurs when the no ack is done to tell the slave the
last byte
+ */
+ if (ByteCount =3D=3D 1) {
+ IntrStatusMask =3D
+ XIIC_INTR_ARB_LOST_MASK |
XIIC_INTR_BNB_MASK;
+ }
+ else {
+ IntrStatusMask =3D
+ XIIC_INTR_ARB_LOST_MASK |
+ XIIC_INTR_TX_ERROR_MASK |
XIIC_INTR_BNB_MASK;
+ }
+
+ /* Wait for the previous transmit and the 1st receive to
complete
+ * by checking the interrupt status register of the IPIF
+ */
+ while (1) {
+ IntrStatus =3D XIIC_READ_IISR(BaseAddress);
+ if (IntrStatus & XIIC_INTR_RX_FULL_MASK) {
+ break;
+ }
+ /* Check the transmit error after the receive
full because when
+ * sending only one byte transmit error will
occur because of the
+ * no ack to indicate the end of the data
+ */
+ if (IntrStatus & IntrStatusMask) {
+ return ByteCount;
+ }
+ }
+
+ CntlReg =3D XIo_In8(BaseAddress + XIIC_CR_REG_OFFSET);
+
+ /* Special conditions exist for the last two bytes so
check for them
+ * Note that the control register must be setup for
these conditions
+ * before the data byte which was already received is
read from the
+ * receive FIFO (while the bus is throttled
+ */
+ if (ByteCount =3D=3D 1) {
+ if (Option =3D=3D XIIC_STOP) {
+
+ /* If the Option is to release the bus
after the last data
+ * byte, it has already been read and no
ack has been done, so
+ * clear MSMS while leaving the device
enabled so it can get off
+ * the IIC bus appropriately with a
stop.
+ */
+ XIo_Out8(BaseAddress +
XIIC_CR_REG_OFFSET,
+ XIIC_CR_ENABLE_DEVICE_MASK);
+ }
+ }
+
+ /* Before the last byte is received, set NOACK to tell
the slave IIC
+ * device that it is the end, this must be done before
reading the byte
+ * from the FIFO
+ */
+ if (ByteCount =3D=3D 2) {
+ /* Write control reg with NO ACK allowing last
byte to
+ * have the No ack set to indicate to slave last
byte read.
+ */
+ XIo_Out8(BaseAddress + XIIC_CR_REG_OFFSET,
+ CntlReg | XIIC_CR_NO_ACK_MASK);
+ }
+
+ /* Read in data from the FIFO and unthrottle the bus
such that the
+ * next byte is read from the IIC bus
+ */
+ *BufferPtr++ =3D XIo_In8(BaseAddress +
XIIC_DRR_REG_OFFSET);
+
+ if ((ByteCount =3D=3D 1) && (Option =3D=3D XIIC_REPEATED_START))
{
+
+ /* RSTA bit should be set only when the FIFO is
completely Empty.
+ */
+ XIo_Out8(BaseAddress + XIIC_CR_REG_OFFSET,
+ XIIC_CR_ENABLE_DEVICE_MASK |
XIIC_CR_MSMS_MASK
+ | XIIC_CR_REPEATED_START_MASK);
+
+ }
+
+ /* Clear the latched interrupt status so that it will be
updated with
+ * the new state when it changes, this must be done
after the receive
+ * register is read
+ */
+ XIic_mClearIisr(BaseAddress, XIIC_INTR_RX_FULL_MASK |
+ XIIC_INTR_TX_ERROR_MASK |
+ XIIC_INTR_ARB_LOST_MASK);
+ ByteCount--;
+ }
+
+
+ if (Option =3D=3D XIIC_STOP) {
+
+ /* If the Option is to release the bus after Reception
of data, wait
+ * for the bus to transition to not busy before
returning, the IIC
+ * device cannot be disabled until this occurs. It
should transition as
+ * the MSMS bit of the control register was cleared
before the last byte
+ * was read from the FIFO.
+ */
+ while (1) {
+ if (XIIC_READ_IISR(BaseAddress) &
+ XIIC_INTR_BNB_MASK) {
+ break;
+ }
+ }
+ }
+
+ return ByteCount;
+}
+
+/**********************************************************************
******/
+/**
+* Send data as a master on the IIC bus. This function sends the data
+* using polled I/O and blocks until the data has been sent. It only
supports
+* 7 bit addressing mode of operation. The user is responsible for
ensuring
+* the bus is not busy if multiple masters are present on the bus.
+*
+* @param BaseAddress contains the base address of the IIC device.
+* @param Address contains the 7 bit IIC address of the device to
send the
+* specified data to.
+* @param BufferPtr points to the data to be sent.
+* @param ByteCount is the number of bytes to be sent.
+* @param Option indicates whether to hold or free the bus after
+* transmitting the data.
+*
+* @return
+*
+* The number of bytes sent.
+*
+* @note
+*
+* None
+*
+***********************************************************************
*******/
+unsigned XIic_Send(u32 BaseAddress, u8 Address,
+ u8 *BufferPtr, unsigned ByteCount, u8 Option)
+{
+ unsigned RemainingByteCount;
+ u8 ControlReg;
+ volatile u8 StatusReg;
+
+ /* Check to see if already Master on the Bus.
+ * If Repeated Start bit is not set send Start bit by setting
MSMS bit else
+ * Send the address.
+ */
+ ControlReg =3D XIo_In8(BaseAddress + XIIC_CR_REG_OFFSET);
+ if ((ControlReg & XIIC_CR_REPEATED_START_MASK) =3D=3D 0) {
+ /* Put the address into the FIFO to be sent and indicate
that the operation
+ * to be performed on the bus is a write operation
+ */
+ XIic_mSend7BitAddress(BaseAddress, Address,
+ XIIC_WRITE_OPERATION);
+ /* Clear the latched interrupt status so that it will be
updated with the
+ * new state when it changes, this must be done after
the address is put
+ * in the FIFO
+ */
+ XIic_mClearIisr(BaseAddress, XIIC_INTR_TX_EMPTY_MASK |
+ XIIC_INTR_TX_ERROR_MASK |
+ XIIC_INTR_ARB_LOST_MASK);
+
+ /* MSMS must be set after putting data into transmit
FIFO, indicate the
+ * direction is transmit, this device is master and
enable the IIC device
+ */
+ XIo_Out8(BaseAddress + XIIC_CR_REG_OFFSET,
+ XIIC_CR_MSMS_MASK | XIIC_CR_DIR_IS_TX_MASK |
+ XIIC_CR_ENABLE_DEVICE_MASK);
+
+ /* Clear the latched interrupt
+ * status for the bus not busy bit which must be done
while the bus is busy
+ */
+ StatusReg =3D XIo_In8(BaseAddress + XIIC_SR_REG_OFFSET);
+ while ((StatusReg & XIIC_SR_BUS_BUSY_MASK) =3D=3D 0) {
+ StatusReg =3D XIo_In8(BaseAddress +
XIIC_SR_REG_OFFSET);
+ }
+
+ XIic_mClearIisr(BaseAddress, XIIC_INTR_BNB_MASK);
+
+ }
+ else {
+ /* Already owns the Bus indicating that its a Repeated
Start call.
+ * 7 bit slave address, send the address for a write
operation
+ * and set the state to indicate the address has been
sent
+ */
+ XIic_mSend7BitAddress(BaseAddress, Address,
+ XIIC_WRITE_OPERATION);
+ }
+
+ /* Send the specified data to the device on the IIC bus
specified by the
+ * the address
+ */
+ RemainingByteCount =3D
+ SendData(BaseAddress, BufferPtr, ByteCount, Option);
+
+ ControlReg =3D XIo_In8(BaseAddress + XIIC_CR_REG_OFFSET);
+ if ((ControlReg & XIIC_CR_REPEATED_START_MASK) =3D=3D 0) {
+ /* The Transmission is completed, disable the IIC device
if the Option
+ * is to release the Bus after transmission of data and
return the number
+ * of bytes that was received. Only wait if master, if
addressed as slave
+ * just reset to release the bus.
+ */
+ if ((ControlReg & XIIC_CR_MSMS_MASK) !=3D 0) {
+ XIo_Out8(BaseAddress + XIIC_CR_REG_OFFSET,
+ (ControlReg & ~XIIC_CR_MSMS_MASK));
+ StatusReg =3D XIo_In8(BaseAddress +
XIIC_SR_REG_OFFSET);
+ while ((StatusReg & XIIC_SR_BUS_BUSY_MASK) !=3D 0)
{
+ StatusReg =3D
+ XIo_In8(BaseAddress +
+ XIIC_SR_REG_OFFSET);
+ }
+ }
+
+ XIo_Out8(BaseAddress + XIIC_CR_REG_OFFSET, 0);
+ }
+
+ return ByteCount - RemainingByteCount;
+}
+
+/**********************************************************************
********
+*
+* Send the specified buffer to the device that has been previously
addressed
+* on the IIC bus. This function assumes that the 7 bit address has
been sent
+* and it should wait for the transmit of the address to complete.
+*
+* @param BaseAddress contains the base address of the IIC device.
+* @param BufferPtr points to the data to be sent.
+* @param ByteCount is the number of bytes to be sent.
+* @param Option indicates whether to hold or free the bus after
+* transmitting the data.
+*
+* @return
+*
+* The number of bytes remaining to be sent.
+*
+* @note
+*
+* This function does not take advantage of the transmit FIFO because it
is
+* designed for minimal code space and complexity. It contains loops
that
+* that could cause the function not to return if the hardware is not
working.
+*
+***********************************************************************
*******/
+static unsigned SendData(u32 BaseAddress, u8 *BufferPtr,
+ unsigned ByteCount, u8 Option)
+{
+ u32 IntrStatus;
+
+ /* Send the specified number of bytes in the specified buffer by
polling
+ * the device registers and blocking until complete
+ */
+ while (ByteCount > 0) {
+ /* Wait for the transmit to be empty before sending any
more data
+ * by polling the interrupt status register
+ */
+ while (1) {
+ IntrStatus =3D XIIC_READ_IISR(BaseAddress);
+
+ if (IntrStatus & (XIIC_INTR_TX_ERROR_MASK |
+ XIIC_INTR_ARB_LOST_MASK |
+ XIIC_INTR_BNB_MASK)) {
+ return ByteCount;
+ }
+
+ if (IntrStatus & XIIC_INTR_TX_EMPTY_MASK) {
+ break;
+ }
+ }
+ /* If there is more than one byte to send then put the
next byte to send
+ * into the transmit FIFO
+ */
+ if (ByteCount > 1) {
+ XIo_Out8(BaseAddress + XIIC_DTR_REG_OFFSET,
+ *BufferPtr++);
+ }
+ else {
+ if (Option =3D=3D XIIC_STOP) {
+ /* If the Option is to release the bus
after the last data
+ * byte, Set the stop Option before
sending the last byte
+ * of data so that the stop Option will
be generated
+ * immediately following the data. This
is done by clearing
+ * the MSMS bit in the control register.
+ */
+ XIo_Out8(BaseAddress +
XIIC_CR_REG_OFFSET,
+ XIIC_CR_ENABLE_DEVICE_MASK |
+ XIIC_CR_DIR_IS_TX_MASK);
+ }
+
+ /* Put the last byte to send in the transmit
FIFO */
+
+ XIo_Out8(BaseAddress + XIIC_DTR_REG_OFFSET,
+ *BufferPtr++);
+
+ if (Option =3D=3D XIIC_REPEATED_START) {
+ XIic_mClearIisr(BaseAddress,
+
XIIC_INTR_TX_EMPTY_MASK);
+ /* Wait for the transmit to be empty
before setting RSTA bit. */
+ while (1) {
+ IntrStatus =3D
+ XIIC_READ_IISR
+ (BaseAddress);
+ if (IntrStatus &
+ XIIC_INTR_TX_EMPTY_MASK) {
+ /* RSTA bit should be
set only when the FIFO is completely Empty.
+ */
+ XIo_Out8(BaseAddress +
+
XIIC_CR_REG_OFFSET,
+
XIIC_CR_REPEATED_START_MASK
+ |
+
XIIC_CR_ENABLE_DEVICE_MASK
+ |
+
XIIC_CR_DIR_IS_TX_MASK
+ |
XIIC_CR_MSMS_MASK);
+ break;
+ }
+ }
+ }
+
+ }
+
+ /* Clear the latched interrupt status register and this
must be done after
+ * the transmit FIFO has been written to or it won't
clear
+ */
+ XIic_mClearIisr(BaseAddress, XIIC_INTR_TX_EMPTY_MASK);
+
+ /* Update the byte count to reflect the byte sent and
clear the latched
+ * interrupt status so it will be updated for the new
state
+ */
+ ByteCount--;
+ }
+
+ if (Option =3D=3D XIIC_STOP) {
+ /* If the Option is to release the bus after
transmission of data,
+ * Wait for the bus to transition to not busy before
returning, the IIC
+ * device cannot be disabled until this occurs.
+ * Note that this is different from a receive operation
because the stop
+ * Option causes the bus to go not busy.
+ */
+ while (1) {
+ if (XIIC_READ_IISR(BaseAddress) &
+ XIIC_INTR_BNB_MASK) {
+ break;
+ }
+ }
+ }
+
+ return ByteCount;
+}
+
+/**********************************************************************
*******/
+/**
+* Receive data as a master on the IIC bus. This function receives the
data
+* using polled I/O and blocks until the data has been received. It only
+* supports 7 bit addressing. The user is responsible for ensuring the
bus is
+* not busy if multiple masters are present on the bus.
+*
+* @param BaseAddress contains the base address of the IIC Device.
+* @param Address contains the 7 bit IIC Device address of the device
to send
+* the specified data to.
+* @param BufferPtr points to the data to be sent.
+* @param ByteCount is the number of bytes to be sent. This value
can't be
+* greater than 255 and needs to be greater than 0.
+*
+* @return The number of bytes received.
+*
+* @note Upon entry to this function, the IIC interface needs to be
already
+* enabled in the CR register.
+*
+***********************************************************************
*******/
+unsigned XIic_DynRecv(u32 BaseAddress, u8 Address, u8 *BufferPtr, u8
ByteCount)
+{
+ unsigned RemainingByteCount;
+ u32 StatusRegister;
+
+ /*
+ * Clear the latched interrupt status so that it will be updated
with
+ * the new state when it changes.
+ */
+ XIic_mClearIisr(BaseAddress, XIIC_INTR_TX_EMPTY_MASK |
+ XIIC_INTR_TX_ERROR_MASK |
XIIC_INTR_ARB_LOST_MASK);
+
+ /*
+ * Send the 7 bit slave address for a read operation and set the
state
+ * to indicate the address has been sent. Upon writing the
address, a
+ * start condition is initiated. MSMS is automatically set to
master
+ * when the address is written to the Fifo. If MSMS was already
set,
+ * then a re-start is sent prior to the address.
+ */
+ XIic_mDynSend7BitAddress(BaseAddress, Address,
XIIC_READ_OPERATION);
+
+ /*
+ * Wait for the bus to go busy.
+ */
+ StatusRegister =3D XIo_In8(BaseAddress + XIIC_SR_REG_OFFSET);
+
+ while (( StatusRegister & XIIC_SR_BUS_BUSY_MASK) !=3D
XIIC_SR_BUS_BUSY_MASK)
+ {
+ StatusRegister =3D XIo_In8(BaseAddress +
XIIC_SR_REG_OFFSET);
+ }
+
+ /*
+ * Clear the latched interrupt status for the bus not busy bit
which
+ * must be done while the bus is busy.
+ */
+ XIic_mClearIisr(BaseAddress, XIIC_INTR_BNB_MASK);
+
+ /*
+ * Write to the Tx Fifo the dynamic stop control bit with the
number of
+ * bytes that are to be read over the IIC interface from the
presently
+ * addressed device.
+ */
+ XIic_mDynSendStop(BaseAddress, ByteCount);
+
+ /*
+ * Receive the data from the IIC bus.
+ */
+ RemainingByteCount =3D DynRecvData(BaseAddress, BufferPtr,
ByteCount);
+
+ /*
+ * The receive is complete. Return the number of bytes that were
+ * received.
+ */
+ return ByteCount - RemainingByteCount;
+}
+
+/**********************************************************************
*******/
+/**
+* Receive the specified data from the device that has been previously
addressed
+* on the IIC bus. This function assumes the following:
+* - The Rx Fifo occupancy depth has been set to its max.
+* - Upon entry, the Rx Fifo is empty.
+* - The 7 bit address has been sent.
+* - The dynamic stop and number of bytes to receive has been written
to Tx
+* Fifo.
+*
+* @param BaseAddress contains the base address of the IIC Device.
+* @param BufferPtr points to the buffer to hold the data that is
received.
+* @param ByteCount is the number of bytes to be received. The range
of this
+* value is greater than 0 and not higher than 255.
+*
+* @return The number of bytes remaining to be received.
+*
+* @note This function contains loops that could cause the function
not
+* to return if the hardware is not working.
+*
+***********************************************************************
*******/
+static unsigned DynRecvData(u32 BaseAddress, u8 *BufferPtr, u8
ByteCount)
+{
+ u8 StatusReg;
+ u32 IntrStatus;
+ u32 IntrStatusMask;
+
+ while (ByteCount > 0) {
+
+ /* Setup the mask to use for checking errors because
when
+ * receiving one byte OR the last byte of a multibyte
message
+ * an error naturally occurs when the no ack is done to
tell
+ * the slave the last byte.
+ */
+ if (ByteCount =3D=3D 1) {
+ IntrStatusMask =3D
+ XIIC_INTR_ARB_LOST_MASK |
XIIC_INTR_BNB_MASK;
+ }
+ else {
+ IntrStatusMask =3D
+ XIIC_INTR_ARB_LOST_MASK |
+ XIIC_INTR_TX_ERROR_MASK |
XIIC_INTR_BNB_MASK;
+ }
+
+ /*
+ * Wait for a byte to show up in the Rx Fifo.
+ */
+ do {
+ StatusReg =3D XIo_In8(BaseAddress +
XIIC_SR_REG_OFFSET);
+ IntrStatus =3D XIIC_READ_IISR(BaseAddress);
+
+ /* Check the transmit error after the receive
full
+ * because when sending only one byte transmit
error
+ * will occur because of the no ack to indicate
the end
+ * of the data.
+ */
+ if (IntrStatus & IntrStatusMask) {
+ return ByteCount;
+ }
+
+ } while ((StatusReg & XIIC_SR_RX_FIFO_EMPTY_MASK) =3D=3D
+ XIIC_SR_RX_FIFO_EMPTY_MASK);
+
+ /*
+ * Read in byte from the Rx Fifo. If the Fifo reached
the
+ * programmed occupancy depth as programmed in the Rx
occupancy
+ * reg, this read access will un throttle the bus such
that
+ * the next byte is read from the IIC bus.
+ */
+ *BufferPtr++ =3D XIo_In8(BaseAddress +
XIIC_DRR_REG_OFFSET);
+ ByteCount--;
+ }
+
+ return ByteCount;
+}
+
+/**********************************************************************
*******/
+/**
+* Send data as a master on the IIC bus. This function sends the data
using
+* polled I/O and blocks until the data has been sent. It only supports
7 bit
+* addressing. The user is responsible for ensuring the bus is not busy
if
+* multiple masters are present on the bus.
+*
+* @param BaseAddress contains the base address of the IIC Device.
+* @param Address contains the 7 bit IIC address of the device to
send the
+* specified data to.
+* @param BufferPtr points to the data to be sent.
+* @param ByteCount is the number of bytes to be sent.
+* @param Option: XIIC_STOP =3D end with STOP condition,
XIIC_REPEATED_START
+* =3D don't end with STOP condition.
+*
+* @return The number of bytes sent.
+*
+* @note None.
+*
+***********************************************************************
*******/
+unsigned XIic_DynSend(u32 BaseAddress, u16 Address, u8 *BufferPtr,
+ u8 ByteCount, u8 Option)
+{
+ unsigned RemainingByteCount;
+ u32 StatusRegister;
+
+ /*
+ * Clear the latched interrupt status so that it will be updated
with
+ * the new state when it changes, this must be done after the
address
+ * is put in the FIFO
+ */
+ XIic_mClearIisr(BaseAddress, XIIC_INTR_TX_EMPTY_MASK |
+ XIIC_INTR_TX_ERROR_MASK |
XIIC_INTR_ARB_LOST_MASK);
+
+ /*
+ * Put the address into the Fifo to be sent and indicate that
the
+ * operation to be performed on the bus is a write operation.
Upon
+ * writing the address, a start condition is initiated. MSMS is
+ * automatically set to master when the address is written to
the Fifo.
+ * If MSMS was already set, then a re-start is sent prior to the
+ * address.
+ */
+ if(!(Address & XIIC_TX_DYN_STOP_MASK))
+ {
+
+ XIic_mDynSend7BitAddress(BaseAddress, Address,
+ XIIC_WRITE_OPERATION);
+ }
+ else
+ {
+ XIic_mDynSendStartStopAddress(BaseAddress, Address,
+ XIIC_WRITE_OPERATION);
+ }
+
+ /*
+ * Wait for the bus to go busy.
+ */
+ StatusRegister =3D XIo_In8(BaseAddress + XIIC_SR_REG_OFFSET);
+
+ while (( StatusRegister & XIIC_SR_BUS_BUSY_MASK) !=3D
XIIC_SR_BUS_BUSY_MASK)
+ {
+ StatusRegister =3D XIo_In8(BaseAddress +
XIIC_SR_REG_OFFSET);
+ }
+
+ /*
+ * Clear the latched interrupt status for the bus not busy bit
which
+ * must be done while the bus is busy.
+ */
+ XIic_mClearIisr(BaseAddress, XIIC_INTR_BNB_MASK);
+
+ /*
+ * Send the specified data to the device on the IIC bus
specified by the
+ * the address.
+ */
+ RemainingByteCount =3D DynSendData(BaseAddress, BufferPtr,
ByteCount,
+ Option);
+
+ /*
+ * The send is complete return the number of bytes that was
sent.
+ */
+ return ByteCount - RemainingByteCount;
+}
+
+/**********************************************************************
********
+*
+* Send the specified buffer to the device that has been previously
addressed
+* on the IIC bus. This function assumes that the 7 bit address has been
sent.
+*
+* @param BaseAddress contains the base address of the IIC Device.
+* @param BufferPtr points to the data to be sent.
+* @param ByteCount is the number of bytes to be sent.
+* @param Option: XIIC_STOP =3D end with STOP condition,
XIIC_REPEATED_START
+* =3D don't end with STOP condition.
+*
+* @return The number of bytes remaining to be sent.
+*
+* @note This function does not take advantage of the transmit Fifo
because
+* it is designed for minimal code space and complexity.
+*
+***********************************************************************
*******/
+static unsigned DynSendData(u32 BaseAddress, u8 *BufferPtr,
+ u8 ByteCount, u8 Option)
+{
+ u32 IntrStatus;
+
+ while (ByteCount > 0) {
+ /*
+ * Wait for the transmit to be empty before sending any
more
+ * data by polling the interrupt status register.
+ */
+ while (1) {
+ IntrStatus =3D XIIC_READ_IISR(BaseAddress);
+ if (IntrStatus & (XIIC_INTR_TX_ERROR_MASK |
+ XIIC_INTR_ARB_LOST_MASK |
+ XIIC_INTR_BNB_MASK)) {
+ /*
+ * Error condition (NACK or ARB Lost or
BNB
+ * Error Has occurred. Clear the Control
+ * register to send a STOP condition on
the Bus
+ * and return the number of bytes still
to
+ * transmit.
+ */
+
+ XIo_Out8(BaseAddress +
XIIC_CR_REG_OFFSET,
+ 0x03);
+ XIo_Out8(BaseAddress +
XIIC_CR_REG_OFFSET,
+ 0x01);
+
+ return ByteCount;
+ }
+
+ /*
+ * Check for the transmit Fifo to become Empty.
+ */
+ if (IntrStatus & XIIC_INTR_TX_EMPTY_MASK) {
+ break;
+ }
+ }
+
+ /*
+ * Send data to Tx Fifo. If a stop condition is
specified and
+ * the last byte is being sent, then set the dynamic
stop bit.
+ */
+ if ((ByteCount =3D=3D 1) && (Option =3D=3D XIIC_STOP)) {
+ /*
+ * The MSMS will be cleared automatically upon
setting
+ * dynamic stop.
+ */
+ XIo_Out16(BaseAddress + XIIC_DTR_REG_OFFSET - 1,
+ XIIC_TX_DYN_STOP_MASK |
*BufferPtr++);
+ }
+ else {
+ XIo_Out8(BaseAddress + XIIC_DTR_REG_OFFSET,
+
*BufferPtr++);
+ }
+
+ /*
+ * Update the byte count to reflect the byte sent.
+ */
+ ByteCount--;
+ }
+
+ if (Option =3D=3D XIIC_STOP) {
+ /*
+ * If the Option is to release the bus after
transmission of
+ * data, Wait for the bus to transition to not busy
before
+ * returning, the IIC device cannot be disabled until
this
+ * occurs.
+ */
+ while (1) {
+ if (XIIC_READ_IISR(BaseAddress) &
XIIC_INTR_BNB_MASK) {
+ break;
+ }
+ }
+ }
+
+ return ByteCount;
+}
+
+/**********************************************************************
********
+*
+* Initialize the IIC core for Dynamic Functionality.
+*
+* @param BaseAddress contains the base address of the IIC Device.
+*
+* @return XST_SUCCESS if Successful else XST_FAILURE.
+*
+* @note None.
+*
+***********************************************************************
*******/
+int XIic_DynInit(u32 BaseAddress)
+{
+ u8 Status;
+
+ /*
+ * Reset IIC Core.
+ */
+ XIIC_RESET(BaseAddress);
+
+ /*
+ * Set receive Fifo depth to maximum (zero based).
+ */
+ XIo_Out8(BaseAddress + XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
+
+ /*
+ * Reset Tx Fifo.
+ */
+ XIo_Out8(BaseAddress + XIIC_CR_REG_OFFSET,
XIIC_CR_TX_FIFO_RESET_MASK);
+
+ /*
+ * Enable IIC Device, remove Tx Fifo reset & disable general call.
+ */
+ XIo_Out8(BaseAddress + XIIC_CR_REG_OFFSET,
XIIC_CR_ENABLE_DEVICE_MASK);
+
+ /*
+ * Read status register and verify IIC Device is in initial state.
Only the
+ * Tx Fifo and Rx Fifo empty bits should be set.
+ */
+ Status =3D XIo_In8(BaseAddress + XIIC_SR_REG_OFFSET);
+ if(Status =3D=3D (XIIC_SR_RX_FIFO_EMPTY_MASK |
XIIC_SR_TX_FIFO_EMPTY_MASK))
+ {
+ return XST_SUCCESS;
+ }
+
+ return XST_FAILURE;
+}
+
diff --git a/drivers/net/xilinx_lltemac/xlltemac_main.c
b/drivers/net/xilinx_lltemac/xlltemac_main.c
index fb1ab28..11bcb48 100644
--- a/drivers/net/xilinx_lltemac/xlltemac_main.c
+++ b/drivers/net/xilinx_lltemac/xlltemac_main.c
@@ -623,27 +623,27 @@ int renegotiate_speed(struct net_device *dev, int
speed, DUPLEX duplex)
return -1;
}
=20
-// #define XILINX_PLB_TEMAC_3_00A_ML403_PHY_SUPPORT
+#define MARVELL_88E1111_PHY
/*
* This function sets up MAC's speed according to link speed of PHY
- * This function is specific to MARVELL 88E1111 PHY chip on Xilinx
ML403
- * board and assumes GMII interface is being used by the TEMAC
+ * This function is specific to MARVELL 88E1111 PHY chip on many Xilinx
+ * boards and assumes GMII interface is being used by the TEMAC
*/
void set_mac_speed(struct net_local *lp)
{
u16 phylinkspeed;
struct net_device *dev =3D lp->ndev;
- int ret;
=20
-#ifndef XILINX_PLB_TEMAC_3_00A_ML403_PHY_SUPPORT
+#ifndef MARVELL_88E1111_PHY
+ int ret;
int retry_count =3D 1;
#endif
=20
/*
- * See comments at top for an explanation of
- * XILINX_PLB_TEMAC_3_00A_ML403_PHY_SUPPORT
+ * See comments at top for an explanation of=20
+ * #undef MARVELL_88E1111_PHY
*/
-#ifdef XILINX_PLB_TEMAC_3_00A_ML403_PHY_SUPPORT
+#ifdef MARVELL_88E1111_PHY
#define MARVELL_88E1111_PHY_SPECIFIC_STATUS_REG_OFFSET 17
#define MARVELL_88E1111_LINKSPEED_MARK 0xC000
#define MARVELL_88E1111_LINKSPEED_SHIFT 14
@@ -687,7 +687,8 @@ void set_mac_speed(struct net_local *lp)
break;
}
=20
-#else
+#else /* generic PHY, there have been issues with 10Mbit with this
code */
+
if (XLlTemac_GetPhysicalInterface(&lp->Emac) =3D=3D
XTE_PHY_TYPE_MII) {
phylinkspeed =3D 100;
}
@@ -881,6 +882,7 @@ static void poll_gmii(unsigned long data)
netif_carrier =3D netif_carrier_ok(dev) !=3D 0;
if (phy_carrier !=3D netif_carrier) {
if (phy_carrier) {
+ set_mac_speed(lp);
printk(KERN_INFO
"%s: XLlTemac: PHY Link carrier
restored.\n",
dev->name);
@@ -1015,7 +1017,7 @@ static irqreturn_t xenet_dma_rx_interrupt(int irq,
void *dev_id)
struct net_local *lp =3D (struct net_local *) dev->priv;
struct list_head *cur_lp;
=20
- unsigned int flags;
+ unsigned long flags;
=20
/* Read pending interrupts */
irq_status =3D XLlDma_mBdRingGetIrq(&lp->Dma.RxBdRing);
@@ -1026,7 +1028,6 @@ static irqreturn_t xenet_dma_rx_interrupt(int irq,
void *dev_id)
XLlDma_Reset(&lp->Dma);
return IRQ_HANDLED;
}
-
if ((irq_status & (XLLDMA_IRQ_DELAY_MASK |
XLLDMA_IRQ_COALESCE_MASK))) {
spin_lock_irqsave(&receivedQueueSpin, flags);
list_for_each(cur_lp, &receivedQueue) {
@@ -1052,7 +1053,7 @@ static irqreturn_t xenet_dma_tx_interrupt(int irq,
void *dev_id)
struct net_local *lp =3D (struct net_local *) dev->priv;
struct list_head *cur_lp;
=20
- unsigned int flags;
+ unsigned long flags;
=20
/* Read pending interrupts */
irq_status =3D XLlDma_mBdRingGetIrq(&(lp->Dma.TxBdRing));
@@ -1401,7 +1402,7 @@ static void FifoSendHandler(struct net_device
*dev)
{
struct net_local *lp;
struct sk_buff *skb;
- unsigned int flags;
+ unsigned long flags;
=20
spin_lock_irqsave(&XTE_tx_spinlock, flags);
lp =3D (struct net_local *) dev->priv;
@@ -2979,7 +2980,7 @@ static int detect_phy(struct net_local *lp, char
*dev_name)
printk(KERN_WARNING "XTemac: No PHY detected. Assuming a PHY at
address 0\n");
return 0; /* default to zero */
}
-
+extern bd_t __res;
=20
/** Shared device initialization code */
static int xtenet_setup(
@@ -3047,8 +3048,10 @@ static int xtenet_setup(
goto error;
}
=20
- /* Set the MAC address */
- memcpy(ndev->dev_addr, pdata->mac_addr, 6);
+ /* Set the MAC address from the iic eeprom info in the board
data */
+ memcpy(ndev->dev_addr, ((bd_t *) &__res)->bi_enetaddr, 6);
+ memcpy(pdata->mac_addr, ((bd_t *) &__res)->bi_enetaddr, 6);
+
if (_XLlTemac_SetMacAddress(&lp->Emac, ndev->dev_addr) !=3D
XST_SUCCESS) {
/* should not fail right after an initialize */
dev_err(dev, "XLlTemac: could not set MAC address.\n");
@@ -3072,17 +3075,20 @@ static int xtenet_setup(
=20
dev_err(dev, "XLlTemac: using DMA mode.\n");
=20
-#ifndef XDCRIO_H
- virt_baddr =3D (u32) ioremap(pdata->ll_dev_baseaddress,
4096);
- if (0 =3D=3D virt_baddr) {
- dev_err(dev,
- "XLlTemac: Could not allocate iomem for
local link connected device.\n");
- rc =3D -EIO;
- goto error;
+ if (pdata->dcr_host) {
+ printk("XLlTemac: DCR address: 0x%0x\n",
pdata->ll_dev_baseaddress);
+ XLlDma_Initialize(&lp->Dma,
pdata->ll_dev_baseaddress);
+ } else {
+ virt_baddr =3D (u32)
ioremap(pdata->ll_dev_baseaddress, 4096);
+ if (0 =3D=3D virt_baddr) {
+ dev_err(dev,
+ "XLlTemac: Could not allocate
iomem for local link connected device.\n");
+ rc =3D -EIO;
+ goto error;
+ }
+ printk("XLlTemac: Dma base address: phy: 0x%x,
virt: 0x%x\n", pdata->ll_dev_baseaddress, virt_baddr);
+ XLlDma_Initialize(&lp->Dma, virt_baddr);
}
-#endif
- printk("XLlTemac: Dma base address: phy: 0x%x, virt:
0x%x\n", pdata->ll_dev_baseaddress, virt_baddr);
- XLlDma_Initialize(&lp->Dma, virt_baddr);
=20
=20
ndev->hard_start_xmit =3D xenet_DmaSend;
--=20
1.5.2.1
^ permalink raw reply related
* FW: [PATCH] Xilinx: BSP: Updated ML405 to match hardware used for testing
From: John Linn @ 2008-02-27 23:15 UTC (permalink / raw)
To: linuxppc-dev, git-dev
The default config file for the ML405 and the xparameters*.h file
were updated to match the hardware used for testing. The platform
data in virtex_devices.c was updated for the LL TEMAC driver
which now uses the dcr_host field to determine if it should use
DCR for the DMA.
Signed-off-by: John Linn <john.linn>
---
arch/ppc/configs/ml405_defconfig | 130 +++--
.../platforms/4xx/xparameters/xparameters_ml405.h | 649
+++++++++-----------
arch/ppc/syslib/virtex_devices.c | 2 +-
3 files changed, 373 insertions(+), 408 deletions(-)
mode change 100644 =3D> 100755
arch/ppc/platforms/4xx/xparameters/xparameters_ml405.h
diff --git a/arch/ppc/configs/ml405_defconfig
b/arch/ppc/configs/ml405_defconfig
index feebe65..e5635cb 100644
--- a/arch/ppc/configs/ml405_defconfig
+++ b/arch/ppc/configs/ml405_defconfig
@@ -1,8 +1,9 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.23xlnx
-# Mon Dec 17 15:41:58 2007
+# Linux kernel version: 2.6.24-rc8-xlnx
+# Tue Feb 26 15:08:13 2008
#
+CONFIG_WORD_SIZE=3D32
CONFIG_MMU=3Dy
CONFIG_GENERIC_HARDIRQS=3Dy
CONFIG_RWSEM_XCHGADD_ALGORITHM=3Dy
@@ -35,9 +36,14 @@ CONFIG_BSD_PROCESS_ACCT=3Dy
CONFIG_BSD_PROCESS_ACCT_V3=3Dy
# CONFIG_TASKSTATS is not set
# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=3D14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=3Dy
+CONFIG_FAIR_USER_SCHED=3Dy
+# CONFIG_FAIR_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=3Dy
# CONFIG_RELAY is not set
CONFIG_BLK_DEV_INITRD=3Dy
@@ -64,6 +70,7 @@ CONFIG_VM_EVENT_COUNTERS=3Dy
CONFIG_SLAB=3Dy
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
+CONFIG_SLABINFO=3Dy
CONFIG_RT_MUTEXES=3Dy
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=3D0
@@ -157,6 +164,7 @@ CONFIG_FLATMEM_MANUAL=3Dy
CONFIG_FLATMEM=3Dy
CONFIG_FLAT_NODE_MEM_MAP=3Dy
# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_SPLIT_PTLOCK_CPUS=3D4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=3D1
@@ -165,10 +173,7 @@ CONFIG_VIRT_TO_BUS=3Dy
CONFIG_BINFMT_ELF=3Dy
# CONFIG_BINFMT_MISC is not set
CONFIG_CMDLINE_BOOL=3Dy
-CONFIG_CMDLINE=3D"console=3DttyS0,9600 ip=3Ddhcp root=3D/dev/nfs rw"
-# CONFIG_PM is not set
-CONFIG_SUSPEND_UP_POSSIBLE=3Dy
-CONFIG_HIBERNATION_UP_POSSIBLE=3Dy
+CONFIG_CMDLINE=3D"console=3DttyS0,9600 ip=3Don root=3D/dev/ram"
CONFIG_SECCOMP=3Dy
CONFIG_ISA_DMA_API=3Dy
=20
@@ -181,10 +186,6 @@ CONFIG_ZONE_DMA=3Dy
# CONFIG_PCI_DOMAINS is not set
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
# CONFIG_PCCARD is not set
=20
#
@@ -239,6 +240,7 @@ CONFIG_IP_PNP_DHCP=3Dy
CONFIG_INET_XFRM_MODE_TRANSPORT=3Dy
CONFIG_INET_XFRM_MODE_TUNNEL=3Dy
CONFIG_INET_XFRM_MODE_BEET=3Dy
+# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=3Dy
CONFIG_INET_TCP_DIAG=3Dy
# CONFIG_TCP_CONG_ADVANCED is not set
@@ -264,10 +266,6 @@ CONFIG_DEFAULT_TCP_CONG=3D"cubic"
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
# CONFIG_NET_SCHED is not set
=20
#
@@ -296,6 +294,7 @@ CONFIG_DEFAULT_TCP_CONG=3D"cubic"
#
# Generic Driver Options
#
+CONFIG_UEVENT_HELPER_PATH=3D"/sbin/hotplug"
CONFIG_STANDALONE=3Dy
CONFIG_PREVENT_FIRMWARE_BUILD=3Dy
# CONFIG_FW_LOADER is not set
@@ -321,6 +320,7 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=3D1024
CONFIG_MISC_DEVICES=3Dy
# CONFIG_EEPROM_93CX6 is not set
CONFIG_XILINX_DRIVERS=3Dy
+CONFIG_NEED_XILINX_LLDMA=3Dy
CONFIG_NEED_XILINX_IPIF=3Dy
# CONFIG_IDE is not set
=20
@@ -341,15 +341,21 @@ CONFIG_NETDEVICES=3Dy
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
CONFIG_TUN=3Dy
+# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=3Dy
# CONFIG_MII is not set
# CONFIG_IBM_EMAC is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
CONFIG_XILINX_EMAC=3Dy
# CONFIG_XILINX_EMACLITE is not set
CONFIG_NETDEV_1000=3Dy
# CONFIG_XILINX_TEMAC is not set
-# CONFIG_XILINX_LLTEMAC is not set
+CONFIG_XILINX_LLTEMAC=3Dy
CONFIG_NETDEV_10000=3Dy
=20
#
@@ -382,7 +388,6 @@ CONFIG_INPUT_MOUSEDEV=3Dy
CONFIG_INPUT_MOUSEDEV_SCREEN_X=3D1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=3D768
# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
=20
@@ -423,13 +428,12 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=3D4
#
# Non-8250 serial port support
#
+# CONFIG_SERIAL_UARTLITE is not set
CONFIG_SERIAL_CORE=3Dy
CONFIG_SERIAL_CORE_CONSOLE=3Dy
-# CONFIG_SERIAL_XILINX_UARTLITE is not set
CONFIG_UNIX98_PTYS=3Dy
# CONFIG_LEGACY_PTYS is not set
# CONFIG_IPMI_HANDLER is not set
-# CONFIG_WATCHDOG is not set
CONFIG_HW_RANDOM=3Dm
# CONFIG_NVRAM is not set
# CONFIG_GEN_RTC is not set
@@ -438,7 +442,45 @@ CONFIG_HW_RANDOM=3Dm
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
-# CONFIG_I2C is not set
+CONFIG_I2C=3Dy
+CONFIG_I2C_BOARDINFO=3Dy
+CONFIG_I2C_CHARDEV=3Dy
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+CONFIG_XILINX_IIC=3Dy
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
=20
#
# SPI support
@@ -448,6 +490,13 @@ CONFIG_HW_RANDOM=3Dm
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=3Dy
+# CONFIG_SSB is not set
=20
#
# Multifunction device drivers
@@ -464,16 +513,15 @@ CONFIG_DAB=3Dy
#
# Graphics support
#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=3Dm
+# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
=20
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
-# CONFIG_VGASTATE is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=3Dm
-# CONFIG_FB is not set
-# CONFIG_FB_IBM_GXT4500 is not set
=20
#
# Console display driver support
@@ -487,6 +535,7 @@ CONFIG_DUMMY_CONSOLE=3Dy
CONFIG_HID_SUPPORT=3Dy
CONFIG_HID=3Dy
CONFIG_HID_DEBUG=3Dy
+# CONFIG_HIDRAW is not set
CONFIG_USB_SUPPORT=3Dy
# CONFIG_USB_ARCH_HAS_HCD is not set
# CONFIG_USB_ARCH_HAS_OHCI is not set
@@ -504,19 +553,6 @@ CONFIG_USB_SUPPORT=3Dy
# CONFIG_NEW_LEDS is not set
# CONFIG_EDAC is not set
# CONFIG_RTC_CLASS is not set
-
-#
-# DMA Engine support
-#
-# CONFIG_DMA_ENGINE is not set
-
-#
-# DMA Clients
-#
-
-#
-# DMA Devices
-#
CONFIG_XILINX_EDK=3Dy
=20
#
@@ -574,7 +610,6 @@ CONFIG_SYSFS=3Dy
CONFIG_TMPFS=3Dy
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=3Dy
# CONFIG_CONFIGFS_FS is not set
=20
#
@@ -593,10 +628,7 @@ CONFIG_RAMFS=3Dy
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=3Dy
CONFIG_NFS_FS=3Dy
CONFIG_NFS_V3=3Dy
# CONFIG_NFS_V3_ACL is not set
@@ -622,10 +654,6 @@ CONFIG_SUNRPC=3Dy
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=3Dy
-
-#
-# Native Language Support
-#
CONFIG_NLS=3Dy
CONFIG_NLS_DEFAULT=3D"iso8859-1"
CONFIG_NLS_CODEPAGE_437=3Dy
@@ -666,10 +694,6 @@ CONFIG_NLS_ISO8859_1=3Dy
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
CONFIG_NLS_UTF8=3Dy
-
-#
-# Distributed Lock Manager
-#
# CONFIG_DLM is not set
=20
#
@@ -690,12 +714,16 @@ CONFIG_PLIST=3Dy
CONFIG_HAS_IOMEM=3Dy
CONFIG_HAS_IOPORT=3Dy
CONFIG_HAS_DMA=3Dy
+CONFIG_INSTRUMENTATION=3Dy
# CONFIG_PROFILING is not set
+# CONFIG_KPROBES is not set
+# CONFIG_MARKERS is not set
=20
#
# Kernel hacking
#
CONFIG_PRINTK_TIME=3Dy
+CONFIG_ENABLE_WARN_DEPRECATED=3Dy
CONFIG_ENABLE_MUST_CHECK=3Dy
CONFIG_MAGIC_SYSRQ=3Dy
# CONFIG_UNUSED_SYMBOLS is not set
@@ -719,9 +747,12 @@ CONFIG_DEBUG_BUGVERBOSE=3Dy
CONFIG_DEBUG_INFO=3Dy
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
CONFIG_FORCED_INLINING=3Dy
+# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SAMPLES is not set
# CONFIG_KGDB is not set
# CONFIG_XMON is not set
# CONFIG_BDI_SWITCH is not set
@@ -732,4 +763,5 @@ CONFIG_FORCED_INLINING=3Dy
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml405.h
b/arch/ppc/platforms/4xx/xparameters/xparameters_ml405.h
old mode 100644
new mode 100755
index f1fabbd..bf41056
--- a/arch/ppc/platforms/4xx/xparameters/xparameters_ml405.h
+++ b/arch/ppc/platforms/4xx/xparameters/xparameters_ml405.h
@@ -1,358 +1,291 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by libgen.
-* Version: Xilinx EDK 9.2 EDK_Jm.16
-* DO NOT EDIT.
-*
-* Copyright (c) 2005 Xilinx, Inc. All rights reserved.
-*
-* Description: Driver parameters
-*
-*******************************************************************/
-
-
-/* Definitions for peripheral PLB_BRAM_IF_CNTLR_0 */
-#define XPAR_PLB_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000
-#define XPAR_PLB_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF
-
-
-/******************************************************************/
-
-
-/* Definitions for peripheral OPB_V20_0 */
-
-
-/* Definitions for peripheral OPB_EMC_0 */
-#define XPAR_OPB_EMC_0_MEM0_BASEADDR 0x20000000
-#define XPAR_OPB_EMC_0_MEM0_HIGHADDR 0x200FFFFF
-#define XPAR_OPB_EMC_0_MEM1_BASEADDR 0x28000000
-#define XPAR_OPB_EMC_0_MEM1_HIGHADDR 0x287FFFFF
-
-
-/* Definitions for peripheral OPB_AC97_CONTROLLER_REF_0 */
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
-
-
-/* Definitions for peripheral OPB_EMC_USB_0 */
-#define XPAR_OPB_EMC_USB_0_MEM0_BASEADDR 0xA5000000
-#define XPAR_OPB_EMC_USB_0_MEM0_HIGHADDR 0xA50000FF
-
-
-/* Definitions for peripheral PLB_DDR_0 */
-#define XPAR_PLB_DDR_0_MEM0_BASEADDR 0x00000000
-#define XPAR_PLB_DDR_0_MEM0_HIGHADDR 0x0FFFFFFF
-
-
-/******************************************************************/
-
-/* Definitions for driver EMAC */
-#define XPAR_XEMAC_NUM_INSTANCES 1
-
-/* Definitions for peripheral OPB_ETHERNET_0 */
-#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
-#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
-#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
-#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
-#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
-#define XPAR_OPB_ETHERNET_0_CAM_EXIST 0
-#define XPAR_OPB_ETHERNET_0_JUMBO_EXIST 0
-#define XPAR_OPB_ETHERNET_0_TX_DRE_TYPE 0
-#define XPAR_OPB_ETHERNET_0_RX_DRE_TYPE 0
-#define XPAR_OPB_ETHERNET_0_TX_INCLUDE_CSUM 0
-#define XPAR_OPB_ETHERNET_0_RX_INCLUDE_CSUM 0
-
-
-/******************************************************************/
-
-
-/* Canonical definitions for peripheral OPB_ETHERNET_0 */
-#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
-#define XPAR_EMAC_0_BASEADDR 0x60000000
-#define XPAR_EMAC_0_HIGHADDR 0x60003FFF
-#define XPAR_EMAC_0_ERR_COUNT_EXIST 1
-#define XPAR_EMAC_0_DMA_PRESENT 1
-#define XPAR_EMAC_0_MII_EXIST 1
-#define XPAR_EMAC_0_CAM_EXIST 0
-#define XPAR_EMAC_0_JUMBO_EXIST 0
-#define XPAR_EMAC_0_TX_DRE_TYPE 0
-#define XPAR_EMAC_0_RX_DRE_TYPE 0
-#define XPAR_EMAC_0_TX_INCLUDE_CSUM 0
-#define XPAR_EMAC_0_RX_INCLUDE_CSUM 0
-
-
-/******************************************************************/
-
-/* Definitions for driver UARTNS550 */
-#define XPAR_XUARTNS550_NUM_INSTANCES 1
-#define XPAR_XUARTNS550_CLOCK_HZ 100000000
-
-/* Definitions for peripheral OPB_UART16550_0 */
-#define XPAR_OPB_UART16550_0_DEVICE_ID 0
-#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
-#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
-
-
-/******************************************************************/
-
-
-/* Canonical definitions for peripheral OPB_UART16550_0 */
-#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
-#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
-#define XPAR_UARTNS550_0_BASEADDR 0xA0000000
-#define XPAR_UARTNS550_0_HIGHADDR 0xA0001FFF
-
-
-/******************************************************************/
-
-/* Definitions for driver GPIO */
-#define XPAR_XGPIO_NUM_INSTANCES 3
-
-/* Definitions for peripheral OPB_GPIO_0 */
-#define XPAR_OPB_GPIO_0_BASEADDR 0x90000000
-#define XPAR_OPB_GPIO_0_HIGHADDR 0x900001FF
-#define XPAR_OPB_GPIO_0_DEVICE_ID 0
-#define XPAR_OPB_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_OPB_GPIO_0_IS_DUAL 1
-
-
-/* Definitions for peripheral OPB_GPIO_EXP_HDR_0 */
-#define XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR 0x90001000
-#define XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR 0x900011FF
-#define XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID 1
-#define XPAR_OPB_GPIO_EXP_HDR_0_INTERRUPT_PRESENT 0
-#define XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL 1
-
-
-/* Definitions for peripheral OPB_GPIO_CHAR_LCD_0 */
-#define XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR 0x90002000
-#define XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR 0x900021FF
-#define XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID 2
-#define XPAR_OPB_GPIO_CHAR_LCD_0_INTERRUPT_PRESENT 0
-#define XPAR_OPB_GPIO_CHAR_LCD_0_IS_DUAL 0
-
-
-/******************************************************************/
-
-#define XPAR_XPS2_NUM_INSTANCES 2
-#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
-#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
-#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
-#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
-#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
-#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
-
-/******************************************************************/
-
-/* Definitions for driver IIC */
-#define XPAR_XIIC_NUM_INSTANCES 1
-
-/* Definitions for peripheral OPB_IIC_0 */
-#define XPAR_OPB_IIC_0_DEVICE_ID 0
-#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
-#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
-#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
-#define XPAR_OPB_IIC_0_GPO_WIDTH 1
-
-
-/******************************************************************/
-
-
-/* Canonical definitions for peripheral OPB_IIC_0 */
-#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
-#define XPAR_IIC_0_BASEADDR 0xA8000000
-#define XPAR_IIC_0_HIGHADDR 0xA80001FF
-#define XPAR_IIC_0_TEN_BIT_ADR 0
-#define XPAR_IIC_0_GPO_WIDTH 1
-
-
-/******************************************************************/
-
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 10
-#define XPAR_XINTC_HAS_IPR 1
-#define XPAR_XINTC_USE_DCR 0
-/* Definitions for driver INTC */
-#define XPAR_XINTC_NUM_INSTANCES 1
-
-/* Definitions for peripheral OPB_INTC_0 */
-#define XPAR_OPB_INTC_0_DEVICE_ID 0
-#define XPAR_OPB_INTC_0_BASEADDR 0xD1000FC0
-#define XPAR_OPB_INTC_0_HIGHADDR 0xD1000FDF
-#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000
-
-
-/******************************************************************/
-
-#define XPAR_INTC_SINGLE_BASEADDR 0xD1000FC0
-#define XPAR_INTC_SINGLE_HIGHADDR 0xD1000FDF
-#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
-#define XPAR_OPB_ETHERNET_0_IP2INTC_IRPT_MASK 0X000001
-#define XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 0
-#define XPAR_SYSTEM_USB_HPI_INT_MASK 0X000002
-#define XPAR_OPB_INTC_0_SYSTEM_USB_HPI_INT_INTR 1
-#define XPAR_MISC_LOGIC_0_PHY_MII_INT_MASK 0X000004
-#define XPAR_OPB_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 2
-#define XPAR_OPB_SYSACE_0_SYSACE_IRQ_MASK 0X000008
-#define XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 3
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_MASK 0X000010
-#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR
4
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_MASK 0X000020
-#define
XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 5
-#define XPAR_OPB_IIC_0_IP2INTC_IRPT_MASK 0X000040
-#define XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 6
-#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR2_MASK 0X000080
-#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 7
-#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR1_MASK 0X000100
-#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
-#define XPAR_OPB_UART16550_0_IP2INTC_IRPT_MASK 0X000200
-#define XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 9
-
-/******************************************************************/
-
-
-/* Canonical definitions for peripheral OPB_INTC_0 */
-#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
-#define XPAR_INTC_0_BASEADDR 0xD1000FC0
-#define XPAR_INTC_0_HIGHADDR 0xD1000FDF
-#define XPAR_INTC_0_KIND_OF_INTR 0
-
-#define XPAR_INTC_0_EMAC_0_VEC_ID
XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_SYSACE_0_VEC_ID
XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR
-#define XPAR_INTC_0_IIC_0_VEC_ID
XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_PS2_1_SYS_INTR2_VEC_ID
XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
-#define XPAR_INTC_0_PS2_0_SYS_INTR1_VEC_ID
XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
-#define XPAR_INTC_0_UARTNS550_0_VEC_ID
XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR
-
-#define XPAR_INTC_0_PS2_1_VEC_ID
XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
-#define XPAR_INTC_0_PS2_0_VEC_ID
XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
-
-/******************************************************************/
-
-/* Definitions for driver TFT_REF */
-#define XPAR_XTFT_NUM_INSTANCES 1
-
-/* Definitions for peripheral PLB_TFT_CNTLR_REF_0 */
-#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
-#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
-#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
-
-
-/******************************************************************/
-
-#define XPAR_XSYSACE_MEM_WIDTH 16
-/* Definitions for driver SYSACE */
-#define XPAR_XSYSACE_NUM_INSTANCES 1
-
-/* Definitions for peripheral OPB_SYSACE_0 */
-#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
-#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
-#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
-#define XPAR_OPB_SYSACE_0_MEM_WIDTH 16
-
-
-/******************************************************************/
-
-
-/* Canonical definitions for peripheral OPB_SYSACE_0 */
-#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID
-#define XPAR_SYSACE_0_BASEADDR 0xCF000000
-#define XPAR_SYSACE_0_HIGHADDR 0xCF0001FF
-#define XPAR_SYSACE_0_MEM_WIDTH 16
-
-
-/******************************************************************/
-
-#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
-
-/******************************************************************/
-
-#define XPAR_CPU_ID 0
-#define XPAR_PPC405_VIRTEX4_ID 0
-#define XPAR_PPC405_VIRTEX4_CORE_CLOCK_FREQ_HZ 300000000
-#define XPAR_PPC405_VIRTEX4_IDCR_BASEADDR 0x00000100
-#define XPAR_PPC405_VIRTEX4_IDCR_HIGHADDR 0x0000010F
-#define XPAR_PPC405_VIRTEX4_DISABLE_OPERAND_FORWARDING 1
-#define XPAR_PPC405_VIRTEX4_MMU_ENABLE 1
-#define XPAR_PPC405_VIRTEX4_DETERMINISTIC_MULT 0
-#define XPAR_PPC405_VIRTEX4_PLBSYNCBYPASS 1
-#define XPAR_PPC405_VIRTEX4_APU_CONTROL 0b1101111000000000
-#define XPAR_PPC405_VIRTEX4_APU_UDI_1 0b101000011000100110000011
-#define XPAR_PPC405_VIRTEX4_APU_UDI_2 0b101000111000100110000011
-#define XPAR_PPC405_VIRTEX4_APU_UDI_3 0b101001011000100111000011
-#define XPAR_PPC405_VIRTEX4_APU_UDI_4 0b101001111000100111000011
-#define XPAR_PPC405_VIRTEX4_APU_UDI_5 0b101010011000110000000011
-#define XPAR_PPC405_VIRTEX4_APU_UDI_6 0b101010111000110000000011
-#define XPAR_PPC405_VIRTEX4_APU_UDI_7 0b101011011000110001000011
-#define XPAR_PPC405_VIRTEX4_APU_UDI_8 0b101011111000110001000011
-#define XPAR_PPC405_VIRTEX4_PVR_HIGH 0b0000
-#define XPAR_PPC405_VIRTEX4_PVR_LOW 0b0000
-#define XPAR_PPC405_VIRTEX4_HW_VER "1.01.a"
-
-/******************************************************************/
-
-
-/******************************************************************/
-
-/* Cannonical Constant Names */
-
-/******************************************************************/
-
-#undef XPAR_UARTNS550_0_BASEADDR
-#define XPAR_UARTNS550_0_BASEADDR
(XPAR_OPB_UART16550_0_BASEADDR+0x1000)
-
-/******************************************************************/
-
-#define XPAR_GPIO_0_BASEADDR XPAR_OPB_GPIO_0_BASEADDR
-#define XPAR_GPIO_0_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR
-#define XPAR_GPIO_0_IS_DUAL XPAR_OPB_GPIO_0_IS_DUAL
-#define XPAR_GPIO_0_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_1_BASEADDR XPAR_OPB_GPIO_0_BASEADDR
-#define XPAR_GPIO_1_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR
-#define XPAR_GPIO_1_IS_DUAL XPAR_OPB_GPIO_0_IS_DUAL
-#define XPAR_GPIO_1_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID
-#define XPAR_GPIO_2_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR
-#define XPAR_GPIO_2_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR
-#define XPAR_GPIO_2_IS_DUAL XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL
-#define XPAR_GPIO_2_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID
-#define XPAR_GPIO_3_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR
-#define XPAR_GPIO_3_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR
-#define XPAR_GPIO_3_IS_DUAL XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL
-#define XPAR_GPIO_3_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID
-#define XPAR_GPIO_4_BASEADDR XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR
-#define XPAR_GPIO_4_HIGHADDR XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR
-#define XPAR_GPIO_4_IS_DUAL XPAR_OPB_GPIO_CHAR_LCD_0_IS_DUAL
-#define XPAR_GPIO_4_DEVICE_ID XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0
-#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0
-#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0
-#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1
-#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1
-#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1
-
-/******************************************************************/
-
-#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR
-
-/******************************************************************/
-
-#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
-#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
-#define XPAR_DDR_0_SIZE 0x4000000
-
-/******************************************************************/
-
-#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 1024
-#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 2047
-#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
-
-/******************************************************************/
-
-#define XPAR_PCI_0_CLOCK_FREQ_HZ 0
-
-/******************************************************************/
-
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by libgen.
+* Version: Xilinx EDK 10.1.1 EDK_K_SP1.1
+* DO NOT EDIT.
+*
+* Copyright (c) 2005 Xilinx, Inc. All rights reserved.=20
+*=20
+* Description: Driver parameters
+*
+*******************************************************************/
+
+#define STDIN_BASEADDRESS 0x83E00000
+#define STDOUT_BASEADDRESS 0x83E00000
+
+/******************************************************************/
+
+/* Definitions for peripheral XPS_BRAM_IF_CNTLR_1 */
+#define XPAR_XPS_BRAM_IF_CNTLR_1_BASEADDR 0xFFFFE000
+#define XPAR_XPS_BRAM_IF_CNTLR_1_HIGHADDR 0xFFFFFFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver UARTNS550 */
+#define XPAR_XUARTNS550_NUM_INSTANCES 1
+#define XPAR_XUARTNS550_CLOCK_HZ 100000000
+
+/* Definitions for peripheral RS232_UART */
+#define XPAR_RS232_UART_DEVICE_ID 0
+#define XPAR_RS232_UART_BASEADDR 0x83E00000
+#define XPAR_RS232_UART_HIGHADDR 0x83E0FFFF
+
+
+/******************************************************************/
+
+
+/* Canonical definitions for peripheral RS232_UART */
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
+#define XPAR_UARTNS550_0_DEVICE_ID XPAR_RS232_UART_DEVICE_ID
+#define XPAR_UARTNS550_0_BASEADDR 0x83E00000
+#define XPAR_UARTNS550_0_HIGHADDR 0x83E0FFFF
+#define XPAR_UARTNS550_0_SIO_CHAN -1
+
+
+/******************************************************************/
+
+/* Definitions for driver GPIO */
+#define XPAR_XGPIO_NUM_INSTANCES 1
+
+/* Definitions for peripheral LEDS_4BIT */
+#define XPAR_LEDS_4BIT_BASEADDR 0x81400000
+#define XPAR_LEDS_4BIT_HIGHADDR 0x8140FFFF
+#define XPAR_LEDS_4BIT_DEVICE_ID 0
+#define XPAR_LEDS_4BIT_INTERRUPT_PRESENT 1
+#define XPAR_LEDS_4BIT_IS_DUAL 0
+
+
+/******************************************************************/
+
+/* Definitions for driver IIC */
+#define XPAR_XIIC_NUM_INSTANCES 1
+
+/* Definitions for peripheral IIC_EEPROM */
+#define XPAR_IIC_EEPROM_DEVICE_ID 0
+#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
+#define XPAR_IIC_EEPROM_HIGHADDR 0x8160FFFF
+#define XPAR_IIC_EEPROM_TEN_BIT_ADR 0
+#define XPAR_IIC_EEPROM_GPO_WIDTH 1
+
+
+/******************************************************************/
+
+
+/* Canonical definitions for peripheral IIC_EEPROM */
+#define XPAR_IIC_0_DEVICE_ID XPAR_IIC_EEPROM_DEVICE_ID
+#define XPAR_IIC_0_BASEADDR 0x81600000
+#define XPAR_IIC_0_HIGHADDR 0x8160FFFF
+#define XPAR_IIC_0_TEN_BIT_ADR 0
+#define XPAR_IIC_0_GPO_WIDTH 1
+
+
+/******************************************************************/
+
+#define XPAR_XSYSACE_MEM_WIDTH 16
+/* Definitions for driver SYSACE */
+#define XPAR_XSYSACE_NUM_INSTANCES 1
+
+/* Definitions for peripheral SYSACE_COMPACTFLASH */
+#define XPAR_SYSACE_COMPACTFLASH_DEVICE_ID 0
+#define XPAR_SYSACE_COMPACTFLASH_BASEADDR 0x83600000
+#define XPAR_SYSACE_COMPACTFLASH_HIGHADDR 0x8360FFFF
+#define XPAR_SYSACE_COMPACTFLASH_MEM_WIDTH 16
+
+
+/******************************************************************/
+
+
+/* Canonical definitions for peripheral SYSACE_COMPACTFLASH */
+#define XPAR_SYSACE_0_DEVICE_ID XPAR_SYSACE_COMPACTFLASH_DEVICE_ID
+#define XPAR_SYSACE_0_BASEADDR 0x83600000
+#define XPAR_SYSACE_0_HIGHADDR 0x8360FFFF
+#define XPAR_SYSACE_0_MEM_WIDTH 16
+
+/******************************************************************/
+
+/* Definitions for driver LLTEMAC */
+#define XPAR_XLLTEMAC_NUM_INSTANCES 1
+
+/* Definitions for peripheral TRIMODE_MAC_GMII Channel 0 */
+#define XPAR_TRIMODE_MAC_GMII_CHAN_0_DEVICE_ID 0
+#define XPAR_TRIMODE_MAC_GMII_CHAN_0_BASEADDR 0x81c00000
+#define XPAR_TRIMODE_MAC_GMII_CHAN_0_TXCSUM 0
+#define XPAR_TRIMODE_MAC_GMII_CHAN_0_RXCSUM 0
+#define XPAR_TRIMODE_MAC_GMII_CHAN_0_PHY_TYPE 1
+
+/* Canonical definitions for peripheral TRIMODE_MAC_GMII Channel 0 */
+#define XPAR_LLTEMAC_0_DEVICE_ID 0
+#define XPAR_LLTEMAC_0_BASEADDR 0x81c00000
+#define XPAR_LLTEMAC_0_TXCSUM 0
+#define XPAR_LLTEMAC_0_RXCSUM 0
+#define XPAR_LLTEMAC_0_PHY_TYPE 1
+#define XPAR_LLTEMAC_0_INTR 2
+
+
+/* LocalLink TYPE Enumerations */
+#define XPAR_LL_FIFO 1
+#define XPAR_LL_DMA 2
+
+
+/* Canonical LocalLink parameters for TRIMODE_MAC_GMII */
+#define XPAR_LLTEMAC_0_LLINK_CONNECTED_TYPE XPAR_LL_DMA
+#define XPAR_LLTEMAC_0_LLINK_CONNECTED_BASEADDR 0x84600100
+#define XPAR_LLTEMAC_0_LLINK_CONNECTED_FIFO_INTR 0xFF
+#define XPAR_LLTEMAC_0_LLINK_CONNECTED_DMARX_INTR 1
+#define XPAR_LLTEMAC_0_LLINK_CONNECTED_DMATX_INTR 0
+
+
+/******************************************************************/
+
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 7
+#define XPAR_XINTC_HAS_IPR 1
+#define XPAR_XINTC_USE_DCR 0
+/* Definitions for driver INTC */
+#define XPAR_XINTC_NUM_INSTANCES 1
+
+/* Definitions for peripheral XPS_INTC_0 */
+#define XPAR_XPS_INTC_0_DEVICE_ID 0
+#define XPAR_XPS_INTC_0_BASEADDR 0x81800000
+#define XPAR_XPS_INTC_0_HIGHADDR 0x8180FFFF
+#define XPAR_XPS_INTC_0_KIND_OF_INTR 0x00000000
+
+
+/******************************************************************/
+
+#define XPAR_INTC_SINGLE_BASEADDR 0x81800000
+#define XPAR_INTC_SINGLE_HIGHADDR 0x8180FFFF
+#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_XPS_INTC_0_DEVICE_ID
+#define XPAR_DDR_SDRAM_SDMA2_TX_INTOUT_MASK 0X000001
+#define XPAR_XPS_INTC_0_DDR_SDRAM_SDMA2_TX_INTOUT_INTR 0
+#define XPAR_DDR_SDRAM_SDMA2_RX_INTOUT_MASK 0X000002
+#define XPAR_XPS_INTC_0_DDR_SDRAM_SDMA2_RX_INTOUT_INTR 1
+#define XPAR_TRIMODE_MAC_GMII_TEMACINTC0_IRPT_MASK 0X000004
+#define XPAR_XPS_INTC_0_TRIMODE_MAC_GMII_TEMACINTC0_IRPT_INTR 2
+#define XPAR_SYSACE_COMPACTFLASH_SYSACE_IRQ_MASK 0X000008
+#define XPAR_XPS_INTC_0_SYSACE_COMPACTFLASH_SYSACE_IRQ_INTR 3
+#define XPAR_IIC_EEPROM_IIC2INTC_IRPT_MASK 0X000010
+#define XPAR_XPS_INTC_0_IIC_EEPROM_IIC2INTC_IRPT_INTR 4
+#define XPAR_LEDS_4BIT_IP2INTC_IRPT_MASK 0X000020
+#define XPAR_XPS_INTC_0_LEDS_4BIT_IP2INTC_IRPT_INTR 5
+#define XPAR_RS232_UART_IP2INTC_IRPT_MASK 0X000040
+#define XPAR_XPS_INTC_0_RS232_UART_IP2INTC_IRPT_INTR 6
+
+/******************************************************************/
+
+
+/* Canonical definitions for peripheral XPS_INTC_0 */
+#define XPAR_INTC_0_DEVICE_ID XPAR_XPS_INTC_0_DEVICE_ID
+#define XPAR_INTC_0_BASEADDR 0x81800000
+#define XPAR_INTC_0_HIGHADDR 0x8180FFFF
+#define XPAR_INTC_0_KIND_OF_INTR 0x00000000
+
+#define XPAR_INTC_0_MPMC_0_SDMA2_TX_INTOUT_VEC_ID
XPAR_XPS_INTC_0_DDR_SDRAM_SDMA2_TX_INTOUT_INTR
+#define XPAR_INTC_0_MPMC_0_SDMA2_RX_INTOUT_VEC_ID
XPAR_XPS_INTC_0_DDR_SDRAM_SDMA2_RX_INTOUT_INTR
+#define XPAR_INTC_0_LLTEMAC_0_VEC_ID
XPAR_XPS_INTC_0_TRIMODE_MAC_GMII_TEMACINTC0_IRPT_INTR
+#define XPAR_INTC_0_SYSACE_0_VEC_ID
XPAR_XPS_INTC_0_SYSACE_COMPACTFLASH_SYSACE_IRQ_INTR
+#define XPAR_INTC_0_IIC_0_VEC_ID
XPAR_XPS_INTC_0_IIC_EEPROM_IIC2INTC_IRPT_INTR
+#define XPAR_INTC_0_GPIO_0_VEC_ID
XPAR_XPS_INTC_0_LEDS_4BIT_IP2INTC_IRPT_INTR
+#define XPAR_INTC_0_UARTNS550_0_VEC_ID
XPAR_XPS_INTC_0_RS232_UART_IP2INTC_IRPT_INTR
+
+/******************************************************************/
+
+/* Definitions for driver MPMC */
+#define XPAR_XMPMC_NUM_INSTANCES 1
+
+/* Definitions for peripheral DDR_SDRAM */
+#define XPAR_DDR_SDRAM_DEVICE_ID 0
+#define XPAR_DDR_SDRAM_MPMC_BASEADDR 0x00000000
+#define XPAR_DDR_SDRAM_MPMC_CTRL_BASEADDR 0xFFFFFFFF
+#define XPAR_DDR_SDRAM_INCLUDE_ECC_SUPPORT 0
+#define XPAR_DDR_SDRAM_USE_STATIC_PHY 0
+#define XPAR_DDR_SDRAM_PM_ENABLE 0
+#define XPAR_DDR_SDRAM_NUM_PORTS 3
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral DDR_SDRAM */
+#define XPAR_DDR_SDRAM_MPMC_BASEADDR 0x00000000
+#define XPAR_DDR_SDRAM_MPMC_HIGHADDR 0x07FFFFFF
+#define XPAR_DDR_SDRAM_SDMA_CTRL_BASEADDR 0x84600000
+#define XPAR_DDR_SDRAM_SDMA_CTRL_HIGHADDR 0x8460FFFF
+
+
+/******************************************************************/
+
+
+/* Canonical definitions for peripheral DDR_SDRAM */
+#define XPAR_MPMC_0_DEVICE_ID XPAR_DDR_SDRAM_DEVICE_ID
+#define XPAR_MPMC_0_MPMC_BASEADDR 0x00000000
+#define XPAR_MPMC_0_MPMC_CTRL_BASEADDR 0xFFFFFFFF
+#define XPAR_MPMC_0_INCLUDE_ECC_SUPPORT 0
+#define XPAR_MPMC_0_USE_STATIC_PHY 0
+#define XPAR_MPMC_0_PM_ENABLE 0
+#define XPAR_MPMC_0_NUM_PORTS 3
+
+
+
+/******************************************************************/
+
+#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
+
+/******************************************************************/
+
+#define XPAR_CPU_ID 0
+#define XPAR_PPC405_VIRTEX4_ID 0
+#define XPAR_PPC405_VIRTEX4_CORE_CLOCK_FREQ_HZ 300000000
+#define XPAR_PPC405_VIRTEX4_DPLB0_DWIDTH 64
+#define XPAR_PPC405_VIRTEX4_DPLB0_NATIVE_DWIDTH 64
+#define XPAR_PPC405_VIRTEX4_IPLB0_DWIDTH 64
+#define XPAR_PPC405_VIRTEX4_IPLB0_NATIVE_DWIDTH 64
+#define XPAR_PPC405_VIRTEX4_DPLB1_DWIDTH 64
+#define XPAR_PPC405_VIRTEX4_DPLB1_NATIVE_DWIDTH 64
+#define XPAR_PPC405_VIRTEX4_IPLB1_DWIDTH 64
+#define XPAR_PPC405_VIRTEX4_IPLB1_NATIVE_DWIDTH 64
+#define XPAR_PPC405_VIRTEX4_DPLB1_ADDR_BASE 0x00000000
+#define XPAR_PPC405_VIRTEX4_DPLB1_ADDR_HIGH 0x07ffffff
+#define XPAR_PPC405_VIRTEX4_IPLB1_ADDR_BASE 0x00000000
+#define XPAR_PPC405_VIRTEX4_IPLB1_ADDR_HIGH 0x07ffffff
+#define XPAR_PPC405_VIRTEX4_FASTEST_PLB_CLOCK DPLB0
+#define XPAR_PPC405_VIRTEX4_GENERATE_PLB_TIMESPECS 1
+#define XPAR_PPC405_VIRTEX4_DPLB0_P2P 0
+#define XPAR_PPC405_VIRTEX4_DPLB1_P2P 1
+#define XPAR_PPC405_VIRTEX4_IPLB0_P2P 0
+#define XPAR_PPC405_VIRTEX4_IPLB1_P2P 1
+#define XPAR_PPC405_VIRTEX4_IDCR_BASEADDR 0x00000100
+#define XPAR_PPC405_VIRTEX4_IDCR_HIGHADDR 0x000001FF
+#define XPAR_PPC405_VIRTEX4_DISABLE_OPERAND_FORWARDING 1
+#define XPAR_PPC405_VIRTEX4_MMU_ENABLE 1
+#define XPAR_PPC405_VIRTEX4_DETERMINISTIC_MULT 0
+#define XPAR_PPC405_VIRTEX4_PLBSYNCBYPASS 1
+#define XPAR_PPC405_VIRTEX4_APU_CONTROL 0b1101111000000000
+#define XPAR_PPC405_VIRTEX4_APU_UDI_1 0b101000011000100110000011
+#define XPAR_PPC405_VIRTEX4_APU_UDI_2 0b101000111000100110000011
+#define XPAR_PPC405_VIRTEX4_APU_UDI_3 0b101001011000100111000011
+#define XPAR_PPC405_VIRTEX4_APU_UDI_4 0b101001111000100111000011
+#define XPAR_PPC405_VIRTEX4_APU_UDI_5 0b101010011000110000000011
+#define XPAR_PPC405_VIRTEX4_APU_UDI_6 0b101010111000110000000011
+#define XPAR_PPC405_VIRTEX4_APU_UDI_7 0b101011011000110001000011
+#define XPAR_PPC405_VIRTEX4_APU_UDI_8 0b101011111000110001000011
+#define XPAR_PPC405_VIRTEX4_PVR_HIGH 0b0000
+#define XPAR_PPC405_VIRTEX4_PVR_LOW 0b0000
+#define XPAR_PPC405_VIRTEX4_HW_VER "2.01.a"
+
+/******************************************************************/
+
+#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
+#define XPAR_DDR_0_SIZE 0x4000000
+
+/******************************************************************/
+
+#define XPAR_PCI_0_CLOCK_FREQ_HZ 0
+
+/******************************************************************/
+
+#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0
+#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 1024
+#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
diff --git a/arch/ppc/syslib/virtex_devices.c
b/arch/ppc/syslib/virtex_devices.c
index cdfc062..addf58a 100644
--- a/arch/ppc/syslib/virtex_devices.c
+++ b/arch/ppc/syslib/virtex_devices.c
@@ -219,7 +219,7 @@
.tx_csum =3D XPAR_LLTEMAC_##num##_TXCSUM, \
.rx_csum =3D XPAR_LLTEMAC_##num##_RXCSUM, \
.phy_type =3D XPAR_LLTEMAC_##num##_PHY_TYPE, \
- .dcr_host =3D 0xff, \
+ .dcr_host =3D 0x00, \
.ll_dev_type =3D
XPAR_LLTEMAC_##num##_LLINK_CONNECTED_TYPE, \
.ll_dev_baseaddress =3D
XPAR_LLTEMAC_##num##_LLINK_CONNECTED_BASEADDR, \
.ll_dev_dma_rx_irq =3D
XPAR_LLTEMAC_##num##_LLINK_CONNECTED_DMARX_INTR, \
--=20
1.5.2.1
^ permalink raw reply related
* Re: FW: [PATCH] Xilinx: LL TEMAC/Bootstrap: Updated driver and bootstrap to pull mac addr from eeprom
From: Stephen Rothwell @ 2008-02-28 0:00 UTC (permalink / raw)
To: John Linn; +Cc: linuxppc-dev, git-dev
In-Reply-To: <20080227231452.DD4124507B7@mail190-dub.bigfish.com>
[-- Attachment #1: Type: text/plain, Size: 670 bytes --]
Hi John,
On Wed, 27 Feb 2008 16:14:50 -0700 "John Linn" <John.Linn@xilinx.com> wrote:
>
> The LL TEMAC driver was updated to use the mac address from the board
> data,
> to use the Marvell specific PHY code so that 10 Mbit works, and to use
> the
> dcr_host from the platform data rather than using conditional
> compilation
> for DCR with DMA. The bootstrap loader was changed to read the mac
> address
> from the eeprom into the board data.
>
> Signed-off-by: John Linn <john.linn@xilinx.com>
This patch was badly wrapped by something ...
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: FW: [PATCH] Xilinx: BSP: Updated ML405 to match hardware used for testing
From: Stephen Rothwell @ 2008-02-28 0:01 UTC (permalink / raw)
To: John Linn; +Cc: linuxppc-dev, git-dev
In-Reply-To: <20080227231521.4673DE3006A@mail124-dub.bigfish.com>
[-- Attachment #1: Type: text/plain, Size: 569 bytes --]
Hi John,
n Wed, 27 Feb 2008 16:15:18 -0700 "John Linn" <John.Linn@xilinx.com> wrote:
>
> The default config file for the ML405 and the xparameters*.h file
> were updated to match the hardware used for testing. The platform
> data in virtex_devices.c was updated for the LL TEMAC driver
> which now uses the dcr_host field to determine if it should use
> DCR for the DMA.
>
> Signed-off-by: John Linn <john.linn>
This was badly wrapped as well.
--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* [patch 4/6] ARM: move bridge enable out of pcibios_enable_resources()
From: Bjorn Helgaas @ 2008-02-28 0:04 UTC (permalink / raw)
To: linux-pci, linux-arch
Cc: Chris Zankel, Grant Grundler, linux-parisc, Matthew Wilcox,
Kyle McMartin, linuxppc-dev, Paul Mackerras, linux-arm-kernel,
Russell King
In-Reply-To: <20080228000437.880811124@ldl.fc.hp.com>
Move bridge enable from pcibios_enable_resources() to
platform_pci_enable_device() so the former matches other
architectures and can be shared.
Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Index: work6/arch/arm/kernel/bios32.c
===================================================================
--- work6.orig/arch/arm/kernel/bios32.c 2008-02-27 11:25:29.000000000 -0700
+++ work6/arch/arm/kernel/bios32.c 2008-02-27 11:55:59.000000000 -0700
@@ -683,15 +683,32 @@
cmd |= PCI_COMMAND_MEMORY;
}
+ if (cmd != old_cmd) {
+ printk("PCI: enabling device %s (%04x -> %04x)\n",
+ pci_name(dev), old_cmd, cmd);
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+ }
+ return 0;
+}
+
+static int platform_pci_enable_device(struct pci_dev *dev)
+{
+ u16 cmd, old_cmd;
+
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ old_cmd = cmd;
+
/*
- * Bridges (eg, cardbus bridges) need to be fully enabled
+ * Bridges (eg, cardbus bridges) need to be fully enabled.
+ * Most architectures do this in pci_enable_bridges(), not
+ * in the pci_enable_device() path.
*/
if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
if (cmd != old_cmd) {
- printk("PCI: enabling device %s (%04x -> %04x)\n",
- pci_name(dev), old_cmd, cmd);
+ dev_info(&dev->dev, "enabling bridge device (%04x -> %04x)\n",
+ old_cmd, cmd);
pci_write_config_word(dev, PCI_COMMAND, cmd);
}
return 0;
@@ -699,7 +716,12 @@
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
- return pcibios_enable_resources(dev, mask);
+ int err;
+
+ if ((err = pcibios_enable_resources(dev, mask)) < 0)
+ return err;
+
+ return platform_pci_enable_device(dev);
}
int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
--
^ permalink raw reply
* [patch 2/6] ppc: make pcibios_enable_device() use pcibios_enable_resources()
From: Bjorn Helgaas @ 2008-02-28 0:04 UTC (permalink / raw)
To: linux-pci, linux-arch
Cc: Chris Zankel, Grant Grundler, linux-parisc, Matthew Wilcox,
Kyle McMartin, linuxppc-dev, Paul Mackerras, linux-arm-kernel,
Russell King
In-Reply-To: <20080228000437.880811124@ldl.fc.hp.com>
pcibios_enable_device() has an almost verbatim copy of
pcibios_enable_resources(), (the only difference is that
pcibios_enable_resources() turns on PCI_COMMAND_MEMORY if
there's a ROM resource).
The duplication might be intentional, but I don't see any callers
of pcibios_enable_resources() on ppc, so I think it's more
likely a historical accident.
This patch removes the duplication, making pcibios_enable_device()
simply call pcibios_enable_resources() as x86 does.
Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Index: work6/arch/ppc/kernel/pci.c
===================================================================
--- work6.orig/arch/ppc/kernel/pci.c 2008-02-18 10:43:50.000000000 -0700
+++ work6/arch/ppc/kernel/pci.c 2008-02-18 11:31:23.000000000 -0700
@@ -785,33 +785,11 @@
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
if (ppc_md.pcibios_enable_device_hook)
if (ppc_md.pcibios_enable_device_hook(dev, 0))
return -EINVAL;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for (idx=0; idx<6; idx++) {
- r = &dev->resource[idx];
- if (r->flags & IORESOURCE_UNSET) {
- printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n",
- pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
+
+ return pcibios_enable_resources(dev, mask);
}
struct pci_controller*
--
^ permalink raw reply
* [patch 3/6] xtensa: make pcibios_enable_device() use pcibios_enable_resources()
From: Bjorn Helgaas @ 2008-02-28 0:04 UTC (permalink / raw)
To: linux-pci, linux-arch
Cc: Chris Zankel, Grant Grundler, linux-parisc, Matthew Wilcox,
Kyle McMartin, linuxppc-dev, Paul Mackerras, linux-arm-kernel,
Russell King
In-Reply-To: <20080228000437.880811124@ldl.fc.hp.com>
pcibios_enable_device() has an almost verbatim copy of
pcibios_enable_resources(), (the only difference is that
pcibios_enable_resources() turns on PCI_COMMAND_MEMORY if
there's a ROM resource).
The duplication might be intentional, but I don't see any callers
of pcibios_enable_resources() on xtensa, so I think it's more
likely a historical accident copied from ppc.
This patch removes the duplication, making pcibios_enable_device()
simply call pcibios_enable_resources() as x86 does.
Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Index: work6/arch/xtensa/kernel/pci.c
===================================================================
--- work6.orig/arch/xtensa/kernel/pci.c 2008-02-18 10:43:50.000000000 -0700
+++ work6/arch/xtensa/kernel/pci.c 2008-02-18 11:32:12.000000000 -0700
@@ -238,31 +238,7 @@
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for (idx=0; idx<6; idx++) {
- r = &dev->resource[idx];
- if (!r->start && r->end) {
- printk(KERN_ERR "PCI: Device %s not available because "
- "of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n",
- pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
-
- return 0;
+ return pcibios_enable_resources(dev, mask);
}
#ifdef CONFIG_PROC_FS
--
^ permalink raw reply
* [patch 1/6] PCI: split pcibios_enable_resources() out of pcibios_enable_device()
From: Bjorn Helgaas @ 2008-02-28 0:04 UTC (permalink / raw)
To: linux-pci, linux-arch
Cc: Chris Zankel, Grant Grundler, linux-parisc, Matthew Wilcox,
Kyle McMartin, linuxppc-dev, Paul Mackerras, linux-arm-kernel,
Russell King
In-Reply-To: <20080228000437.880811124@ldl.fc.hp.com>
On x86, pcibios_enable_device() is factored into
pcibios_enable_resources() and pcibios_enable_irq(). On several other
architectures, the functional equivalent of pcibios_enable_resources()
is expanded directly inside pcibios_enable_device().
This splits these pcibios_enable_device() implementations to make them
more similar to the x86 implementation.
There should be no functional change from this patch.
Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/alpha/kernel/pci.c | 8 +++++++-
arch/arm/kernel/bios32.c | 9 +++++++--
arch/parisc/kernel/pci.c | 6 +++++-
arch/powerpc/kernel/pci-common.c | 14 +++++++++-----
arch/sh/drivers/pci/pci.c | 7 ++++++-
arch/sparc64/kernel/pci.c | 7 ++++++-
arch/v850/kernel/rte_mb_a_pci.c | 7 ++++++-
7 files changed, 46 insertions(+), 12 deletions(-)
Index: work6/arch/alpha/kernel/pci.c
===================================================================
--- work6.orig/arch/alpha/kernel/pci.c 2008-02-18 10:43:50.000000000 -0700
+++ work6/arch/alpha/kernel/pci.c 2008-02-18 10:45:14.000000000 -0700
@@ -370,7 +370,7 @@
#endif
int
-pcibios_enable_device(struct pci_dev *dev, int mask)
+pcibios_enable_resources(struct pci_dev *dev, int mask)
{
u16 cmd, oldcmd;
int i;
@@ -396,6 +396,12 @@
return 0;
}
+int
+pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+ return pcibios_enable_resources(dev, mask);
+}
+
/*
* If we set up a device for bus mastering, we need to check the latency
* timer as certain firmware forgets to set it properly, as seen
Index: work6/arch/arm/kernel/bios32.c
===================================================================
--- work6.orig/arch/arm/kernel/bios32.c 2008-02-18 10:43:50.000000000 -0700
+++ work6/arch/arm/kernel/bios32.c 2008-02-18 10:45:14.000000000 -0700
@@ -655,10 +655,10 @@
}
/**
- * pcibios_enable_device - Enable I/O and memory.
+ * pcibios_enable_resources - Enable I/O and memory.
* @dev: PCI device to be enabled
*/
-int pcibios_enable_device(struct pci_dev *dev, int mask)
+int pcibios_enable_resources(struct pci_dev *dev, int mask)
{
u16 cmd, old_cmd;
int idx;
@@ -697,6 +697,11 @@
return 0;
}
+int pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+ return pcibios_enable_resources(dev, mask);
+}
+
int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
enum pci_mmap_state mmap_state, int write_combine)
{
Index: work6/arch/parisc/kernel/pci.c
===================================================================
--- work6.orig/arch/parisc/kernel/pci.c 2008-02-18 10:43:50.000000000 -0700
+++ work6/arch/parisc/kernel/pci.c 2008-02-18 10:45:14.000000000 -0700
@@ -285,7 +285,7 @@
* Drivers that do not need parity (eg graphics and possibly networking)
* can clear these bits if they want.
*/
-int pcibios_enable_device(struct pci_dev *dev, int mask)
+int pcibios_enable_resources(struct pci_dev *dev, int mask)
{
u16 cmd;
int idx;
@@ -317,6 +317,10 @@
return 0;
}
+int pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+ return pcibios_enable_resources(dev, mask);
+}
/* PA-RISC specific */
void pcibios_register_hba(struct pci_hba_data *hba)
Index: work6/arch/powerpc/kernel/pci-common.c
===================================================================
--- work6.orig/arch/powerpc/kernel/pci-common.c 2008-02-18 10:43:50.000000000 -0700
+++ work6/arch/powerpc/kernel/pci-common.c 2008-02-18 10:45:14.000000000 -0700
@@ -1153,16 +1153,12 @@
EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
#endif /* CONFIG_HOTPLUG */
-int pcibios_enable_device(struct pci_dev *dev, int mask)
+int pcibios_enable_resources(struct pci_dev *dev, int mask)
{
u16 cmd, old_cmd;
int idx;
struct resource *r;
- if (ppc_md.pcibios_enable_device_hook)
- if (ppc_md.pcibios_enable_device_hook(dev))
- return -EINVAL;
-
pci_read_config_word(dev, PCI_COMMAND, &cmd);
old_cmd = cmd;
for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
@@ -1193,3 +1189,11 @@
return 0;
}
+int pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+ if (ppc_md.pcibios_enable_device_hook)
+ if (ppc_md.pcibios_enable_device_hook(dev))
+ return -EINVAL;
+
+ return pcibios_enable_resources(dev, mask);
+}
Index: work6/arch/sh/drivers/pci/pci.c
===================================================================
--- work6.orig/arch/sh/drivers/pci/pci.c 2008-02-18 10:43:50.000000000 -0700
+++ work6/arch/sh/drivers/pci/pci.c 2008-02-18 10:45:14.000000000 -0700
@@ -131,7 +131,7 @@
}
}
-int pcibios_enable_device(struct pci_dev *dev, int mask)
+int pcibios_enable_resources(struct pci_dev *dev, int mask)
{
u16 cmd, old_cmd;
int idx;
@@ -163,6 +163,11 @@
return 0;
}
+int pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+ return pcibios_enable_resources(dev, mask);
+}
+
/*
* If we set up a device for bus mastering, we need to check and set
* the latency timer as it may not be properly set.
Index: work6/arch/sparc64/kernel/pci.c
===================================================================
--- work6.orig/arch/sparc64/kernel/pci.c 2008-02-18 10:43:50.000000000 -0700
+++ work6/arch/sparc64/kernel/pci.c 2008-02-18 10:45:14.000000000 -0700
@@ -946,7 +946,7 @@
{
}
-int pcibios_enable_device(struct pci_dev *dev, int mask)
+int pcibios_enable_resources(struct pci_dev *dev, int mask)
{
u16 cmd, oldcmd;
int i;
@@ -976,6 +976,11 @@
return 0;
}
+int pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+ return pcibios_enable_resources(dev, mask);
+}
+
void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
struct resource *res)
{
Index: work6/arch/v850/kernel/rte_mb_a_pci.c
===================================================================
--- work6.orig/arch/v850/kernel/rte_mb_a_pci.c 2008-02-18 10:43:50.000000000 -0700
+++ work6/arch/v850/kernel/rte_mb_a_pci.c 2008-02-18 10:45:14.000000000 -0700
@@ -217,7 +217,7 @@
}
\f
-int __nomods_init pcibios_enable_device (struct pci_dev *dev, int mask)
+int __nomods_init pcibios_enable_resources (struct pci_dev *dev, int mask)
{
u16 cmd, old_cmd;
int idx;
@@ -245,6 +245,11 @@
return 0;
}
+int __nomods_init pcibios_enable_device (struct pci_dev *dev, int mask)
+{
+ return pcibios_enable_resources(dev, mask);
+}
+
\f
/* Resource allocation. */
static void __devinit pcibios_assign_resources (void)
--
^ permalink raw reply
* [patch 5/6] PARISC: move PERR & SERR enables out of pcibios_enable_resources()
From: Bjorn Helgaas @ 2008-02-28 0:04 UTC (permalink / raw)
To: linux-pci, linux-arch
Cc: Chris Zankel, Grant Grundler, linux-parisc, Matthew Wilcox,
Kyle McMartin, linuxppc-dev, Paul Mackerras, linux-arm-kernel,
Russell King
In-Reply-To: <20080228000437.880811124@ldl.fc.hp.com>
Move PERR and SERR enables from pcibios_enable_resources() to
platform_pci_enable_device() so the former matches other
architectures and can be shared.
Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Index: work6/arch/parisc/kernel/pci.c
===================================================================
--- work6.orig/arch/parisc/kernel/pci.c 2008-02-27 11:30:02.000000000 -0700
+++ work6/arch/parisc/kernel/pci.c 2008-02-27 11:38:11.000000000 -0700
@@ -281,9 +281,7 @@
* A driver is enabling the device. We make sure that all the appropriate
* bits are set to allow the device to operate as the driver is expecting.
* We enable the port IO and memory IO bits if the device has any BARs of
- * that type, and we enable the PERR and SERR bits unconditionally.
- * Drivers that do not need parity (eg graphics and possibly networking)
- * can clear these bits if they want.
+ * that type.
*/
int pcibios_enable_resources(struct pci_dev *dev, int mask)
{
@@ -305,8 +303,6 @@
cmd |= PCI_COMMAND_MEMORY;
}
- cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
-
#if 0
/* If bridge/bus controller has FBB enabled, child must too. */
if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
@@ -317,9 +313,38 @@
return 0;
}
+/*
+ * A driver is enabling the device. We enable the PERR and SERR bits
+ * unconditionally. Drivers that do not need parity (eg graphics and
+ * possibly networking) can clear these bits if they want.
+ */
+static int platform_pci_enable_device(struct pci_dev *dev)
+{
+ u16 cmd, old_cmd;
+ int idx;
+
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ old_cmd = cmd;
+
+ cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
+
+ if (cmd != old_cmd) {
+ dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n",
+ old_cmd, cmd);
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+ }
+
+ return 0;
+}
+
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
- return pcibios_enable_resources(dev, mask);
+ int err;
+
+ if ((err = pcibios_enable_resources(dev, mask)) < 0)
+ return err;
+
+ return platform_pci_enable_device(dev);
}
/* PA-RISC specific */
--
^ permalink raw reply
* [patch 6/6] PCI: consolidate several pcibios_enable_resources() implementations
From: Bjorn Helgaas @ 2008-02-28 0:04 UTC (permalink / raw)
To: linux-pci, linux-arch
Cc: Chris Zankel, Grant Grundler, linux-parisc, Matthew Wilcox,
Kyle McMartin, linuxppc-dev, Paul Mackerras, linux-arm-kernel,
Russell King
In-Reply-To: <20080228000437.880811124@ldl.fc.hp.com>
There are many implementations of pcibios_enable_resources() that differ
in minor ways that look more like bugs than architectural differences.
This patch consolidates most of them to use the version annotated below.
This is the original x86 version, except that it uses the resource
collision check from powerpc at (5):
int pcibios_enable_resources(struct pci_dev *dev, int mask)
{
u16 cmd, old_cmd;
int i;
struct resource *r;
(0)
pci_read_config_word(dev, PCI_COMMAND, &cmd);
old_cmd = cmd;
(1) for (i = 0; i < PCI_NUM_RESOURCES; i++) {
(2) if (!(mask & (1 << i)))
continue;
r = &dev->resource[i];
(3) if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
continue;
(4) if ((i == PCI_ROM_RESOURCE) &&
(!(r->flags & IORESOURCE_ROM_ENABLE)))
continue;
(5) if (!r->parent) {
dev_err(&dev->dev, "device not available because of "
"BAR %d [%llx:%llx] collisions\n", i,
(unsigned long long) r->start,
(unsigned long long) r->end);
return -EINVAL;
}
if (r->flags & IORESOURCE_IO)
cmd |= PCI_COMMAND_IO;
if (r->flags & IORESOURCE_MEM)
cmd |= PCI_COMMAND_MEMORY;
}
(6)
(7) if (cmd != old_cmd) {
dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
old_cmd, cmd);
pci_write_config_word(dev, PCI_COMMAND, cmd);
}
return 0;
}
Compared with the above version, other architectures have the following
functional differences:
alpha: ignores mask at (2), has no PCI_ROM_RESOURCE check at (4),
has no collision check at (5)
arm: checks only 6 resources at (1), has no PCI_ROM_RESOURCE check at (4),
always fully enables bridges at (6)
cris: checks only 6 resources at (1), has a different ROM
resource check at (4) and (6) that ignores IORESOURCE_ROM_ENABLE
frv: checks only 6 resources at (1), has a different ROM
resource check at (4) and (6) that ignores IORESOURCE_ROM_ENABLE
ia64: checks for NULL dev at (0)
mips: has no IORESOURCE_{IO,MEM} check at (3), has a different
ROM resource check at (4) and (6) that ignores IORESOURCE_ROM_ENABLE
mn10300: checks only 6 resources at (1), has no IORESOURCE_{IO,MEM}
check at (3), has a different ROM resource check at (4) and (6)
that ignores IORESOURCE_ROM_ENABLE
parisc: checks DEVICE_COUNT_RESOURCE (12) instead of PCI_NUM_RESOURCES (11)
resources at (1), has no IORESOURCE_{IO,MEM} check at (3),
has no PCI_ROM_RESOURCE check at (4), has no collision check at (5)
always turns on PCI_COMMAND_SERR | PCI_COMMAND_PARITY at (6),
writes cmd even if unchanged at (7)
powerpc: has a different collision check at (5)
ppc: checks only 6 resources at (1), has no IORESOURCE_{IO,MEM} check
at (3), has a different ROM resource check at (4) and (6) that
ignores IORESOURCE_ROM_ENABLE, has a different collision check using
IORESOURCE_UNSET at (5)
sh: checks only 6 resources at (1), has no IORESOURCE_{IO,MEM} check
at (3), has a different ROM resource check at (4) and (6) that
ignores IORESOURCE_ROM_ENABLE
sparc64: has no IORESOURCE_{IO,MEM} check at (3), has no PCI_ROM_RESOURCE
check at (4)
v850: checks only 6 resources at (1), has no IORESOURCE_{IO,MEM} check
at (3), has no PCI_ROM_RESOURCE check at (4)
xtensa: checks only 6 resources at (1), has no IORESOURCE_{IO,MEM} check
at (3), has a different ROM resource check at (4) and (6) that
ignores IORESOURCE_ROM_ENABLE
x86: has a different collision check at (5)
The mips/pmc-sierra implementation of pcibios_enable_resources() is
cluttered with a bunch of titan stuff, so I can't immediately consolidate
it with the others. So I made the generic version "weak" so pmc-sierra
can override it.
Not-Yet-Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
---
arch/alpha/kernel/pci.c | 27 --------------------
arch/arm/kernel/bios32.c | 37 ----------------------------
arch/cris/arch-v32/drivers/pci/bios.c | 32 ------------------------
arch/frv/mb93090-mb00/pci-frv.c | 32 ------------------------
arch/ia64/pci/pci.c | 42 --------------------------------
arch/mips/pci/pci.c | 32 ------------------------
arch/mn10300/unit-asb2305/pci-asb2305.c | 39 -----------------------------
arch/parisc/kernel/pci.c | 37 ----------------------------
arch/powerpc/kernel/pci-common.c | 36 ---------------------------
arch/ppc/kernel/pci.c | 33 -------------------------
arch/sh/drivers/pci/pci.c | 32 ------------------------
arch/sparc64/kernel/pci.c | 30 ----------------------
arch/v850/kernel/rte_mb_a_pci.c | 28 ---------------------
arch/x86/pci/i386.c | 38 ----------------------------
arch/x86/pci/pci.h | 1
arch/xtensa/kernel/pci.c | 31 -----------------------
drivers/pci/setup-res.c | 42 ++++++++++++++++++++++++++++++++
include/linux/pci.h | 1
18 files changed, 43 insertions(+), 507 deletions(-)
Index: work6/arch/alpha/kernel/pci.c
===================================================================
--- work6.orig/arch/alpha/kernel/pci.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/alpha/kernel/pci.c 2008-02-27 14:40:34.000000000 -0700
@@ -370,33 +370,6 @@
#endif
int
-pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, oldcmd;
- int i;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- oldcmd = cmd;
-
- for (i = 0; i < PCI_NUM_RESOURCES; i++) {
- struct resource *res = &dev->resource[i];
-
- if (res->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- else if (res->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
-
- if (cmd != oldcmd) {
- printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
- pci_name(dev), cmd);
- /* Enable the appropriate bits in the PCI command register. */
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
-int
pcibios_enable_device(struct pci_dev *dev, int mask)
{
return pcibios_enable_resources(dev, mask);
Index: work6/arch/arm/kernel/bios32.c
===================================================================
--- work6.orig/arch/arm/kernel/bios32.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/arm/kernel/bios32.c 2008-02-27 14:40:34.000000000 -0700
@@ -654,43 +654,6 @@
res->start = (start + align - 1) & ~(align - 1);
}
-/**
- * pcibios_enable_resources - Enable I/O and memory.
- * @dev: PCI device to be enabled
- */
-int pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for (idx = 0; idx < 6; idx++) {
- /* Only set up the requested stuff */
- if (!(mask & (1 << idx)))
- continue;
-
- r = dev->resource + idx;
- if (!r->start && r->end) {
- printk(KERN_ERR "PCI: Device %s not available because"
- " of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
-
- if (cmd != old_cmd) {
- printk("PCI: enabling device %s (%04x -> %04x)\n",
- pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
static int platform_pci_enable_device(struct pci_dev *dev)
{
u16 cmd, old_cmd;
Index: work6/arch/cris/arch-v32/drivers/pci/bios.c
===================================================================
--- work6.orig/arch/cris/arch-v32/drivers/pci/bios.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/cris/arch-v32/drivers/pci/bios.c 2008-02-27 14:40:34.000000000 -0700
@@ -55,38 +55,6 @@
}
}
-int pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for(idx=0; idx<6; idx++) {
- /* Only set up the requested stuff */
- if (!(mask & (1<<idx)))
- continue;
-
- r = &dev->resource[idx];
- if (!r->start && r->end) {
- printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (dev->resource[PCI_ROM_RESOURCE].start)
- cmd |= PCI_COMMAND_MEMORY;
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
int pcibios_enable_irq(struct pci_dev *dev)
{
dev->irq = EXT_INTR_VECT;
Index: work6/arch/frv/mb93090-mb00/pci-frv.c
===================================================================
--- work6.orig/arch/frv/mb93090-mb00/pci-frv.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/frv/mb93090-mb00/pci-frv.c 2008-02-27 14:40:34.000000000 -0700
@@ -231,38 +231,6 @@
pcibios_assign_resources();
}
-int pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for(idx=0; idx<6; idx++) {
- /* Only set up the requested stuff */
- if (!(mask & (1<<idx)))
- continue;
-
- r = &dev->resource[idx];
- if (!r->start && r->end) {
- printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (dev->resource[PCI_ROM_RESOURCE].start)
- cmd |= PCI_COMMAND_MEMORY;
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
/*
* If we set up a device for bus mastering, we need to check the latency
* timer as certain crappy BIOSes forget to set it properly.
Index: work6/arch/ia64/pci/pci.c
===================================================================
--- work6.orig/arch/ia64/pci/pci.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/ia64/pci/pci.c 2008-02-27 14:40:34.000000000 -0700
@@ -499,48 +499,6 @@
/* ??? FIXME -- record old value for shutdown. */
}
-static inline int
-pcibios_enable_resources (struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
- unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM;
-
- if (!dev)
- return -EINVAL;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for (idx=0; idx<PCI_NUM_RESOURCES; idx++) {
- /* Only set up the desired resources. */
- if (!(mask & (1 << idx)))
- continue;
-
- r = &dev->resource[idx];
- if (!(r->flags & type_mask))
- continue;
- if ((idx == PCI_ROM_RESOURCE) &&
- (!(r->flags & IORESOURCE_ROM_ENABLE)))
- continue;
- if (!r->start && r->end) {
- printk(KERN_ERR
- "PCI: Device %s not available because of resource collisions\n",
- pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
int
pcibios_enable_device (struct pci_dev *dev, int mask)
{
Index: work6/arch/mips/pci/pci.c
===================================================================
--- work6.orig/arch/mips/pci/pci.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/mips/pci/pci.c 2008-02-27 14:40:34.000000000 -0700
@@ -163,38 +163,6 @@
subsys_initcall(pcibios_init);
-static int pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
- /* Only set up the requested stuff */
- if (!(mask & (1<<idx)))
- continue;
-
- r = &dev->resource[idx];
- if (!r->start && r->end) {
- printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (dev->resource[PCI_ROM_RESOURCE].start)
- cmd |= PCI_COMMAND_MEMORY;
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
/*
* If we set up a device for bus mastering, we need to check the latency
* timer as certain crappy BIOSes forget to set it properly.
Index: work6/arch/mn10300/unit-asb2305/pci-asb2305.c
===================================================================
--- work6.orig/arch/mn10300/unit-asb2305/pci-asb2305.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/mn10300/unit-asb2305/pci-asb2305.c 2008-02-27 14:40:34.000000000 -0700
@@ -218,45 +218,6 @@
pcibios_allocate_resources(1);
}
-int pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
-
- for (idx = 0; idx < 6; idx++) {
- /* Only set up the requested stuff */
- if (!(mask & (1 << idx)))
- continue;
-
- r = &dev->resource[idx];
-
- if (!r->start && r->end) {
- printk(KERN_ERR
- "PCI: Device %s not available because of"
- " resource collisions\n",
- pci_name(dev));
- return -EINVAL;
- }
-
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
-
- if (dev->resource[PCI_ROM_RESOURCE].start)
- cmd |= PCI_COMMAND_MEMORY;
-
- if (cmd != old_cmd)
- pci_write_config_word(dev, PCI_COMMAND, cmd);
-
- return 0;
-}
-
/*
* If we set up a device for bus mastering, we need to check the latency
* timer as certain crappy BIOSes forget to set it properly.
Index: work6/arch/parisc/kernel/pci.c
===================================================================
--- work6.orig/arch/parisc/kernel/pci.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/parisc/kernel/pci.c 2008-02-27 14:40:34.000000000 -0700
@@ -276,43 +276,6 @@
/* The caller updates the end field, we don't. */
}
-
-/*
- * A driver is enabling the device. We make sure that all the appropriate
- * bits are set to allow the device to operate as the driver is expecting.
- * We enable the port IO and memory IO bits if the device has any BARs of
- * that type.
- */
-int pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd;
- int idx;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
-
- for (idx = 0; idx < DEVICE_COUNT_RESOURCE; idx++) {
- struct resource *r = &dev->resource[idx];
-
- /* only setup requested resources */
- if (!(mask & (1<<idx)))
- continue;
-
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
-
-#if 0
- /* If bridge/bus controller has FBB enabled, child must too. */
- if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK)
- cmd |= PCI_COMMAND_FAST_BACK;
-#endif
- DBGC("PCIBIOS: Enabling device %s cmd 0x%04x\n", pci_name(dev), cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- return 0;
-}
-
/*
* A driver is enabling the device. We enable the PERR and SERR bits
* unconditionally. Drivers that do not need parity (eg graphics and
Index: work6/arch/powerpc/kernel/pci-common.c
===================================================================
--- work6.orig/arch/powerpc/kernel/pci-common.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/powerpc/kernel/pci-common.c 2008-02-27 14:40:34.000000000 -0700
@@ -1153,42 +1153,6 @@
EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
#endif /* CONFIG_HOTPLUG */
-int pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
- /* Only set up the requested stuff */
- if (!(mask & (1 << idx)))
- continue;
- r = &dev->resource[idx];
- if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
- continue;
- if ((idx == PCI_ROM_RESOURCE) &&
- (!(r->flags & IORESOURCE_ROM_ENABLE)))
- continue;
- if (r->parent == NULL) {
- printk(KERN_ERR "PCI: Device %s not available because"
- " of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n",
- pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
if (ppc_md.pcibios_enable_device_hook)
Index: work6/arch/ppc/kernel/pci.c
===================================================================
--- work6.orig/arch/ppc/kernel/pci.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/ppc/kernel/pci.c 2008-02-27 14:40:34.000000000 -0700
@@ -578,39 +578,6 @@
}
-int
-pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for (idx=0; idx<6; idx++) {
- /* Only set up the requested stuff */
- if (!(mask & (1<<idx)))
- continue;
-
- r = &dev->resource[idx];
- if (r->flags & IORESOURCE_UNSET) {
- printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (dev->resource[PCI_ROM_RESOURCE].start)
- cmd |= PCI_COMMAND_MEMORY;
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
static int next_controller_index;
struct pci_controller * __init
Index: work6/arch/sh/drivers/pci/pci.c
===================================================================
--- work6.orig/arch/sh/drivers/pci/pci.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/sh/drivers/pci/pci.c 2008-02-27 14:40:34.000000000 -0700
@@ -131,38 +131,6 @@
}
}
-int pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for(idx=0; idx<6; idx++) {
- if (!(mask & (1 << idx)))
- continue;
- r = &dev->resource[idx];
- if (!r->start && r->end) {
- printk(KERN_ERR "PCI: Device %s not available because "
- "of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (dev->resource[PCI_ROM_RESOURCE].start)
- cmd |= PCI_COMMAND_MEMORY;
- if (cmd != old_cmd) {
- printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n",
- pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
return pcibios_enable_resources(dev, mask);
Index: work6/arch/sparc64/kernel/pci.c
===================================================================
--- work6.orig/arch/sparc64/kernel/pci.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/sparc64/kernel/pci.c 2008-02-27 14:40:34.000000000 -0700
@@ -946,36 +946,6 @@
{
}
-int pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, oldcmd;
- int i;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- oldcmd = cmd;
-
- for (i = 0; i < PCI_NUM_RESOURCES; i++) {
- struct resource *res = &dev->resource[i];
-
- /* Only set up the requested stuff */
- if (!(mask & (1<<i)))
- continue;
-
- if (res->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (res->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
-
- if (cmd != oldcmd) {
- printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
- pci_name(dev), cmd);
- /* Enable the appropriate bits in the PCI command register. */
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
int pcibios_enable_device(struct pci_dev *dev, int mask)
{
return pcibios_enable_resources(dev, mask);
Index: work6/arch/v850/kernel/rte_mb_a_pci.c
===================================================================
--- work6.orig/arch/v850/kernel/rte_mb_a_pci.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/v850/kernel/rte_mb_a_pci.c 2008-02-27 14:40:34.000000000 -0700
@@ -217,34 +217,6 @@
}
\f
-int __nomods_init pcibios_enable_resources (struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for (idx = 0; idx < 6; idx++) {
- r = &dev->resource[idx];
- if (!r->start && r->end) {
- printk(KERN_ERR "PCI: Device %s not available because "
- "of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n",
- pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
int __nomods_init pcibios_enable_device (struct pci_dev *dev, int mask)
{
return pcibios_enable_resources(dev, mask);
Index: work6/arch/x86/pci/i386.c
===================================================================
--- work6.orig/arch/x86/pci/i386.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/x86/pci/i386.c 2008-02-27 14:40:34.000000000 -0700
@@ -238,44 +238,6 @@
*/
fs_initcall(pcibios_assign_resources);
-int pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
- /* Only set up the requested stuff */
- if (!(mask & (1 << idx)))
- continue;
-
- r = &dev->resource[idx];
- if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
- continue;
- if ((idx == PCI_ROM_RESOURCE) &&
- (!(r->flags & IORESOURCE_ROM_ENABLE)))
- continue;
- if (!r->start && r->end) {
- printk(KERN_ERR "PCI: Device %s not available "
- "because of resource %d collisions\n",
- pci_name(dev), idx);
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n",
- pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
/*
* If we set up a device for bus mastering, we need to check the latency
* timer as certain crappy BIOSes forget to set it properly.
Index: work6/arch/x86/pci/pci.h
===================================================================
--- work6.orig/arch/x86/pci/pci.h 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/x86/pci/pci.h 2008-02-27 14:40:34.000000000 -0700
@@ -44,7 +44,6 @@
extern unsigned int pcibios_max_latency;
void pcibios_resource_survey(void);
-int pcibios_enable_resources(struct pci_dev *, int);
/* pci-pc.c */
Index: work6/arch/xtensa/kernel/pci.c
===================================================================
--- work6.orig/arch/xtensa/kernel/pci.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/arch/xtensa/kernel/pci.c 2008-02-27 14:40:34.000000000 -0700
@@ -91,37 +91,6 @@
}
}
-int
-pcibios_enable_resources(struct pci_dev *dev, int mask)
-{
- u16 cmd, old_cmd;
- int idx;
- struct resource *r;
-
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- old_cmd = cmd;
- for(idx=0; idx<6; idx++) {
- r = &dev->resource[idx];
- if (!r->start && r->end) {
- printk (KERN_ERR "PCI: Device %s not available because "
- "of resource collisions\n", pci_name(dev));
- return -EINVAL;
- }
- if (r->flags & IORESOURCE_IO)
- cmd |= PCI_COMMAND_IO;
- if (r->flags & IORESOURCE_MEM)
- cmd |= PCI_COMMAND_MEMORY;
- }
- if (dev->resource[PCI_ROM_RESOURCE].start)
- cmd |= PCI_COMMAND_MEMORY;
- if (cmd != old_cmd) {
- printk("PCI: Enabling device %s (%04x -> %04x)\n",
- pci_name(dev), old_cmd, cmd);
- pci_write_config_word(dev, PCI_COMMAND, cmd);
- }
- return 0;
-}
-
struct pci_controller * __init pcibios_alloc_controller(void)
{
struct pci_controller *pci_ctrl;
Index: work6/drivers/pci/setup-res.c
===================================================================
--- work6.orig/drivers/pci/setup-res.c 2008-02-27 14:37:14.000000000 -0700
+++ work6/drivers/pci/setup-res.c 2008-02-27 16:53:59.000000000 -0700
@@ -263,3 +263,47 @@
}
}
}
+
+int __attribute__ ((weak)) pcibios_enable_resources(struct pci_dev *dev,
+ int mask)
+{
+ u16 cmd, old_cmd;
+ int i;
+ struct resource *r;
+
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ old_cmd = cmd;
+
+ for (i = 0; i < PCI_NUM_RESOURCES; i++) {
+ if (!(mask & (1 << i)))
+ continue;
+
+ r = &dev->resource[i];
+
+ if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
+ continue;
+ if ((i == PCI_ROM_RESOURCE) &&
+ (!(r->flags & IORESOURCE_ROM_ENABLE)))
+ continue;
+
+ if (!r->parent) {
+ dev_err(&dev->dev, "device not available because of "
+ "BAR %d [%llx:%llx] collisions\n", i,
+ (unsigned long long) r->start,
+ (unsigned long long) r->end);
+ return -EINVAL;
+ }
+
+ if (r->flags & IORESOURCE_IO)
+ cmd |= PCI_COMMAND_IO;
+ if (r->flags & IORESOURCE_MEM)
+ cmd |= PCI_COMMAND_MEMORY;
+ }
+
+ if (cmd != old_cmd) {
+ dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
+ old_cmd, cmd);
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+ }
+ return 0;
+}
Index: work6/include/linux/pci.h
===================================================================
--- work6.orig/include/linux/pci.h 2008-02-27 14:37:14.000000000 -0700
+++ work6/include/linux/pci.h 2008-02-27 14:40:34.000000000 -0700
@@ -616,6 +616,7 @@
void pci_assign_unassigned_resources(void);
void pdev_enable_device(struct pci_dev *);
void pdev_sort_resources(struct pci_dev *, struct resource_list *);
+int pcibios_enable_resources(struct pci_dev *, int mask);
void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
int (*)(struct pci_dev *, u8, u8));
#define HAVE_PCI_REQ_REGIONS 2
--
^ permalink raw reply
* [patch 0/6] RFC: PCI: consolidate pcibios_enable_resources() implementations, v2
From: Bjorn Helgaas @ 2008-02-28 0:04 UTC (permalink / raw)
To: linux-pci, linux-arch
Cc: Chris Zankel, Grant Grundler, linux-parisc, Matthew Wilcox,
Kyle McMartin, linuxppc-dev, Paul Mackerras, linux-arm-kernel,
Russell King
There are many implementations of pcibios_enable_resources() that differ
in minor ways that look more like bugs than architectural differences.
This patch series consolidates most of them to use the x86 version.
Changes between v1 and v2:
- Moved ARM bridge enable to new platform_pci_enable_device(),
called by pcibios_enable_device()
- Moved PA-RISC SERR & PERR enable to new platform_pci_enable_device(),
called by pcibios_enable_device()
- In the generic pcibios_enable_resources(), adopted powerpc resource
collision detection (check for (!r->parent) instead of
(!r->start && r->end))
- In the generic pcibios_enable_resources(), added a little more detail to
the resource collision error message
- Moved consolidated pcibios_enable_resources() from bios.c to setup-res.c
Thanks for the comments on the first version. I think this addresses
all of them.
Any other comments would be welcome.
Bjorn
--
^ permalink raw reply
* Re: patchwork missing patches?
From: Josh Boyer @ 2008-02-28 1:35 UTC (permalink / raw)
To: Paul Mackerras; +Cc: linuxppc-dev, jk
In-Reply-To: <18373.60272.351572.363687@cargo.ozlabs.ibm.com>
On Thu, 28 Feb 2008 10:00:00 +1100
Paul Mackerras <paulus@samba.org> wrote:
> Josh Boyer writes:
>
> > I'm trying to find some patches that went to the list recently in
> > patchwork and they seem to be missing. Here are a few:
> >
> > http://ozlabs.org/pipermail/linuxppc-dev/2008-February/052196.html
>
> That one was in "awaiting upstream" state since I put it in the
> bundle, then realized it should probably go through your tree, and
> didn't apply it. I've put it back to "new" state now.
Ok. Not sure why I couldn't find it under the "All" state earlier. I
see it now.
> > http://ozlabs.org/pipermail/linuxppc-dev/2008-February/052164.html
>
> I seem to recall putting that one in "changes requested" state, but
> now I can't find it either. Strange...
"changes requested" is what I was expecting, but didn't see it.
Strange indeed.
> > http://ozlabs.org/pipermail/linuxppc-dev/2008-February/052129.html
>
> Not sure where that one has gone.
It's not overly important, since it was whitespace corrupted and I have
a fixed version anyway. But it's still odd it's not on patchwork.
> > http://ozlabs.org/pipermail/linuxppc-dev/2008-February/052050.html
>
> I have been deleting patches that go through other maintainers to try
> to keep the number of patches down to a manageable level, and that
> includes ibm_newemac patches, since they go through Jeff Garzik.
> That's probably what happened to this one. I'll leave ibm_newemac
> patches alone if you promise to clean them up periodically. :)
Oh, I didn't realize you could actually outright delete them. I tend
to look after ibm_newemac because it's mostly related to 4xx and I get
to bug BenH to do the jgarzik bugging because he said he wants to be
the maintainer. I have no problems cleaning them up.
josh
^ permalink raw reply
* Re: [dtc] breaking out libfdt from dtc so other progs can use it
From: David Gibson @ 2008-02-28 1:41 UTC (permalink / raw)
To: Jerone Young; +Cc: linuxppc-dev
In-Reply-To: <1204141243.18831.12.camel@thinkpad.austin.ibm.com>
On Wed, Feb 27, 2008 at 01:40:43PM -0600, Jerone Young wrote:
> Currently the dtc source code has libfdt integrated in it. This seems to
> have become place for upstream libfdt changes. Now we all know everyone
> (linux kernel, cuboot) also have their own versions over libfdt. But if
> another userspace app wants to use libfdt , it has to copy it from the
> dtc source and try to maintain it's own copy.
>
> The question I have is can libfdt be split out from dtc source, and
> become it's own thing. This way other userspace apps can easily download
> it and link with it?
>
> The reason I ask is I have added dynamic manipulation support of device
> trees in memory into qemu for KVM. But the issue is keeping a copy of
> libfdt in the KVM userspace repository, which is getting some opposition
> (understandably). But this would be much easier if there was a libfdt
> repo for the library so that we wouldn't need to keep our own copy.
Um.. libfdt was moved into the dtc repo for convenience, both for us
writing it (they help to test each other), and for those using it -
don't have to have separate pulls for these closely related tools.
I don't understand why you're finding the merged libfdt inconvenient.
"make" will build both dtc and libfdt, and libfdt can be easily taken
out and embedded on other projects.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH 1/2] firewire: endianess fix
From: Benjamin Herrenschmidt @ 2008-02-28 2:40 UTC (permalink / raw)
To: Jarod Wilson
Cc: Kristian Hoegsberg, linux-kernel, linuxppc-dev, Stefan Richter,
sparclinux, linux1394-devel, Sam Ravnborg, Harvey Harrison
In-Reply-To: <200802271458.28401.jwilson@redhat.com>
On Wed, 2008-02-27 at 14:58 -0500, Jarod Wilson wrote:
> On Saturday 23 February 2008 06:24:17 am Stefan Richter wrote:
> > The generation of incoming requests was filled in in wrong byte order on
> > machines with big endian CPU.
> >
> > Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
> > Cc: sparclinux@vger.kernel.org
> > Cc: linuxppc-dev@ozlabs.org
> > ---
> >
> > This patch is a shot in the dark, based on a warning when building with
> > C=1 CHECKFLAGS="-D__CHECK_ENDIAN__". Is it really a fix, or was the
> > previous code accidentally correct?
> >
> > This needs to be tested on different big endian PCs, if possible with
> > the Apple Uninorth FireWire controller and other types of controllers.
> > One test which involves ohci->request_generation is simply with an SBP-2
> > device (harddisk, CD-ROM...). Does SBP-2 login etc. work?
>
> Works just fine with the Apple UniNorth controller in my powerbook in cursory
> testing. Tested with multiple sbp2 hard disks, plugging and unplugging,
> mounting and unmounting, etc.
Which specific rev/version of the uninorth controller ?
There is the "interesting" one has vendorID Apple and deviceID 0x0018,
the normal ones have different deviceIDs (and are just lucent
controllers afaik).
Ben.
^ permalink raw reply
* Re: [PATCH 1/2] firewire: endianess fix
From: Benjamin Herrenschmidt @ 2008-02-28 2:41 UTC (permalink / raw)
To: Stefan Richter
Cc: Kristian Hoegsberg, linux-kernel, linuxppc-dev, sparclinux,
Jarod Wilson, linux1394-devel, Sam Ravnborg, Harvey Harrison
In-Reply-To: <tkrat.9e19fa31951506af@s5r6.in-berlin.de>
On Sat, 2008-02-23 at 12:24 +0100, Stefan Richter wrote:
> The generation of incoming requests was filled in in wrong byte order on
> machines with big endian CPU.
>
> Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
> Cc: sparclinux@vger.kernel.org
> Cc: linuxppc-dev@ozlabs.org
> ---
>
> This patch is a shot in the dark, based on a warning when building with
> C=1 CHECKFLAGS="-D__CHECK_ENDIAN__". Is it really a fix, or was the
> previous code accidentally correct?
>
> This needs to be tested on different big endian PCs, if possible with
> the Apple Uninorth FireWire controller and other types of controllers.
> One test which involves ohci->request_generation is simply with an SBP-2
> device (harddisk, CD-ROM...). Does SBP-2 login etc. work?
Do we have the workaround for the old Apple UniNorth in the new FW OHCI
driver (for selfID swapping iirc ?)
There are several variants of Apple OHCI's here, but afaik only one with
a "problem".
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 1/2] firewire: endianess fix
From: Jarod Wilson @ 2008-02-28 3:21 UTC (permalink / raw)
To: benh
Cc: Kristian Hoegsberg, linux-kernel, linuxppc-dev, Stefan Richter,
sparclinux, linux1394-devel, Sam Ravnborg, Harvey Harrison
In-Reply-To: <1204166422.15052.334.camel@pasglop>
On Wednesday 27 February 2008 09:40:22 pm Benjamin Herrenschmidt wrote:
> On Wed, 2008-02-27 at 14:58 -0500, Jarod Wilson wrote:
> > On Saturday 23 February 2008 06:24:17 am Stefan Richter wrote:
> > > The generation of incoming requests was filled in in wrong byte order
> > > on machines with big endian CPU.
> > >
> > > Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
> > > Cc: sparclinux@vger.kernel.org
> > > Cc: linuxppc-dev@ozlabs.org
> > > ---
> > >
> > > This patch is a shot in the dark, based on a warning when building with
> > > C=1 CHECKFLAGS="-D__CHECK_ENDIAN__". Is it really a fix, or was the
> > > previous code accidentally correct?
> > >
> > > This needs to be tested on different big endian PCs, if possible with
> > > the Apple Uninorth FireWire controller and other types of controllers.
> > > One test which involves ohci->request_generation is simply with an
> > > SBP-2 device (harddisk, CD-ROM...). Does SBP-2 login etc. work?
> >
> > Works just fine with the Apple UniNorth controller in my powerbook in
> > cursory testing. Tested with multiple sbp2 hard disks, plugging and
> > unplugging, mounting and unmounting, etc.
>
> Which specific rev/version of the uninorth controller ?
lspci says Apple Computer Inc. UniNorth 2 FireWire (rev 81), pci id 106b:0031,
subsys id 106b:5811.
(Its a circa 2004 Aluminum 15" PowerBook G4 @ 1.67GHz, fwiw).
> There is the "interesting" one has vendorID Apple and deviceID 0x0018,
> the normal ones have different deviceIDs (and are just lucent
> controllers afaik).
Under Mac OS X, system.log says "FireWire (OHCI) Apple ID 31 built-in now
active". Could still be lucent though, judging by the subsys device ID of
5811, which matches up w/the Lucent/Agere FW323. But no, apparently I don't
have the interesting one.
--
Jarod Wilson
jwilson@redhat.com
^ permalink raw reply
* Re: [PATCH 1/2] firewire: endianess fix
From: Jarod Wilson @ 2008-02-28 3:33 UTC (permalink / raw)
To: linux1394-devel
Cc: Kristian Hoegsberg, linux-kernel, linuxppc-dev, Stefan Richter,
sparclinux, Sam Ravnborg, Harvey Harrison
In-Reply-To: <200802271458.28401.jwilson@redhat.com>
On Wednesday 27 February 2008 02:58:28 pm Jarod Wilson wrote:
> On Saturday 23 February 2008 06:24:17 am Stefan Richter wrote:
> > The generation of incoming requests was filled in in wrong byte order on
> > machines with big endian CPU.
> >
> > Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
> > Cc: sparclinux@vger.kernel.org
> > Cc: linuxppc-dev@ozlabs.org
> > ---
> >
> > This patch is a shot in the dark, based on a warning when building with
> > C=1 CHECKFLAGS="-D__CHECK_ENDIAN__". Is it really a fix, or was the
> > previous code accidentally correct?
> >
> > This needs to be tested on different big endian PCs, if possible with
> > the Apple Uninorth FireWire controller and other types of controllers.
> > One test which involves ohci->request_generation is simply with an SBP-2
> > device (harddisk, CD-ROM...). Does SBP-2 login etc. work?
>
> Works just fine with the Apple UniNorth controller in my powerbook in
> cursory testing. Tested with multiple sbp2 hard disks, plugging and
> unplugging, mounting and unmounting, etc.
>
> > If possible, also test whether the device remains accessible after
> > forcing a bus reset, e.g. by "echo br short > firecontrol". You need
> > the easy to build utility firecontrol and a libraw1394 with "juju"
> > backend. See wiki.linux1394.org for directions.
>
> Forgot to check that it survived bus resets. Will try to double-check that
> tonight.
Survives bus resets just fine, including with ongoing I/O from an sbp2 disk.
--
Jarod Wilson
jwilson@redhat.com
^ permalink raw reply
* dtc: Fix indentation of fixup_phandle_references
From: David Gibson @ 2008-02-28 5:42 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
Somehow the indentation of this function is messed up - 7 spaces
instead of 1 tab (probably a bad copy paste from a patch file). This
patch fixes it.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Index: dtc/checks.c
===================================================================
--- dtc.orig/checks.c 2008-02-28 16:40:04.000000000 +1100
+++ dtc/checks.c 2008-02-28 16:40:13.000000000 +1100
@@ -337,23 +337,23 @@
static void fixup_phandle_references(struct check *c, struct node *dt,
struct node *node, struct property *prop)
{
- struct marker *m = prop->val.markers;
- struct node *refnode;
- cell_t phandle;
-
- for_each_marker_of_type(m, REF_PHANDLE) {
- assert(m->offset + sizeof(cell_t) <= prop->val.len);
-
- refnode = get_node_by_ref(dt, m->ref);
- if (! refnode) {
- FAIL(c, "Reference to non-existent node or label \"%s\"\n",
- m->ref);
- continue;
- }
-
- phandle = get_node_phandle(dt, refnode);
- *((cell_t *)(prop->val.val + m->offset)) = cpu_to_be32(phandle);
- }
+ struct marker *m = prop->val.markers;
+ struct node *refnode;
+ cell_t phandle;
+
+ for_each_marker_of_type(m, REF_PHANDLE) {
+ assert(m->offset + sizeof(cell_t) <= prop->val.len);
+
+ refnode = get_node_by_ref(dt, m->ref);
+ if (! refnode) {
+ FAIL(c, "Reference to non-existent node or label \"%s\"\n",
+ m->ref);
+ continue;
+ }
+
+ phandle = get_node_phandle(dt, refnode);
+ *((cell_t *)(prop->val.val + m->offset)) = cpu_to_be32(phandle);
+ }
}
CHECK(phandle_references, NULL, NULL, fixup_phandle_references, NULL, ERROR,
&duplicate_node_names, &explicit_phandles);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: [PATCH 1/2] firewire: endianess fix
From: Benjamin Herrenschmidt @ 2008-02-28 6:25 UTC (permalink / raw)
To: Jarod Wilson
Cc: Kristian Hoegsberg, linux-kernel, linuxppc-dev, Stefan Richter,
sparclinux, linux1394-devel, Sam Ravnborg, Harvey Harrison
In-Reply-To: <200802272221.38985.jwilson@redhat.com>
> Under Mac OS X, system.log says "FireWire (OHCI) Apple ID 31 built-in now
> active". Could still be lucent though, judging by the subsys device ID of
> 5811, which matches up w/the Lucent/Agere FW323. But no, apparently I don't
> have the interesting one.
Well, it's interesting in the sense that it's a "normal" OHCI then on a
BE machine :-) My Pismo, which had the weirdo one, unfortunately died a
while ago. I'll see if I can find another machine with that one in.
Cheers,
Ben.
^ permalink raw reply
* Re: 2.6.25-rc3 on mpc8548amc doesn't boot
From: Kumar Gala @ 2008-02-28 7:03 UTC (permalink / raw)
To: maxime louvel; +Cc: linuxppc-embedded
In-Reply-To: <dda529d0802270825p527fd1b5i3e5a72a16bd95a75@mail.gmail.com>
On Feb 27, 2008, at 10:25 AM, maxime louvel wrote:
> Hi again,
>
> I am answering my self sorry for the spam...
> Just to say that my problem has been solve if someone has something
> similar...
> My changes were good, I just didn't compile the good file...
Any plans to submit patches to add support for this board to the kernel?
- k
^ permalink raw reply
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