* dtc: Rework handling of boot_cpuid_phys
From: David Gibson @ 2008-03-26 6:56 UTC (permalink / raw)
To: Jon Loeliger; +Cc: linuxppc-dev
Currently, dtc will put the nonsense value 0xfeedbeef into the
boot_cpuid_phys field of an output blob, unless explicitly given
another value with the -b command line option. As well as being a
totally unuseful default value, this also means that dtc won't
properly preserve the boot_cpuid_phys field in -I dtb -O dtb mode.
This patch reworks things to improve the boot_cpuid handling. The new
semantics are that the output's boot_cpuid_phys value is:
the value given on the command line if -b is used
otherwise
the value from the input, if in -I dtb mode
otherwise
0
Implementation-wise we do the following:
- boot_cpuid_phys is added to struct boot_info, so that
structure now contains all of the blob's semantic information.
- dt_to_blob() and dt_to_asm() output the cpuid given in
boot_info
- dt_from_blob() fills in boot_info based on the input blob
- The other dt_from_*() functions just record 0, but we can
change this easily if e.g. we invent a way of specifying the boot cpu
in the source format.
- main() overrides the cpuid in the boot_info between input
and output if -b is given
We add some testcases to check this new behaviour.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
dtc-parser.y | 4 +--
dtc.c | 12 +++++++----
dtc.h | 9 +++-----
flattree.c | 14 ++++++-------
fstree.c | 2 -
livetree.c | 3 +-
tests/Makefile.tests | 2 -
tests/boot-cpuid.c | 48 +++++++++++++++++++++++++++++++++++++++++++++
tests/dtbs_equal_ordered.c | 7 ++++++
tests/run_tests.sh | 8 +++++++
10 files changed, 88 insertions(+), 21 deletions(-)
Index: dtc/tests/dtbs_equal_ordered.c
===================================================================
--- dtc.orig/tests/dtbs_equal_ordered.c 2008-03-26 17:53:17.000000000 +1100
+++ dtc/tests/dtbs_equal_ordered.c 2008-03-26 17:53:17.000000000 +1100
@@ -125,6 +125,7 @@
int main(int argc, char *argv[])
{
void *fdt1, *fdt2;
+ uint32_t cpuid1, cpuid2;
test_init(argc, argv);
if (argc != 3)
@@ -135,5 +136,11 @@
compare_mem_rsv(fdt1, fdt2);
compare_structure(fdt1, fdt2);
+ cpuid1 = fdt_boot_cpuid_phys(fdt1);
+ cpuid2 = fdt_boot_cpuid_phys(fdt2);
+ if (cpuid1 != cpuid2)
+ FAIL("boot_cpuid_phys mismatch 0x%x != 0x%x",
+ cpuid1, cpuid2);
+
PASS();
}
Index: dtc/dtc-parser.y
===================================================================
--- dtc.orig/dtc-parser.y 2008-03-26 17:53:17.000000000 +1100
+++ dtc/dtc-parser.y 2008-03-26 17:53:17.000000000 +1100
@@ -85,11 +85,11 @@
sourcefile:
DT_V1 ';' memreserves devicetree
{
- the_boot_info = build_boot_info($3, $4);
+ the_boot_info = build_boot_info($3, $4, 0);
}
| v0_memreserves devicetree
{
- the_boot_info = build_boot_info($1, $2);
+ the_boot_info = build_boot_info($1, $2, 0);
}
;
Index: dtc/dtc.c
===================================================================
--- dtc.orig/dtc.c 2008-03-26 17:53:17.000000000 +1100
+++ dtc/dtc.c 2008-03-26 17:53:17.000000000 +1100
@@ -120,7 +120,7 @@
int opt;
FILE *outf = NULL;
int outversion = DEFAULT_FDT_VERSION;
- int boot_cpuid_phys = 0xfeedbeef;
+ long long cmdline_boot_cpuid = -1;
quiet = 0;
reservenum = 0;
@@ -160,7 +160,7 @@
quiet++;
break;
case 'b':
- boot_cpuid_phys = strtol(optarg, NULL, 0);
+ cmdline_boot_cpuid = strtoll(optarg, NULL, 0);
break;
case 'v':
printf("Version: %s\n", DTC_VERSION);
@@ -194,9 +194,13 @@
else
die("Unknown input format \"%s\"\n", inform);
+ if (cmdline_boot_cpuid != -1)
+ bi->boot_cpuid_phys = cmdline_boot_cpuid;
+
fill_fullpaths(bi->dt, "");
process_checks(force, bi);
+
if (streq(outname, "-")) {
outf = stdout;
} else {
@@ -209,9 +213,9 @@
if (streq(outform, "dts")) {
dt_to_source(outf, bi);
} else if (streq(outform, "dtb")) {
- dt_to_blob(outf, bi, outversion, boot_cpuid_phys);
+ dt_to_blob(outf, bi, outversion);
} else if (streq(outform, "asm")) {
- dt_to_asm(outf, bi, outversion, boot_cpuid_phys);
+ dt_to_asm(outf, bi, outversion);
} else if (streq(outform, "null")) {
/* do nothing */
} else {
Index: dtc/dtc.h
===================================================================
--- dtc.orig/dtc.h 2008-03-26 17:53:17.000000000 +1100
+++ dtc/dtc.h 2008-03-26 17:53:17.000000000 +1100
@@ -232,10 +232,11 @@
struct boot_info {
struct reserve_info *reservelist;
struct node *dt; /* the device tree */
+ u32 boot_cpuid_phys;
};
struct boot_info *build_boot_info(struct reserve_info *reservelist,
- struct node *tree);
+ struct node *tree, u32 boot_cpuid_phys);
/* Checks */
@@ -243,10 +244,8 @@
/* Flattened trees */
-void dt_to_blob(FILE *f, struct boot_info *bi, int version,
- int boot_cpuid_phys);
-void dt_to_asm(FILE *f, struct boot_info *bi, int version,
- int boot_cpuid_phys);
+void dt_to_blob(FILE *f, struct boot_info *bi, int version);
+void dt_to_asm(FILE *f, struct boot_info *bi, int version);
struct boot_info *dt_from_blob(const char *fname);
Index: dtc/flattree.c
===================================================================
--- dtc.orig/flattree.c 2008-03-26 17:53:17.000000000 +1100
+++ dtc/flattree.c 2008-03-26 17:53:17.000000000 +1100
@@ -354,8 +354,7 @@
fdt->size_dt_struct = cpu_to_be32(dtsize);
}
-void dt_to_blob(FILE *f, struct boot_info *bi, int version,
- int boot_cpuid_phys)
+void dt_to_blob(FILE *f, struct boot_info *bi, int version)
{
struct version_info *vi = NULL;
int i;
@@ -380,7 +379,7 @@
/* Make header */
make_fdt_header(&fdt, vi, reservebuf.len, dtbuf.len, strbuf.len,
- boot_cpuid_phys);
+ bi->boot_cpuid_phys);
/*
* If the user asked for more space than is used, adjust the totalsize.
@@ -446,7 +445,7 @@
}
}
-void dt_to_asm(FILE *f, struct boot_info *bi, int version, int boot_cpuid_phys)
+void dt_to_asm(FILE *f, struct boot_info *bi, int version)
{
struct version_info *vi = NULL;
int i;
@@ -486,7 +485,7 @@
if (vi->flags & FTF_BOOTCPUID)
fprintf(f, "\t.long\t%i\t\t\t\t\t/* boot_cpuid_phys */\n",
- boot_cpuid_phys);
+ bi->boot_cpuid_phys);
if (vi->flags & FTF_STRTABSIZE)
fprintf(f, "\t.long\t_%s_strings_end - _%s_strings_start\t/* size_dt_strings */\n",
@@ -784,7 +783,7 @@
struct boot_info *dt_from_blob(const char *fname)
{
struct dtc_file *dtcf;
- u32 magic, totalsize, version, size_dt;
+ u32 magic, totalsize, version, size_dt, boot_cpuid_phys;
u32 off_dt, off_str, off_mem_rsvmap;
int rc;
char *blob;
@@ -856,6 +855,7 @@
off_str = be32_to_cpu(fdt->off_dt_strings);
off_mem_rsvmap = be32_to_cpu(fdt->off_mem_rsvmap);
version = be32_to_cpu(fdt->version);
+ boot_cpuid_phys = be32_to_cpu(fdt->boot_cpuid_phys);
if (off_mem_rsvmap >= totalsize)
die("Mem Reserve structure offset exceeds total size\n");
@@ -908,5 +908,5 @@
dtc_close_file(dtcf);
- return build_boot_info(reservelist, tree);
+ return build_boot_info(reservelist, tree, boot_cpuid_phys);
}
Index: dtc/fstree.c
===================================================================
--- dtc.orig/fstree.c 2008-03-26 17:53:17.000000000 +1100
+++ dtc/fstree.c 2008-03-26 17:53:17.000000000 +1100
@@ -87,6 +87,6 @@
tree = read_fstree(dirname);
tree = name_node(tree, "", NULL);
- return build_boot_info(NULL, tree);
+ return build_boot_info(NULL, tree, 0);
}
Index: dtc/livetree.c
===================================================================
--- dtc.orig/livetree.c 2008-03-26 17:53:17.000000000 +1100
+++ dtc/livetree.c 2008-03-26 17:53:17.000000000 +1100
@@ -165,13 +165,14 @@
}
struct boot_info *build_boot_info(struct reserve_info *reservelist,
- struct node *tree)
+ struct node *tree, u32 boot_cpuid_phys)
{
struct boot_info *bi;
bi = xmalloc(sizeof(*bi));
bi->reservelist = reservelist;
bi->dt = tree;
+ bi->boot_cpuid_phys = boot_cpuid_phys;
return bi;
}
Index: dtc/tests/run_tests.sh
===================================================================
--- dtc.orig/tests/run_tests.sh 2008-03-26 17:53:17.000000000 +1100
+++ dtc/tests/run_tests.sh 2008-03-26 17:55:14.000000000 +1100
@@ -200,6 +200,14 @@
run_dtc_test -I dts -O dtb -o dtc_comments-cmp.test.dtb comments-cmp.dts
run_test dtbs_equal_ordered dtc_comments.test.dtb dtc_comments-cmp.test.dtb
+ # Check boot_cpuid_phys handling
+ run_dtc_test -I dts -O dtb -b 17 -o boot_cpuid.test.dtb empty.dts
+ run_test boot-cpuid boot_cpuid.test.dtb 17
+ run_dtc_test -I dtb -O dtb -b 17 -o boot_cpuid_test_tree1.test.dtb test_tree1.dtb
+ run_test boot-cpuid boot_cpuid_test_tree1.test.dtb 17
+ run_dtc_test -I dtb -O dtb -o boot_cpuid_preserved_test_tree1.test.dtb boot_cpuid_test_tree1.test.dtb
+ run_test dtbs_equal_ordered boot_cpuid_preserved_test_tree1.test.dtb boot_cpuid_test_tree1.test.dtb
+
# Check -Odts mode preserve all dtb information
for tree in test_tree1.dtb dtc_tree1.test.dtb dtc_escapes.test.dtb ; do
run_dtc_test -I dtb -O dts -o odts_$tree.test.dts $tree
Index: dtc/tests/Makefile.tests
===================================================================
--- dtc.orig/tests/Makefile.tests 2008-03-26 17:53:17.000000000 +1100
+++ dtc/tests/Makefile.tests 2008-03-26 17:53:17.000000000 +1100
@@ -9,7 +9,7 @@
sw_tree1 \
move_and_save mangle-layout nopulate \
open_pack rw_tree1 set_name setprop del_property del_node \
- string_escapes references path-references \
+ string_escapes references path-references boot-cpuid \
dtbs_equal_ordered \
add_subnode_with_nops
LIB_TESTS = $(LIB_TESTS_L:%=$(TESTS_PREFIX)%)
Index: dtc/tests/boot-cpuid.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ dtc/tests/boot-cpuid.c 2008-03-26 17:53:17.000000000 +1100
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2008 David Gibson, IBM Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2.1 of
+ * the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdint.h>
+
+#include <fdt.h>
+#include <libfdt.h>
+
+#include "tests.h"
+#include "testdata.h"
+
+int main(int argc, char *argv[])
+{
+ void *fdt;
+ uint32_t cpuid;
+
+ test_init(argc, argv);
+
+ if (argc != 3)
+ CONFIG("Usage: %s <dtb file> <cpuid>", argv[0]);
+
+ fdt = load_blob(argv[1]);
+ cpuid = strtoul(argv[2], NULL, 0);
+
+ if (fdt_boot_cpuid_phys(fdt) != cpuid)
+ FAIL("Incorrect boot_cpuid_phys (0x%x instead of 0x%x)",
+ fdt_boot_cpuid_phys(fdt), cpuid);
+
+ PASS();
+}
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
^ permalink raw reply
* Re: how to use head_fsl_booke.S:abort to restart
From: Philippe De Muyter @ 2008-03-26 8:05 UTC (permalink / raw)
To: Haiying Wang; +Cc: linuxppc-dev, kumar.gala
In-Reply-To: <1206478103.2960.29.camel@r54964-12.am.freescale.net>
Hi Haiying,
On Tue, Mar 25, 2008 at 04:48:23PM -0400, Haiying Wang wrote:
> Ok, I see the problem here. For 8540/60 which has e500 v1 core, it
> doesn't use RSTCR to assert HRESET_REQ signal to reset the whole system.
> We probably need to add abort() in fsl_rstcr_restart() for those
> silicons:
>
> diff --git a/arch/powerpc/sysdev/fsl_soc.c
> b/arch/powerpc/sysdev/fsl_soc.c
> index 2c5388c..c2d07cd 100644
> --- a/arch/powerpc/sysdev/fsl_soc.c
> +++ b/arch/powerpc/sysdev/fsl_soc.c
> @@ -1434,7 +1434,8 @@ void fsl_rstcr_restart(char *cmd)
> if (rstcr)
> /* set reset control register */
> out_be32(rstcr, 0x2); /* HRESET_REQ */
> -
> + else
> + abort();
> while (1) ;
> }
> #endif
I have a 8540 board, and that works, but as your patch is written,
compilation fails with :
arch/powerpc/sysdev/fsl_soc.c: In function 'fsl_rstcr_restart':
arch/powerpc/sysdev/fsl_soc.c:1445: error: implicit declaration
of function 'abort'
arch/powerpc/sysdev/fsl_soc.c:1445: warning: incompatible implicit
declaration of built-in function 'abort'
make[1]: *** [arch/powerpc/sysdev/fsl_soc.o] Error 1
make: *** [arch/powerpc/sysdev] Error 2
and if I fix that with :
arch_initcall(setup_rstcr);
+extern void abort(void);
+
void fsl_rstcr_restart(char *cmd)
{
it compiles and does reboot, but at startup I still get the following
annoying message :
rstcr compatible register does not exist!
Philippe
^ permalink raw reply
* Re: [PATCH] cpm_uart: Allocate DPRAM memory for SMC ports onCPM2-based platforms.
From: Sergej Stepanov @ 2008-03-26 8:31 UTC (permalink / raw)
To: Laurent Pinchart; +Cc: scottwood, linuxppc-dev
In-Reply-To: <200803251732.32569.laurentp@cse-semaphore.com>
Am Dienstag, den 25.03.2008, 17:32 +0100 schrieb Laurent Pinchart:
> Do you have any opinion about the proposed patch ?
>
I have to say, it could be some off-topic.
But if you would use the cpm_uart-driver for cpm2(or cpm1) as kernel
module, at linking you can get warnings about:
- cpm_setbrg (cpm_set_brg): something with section mismatch
- __alloc_bootmem (cpm_uart_allocbuf): the same
The symbols are not exported.
Is it ok, about kernel modules?
Sergej.
^ permalink raw reply
* Could PowerPC(IBM power blade, js 21, 8844) boot via usb key?
From: Kelvin Lin @ 2008-03-26 9:41 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 1613 bytes --]
Hi guys,
I created a PReP partition in usb key and then did "dd" and something like that to configure yaboot on it.
But the key point is that, when I boot power blade, there is not usb key in the bootable list. I mean, there are just:
1. - Ethernet
( loc=U788D.001.99DXC6K-P1-T7 )
2. - Ethernet
( loc=U788D.001.99DXC6K-P1-T8 )
3. - USB CD-ROM
( loc=U788D.001.99DXC6K-P1-T1-L1-L3 )
4. 1 SCSI 36401 MB Harddisk, part=1 ()
( loc=U788D.001.99DXC6K-P1-T10-L1-L0 )
My usb key is Kingston's DataTraveler 2GB.
Then I change another Sandisk cruzer 2GB usb key, it shows as follows in the boot menu:
1. - Ethernet
( loc=U788D.001.99DXC6K-P1-T7 )
2. - Ethernet
( loc=U788D.001.99DXC6K-P1-T8 )
3. - USB CD-ROM
( loc=U788D.001.99DXC6K-P1-T1-L1-L3 )
4. 1 SCSI 36401 MB Harddisk, part=1 ()
( loc=U788D.001.99DXC6K-P1-T10-L1-L0 )
5. - USB CD-ROM
( loc=U788D.001.99DXC6K-P1-T1-L1-L2-L1-L0 )
But this item 5 USB CD-ROM is simulated by Sandisk, not the actual usb key. I can't boot my server via item 5.
Could IBM power blade, js 21, 8844 boot via usb key? If not, could you please provide official doc to prove it. Because I have to persuade my boss to give up it. -:)
Any comment is appreciated. Thanks a lot in advanced.
Kelvin.
---------------------------------
雅虎邮箱，您的终生邮箱！
[-- Attachment #2: Type: text/html, Size: 3282 bytes --]
^ permalink raw reply
* Getting CYPRESS CYC67300 (through opb_epc) and SystemAce to work in the ML403
From: A. Nolson @ 2008-03-26 10:10 UTC (permalink / raw)
To: linuxppc-embedded
Hi,
I need to configure a system in a ML403 to make work the USB host
(CYPRESS CYC67300) toguether with the SystemAce core in my Linux 2.6.23
( secretlab ) . By now I have everything succesfully running without the
USB so I tried to follow the Xilinx Xapp925. Unfortunately, when looking
into the BSS there is no use of SystemAce. In fact, when if I try to use
the wizard to build a system from scratch, it argues that the Cypress
controller and the SystemAce cannot be used at the same time since they
share some resources. When looking more deeply into the files in
Xapp925, I have seen they include a simple IP core (glue logic) for some
pin multiplexing, but they don't make use of it.
The code itself is ( inside pcores/misc_logic_0_1.00.a/:
(...)
always @(posedge clk)
usb_ce_d1 <= usb_ce;
// USB and SysAce Mux Logic
assign usb_data_i = {sace_usb_d_I, 16'b0};
assign sysace_mpd_i = sace_usb_d_I;
assign sace_usb_a = (usb_ce | usb_ce_d1)?
{4'b0,usb_addr[28:29],1'b0} : sysace_mpa;
assign sace_usb_d_O = (usb_ce | usb_ce_d1)? usb_data_o[0:15] :
sysace_mpd_o;
assign sace_usb_d_T = (usb_ce | usb_ce_d1)? usb_data_t[0:15] :
sysace_mpd_t;
assign sace_usb_oen = (usb_ce_d1)? usb_rdn : sysace_mpoe;
assign sace_usb_wen = (usb_ce & usb_ce_d1)? usb_wrn : sysace_mpwe;
(...)
My questions are:
1. Will I be able to have both of them working in the same system?
2. Will the Linux drivers be able to cope with this "muxing"?
3. Will I have a penalty in performance if I use it?
I think this a very interesting question which I could not find any info
neither in this list or internet, but I suppose there must be many
people in the siltation of needing both USB and SystemACE to work together.
Thank you very much in advance,
/A
^ permalink raw reply
* system call ioctl() problem
From: 刘小双 @ 2008-03-26 10:13 UTC (permalink / raw)
To: linuxppc-embedded
[-- Attachment #1: Type: text/plain, Size: 4270 bytes --]
hi,all
Here is a question I didn't make out, i wonder if anybody can figure it
out. My platform is mpc8540 with graphics chip Fujitsu MB86296, my kernel
version is 2.6.12.6. I'm about to write a gfxdriver so DirectFB can call
this gfxdriver to make MB86296 do some drawing things. I wrote a program to
test if the MB86296 drawing registers can be read and written. here is some
part of the pragram:
/* fbtest.c */
int fb; //descriptor of framebuffer device
unsigned long mmio;
fb = open("/dev/fb",O_RDWR);
mmio = (unsigned long
*)mmap(0,0x2000000,PROT_READ|PROT_WRITE,MAP_SHARED,fb,0);
unsigned long ntest=0x5f5f5f5f;
*( unsigned long
*)(mmio+GDC_DRAW_BASE-GDC_HOST_BASE+GDC_REG_BACKGROUND_COLOR)=ntest; // set
value in Background Color register with ntest
printf("*( unsigned long
*)(mmio+GDC_DRAW_BASE-GDC_HOST_BASE+GDC_REG_BACKGROUND_COLOR)=%x\n",*(unsigned
long *)(mmio+GDC_DRAW_BASE-GDC_HOST_BASE+GDC_REG_BACKGROUND_COLOR));
msync((void *)mmio,0x2000000,MS_SYNC);
unsigned long ioctlReadRes[2];
ioctlReadRes[0]=GDC_REG_BACKGROUND_COLOR; //Background Color register
offset address from drawing register bsae address
printf("ioctlReadRes = %x\n",ioctlReadRes);
ioctl(fb,FBIO_MB86290_READ_DRAW_REG,ioctlReadRes); // read what is in
Background Color register,put it in ioctlReadRes[1]
printf("ioctlReadRes[0]=%x,ioctlReadRes[1]=%x\n",ioctlReadRes[0],ioctlReadRes[1]);
Then I use debug tool strace to trace exe of this program,here is the
result:
bash-3.00# strace ./fbtest
execve("./fbtest", ["./fbtest"], [/* 18 vars */]) = 0
uname({sys="Linux", node="super85xx", ...}) = 0
brk(0) = 0x10011000
mmap(NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) =
0x30017000
access("/etc/ld.so.preload", R_OK) = -1 ENOENT (No such file or
directory)
open("/mnt/gtkdfb/lib/tls/libc.so.6", O_RDONLY) = -1 ENOENT (No such file or
directory)
stat64("/mnt/gtkdfb/lib/tls", 0x7fe46fb8) = -1 ENOENT (No such file or
directory)
open("/mnt/gtkdfb/lib/libc.so.6", O_RDONLY) = -1 ENOENT (No such file or
directory)
stat64("/mnt/gtkdfb/lib", {st_mode=S_IFDIR|0777, st_size=4096, ...}) = 0
open("/etc/ld.so.cache", O_RDONLY) = 3
fstat64(3, {st_mode=S_IFREG|0644, st_size=12946, ...}) = 0
mmap(NULL, 12946, PROT_READ, MAP_PRIVATE, 3, 0) = 0x30018000
close(3) = 0
open("/lib/tls/libc.so.6", O_RDONLY) = 3
read(3, "\177ELF\1\2\1\0\0\0\0\0\0\0\0\0\0\3\0\24\0\0\0\1\0\1\307"..., 512)
=
512
fstat64(3, {st_mode=S_IFREG|0777, st_size=1303116, ...}) = 0
mmap(0xfeab000, 1328676, PROT_READ|PROT_EXEC, MAP_PRIVATE|MAP_DENYWRITE, 3,
0)
= 0xfeab000
mprotect(0xffd8000, 95780, PROT_NONE) = 0
mmap(0xffe7000, 24576, PROT_READ|PROT_WRITE|PROT_EXEC,
MAP_PRIVATE|MAP_FIXED|MAP_DENYWRITE, 3, 0x12c000) = 0xffe7000
mmap(0xffed000, 9764, PROT_READ|PROT_WRITE|PROT_EXEC,
MAP_PRIVATE|MAP_FIXED|MAP_ANONYMOUS, -1, 0) = 0xffed000
close(3) = 0
mmap(NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) =
0x3001c000
mprotect(0xffe7000, 8192, PROT_READ) = 0
mprotect(0x30026000, 4096, PROT_READ) = 0
munmap(0x30018000, 12946) = 0
open("/dev/fb", O_RDWR) = 3
mmap(NULL, 33554432, PROT_READ|PROT_WRITE, MAP_SHARED, 3, 0) = 0x30028000
fstat64(1, {st_mode=S_IFCHR|0620, st_rdev=makedev(5, 1), ...}) = 0
ioctl(1, TCGETS or TCGETS, {B115200 opost isig icanon echo ...}) = 0
mmap(NULL, 4096, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0) =
0x32028000
write(1, "*( unsigned long *)(mmio+GDC_DRA"..., 74*( unsigned long
*)(mmio+GDC_DRAW_BASE+GDC_REG_BACKGROUND_COLOR)=5f5f5f5f
) = 74
msync(0x30028000, 33554432, MS_SYNC) = 0
write(1, "ioctlReadRes = 7fe47914\n", 24ioctlReadRes = 7fe47914
) = 24
ioctl(3, 0x20004d2f, 0x7fe47914) = -1 EINVAL (Invalid argument)
write(1, "ioctlReadRes[0]=484,ioctlReadRes"...,
45ioctlReadRes[0]=484,ioctlReadRes[1]=30026f58
) = 45
munmap(0x32028000, 4096) = 0
exit_group(45) = ?
from above, I think the problem is in ioctl call, which shows "EINVAL
(Invalid argument)", so I added printk() to xx_ioctl() in fb driver, and it
showed xx_ioctl() was not called .Then I checked xx_ioctl() was right.
where is my problem? how to call ioctl() right??
Thanks
[-- Attachment #2: Type: text/html, Size: 5774 bytes --]
^ permalink raw reply
* [PATCHv2 0/3] cpm2: Reset the CPM at startup and fix the cpm_uart driver accordingly.
From: Laurent Pinchart @ 2008-03-26 11:17 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood
[-- Attachment #1: Type: text/plain, Size: 437 bytes --]
Hi everybody,
these 3 patches reset the CPM in cpm2_reset() and fix the cpm_uart driver to
initialise SMC ports correctly without relying on any initialisation
performed by the boot loader/wrapper. They update the EP8248E device tree to
match the new SMC registers description.
--
Laurent Pinchart
CSE Semaphore Belgium
Chaussée de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
F +32 (2) 387 42 75
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* [PATCHv2 1/3] cpm_uart: Allocate DPRAM memory for SMC ports on CPM2-based platforms.
From: Laurent Pinchart @ 2008-03-26 11:19 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood
In-Reply-To: <200803261217.46671.laurentp@cse-semaphore.com>
[-- Attachment #1: Type: text/plain, Size: 5713 bytes --]
This patch allocates parameter RAM for SMC serial ports without relying on
previous initialisation by a boot loader or a wrapper layer.
SMC parameter RAM on CPM2-based platforms can be allocated anywhere in the
general-purpose areas of the dual-port RAM. The current code relies on the
boot loader to allocate a section of general-purpose CPM RAM and gets the
section address from the device tree.
This patch modifies the device tree address usage to reference the SMC
parameter RAM base pointer instead of a pre-allocated RAM section and
allocates memory from the CPM dual-port RAM when initialising the SMC port.
CPM1-based platforms are not affected.
Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
---
drivers/serial/cpm_uart/cpm_uart.h | 3 ++
drivers/serial/cpm_uart/cpm_uart_core.c | 19 +++++------
drivers/serial/cpm_uart/cpm_uart_cpm1.c | 12 +++++++
drivers/serial/cpm_uart/cpm_uart_cpm2.c | 52 +++++++++++++++++++++++++++++++
4 files changed, 76 insertions(+), 10 deletions(-)
diff --git a/drivers/serial/cpm_uart/cpm_uart.h b/drivers/serial/cpm_uart/cpm_uart.h
index 80a7d60..5334653 100644
--- a/drivers/serial/cpm_uart/cpm_uart.h
+++ b/drivers/serial/cpm_uart/cpm_uart.h
@@ -93,6 +93,9 @@ extern struct uart_cpm_port cpm_uart_ports[UART_NR];
/* these are located in their respective files */
void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd);
+void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
+ struct device_node *np);
+void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram);
int cpm_uart_init_portdesc(void);
int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con);
void cpm_uart_freebuf(struct uart_cpm_port *pinfo);
diff --git a/drivers/serial/cpm_uart/cpm_uart_core.c b/drivers/serial/cpm_uart/cpm_uart_core.c
index 1ea123c..3a44a3f 100644
--- a/drivers/serial/cpm_uart/cpm_uart_core.c
+++ b/drivers/serial/cpm_uart/cpm_uart_core.c
@@ -997,24 +997,23 @@ static int cpm_uart_init_port(struct device_node *np,
if (!mem)
return -ENOMEM;
- pram = of_iomap(np, 1);
- if (!pram) {
- ret = -ENOMEM;
- goto out_mem;
- }
-
if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") ||
of_device_is_compatible(np, "fsl,cpm2-scc-uart")) {
pinfo->sccp = mem;
- pinfo->sccup = pram;
+ pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np);
} else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") ||
of_device_is_compatible(np, "fsl,cpm2-smc-uart")) {
pinfo->flags |= FLAG_SMC;
pinfo->smcp = mem;
- pinfo->smcup = pram;
+ pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np);
} else {
ret = -ENODEV;
- goto out_pram;
+ goto out_mem;
+ }
+
+ if (!pram) {
+ ret = -ENOMEM;
+ goto out_mem;
}
pinfo->tx_nrfifos = TX_NUM_FIFO;
@@ -1038,7 +1037,7 @@ static int cpm_uart_init_port(struct device_node *np,
return cpm_uart_request_port(&pinfo->port);
out_pram:
- iounmap(pram);
+ cpm_uart_unmap_pram(pinfo, pram);
out_mem:
iounmap(mem);
return ret;
diff --git a/drivers/serial/cpm_uart/cpm_uart_cpm1.c b/drivers/serial/cpm_uart/cpm_uart_cpm1.c
index 6ea0366..e692593 100644
--- a/drivers/serial/cpm_uart/cpm_uart_cpm1.c
+++ b/drivers/serial/cpm_uart/cpm_uart_cpm1.c
@@ -54,6 +54,18 @@ void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
{
cpm_command(port->command, cmd);
}
+
+void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
+ struct device_node *np)
+{
+ return of_iomap(np, 1);
+}
+
+void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram)
+{
+ iounmap(pram);
+}
+
#else
void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
{
diff --git a/drivers/serial/cpm_uart/cpm_uart_cpm2.c b/drivers/serial/cpm_uart/cpm_uart_cpm2.c
index 6291094..a4cfb0b 100644
--- a/drivers/serial/cpm_uart/cpm_uart_cpm2.c
+++ b/drivers/serial/cpm_uart/cpm_uart_cpm2.c
@@ -41,6 +41,9 @@
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/fs_pd.h>
+#ifdef CONFIG_PPC_CPM_NEW_BINDING
+#include <asm/prom.h>
+#endif
#include <linux/serial_core.h>
#include <linux/kernel.h>
@@ -54,6 +57,55 @@ void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
{
cpm_command(port->command, cmd);
}
+
+void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port,
+ struct device_node *np)
+{
+ void __iomem *pram;
+ unsigned long offset;
+ struct resource res;
+ unsigned long len;
+
+ /* Don't remap parameter RAM if it has already been initialized
+ * during console setup.
+ */
+ if (IS_SMC(port) && port->smcup)
+ return port->smcup;
+ else if (!IS_SMC(port) && port->sccup)
+ return port->sccup;
+
+ if (of_address_to_resource(np, 1, &res))
+ return NULL;
+
+ len = 1 + res.end - res.start;
+ pram = ioremap(res.start, len);
+ if (!pram)
+ return NULL;
+
+ if (!IS_SMC(port))
+ return pram;
+
+ if (len != 2) {
+ printk(KERN_WARNING "cpm_uart[%d]: device tree references "
+ "SMC pram, using boot loader/wrapper pram mapping. "
+ "Please fix your device tree to reference the pram "
+ "base register instead.\n",
+ port->port.line);
+ return pram;
+ }
+
+ offset = cpm_dpalloc(PROFF_SMC_SIZE, 64);
+ out_be16(pram, offset);
+ iounmap(pram);
+ return cpm_muram_addr(offset);
+}
+
+void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram)
+{
+ if (!IS_SMC(port))
+ iounmap(pram);
+}
+
#else
void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd)
{
--
1.5.0
--
Laurent Pinchart
CSE Semaphore Belgium
Chaussée de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
F +32 (2) 387 42 75
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply related
* [PATCHv2 2/3] ep8248e: Reference SMC parameter RAM base in the device tree.
From: Laurent Pinchart @ 2008-03-26 11:20 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood
In-Reply-To: <200803261217.46671.laurentp@cse-semaphore.com>
[-- Attachment #1: Type: text/plain, Size: 1332 bytes --]
This patch modifies the Embedded Planet EP8248E device tree to reference the
SMC paramater RAM base register instead of the parameter RAM allocated by the
boot loader.
The cpm_uart driver will allocate parameter RAM itself, making the serial port
initialisation independent of the boot loader.
Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
---
arch/powerpc/boot/dts/ep8248e.dts | 5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/boot/dts/ep8248e.dts b/arch/powerpc/boot/dts/ep8248e.dts
index 5d2fb76..756758f 100644
--- a/arch/powerpc/boot/dts/ep8248e.dts
+++ b/arch/powerpc/boot/dts/ep8248e.dts
@@ -121,8 +121,7 @@
data@0 {
compatible = "fsl,cpm-muram-data";
- reg = <0 0x1100 0x1140
- 0xec0 0x9800 0x800>;
+ reg = <0 0x2000 0x9800 0x800>;
};
};
@@ -138,7 +137,7 @@
device_type = "serial";
compatible = "fsl,mpc8248-smc-uart",
"fsl,cpm2-smc-uart";
- reg = <0x11a80 0x20 0x1100 0x40>;
+ reg = <0x11a80 0x20 0x87fc 2>;
interrupts = <4 8>;
interrupt-parent = <&PIC>;
fsl,cpm-brg = <7>;
--
1.5.0
--
Laurent Pinchart
CSE Semaphore Belgium
Chaussée de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
F +32 (2) 387 42 75
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply related
* [PATCHv2 0/3] cpm2: Reset the CPM when early debugging is not enabled.
From: Laurent Pinchart @ 2008-03-26 11:21 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood
In-Reply-To: <200803261217.46671.laurentp@cse-semaphore.com>
[-- Attachment #1: Type: text/plain, Size: 1046 bytes --]
Similarly to what is done for PQ1-based platforms, this patch resets the
PQ2 Communication Processor Module in cpm2_reset() when early debugging
is not enabled. This helps avoiding conflicts when the boot loader configured
the CPM in an unexpected way.
Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
---
arch/powerpc/sysdev/cpm2.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index 7be7112..57ed1a4 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -80,6 +80,12 @@ void __init cpm2_reset(void)
/* Tell everyone where the comm processor resides.
*/
cpmp = &cpm2_immr->im_cpm;
+
+#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
+ /* Reset the CPM.
+ */
+ cpm_command(CPM_CR_RST, 0);
+#endif
}
static DEFINE_SPINLOCK(cmd_lock);
--
1.5.0
--
Laurent Pinchart
CSE Semaphore Belgium
Chaussée de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
F +32 (2) 387 42 75
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply related
* Re: [PATCHv2 0/3] cpm2: Reset the CPM when early debugging is not enabled.
From: Laurent Pinchart @ 2008-03-26 11:22 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood
In-Reply-To: <200803261221.12274.laurentp@cse-semaphore.com>
[-- Attachment #1: Type: text/plain, Size: 200 bytes --]
This one should of course have been PATCHv2 3/3.
--
Laurent Pinchart
CSE Semaphore Belgium
Chaussée de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
F +32 (2) 387 42 75
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* [PATCH 1/2 v3] [POWERPC] Add PPC4xx L2-cache support (440GX)
From: Stefan Roese @ 2008-03-26 11:39 UTC (permalink / raw)
To: linuxppc-dev
This patch adds support for the 256k L2 cache found on some IBM/AMCC
4xx PPC's. It introduces a common 4xx SoC file (sysdev/ppc4xx_soc.c)
which currently "only" adds the L2 cache init code. Other common 4xx
stuff can be added later here.
The L2 cache handling code is a copy of Eugene's code in arch/ppc
with small modifications.
Tested on AMCC Taishan 440GX.
Signed-off-by: Stefan Roese <sr@denx.de>
---
ver3:
- Change global variable name from dcrbase to dcrbase_l2c
- Get l2 cache-size from node property
ver2:
Small changes included as suggested by Stephen Rothwell. It also removes
mentioning 460EX/GT, since L2 cache handling on these PPC's is not clear
right now.
arch/powerpc/Kconfig | 3 +
arch/powerpc/platforms/44x/Kconfig | 2 +
arch/powerpc/sysdev/Makefile | 1 +
arch/powerpc/sysdev/ppc4xx_soc.c | 189 ++++++++++++++++++++++++++++++++++++
include/asm-powerpc/dcr-regs.h | 78 ++++++++++++++++
5 files changed, 258 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/sysdev/ppc4xx_soc.c
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 1189d8d..69d4738 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -490,6 +490,9 @@ config FSL_PCI
bool
select PPC_INDIRECT_PCI
+config 4xx_SOC
+ bool
+
# Yes MCA RS/6000s exist but Linux-PPC does not currently support any
config MCA
bool
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index 83155fe..061ba3c 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -120,6 +120,7 @@ config 440GP
config 440GX
bool
+ select 4xx_SOC
select IBM_NEW_EMAC_EMAC4
select IBM_NEW_EMAC_RGMII
select IBM_NEW_EMAC_ZMII #test only
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 15f3e85..851a0be 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
obj-$(CONFIG_PPC_I8259) += i8259.o
obj-$(CONFIG_IPIC) += ipic.o
obj-$(CONFIG_4xx) += uic.o
+obj-$(CONFIG_4xx_SOC) += ppc4xx_soc.o
obj-$(CONFIG_XILINX_VIRTEX) += xilinx_intc.o
obj-$(CONFIG_OF_RTC) += of_rtc.o
ifeq ($(CONFIG_PCI),y)
diff --git a/arch/powerpc/sysdev/ppc4xx_soc.c b/arch/powerpc/sysdev/ppc4xx_soc.c
new file mode 100644
index 0000000..4847555
--- /dev/null
+++ b/arch/powerpc/sysdev/ppc4xx_soc.c
@@ -0,0 +1,189 @@
+/*
+ * IBM/AMCC PPC4xx SoC setup code
+ *
+ * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ *
+ * L2 cache routines cloned from arch/ppc/syslib/ibm440gx_common.c which is:
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ * Copyright (c) 2003 - 2006 Zultys Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/dcr.h>
+#include <asm/dcr-regs.h>
+
+static u32 dcrbase_l2c;
+
+/*
+ * L2-cache
+ */
+
+/* Issue L2C diagnostic command */
+static inline u32 l2c_diag(u32 addr)
+{
+ mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr);
+ mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_DIAG);
+ while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
+ ;
+
+ return mfdcr(dcrbase_l2c + DCRN_L2C0_DATA);
+}
+
+static irqreturn_t l2c_error_handler(int irq, void *dev)
+{
+ u32 sr = mfdcr(dcrbase_l2c + DCRN_L2C0_SR);
+
+ if (sr & L2C_SR_CPE) {
+ /* Read cache trapped address */
+ u32 addr = l2c_diag(0x42000000);
+ printk(KERN_EMERG "L2C: Cache Parity Error, addr[16:26] = 0x%08x\n",
+ addr);
+ }
+ if (sr & L2C_SR_TPE) {
+ /* Read tag trapped address */
+ u32 addr = l2c_diag(0x82000000) >> 16;
+ printk(KERN_EMERG "L2C: Tag Parity Error, addr[16:26] = 0x%08x\n",
+ addr);
+ }
+
+ /* Clear parity errors */
+ if (sr & (L2C_SR_CPE | L2C_SR_TPE)){
+ mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
+ mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
+ } else {
+ printk(KERN_EMERG "L2C: LRU error\n");
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int __init ppc4xx_l2c_probe(void)
+{
+ struct device_node *np;
+ u32 r;
+ unsigned long flags;
+ int irq;
+ const u32 *dcrreg;
+ u32 dcrbase_isram;
+ int len;
+ const u32 *prop;
+ u32 l2_size;
+
+ np = of_find_compatible_node(NULL, NULL, "ibm,l2-cache");
+ if (!np)
+ return 0;
+
+ /* Get l2 cache size */
+ prop = of_get_property(np, "cache-size", NULL);
+ if (prop == NULL) {
+ printk(KERN_ERR "%s: Can't get cache-size!\n", np->full_name);
+ of_node_put(np);
+ return -ENODEV;
+ }
+ l2_size = prop[0];
+
+ /* Map DCRs */
+ dcrreg = of_get_property(np, "dcr-reg", &len);
+ if (!dcrreg || (len != 4 * sizeof(u32))) {
+ printk(KERN_ERR "%s: Can't get DCR register base !",
+ np->full_name);
+ of_node_put(np);
+ return -ENODEV;
+ }
+ dcrbase_isram = dcrreg[0];
+ dcrbase_l2c = dcrreg[2];
+
+ /* Get and map irq number from device tree */
+ irq = irq_of_parse_and_map(np, 0);
+ if (irq == NO_IRQ) {
+ printk(KERN_ERR "irq_of_parse_and_map failed\n");
+ of_node_put(np);
+ return -ENODEV;
+ }
+
+ /* Install error handler */
+ if (request_irq(irq, l2c_error_handler, IRQF_DISABLED, "L2C", 0) < 0) {
+ printk(KERN_ERR "Cannot install L2C error handler"
+ ", cache is not enabled\n");
+ of_node_put(np);
+ return -ENODEV;
+ }
+
+ local_irq_save(flags);
+ asm volatile ("sync" ::: "memory");
+
+ /* Disable SRAM */
+ mtdcr(dcrbase_isram + DCRN_SRAM0_DPC,
+ mfdcr(dcrbase_isram + DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE);
+ mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR,
+ mfdcr(dcrbase_isram + DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK);
+ mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR,
+ mfdcr(dcrbase_isram + DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK);
+ mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR,
+ mfdcr(dcrbase_isram + DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK);
+ mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR,
+ mfdcr(dcrbase_isram + DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK);
+
+ /* Enable L2_MODE without ICU/DCU */
+ r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG) &
+ ~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK);
+ r |= L2C_CFG_L2M | L2C_CFG_SS_256;
+ mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
+
+ mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0);
+
+ /* Hardware Clear Command */
+ mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_HCC);
+ while (!(mfdcr(dcrbase_l2c + DCRN_L2C0_SR) & L2C_SR_CC))
+ ;
+
+ /* Clear Cache Parity and Tag Errors */
+ mtdcr(dcrbase_l2c + DCRN_L2C0_CMD, L2C_CMD_CCP | L2C_CMD_CTE);
+
+ /* Enable 64G snoop region starting at 0 */
+ r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP0) &
+ ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
+ r |= L2C_SNP_SSR_32G | L2C_SNP_ESR;
+ mtdcr(dcrbase_l2c + DCRN_L2C0_SNP0, r);
+
+ r = mfdcr(dcrbase_l2c + DCRN_L2C0_SNP1) &
+ ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK);
+ r |= 0x80000000 | L2C_SNP_SSR_32G | L2C_SNP_ESR;
+ mtdcr(dcrbase_l2c + DCRN_L2C0_SNP1, r);
+
+ asm volatile ("sync" ::: "memory");
+
+ /* Enable ICU/DCU ports */
+ r = mfdcr(dcrbase_l2c + DCRN_L2C0_CFG);
+ r &= ~(L2C_CFG_DCW_MASK | L2C_CFG_PMUX_MASK | L2C_CFG_PMIM
+ | L2C_CFG_TPEI | L2C_CFG_CPEI | L2C_CFG_NAM | L2C_CFG_NBRM);
+ r |= L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_TPC | L2C_CFG_CPC | L2C_CFG_FRAN
+ | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;
+
+ /* Check for 460EX/GT special handling */
+ if (of_device_is_compatible(np, "ibm,l2-cache-460ex"))
+ r |= L2C_CFG_RDBW;
+
+ mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
+
+ asm volatile ("sync; isync" ::: "memory");
+ local_irq_restore(flags);
+
+ printk(KERN_INFO "%dk L2-cache enabled\n", l2_size >> 10);
+
+ of_node_put(np);
+ return 0;
+}
+arch_initcall(ppc4xx_l2c_probe);
diff --git a/include/asm-powerpc/dcr-regs.h b/include/asm-powerpc/dcr-regs.h
index 9f1fb98..29b0ece 100644
--- a/include/asm-powerpc/dcr-regs.h
+++ b/include/asm-powerpc/dcr-regs.h
@@ -68,4 +68,82 @@
#define SDR0_UART3 0x0123
#define SDR0_CUST0 0x4000
+/*
+ * All those DCR register addresses are offsets from the base address
+ * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is
+ * excluded here and configured in the device tree.
+ */
+#define DCRN_SRAM0_SB0CR 0x00
+#define DCRN_SRAM0_SB1CR 0x01
+#define DCRN_SRAM0_SB2CR 0x02
+#define DCRN_SRAM0_SB3CR 0x03
+#define SRAM_SBCR_BU_MASK 0x00000180
+#define SRAM_SBCR_BS_64KB 0x00000800
+#define SRAM_SBCR_BU_RO 0x00000080
+#define SRAM_SBCR_BU_RW 0x00000180
+#define DCRN_SRAM0_BEAR 0x04
+#define DCRN_SRAM0_BESR0 0x05
+#define DCRN_SRAM0_BESR1 0x06
+#define DCRN_SRAM0_PMEG 0x07
+#define DCRN_SRAM0_CID 0x08
+#define DCRN_SRAM0_REVID 0x09
+#define DCRN_SRAM0_DPC 0x0a
+#define SRAM_DPC_ENABLE 0x80000000
+
+/*
+ * All those DCR register addresses are offsets from the base address
+ * for the SRAM0 controller (e.g. 0x30 on 440GX). The base address is
+ * excluded here and configured in the device tree.
+ */
+#define DCRN_L2C0_CFG 0x00
+#define L2C_CFG_L2M 0x80000000
+#define L2C_CFG_ICU 0x40000000
+#define L2C_CFG_DCU 0x20000000
+#define L2C_CFG_DCW_MASK 0x1e000000
+#define L2C_CFG_TPC 0x01000000
+#define L2C_CFG_CPC 0x00800000
+#define L2C_CFG_FRAN 0x00200000
+#define L2C_CFG_SS_MASK 0x00180000
+#define L2C_CFG_SS_256 0x00000000
+#define L2C_CFG_CPIM 0x00040000
+#define L2C_CFG_TPIM 0x00020000
+#define L2C_CFG_LIM 0x00010000
+#define L2C_CFG_PMUX_MASK 0x00007000
+#define L2C_CFG_PMUX_SNP 0x00000000
+#define L2C_CFG_PMUX_IF 0x00001000
+#define L2C_CFG_PMUX_DF 0x00002000
+#define L2C_CFG_PMUX_DS 0x00003000
+#define L2C_CFG_PMIM 0x00000800
+#define L2C_CFG_TPEI 0x00000400
+#define L2C_CFG_CPEI 0x00000200
+#define L2C_CFG_NAM 0x00000100
+#define L2C_CFG_SMCM 0x00000080
+#define L2C_CFG_NBRM 0x00000040
+#define L2C_CFG_RDBW 0x00000008 /* only 460EX/GT */
+#define DCRN_L2C0_CMD 0x01
+#define L2C_CMD_CLR 0x80000000
+#define L2C_CMD_DIAG 0x40000000
+#define L2C_CMD_INV 0x20000000
+#define L2C_CMD_CCP 0x10000000
+#define L2C_CMD_CTE 0x08000000
+#define L2C_CMD_STRC 0x04000000
+#define L2C_CMD_STPC 0x02000000
+#define L2C_CMD_RPMC 0x01000000
+#define L2C_CMD_HCC 0x00800000
+#define DCRN_L2C0_ADDR 0x02
+#define DCRN_L2C0_DATA 0x03
+#define DCRN_L2C0_SR 0x04
+#define L2C_SR_CC 0x80000000
+#define L2C_SR_CPE 0x40000000
+#define L2C_SR_TPE 0x20000000
+#define L2C_SR_LRU 0x10000000
+#define L2C_SR_PCS 0x08000000
+#define DCRN_L2C0_REVID 0x05
+#define DCRN_L2C0_SNP0 0x06
+#define DCRN_L2C0_SNP1 0x07
+#define L2C_SNP_BA_MASK 0xffff0000
+#define L2C_SNP_SSR_MASK 0x0000f000
+#define L2C_SNP_SSR_32G 0x0000f000
+#define L2C_SNP_ESR 0x00000800
+
#endif /* __DCR_REGS_H__ */
--
1.5.4.4
^ permalink raw reply related
* [PATCH 2/2 v3] [POWERPC] Add L2 cache node to AMCC Taishan dts file
From: Stefan Roese @ 2008-03-26 11:42 UTC (permalink / raw)
To: linuxppc-dev
This patch adds the L2 cache node to the Taishan 440GX dts file.
Signed-off-by: Stefan Roese <sr@denx.de>
---
ver3:
Nothing changed
ver2:
Unit address removed.
arch/powerpc/boot/dts/taishan.dts | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts
index 8278068..d0bff33 100644
--- a/arch/powerpc/boot/dts/taishan.dts
+++ b/arch/powerpc/boot/dts/taishan.dts
@@ -104,6 +104,16 @@
// FIXME: anything else?
};
+ L2C0: l2c {
+ compatible = "ibm,l2-cache-440gx", "ibm,l2-cache";
+ dcr-reg = <20 8 /* Internal SRAM DCR's */
+ 30 8>; /* L2 cache DCR's */
+ cache-line-size = <20>; /* 32 bytes */
+ cache-size = <40000>; /* L2, 256K */
+ interrupt-parent = <&UIC2>;
+ interrupts = <17 1>;
+ };
+
plb {
compatible = "ibm,plb-440gx", "ibm,plb4";
#address-cells = <2>;
--
1.5.4.4
^ permalink raw reply related
* Re: system call ioctl() problem
From: Anatolij Gustschin @ 2008-03-26 12:04 UTC (permalink / raw)
To: ???; +Cc: linuxppc-embedded
In-Reply-To: <e81b2fb40803260313i14fe5a6dmc21513180466c454@mail.gmail.com>
Hello,
??? wrote:
> hi,all
> Here is a question I didn't make out, i wonder if anybody can figure
> it out. My platform is mpc8540 with graphics chip Fujitsu MB86296, my
> kernel version is 2.6.12.6 <http://2.6.12.6>. I'm about to write a
> gfxdriver so DirectFB can call this gfxdriver to make MB86296 do some
> drawing things. I wrote a program to test if the MB86296 drawing
> registers can be read and written. here is some part of the pragram:
[snip]
> ioctl(3, 0x20004d2f, 0x7fe47914) = -1 EINVAL (Invalid argument)
> write(1, "ioctlReadRes[0]=484,ioctlReadRes"...,
> 45ioctlReadRes[0]=484,ioctlReadRes[1]=30026f58
> ) = 45
> munmap(0x32028000, 4096) = 0
> exit_group(45) = ?
>
>
> from above, I think the problem is in ioctl call, which shows "EINVAL
> (Invalid argument)", so I added printk() to xx_ioctl() in fb driver, and
> it showed xx_ioctl() was not called .Then I checked xx_ioctl() was
> right. where is my problem? how to call ioctl() right??
probably, your problem is missing mb86290-driver specific ioctl
hook in the "mb86290fb_ops" structure definition in
drivers/video/mb86290/mb86290fb.c.
Ensure that this structure definition contains something like this:
.fb_ioctl = mb86290fb_ioctl,
Without this assignment only generic framebuffer ioctl will be called,
maybe therefore you can not see driver specific ioctl call. Generic
ioctl "doesn't understand" FBIO_MB86290_READ_DRAW_REG argument and
simply returns -EINVAL.
Best regards,
Anatolij
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de
^ permalink raw reply
* Re: [PATCH] cpm_uart: Allocate DPRAM memory for SMC ports onCPM2-based platforms.
From: Laurent Pinchart @ 2008-03-26 12:34 UTC (permalink / raw)
To: Sergej Stepanov; +Cc: scottwood, linuxppc-dev
In-Reply-To: <1206520313.26613.14.camel@p60365-ste>
[-- Attachment #1: Type: text/plain, Size: 856 bytes --]
On Wednesday 26 March 2008 09:31, Sergej Stepanov wrote:
>
> Am Dienstag, den 25.03.2008, 17:32 +0100 schrieb Laurent Pinchart:
>
> > Do you have any opinion about the proposed patch ?
> >
>
> I have to say, it could be some off-topic.
> But if you would use the cpm_uart-driver for cpm2(or cpm1) as kernel
> module, at linking you can get warnings about:
> - cpm_setbrg (cpm_set_brg): something with section mismatch
> - __alloc_bootmem (cpm_uart_allocbuf): the same
>
> The symbols are not exported.
> Is it ok, about kernel modules?
I get the same section-mismatch warning for __alloc_bootmem in
cpm_uart_allocbuf. cpm_setbrg doesn't cause any warning here.
Best regards,
--
Laurent Pinchart
CSE Semaphore Belgium
Chaussée de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
F +32 (2) 387 42 75
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Re: [PATCH 2/2] ibm_newemac: PowerPC 440EP/440GR EMAC PHY clock workaround
From: Josh Boyer @ 2008-03-26 12:35 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
In-Reply-To: <1206400935.7197.59.camel@pasglop>
On Tue, 25 Mar 2008 10:22:15 +1100
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
>
> On Thu, 2008-03-06 at 16:43 +0300, Valentine Barshak wrote:
> > This patch adds ibm_newemac PHY clock workaround for 440EP/440GR EMAC
> > attached to a PHY which doesn't generate RX clock if there is no link.
> > The code is based on the previous ibm_emac driver stuff. The 440EP/440GR
> > allows controlling each EMAC clock separately as opposed to global clock
> > selection for 440GX.
> >
> > Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
>
> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This never went to netdev or Jeff from what I can see.
josh
^ permalink raw reply
* Re: [PATCH 1/2] ibm_newemac: PowerPC 440GX EMAC PHY clock workaround
From: Josh Boyer @ 2008-03-26 12:36 UTC (permalink / raw)
To: benh; +Cc: linuxppc-dev
In-Reply-To: <1206400913.7197.57.camel@pasglop>
On Tue, 25 Mar 2008 10:21:53 +1100
Benjamin Herrenschmidt <benh@kernel.crashing.org> wrote:
>
> On Thu, 2008-03-06 at 16:41 +0300, Valentine Barshak wrote:
> > The PowerPC 440GX Taishan board fails to reset EMAC3 (reset timeout error)
> > if there's no link. Because of that it fails to find PHY chip. The older ibm_emac
> > driver had a workaround for that: the EMAC_CLK_INTERNAL/EMAC_CLK_EXTERNAL macros,
> > which toggle the Ethernet Clock Select bit in the SDR0_MFR register. This patch
> > does the same for "ibm,emac-440gx" compatible chips. The workaround forces
> > clock on -all- EMACs, so we select clock under global emac_phy_map_lock.
> >
> > Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
>
> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Just get them acked by Jeff now and they can go in via Josh tree.
This never went to netdev or Jeff from what I can see.
josh
^ permalink raw reply
* Re: [PATCH 2/2] pasemi_mac: Netpoll support
From: Valentine Barshak @ 2008-03-26 12:41 UTC (permalink / raw)
To: Olof Johansson; +Cc: linuxppc-dev, pasemi-linux, jgarzik, netdev
In-Reply-To: <20080326015801.GC23103@lixom.net>
Olof Johansson wrote:
> Add netpoll support to allow use of netconsole.
>
> Signed-off-by: Nate Case <ncase@xes-inc.com>
> Signed-off-by: Olof Johansson <olof@lixom.net>
>
> diff --git a/drivers/net/pasemi_mac.c b/drivers/net/pasemi_mac.c
> index abb1dc4..6030ffe 100644
> --- a/drivers/net/pasemi_mac.c
> +++ b/drivers/net/pasemi_mac.c
> @@ -1648,6 +1648,26 @@ static int pasemi_mac_poll(struct napi_struct *napi, int budget)
> return pkts;
> }
>
> +#ifdef CONFIG_NET_POLL_CONTROLLER
> +/*
> + * Polling 'interrupt' - used by things like netconsole to send skbs
> + * without having to re-enable interrupts. It's not called while
> + * the interrupt routine is executing.
> + */
> +static void pasemi_mac_netpoll(struct net_device *dev)
> +{
> + const struct pasemi_mac *mac = netdev_priv(dev);
> +
> + disable_irq(mac->tx->chan.irq);
> + pasemi_mac_tx_intr(mac->tx->chan.irq, mac->tx);
> + enable_irq(mac->tx->chan.irq);
> +
> + disable_irq(mac->rx->chan.irq);
> + pasemi_mac_rx_intr(mac->rx->chan.irq, dev);
Shouldn't this actually be pasemi_mac_rx_intr(mac->rx->chan.irq, mac->rx)?
Thanks,
Valentine.
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
^ permalink raw reply
* [PATCH 0/2] Add support for RAM & ROM mappings to the physmap_of driver
From: Laurent Pinchart @ 2008-03-26 12:41 UTC (permalink / raw)
To: linux-mtd; +Cc: ben, linuxppc-dev, David Gibson
Hi everybody,
these two patches add support for memory-mapped RAM & ROM chips to the=20
physmap_of MTD driver.
Best regards,
=2D-=20
Laurent Pinchart
CSE Semaphore Belgium
Chauss=E9e de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
=46 +32 (2) 387 42 75
^ permalink raw reply
* RE: [PATCH] ucc_geth: Add 8 bytes to max TX frame for VLANs
From: Li Yang @ 2008-03-26 12:43 UTC (permalink / raw)
To: joakim.tjernlund; +Cc: Netdev, Linuxppc-Embedded@Ozlabs.Org
In-Reply-To: <1206436671.7589.208.camel@gentoo-jocke.transmode.se>
> -----Original Message-----
> From: Joakim Tjernlund [mailto:joakim.tjernlund@transmode.se]=20
> Sent: Tuesday, March 25, 2008 5:18 PM
> To: Li Yang
> Cc: Netdev; Linuxppc-Embedded@Ozlabs.Org
> Subject: Re: [PATCH] ucc_geth: Add 8 bytes to max TX frame for VLANs
>=20
>=20
> On Sat, 2008-03-22 at 12:51 +0100, Joakim Tjernlund wrote:
> > >> -----Original Message-----
> > >> From: netdev-owner@vger.kernel.org
> > >> [mailto:netdev-owner@vger.kernel.org] On Behalf Of=20
> Joakim Tjernlund
> > > Sent: Tuesday, March 18, 2008 11:11 PM
> > >> To: Netdev; Li Yang
> > >> Cc: Joakim Tjernlund
> > >>Subject: [PATCH] ucc_geth: Add 8 bytes to max TX frame for VLANs
> > >>
> > >> Creating a VLAN interface on top of ucc_geth adds 4 bytes to the=20
> > >> frame and the HW controller is not prepared to TX a frame bigger=20
> > >> than 1518 bytes which is 4 bytes too small for a full=20
> VLAN frame.=20
> > >> Also add 4 extra bytes for future expansion.
> > >=20
> > > IMO, VLAN and Jumbo packet support is not general case of=20
> Ethernet.
> > > Could you make this change optional? Thanks.
> > >=20
> > > - Leo
> >=20
> > hmm, I do not agree. VLAN is common today.
> >=20
> > If you were to enable HW support for VLAN then the ethernet=20
> controller=20
> > would inject an extra 4 bytes into the frame.
> > This change does not change the visible MTU for the user.=20
> As is now,=20
> > soft VLAN is silently broken. Do you really want the user=20
> to find and=20
> > turn on a controller specific feature to use VLAN?
> >=20
> > What does netdev people think?=20
> >=20
> > Jocke
>=20
> hmm, I misread the HW specs. The change has nothing to do=20
> with TX, it is the MAX RX frame size that was too small for=20
> VLAN and that is what the patch addresses. I see that tg3.c=20
> adds 4 bytes to MAX RX pkgs:
> /* MTU + ethernet header + FCS + optional VLAN tag */
> tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8); So=20
> I don't think this change should be hidden behind a new=20
> CONFIG option. Updated patch below with changed description.
Hi Jocke,
QUICC engine supports dynamic maximum frame length. If you are not
expecting to receive only tagged frames, I recommend to use this feature
by setting dynamicMaxFrameLength and dynamicMinFrameLength in ug_info
instead of increasing the MaxLength for both tagged and untagged frames.
See the following part from the reference manual.
The MFLR entry in the Global Parameter RAM defines the length of the
largest frame, excluding Q TAG
but including FCS, that is still valid. When REMODER[DXE]=3D1, a tagged
frame that has length equals
MaxLength+4 considered valid, and a non tagged frame that has length
equals MaxLength is the longest
that is still considered valid. When REMODER[DXE]=3D0, any frame longer
than MaxLength consider
erroneous frame.
For systems with only tagged frames, set REMODER[DXE]=3D0 and set
MaxLength =3D Max LLC size+4.
- Leo
^ permalink raw reply
* [PATCH 1/2] [MTD] Add support for RAM & ROM mappings in the physmap_of MTD driver.
From: Laurent Pinchart @ 2008-03-26 12:44 UTC (permalink / raw)
To: linux-mtd; +Cc: ben, linuxppc-dev, David Gibson
Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
=2D--
drivers/mtd/maps/physmap_of.c | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/maps/physmap_of.c b/drivers/mtd/maps/physmap_of.c
index 49acd41..65c30b5 100644
=2D-- a/drivers/mtd/maps/physmap_of.c
+++ b/drivers/mtd/maps/physmap_of.c
@@ -273,6 +273,14 @@ static struct of_device_id of_flash_match[] =3D {
.data =3D (void *)"jedec_probe",
},
{
+ .compatible =3D "physmap-ram",
+ .data =3D (void *)"map_ram",
+ },
+ {
+ .compatible =3D "physmap-rom",
+ .data =3D (void *)"map_rom",
+ },
+ {
.type =3D "rom",
.compatible =3D "direct-mapped"
},
=2D-=20
1.5.0
=2D-=20
Laurent Pinchart
CSE Semaphore Belgium
Chauss=E9e de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
=46 +32 (2) 387 42 75
^ permalink raw reply
* Re: Patch: FW:Xilinx: BSP: Updated ML405 to match hardware used for testing
From: Guillaume Dargaud @ 2008-03-26 11:47 UTC (permalink / raw)
To: linuxppc-dev
Hello all,
I'm trying to get things up and running on a Xilinx Virtex-4 ml405 board,
and as such I've been trying to figure out the following recent message to
the list:
http://patchwork.ozlabs.org/linuxppc/patch?person=1226&id=17037
I don't understand what this patch applies to: it references files such as
ml405_defconfig which are not part of the normal kernel tree and which I
cannot find anywhere. Is there some other kind of patch that needs to apply
first in order to get for instance CONFIG_XILINX_DRIVERS,
CONFIG_XILINX_EMAC, etc...
Thanks
--
Guillaume Dargaud
http://www.gdargaud.net/
^ permalink raw reply
* [PATCH 2/2] [POWERPC] Describe memory-mapped RAM&ROM chips of bindings
From: Laurent Pinchart @ 2008-03-26 12:44 UTC (permalink / raw)
To: linux-mtd; +Cc: ben, linuxppc-dev, David Gibson
Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
=2D--
Documentation/powerpc/booting-without-of.txt | 31 ++++++++++++++++++++++=
+++-
1 files changed, 30 insertions(+), 1 deletions(-)
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/p=
owerpc/booting-without-of.txt
index 7b4e8a7..53d1cf8 100644
=2D-- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -57,7 +57,8 @@ Table of Contents
n) 4xx/Axon EMAC ethernet nodes
o) Xilinx IP cores
p) Freescale Synchronous Serial Interface
=2D q) USB EHCI controllers
+ q) USB EHCI controllers
+ r) Memory-mapped RAM & ROM
=20
VII - Specifying interrupt information for devices
1) interrupts property
@@ -2816,6 +2817,34 @@ platforms are moved over to use the flattened-device=
=2Dtree model.
big-endian;
};
=20
+ r) Memory-mapped RAM & ROM
+
+ Dedicated RAM and ROM chips are often used as storage for temporary or
+ permanent data in embedded devices. Possible usage include non-volatile
+ storage in battery-backed SRAM, semi-permanent storage in dedicated SR=
AM
+ to preserve data accross reboots and firmware storage in dedicated ROM.
+
+ - compatible : should contain the specific model of RAM/ROM chip(s)
+ used, if known, followed by either "physmap-ram" or "physmap-rom"
+ - reg : Address range of the RAM/ROM chip
+ - bank-width : Width (in bytes) of the RAM/ROM bank. Equal to the
+ device width times the number of interleaved chips.
+ - device-width : (optional) Width of a single RAM/ROM chip. If
+ omitted, assumed to be equal to 'bank-width'.
+
+ Similarly to memory-mapped NOR flash, memory-mapped RAM & ROM chips
+ can be partionned. See the "j) CFI and JEDEC memory-mapped NOR flash"
+ section for information about how to represent partitions in the
+ device tree.
+
+ Example:
+
+ mmram@f2000000 {
+ compatible =3D "renesas,m5m5w816", "physmap-ram";
+ reg =3D <f2000000 00100000>;
+ bank-width =3D <2>;
+ };
+
=20
More devices will be defined as this spec matures.
=20
=2D-=20
1.5.0
=2D-=20
Laurent Pinchart
CSE Semaphore Belgium
Chauss=E9e de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
=46 +32 (2) 387 42 75
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* Re: OF compatible MTD platform RAM driver ?
From: Sergei Shtylyov @ 2008-03-26 12:53 UTC (permalink / raw)
To: Laurent Pinchart; +Cc: ben, linuxppc-dev, linux-mtd, David Gibson
In-Reply-To: <200803251914.24021.laurentp@cse-semaphore.com>
Laurent Pinchart wrote:
>>>Regarding non-volatility nothing prevents a user from using a
>>>volatile RAM as an MTD device, but there's little point in doing so.
>>>Would it be acceptable for the "linear-nvram" specification
>>>not to include > volatile RAM ? ROM chips would be excluded too. Is
>>that an issue ?
>>We actually use a volatile ram (SRAM) as an MTD device. We use it to
>>store info from bootloader and system specific values between resets.
> So we're left with two main options.
> - Reusing the nvram device type from the Device Support Extensions. Volatile
> devices wouldn't be supported, and we'd need a separate device specification
> for linear-mapped volatile RAMs. I'm not very happy with that.
> - Using another device node with a compatible value set to "linear-ram" (or
> something similar). This would support both volatile and non-volatile
> devices, and a property could be added to specify if the device is volatile
> or not.
> I'd go for the second option, and I'd specify a "linear-rom" compatible value
> as well while we're at it.
> Both volatile and non-volatile RAMs can be handled by the physmap_of MTD
> driver. They both use the same map probe type ("map_ram"). Volatility isn't
> handled there.
> ROMs should be handled by the same driver and should use the "mtd_rom" map
> probe type.
OK, let's go with it.
> As all those devices use the physmap_of MTD driver, what about
> using "physmap-ram" and "physmap-rom" as compatibility names ?
Heh, we've gone thru "physmap" before -- it was labelled Linux-specific
name (well, I'd agree with that).
> Best regards,
WBR, Sergei
^ permalink raw reply
* Re: Patch: FW:Xilinx: BSP: Updated ML405 to match hardware used for testing
From: Grant Likely @ 2008-03-26 13:01 UTC (permalink / raw)
To: Guillaume Dargaud; +Cc: linuxppc-dev
In-Reply-To: <052801c88f37$3b51f7e0$ad289e86@LPSC0173W>
On Wed, Mar 26, 2008 at 5:47 AM, Guillaume Dargaud
<dargaud@lpsc.in2p3.fr> wrote:
> Hello all,
>
> I'm trying to get things up and running on a Xilinx Virtex-4 ml405 board,
> and as such I've been trying to figure out the following recent message to
> the list:
> http://patchwork.ozlabs.org/linuxppc/patch?person=1226&id=17037
>
> I don't understand what this patch applies to: it references files such as
> ml405_defconfig which are not part of the normal kernel tree and which I
> cannot find anywhere. Is there some other kind of patch that needs to apply
> first in order to get for instance CONFIG_XILINX_DRIVERS,
> CONFIG_XILINX_EMAC, etc...
>
> Thanks
It applies to Xilinx's git tree of the Linux kernel.
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
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