* Re: [PATCH] powerpc: Fix deadlock with mmu_hash_lock in hash_page_sync
From: Gaash Hazan @ 2008-03-31 8:30 UTC (permalink / raw)
To: Benjamin Herrenschmidt
Cc: linuxppc-dev, Paul Mackerras, gaash-ppclnx, Gilad Ben-Yossef
In-Reply-To: <8C22373EA650AF40928EEA0C188D62D206C71041@xmb-ams-338.emea.cisco.com>
> -----Original Message-----
> From: Benjamin Herrenschmidt
> [mailto:benh@kernel.crashing.org]
> Sent: Monday, March 31, 2008 0:49
> To: gaash-ppclnx@gaashh.com
> Cc: linuxppc-dev@ozlabs.org; Gilad Ben-Yossef; Paul
> Mackerras
> Subject: [PATCH] powerpc: Fix deadlock with
> mmu_hash_lock in
> hash_page_sync
>
> hash_page_sync() takes and releases the low level
> mmu hash lock in order
> to sync with other processors disposing of page
> tables. Because that
> lock can be needed to service hash misses triggered
> by interrupt
> handler, taking it must be done with interrupts off.
> However,
> hash_page_sync() appear to be called with interrupts
> enabled, thus
> causing occasional deadlocks.
>
> We fix it by making sure hash_page_sync() masks
> interrupts while holding
> the lock.
>
> Signed-off-by: Benjamin Herrenschmidt
> <benh@kernel.crashing.org>
> ---
>
> Please test and report asap thought it's probably
> too late for 2.6.25,
> it can still go into stable later on.
>
Thank you for the quick acknowledgment and patch.
Patch works well.
Thanks,
Gaash
^ permalink raw reply
* Re: Xilinx LLTEMAC driver issues
From: rza1 @ 2008-03-31 9:14 UTC (permalink / raw)
To: Magnus Hjorth; +Cc: linuxppc-embedded, John Linn, git
In-Reply-To: <1206802234.5247.19.camel@magnus-desktop>
Hi Magnus,
1.
I am using nearly the same versions then you and got the same problems
too ;-).
I think there are some problems with the checksum offloading.
Try to sniff the some packages (e.g. wireshark)...
For me ICMP (ping) worked but udp and tcp not (because off a wrong
checksum in the transport layer).
A quick solution is to just deactivate checksum offloading.
2.
I remember some problems with Virtex-4 presamples too.
There where problems with the hard-temac wrapper. You had to use 1.00.a
and not b version.
But I don't have these problems with the EDK 9.2sp2/ISE9.2sp3 anymore.
all the best,
Robert
Magnus Hjorth wrote:
> Hi John,
>
> Thanks for the very fast reply! Right now I'm not at work so I don't
> have the board or EDK here to test anything.
>
> I'm using checksum offload, but I don't know if DRE is enabled or not. I
> can't recall seeing any setting to enable/disable DRE..
>
> A few things that crossed my mind:
>
> Last year I did a design with EDK 8.2, back then there was an issue with
> the ML403 boards having an old revision of the FPGA which wasn't
> compatible with some versions of the IP core. There are no such version
> issues with the xps_ll_temac?
>
> I don't think that I had phy-addr set in the DTS file. Will test that on
> Monday.
>
> Best regards,
> Magnus
>
>
> On Sat, 2008-03-29 at 07:58 -0600, John Linn wrote:
>
>> Hi Magnus,
>>
>> Sorry to hear you're having problems with it.
>>
>> I am doing testing on an ML405 which is the same board but with a bigger FPGA, but with ppc arch and I don't see this issue. I have done limited testing with powerpc arch and the LL TEMAC, but I didn't see this issue there either. Powerpc arch is definitely less mature in my experience than the ppc arch. I'll do a quick test with my powerpc arch and make sure again I'm not seeing it.
>>
>> My kernel is from the Xilinx Git tree, but there have been a number of changes we have pushed out so I don't know how long ago you pulled from the Git tree.
>>
>> My EDK project is 10.1 so it's a little newer. I am using LL TEMAC 1.01a so it's a little newer. I reviewed the change log for the LL TEMAC and don't see any big problems that were fixed in the newer versions, more new features. I'll check with some others here to see if I missed something there.
>>
>> I am using DMA also, but no DRE or checksum offload. You didn't say anything about those. I'm going to insert my mhs file that describes my system to let you compare your system configuration. It's not clear to me yet if you have a h/w or s/w problem.
>>
>> I'll also insert some of my device tree with the LL TEMAC so you can compare (ignore 16550 stuff as we are still working on that).
>>
>> Since you can't ping reliably I would probably focus on that since it's simpler than the other issues you're seeing.
>>
>> Thanks,
>> John
>>
>>
>>
>> # ##############################################################################
>> # Created by Base System Builder Wizard for Xilinx EDK 10.1.1 Build EDK_K_SP1.1
>> # Thu Feb 14 14:11:12 2008
>> # Target Board: Xilinx Virtex 4 ML405 Evaluation Platform Rev 1
>> # Family: virtex4
>> # Device: xc4vfx20
>> # Package: ff672
>> # Speed Grade: -10
>> # Processor: ppc405_0
>> # Processor clock frequency: 300.00 MHz
>> # Bus clock frequency: 100.00 MHz
>> # On Chip Memory : 8 KB
>> # Total Off Chip Memory : 128 MB
>> # - DDR_SDRAM = 128 MB
>> # ##############################################################################
>> PARAMETER VERSION = 2.1.0
>>
>>
>> PORT fpga_0_RS232_Uart_sin_pin = fpga_0_RS232_Uart_sin, DIR = I
>> PORT fpga_0_RS232_Uart_sout_pin = fpga_0_RS232_Uart_sout, DIR = O
>> PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
>> PORT fpga_0_IIC_EEPROM_Scl_pin = fpga_0_IIC_EEPROM_Scl, DIR = IO
>> PORT fpga_0_IIC_EEPROM_Sda_pin = fpga_0_IIC_EEPROM_Sda, DIR = IO
>> PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin = fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR = I
>> PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin = fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR = O, VEC = [6:1]
>> PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin = fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR = IO, VEC = [15:0]
>> PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin = fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR = O
>> PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin = fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR = O
>> PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin = fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR = O
>> PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR = I
>> PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O
>> PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR = O
>> PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC = [12:0]
>> PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0]
>> PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O
>> PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O
>> PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O
>> PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O
>> PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O
>> PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O, VEC = [3:0]
>> PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = [3:0]
>> PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = [31:0]
>> PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TXD_0, DIR = O, VEC = [7:0]
>> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0, DIR = O
>> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0, DIR = O
>> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0, DIR = O
>> PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RXD_0, DIR = I, VEC = [7:0]
>> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0, DIR = I
>> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0, DIR = I
>> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0, DIR = I
>> PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0, DIR = I
>> PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin = fpga_0_TriMode_MAC_GMII_MDIO_0, DIR = IO
>> PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin = fpga_0_TriMode_MAC_GMII_MDC_0, DIR = O
>> PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n, DIR = O
>> PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
>> PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
>>
>>
>> BEGIN ppc405_virtex4
>> PARAMETER INSTANCE = ppc405_0
>> PARAMETER HW_VER = 2.01.a
>> PARAMETER C_FASTEST_PLB_CLOCK = DPLB1
>> PARAMETER C_IDCR_BASEADDR = 0b0100000000
>> PARAMETER C_IDCR_HIGHADDR = 0b0111111111
>> BUS_INTERFACE JTAGPPC = jtagppc_0_0
>> BUS_INTERFACE IPLB0 = plb
>> BUS_INTERFACE DPLB0 = plb
>> BUS_INTERFACE IPLB1 = ppc405_0_iplb1
>> BUS_INTERFACE DPLB1 = ppc405_0_dplb1
>> BUS_INTERFACE RESETPPC = ppc_reset_bus
>> PORT CPMC405CLOCK = proc_clk_s
>> PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
>> END
>>
>> BEGIN jtagppc_cntlr
>> PARAMETER INSTANCE = jtagppc_0
>> PARAMETER HW_VER = 2.01.a
>> BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
>> END
>>
>> BEGIN plb_v46
>> PARAMETER INSTANCE = plb
>> PARAMETER C_DCR_INTFCE = 0
>> PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
>> PARAMETER HW_VER = 1.02.a
>> PORT PLB_Clk = sys_clk_s
>> PORT SYS_Rst = sys_bus_reset
>> END
>>
>> BEGIN xps_bram_if_cntlr
>> PARAMETER INSTANCE = xps_bram_if_cntlr_1
>> PARAMETER HW_VER = 1.00.a
>> PARAMETER C_SPLB_NATIVE_DWIDTH = 64
>> PARAMETER C_BASEADDR = 0xffffe000
>> PARAMETER C_HIGHADDR = 0xffffffff
>> BUS_INTERFACE SPLB = plb
>> BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
>> END
>>
>> BEGIN bram_block
>> PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
>> PARAMETER HW_VER = 1.00.a
>> BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
>> END
>>
>> BEGIN xps_uart16550
>> PARAMETER INSTANCE = RS232_Uart
>> PARAMETER HW_VER = 2.00.a
>> PARAMETER C_IS_A_16550 = 1
>> PARAMETER C_BASEADDR = 0x83e00000
>> PARAMETER C_HIGHADDR = 0x83e0ffff
>> BUS_INTERFACE SPLB = plb
>> PORT sin = fpga_0_RS232_Uart_sin
>> PORT sout = fpga_0_RS232_Uart_sout
>> PORT IP2INTC_Irpt = RS232_Uart_IP2INTC_Irpt
>> END
>>
>> BEGIN xps_gpio
>> PARAMETER INSTANCE = LEDs_4Bit
>> PARAMETER HW_VER = 1.00.a
>> PARAMETER C_INTERRUPT_PRESENT = 1
>> PARAMETER C_GPIO_WIDTH = 4
>> PARAMETER C_IS_DUAL = 0
>> PARAMETER C_IS_BIDIR = 1
>> PARAMETER C_ALL_INPUTS = 0
>> PARAMETER C_BASEADDR = 0x81400000
>> PARAMETER C_HIGHADDR = 0x8140ffff
>> BUS_INTERFACE SPLB = plb
>> PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
>> PORT IP2INTC_Irpt = LEDs_4Bit_IP2INTC_Irpt
>> END
>>
>> BEGIN xps_iic
>> PARAMETER INSTANCE = IIC_EEPROM
>> PARAMETER HW_VER = 2.00.a
>> PARAMETER C_CLK_FREQ = 100000000
>> PARAMETER C_IIC_FREQ = 100000
>> PARAMETER C_TEN_BIT_ADR = 0
>> PARAMETER C_BASEADDR = 0x81600000
>> PARAMETER C_HIGHADDR = 0x8160ffff
>> BUS_INTERFACE SPLB = plb
>> PORT Scl = fpga_0_IIC_EEPROM_Scl
>> PORT Sda = fpga_0_IIC_EEPROM_Sda
>> PORT IIC2INTC_Irpt = IIC_EEPROM_IIC2INTC_Irpt
>> END
>>
>> BEGIN xps_sysace
>> PARAMETER INSTANCE = SysACE_CompactFlash
>> PARAMETER HW_VER = 1.00.a
>> PARAMETER C_MEM_WIDTH = 16
>> PARAMETER C_BASEADDR = 0x83600000
>> PARAMETER C_HIGHADDR = 0x8360ffff
>> BUS_INTERFACE SPLB = plb
>> PORT SysACE_CLK = fpga_0_SysACE_CompactFlash_SysACE_CLK
>> PORT SysACE_MPA = fpga_0_SysACE_CompactFlash_SysACE_MPA_split
>> PORT SysACE_MPD = fpga_0_SysACE_CompactFlash_SysACE_MPD
>> PORT SysACE_CEN = fpga_0_SysACE_CompactFlash_SysACE_CEN
>> PORT SysACE_OEN = fpga_0_SysACE_CompactFlash_SysACE_OEN
>> PORT SysACE_WEN = fpga_0_SysACE_CompactFlash_SysACE_WEN
>> PORT SysACE_MPIRQ = fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
>> PORT SysACE_IRQ = SysACE_CompactFlash_SysACE_IRQ
>> END
>>
>> BEGIN mpmc
>> PARAMETER INSTANCE = DDR_SDRAM
>> PARAMETER HW_VER = 4.00.a
>> PARAMETER C_NUM_PORTS = 3
>> PARAMETER C_MEM_PARTNO = HYB25D512160BE-5
>> PARAMETER C_MEM_DATA_WIDTH = 32
>> PARAMETER C_MEM_DQS_WIDTH = 4
>> PARAMETER C_MEM_DM_WIDTH = 4
>> PARAMETER C_MEM_TYPE = DDR
>> PARAMETER C_NUM_IDELAYCTRL = 2
>> PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2
>> PARAMETER C_PIM0_BASETYPE = 2
>> PARAMETER C_PIM1_BASETYPE = 2
>> PARAMETER C_PIM2_BASETYPE = 3
>> PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
>> PARAMETER C_SDMA2_PI2LL_CLK_RATIO = 1
>> PARAMETER C_MPMC_BASEADDR = 0x00000000
>> PARAMETER C_MPMC_HIGHADDR = 0x07ffffff
>> PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000
>> PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460ffff
>> BUS_INTERFACE SPLB0 = ppc405_0_iplb1
>> BUS_INTERFACE SPLB1 = ppc405_0_dplb1
>> BUS_INTERFACE SDMA_LL2 = TriMode_MAC_GMII_LLINK0
>> BUS_INTERFACE SDMA_CTRL2 = plb
>> PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
>> PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
>> PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
>> PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
>> PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
>> PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
>> PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
>> PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
>> PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
>> PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
>> PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
>> PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
>> PORT MPMC_Clk0 = sys_clk_s
>> PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
>> PORT SDMA2_Clk = sys_clk_s
>> PORT MPMC_Clk_200MHz = clk_200mhz_s
>> PORT MPMC_Rst = sys_periph_reset
>> PORT SDMA2_Rx_IntOut = DDR_SDRAM_SDMA2_Rx_IntOut
>> PORT SDMA2_Tx_IntOut = DDR_SDRAM_SDMA2_Tx_IntOut
>> END
>>
>> BEGIN xps_ll_temac
>> PARAMETER INSTANCE = TriMode_MAC_GMII
>> PARAMETER HW_VER = 1.01.a
>> PARAMETER C_SPLB_CLK_PERIOD_PS = 10000
>> PARAMETER C_PHY_TYPE = 1
>> PARAMETER C_NUM_IDELAYCTRL = 4
>> PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3
>> PARAMETER C_TEMAC_TYPE = 1
>> PARAMETER C_BUS2CORE_CLK_RATIO = 1
>> PARAMETER C_BASEADDR = 0x81c00000
>> PARAMETER C_HIGHADDR = 0x81c0ffff
>> BUS_INTERFACE SPLB = plb
>> BUS_INTERFACE LLINK0 = TriMode_MAC_GMII_LLINK0
>> PORT GMII_TXD_0 = fpga_0_TriMode_MAC_GMII_GMII_TXD_0
>> PORT GMII_TX_EN_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0
>> PORT GMII_TX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0
>> PORT GMII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0
>> PORT GMII_RXD_0 = fpga_0_TriMode_MAC_GMII_GMII_RXD_0
>> PORT GMII_RX_DV_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0
>> PORT GMII_RX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0
>> PORT GMII_RX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0
>> PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0
>> PORT MDIO_0 = fpga_0_TriMode_MAC_GMII_MDIO_0
>> PORT MDC_0 = fpga_0_TriMode_MAC_GMII_MDC_0
>> PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n
>> PORT GTX_CLK_0 = temac_clk_s
>> PORT REFCLK = clk_200mhz_s
>> PORT LlinkTemac0_CLK = sys_clk_s
>> PORT TemacIntc0_Irpt = TriMode_MAC_GMII_TemacIntc0_Irpt
>> END
>>
>> BEGIN util_bus_split
>> PARAMETER INSTANCE = SysACE_CompactFlash_util_bus_split_0
>> PARAMETER HW_VER = 1.00.a
>> PARAMETER C_SIZE_IN = 7
>> PARAMETER C_LEFT_POS = 0
>> PARAMETER C_SPLIT = 6
>> PORT Sig = fpga_0_SysACE_CompactFlash_SysACE_MPA_split
>> PORT Out1 = fpga_0_SysACE_CompactFlash_SysACE_MPA
>> END
>>
>> BEGIN plb_v46
>> PARAMETER INSTANCE = ppc405_0_iplb1
>> PARAMETER HW_VER = 1.02.a
>> PORT PLB_Clk = sys_clk_s
>> PORT SYS_Rst = sys_bus_reset
>> END
>>
>> BEGIN plb_v46
>> PARAMETER INSTANCE = ppc405_0_dplb1
>> PARAMETER HW_VER = 1.02.a
>> PORT PLB_Clk = sys_clk_s
>> PORT SYS_Rst = sys_bus_reset
>> END
>>
>> BEGIN clock_generator
>> PARAMETER INSTANCE = clock_generator_0
>> PARAMETER HW_VER = 2.00.a
>> PARAMETER C_EXT_RESET_HIGH = 1
>> PARAMETER C_CLKIN_FREQ = 100000000
>> PARAMETER C_CLKOUT0_FREQ = 100000000
>> PARAMETER C_CLKOUT0_BUF = TRUE
>> PARAMETER C_CLKOUT0_PHASE = 0
>> PARAMETER C_CLKOUT0_GROUP = DCM0
>> PARAMETER C_CLKOUT1_FREQ = 100000000
>> PARAMETER C_CLKOUT1_BUF = TRUE
>> PARAMETER C_CLKOUT1_PHASE = 90
>> PARAMETER C_CLKOUT1_GROUP = DCM0
>> PARAMETER C_CLKOUT2_FREQ = 300000000
>> PARAMETER C_CLKOUT2_BUF = TRUE
>> PARAMETER C_CLKOUT2_PHASE = 0
>> PARAMETER C_CLKOUT2_GROUP = DCM0
>> PARAMETER C_CLKOUT3_FREQ = 200000000
>> PARAMETER C_CLKOUT3_BUF = TRUE
>> PARAMETER C_CLKOUT3_PHASE = 0
>> PARAMETER C_CLKOUT3_GROUP = NONE
>> PARAMETER C_CLKOUT4_FREQ = 125000000
>> PARAMETER C_CLKOUT4_BUF = TRUE
>> PARAMETER C_CLKOUT4_PHASE = 0
>> PARAMETER C_CLKOUT4_GROUP = NONE
>> PORT CLKOUT0 = sys_clk_s
>> PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_90_s
>> PORT CLKOUT2 = proc_clk_s
>> PORT CLKOUT3 = clk_200mhz_s
>> PORT CLKOUT4 = temac_clk_s
>> PORT CLKIN = dcm_clk_s
>> PORT LOCKED = Dcm_all_locked
>> PORT RST = net_gnd
>> END
>>
>> BEGIN proc_sys_reset
>> PARAMETER INSTANCE = proc_sys_reset_0
>> PARAMETER HW_VER = 2.00.a
>> PARAMETER C_EXT_RESET_HIGH = 0
>> BUS_INTERFACE RESETPPC0 = ppc_reset_bus
>> PORT Slowest_sync_clk = sys_clk_s
>> PORT Dcm_locked = Dcm_all_locked
>> PORT Ext_Reset_In = sys_rst_s
>> PORT Bus_Struct_Reset = sys_bus_reset
>> PORT Peripheral_Reset = sys_periph_reset
>> END
>>
>> BEGIN xps_intc
>> PARAMETER INSTANCE = xps_intc_0
>> PARAMETER HW_VER = 1.00.a
>> PARAMETER C_BASEADDR = 0x81800000
>> PARAMETER C_HIGHADDR = 0x8180ffff
>> BUS_INTERFACE SPLB = plb
>> PORT Irq = EICC405EXTINPUTIRQ
>> PORT Intr = RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt & IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ & TriMode_MAC_GMII_TemacIntc0_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut & DDR_SDRAM_SDMA2_Tx_IntOut
>> END
>>
>>
>>
>> #address-cells = <1>;
>> #size-cells = <1>;
>> compatible = "xlnx,virtex";
>> model = "testing";
>> DDR_SDRAM: memory@0 {
>> device_type = "memory";
>> reg = < 0 8000000 >;
>> } ;
>> chosen {
>> bootargs = "console=ttyS0,9600 ip=on nfsroot=172.16.40.76:/v2pclients/jhl26,tcp";
>> linux,stdout-path = "/plb@0/serial@83e00000";
>> } ;
>> cpus {
>> #address-cells = <1>;
>> #cpus = <1>;
>> #size-cells = <0>;
>> ppc405_0: cpu@0 {
>> clock-frequency = <11e1a300>;
>> compatible = "PowerPC,405", "ibm,ppc405";
>> d-cache-line-size = <20>;
>> d-cache-size = <4000>;
>> device_type = "cpu";
>> i-cache-line-size = <20>;
>> i-cache-size = <4000>;
>> model = "PowerPC,405";
>> reg = <0>;
>> timebase-frequency = <11e1a300>;
>> xlnx,apu-control = <de00>;
>> xlnx,apu-udi-1 = <a18983>;
>> xlnx,apu-udi-2 = <a38983>;
>> xlnx,apu-udi-3 = <a589c3>;
>> xlnx,apu-udi-4 = <a789c3>;
>> xlnx,apu-udi-5 = <a98c03>;
>> xlnx,apu-udi-6 = <ab8c03>;
>> xlnx,apu-udi-7 = <ad8c43>;
>> xlnx,apu-udi-8 = <af8c43>;
>> xlnx,deterministic-mult = <0>;
>> xlnx,disable-operand-forwarding = <1>;
>> xlnx,fastest-plb-clock = "DPLB0";
>> xlnx,generate-plb-timespecs = <1>;
>> xlnx,mmu-enable = <1>;
>> xlnx,pvr-high = <0>;
>> xlnx,pvr-low = <0>;
>> } ;
>> } ;
>> plb: plb@0 {
>> #address-cells = <1>;
>> #size-cells = <1>;
>> compatible = "xlnx,plb-v46-1.02.a";
>> ranges ;
>> IIC_EEPROM: i2c@81600000 {
>> compatible = "xlnx,xps-iic-2.00.a";
>> interrupt-parent = <&xps_intc_0>;
>> interrupts = < 4 2 >;
>> reg = < 81600000 10000 >;
>> xlnx,clk-freq = <5f5e100>;
>> xlnx,family = "virtex4";
>> xlnx,gpo-width = <1>;
>> xlnx,iic-freq = <186a0>;
>> xlnx,scl-inertial-delay = <0>;
>> xlnx,sda-inertial-delay = <0>;
>> xlnx,ten-bit-adr = <0>;
>> } ;
>> LEDs_4Bit: gpio@81400000 {
>> compatible = "xlnx,xps-gpio-1.00.a";
>> interrupt-parent = <&xps_intc_0>;
>> interrupts = < 5 2 >;
>> reg = < 81400000 10000 >;
>> xlnx,all-inputs = <0>;
>> xlnx,all-inputs-2 = <0>;
>> xlnx,dout-default = <0>;
>> xlnx,dout-default-2 = <0>;
>> xlnx,family = "virtex4";
>> xlnx,gpio-width = <4>;
>> xlnx,interrupt-present = <1>;
>> xlnx,is-bidir = <1>;
>> xlnx,is-bidir-2 = <1>;
>> xlnx,is-dual = <0>;
>> xlnx,tri-default = <ffffffff>;
>> xlnx,tri-default-2 = <ffffffff>;
>> } ;
>> RS232_Uart: serial@83e00000 {
>> compatible = "xlnx,xps-uart16550-2.00.a";
>> // compatible = "ns16550";
>> device_type = "serial";
>> interrupt-parent = <&xps_intc_0>;
>> interrupts = < 6 2 >;
>> reg = < 83e00000 10000 >;
>> current-speed = <d#9600>;
>> clock-frequency = <d#100000000>; /* added by jhl */
>> reg-shift = <2>;
>> xlnx,family = "virtex4";
>> xlnx,has-external-rclk = <0>;
>> xlnx,has-external-xin = <0>;
>> xlnx,is-a-16550 = <1>;
>> } ;
>> SysACE_CompactFlash: sysace@83600000 {
>> compatible = "xlnx,xps-sysace-1.00.a";
>> interrupt-parent = <&xps_intc_0>;
>> interrupts = < 3 2 >;
>> reg = < 83600000 10000 >;
>> xlnx,family = "virtex4";
>> xlnx,mem-width = <10>;
>> } ;
>> TriMode_MAC_GMII: xps-ll-temac@81c00000 {
>> #address-cells = <1>;
>> #size-cells = <1>;
>> compatible = "xlnx,compound";
>> ethernet@81c00000 {
>> compatible = "xlnx,xps-ll-temac-1.01.a";
>> device_type = "network";
>> interrupt-parent = <&xps_intc_0>;
>> interrupts = < 2 2 >;
>> llink-connected = <&PIM2>;
>> local-mac-address = [ 02 00 00 00 00 01 ];
>> reg = < 81c00000 40 >;
>> xlnx,bus2core-clk-ratio = <1>;
>> xlnx,phy-type = <1>;
>> xlnx,phyaddr = <1>;
>> xlnx,rxcsum = <0>;
>> xlnx,rxfifo = <1000>;
>> xlnx,temac-type = <1>;
>> xlnx,txcsum = <0>;
>> xlnx,txfifo = <1000>;
>> } ;
>> } ;
>> mpmc@0 {
>> #address-cells = <1>;
>> #size-cells = <1>;
>> compatible = "xlnx,mpmc-4.00.a";
>> PIM2: sdma@84600100 {
>> compatible = "xlnx,ll-dma-1.00.a";
>> interrupt-parent = <&xps_intc_0>;
>> interrupts = < 1 2 0 2 >;
>> reg = < 84600100 80 >;
>> } ;
>> } ;
>> xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 {
>> compatible = "xlnx,xps-bram-if-cntlr-1.00.a";
>> reg = < ffffe000 2000 >;
>> xlnx,family = "virtex4";
>> } ;
>> xps_intc_0: interrupt-controller@81800000 {
>> #interrupt-cells = <2>;
>> compatible = "xlnx,xps-intc-1.00.a";
>> interrupt-controller ;
>> reg = < 81800000 10000 >;
>> xlnx,num-intr-inputs = <7>;
>> } ;
>> } ;
>> ppc405_0_dplb1: plb@1 {
>> #address-cells = <1>;
>> #size-cells = <1>;
>> compatible = "xlnx,plb-v46-1.02.a";
>> ranges ;
>> } ;
>> } ;
>>
>>
>>
>> -----Original Message-----
>> From: Magnus Hjorth [mailto:mh@omnisys.se]
>> Sent: Saturday, March 29, 2008 6:54 AM
>> To: git
>> Cc: linuxppc-embedded@ozlabs.org
>> Subject: Xilinx LLTEMAC driver issues
>>
>> Hi,
>>
>> I'm having some networking troubles with the Xilinx LLTEMAC driver from the
>> Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,
>> xps_ll_temac v1.00.b
>>
>> The weird thing is, that it sort of half works. It successfully makes a DHCP
>> request and gets its IP address. I tried setting up a tftpd server, and I can
>> see UDP requests coming in but the response doesn't seem to come out. I also
>> tried running a TCP server on the board, and it can see and accept incoming
>> connections but after that no data seems to get through. I can ping out and
>> get around 40% packet loss.
>>
>> Looking at /proc/interrupts, I can see both TxDma interrupts and RxDma
>> interrupts. No eth0 interrupts but that seems to be OK judging by the driver
>> source comments. Ifconfig shows no collistions, no dropped packets, no errors,
>> so the system seems to think that everything is OK.
>>
>> Clues anyone? I'm starting to run out of ideas...
>>
>> Best regards,
>> Magnus
>>
>>
>> --
>>
>> Magnus Hjorth, M.Sc.
>> Omnisys Instruments AB
>> Gruvgatan 8
>> SE-421 30 Västra Frölunda, SWEDEN
>> Phone: +46 31 734 34 09
>> Fax: +46 31 734 34 29
>> http://www.omnisys.se
>>
>
> _______________________________________________
> Linuxppc-embedded mailing list
> Linuxppc-embedded@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: [PATCHv2 2/3] ep8248e: Reference SMC parameter RAM base in the device tree.
From: Laurent Pinchart @ 2008-03-31 9:08 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <47ED33FC.3020107@freescale.com>
[-- Attachment #1: Type: text/plain, Size: 3708 bytes --]
On Friday 28 March 2008 19:07, Scott Wood wrote:
> Laurent Pinchart wrote:
> > On Friday 28 March 2008 18:11, Scott Wood wrote:
> >> Laurent Pinchart wrote:
> >>> Locating the end of the muram isn't as straightforward as it
> >>> could be. As the current code already uses the beginning of the
> >>> muram to store the BDs and data buffers, should I really bother
> >>> locating the end or can I store the SMC parameter ram at the
> >>> beginning as well ?
> >> Maybe, but the end would be safer. What's the problem with finding
> >> the end?
> >
> > That requires manual parsing of all the cells in the reg property.
> > The device-tree API doesn't provide a way to get the length of a
> > property,
>
> Sure it does. Do a getprop with an insufficiently large buffer, and it
> tells you how much you really need. :-)
Ok thanks.
> > so I'll have to use a big enough pre-allocated buffer. I'm also not
> > sure if resources are guaranteed to be sorted in increasing order.
>
> Ah, good point.
>
> > This doesn't make finding the end of the muram really difficult. I
> > was just wondering if the increased code complexity was worth it,
> > especially seeing how the cpm_serial code in the boot wrapper seem
> > quite unstable.
>
> Unstable in what way?
I was refering to the virtual-reg (non-)issue I mentionned below.
> > I'm not familiar with the boot wrapper code so I'm sometimes not very
> > confident in my assumptions, but isn't the handling of the
> > virtual-reg property in cpm_console_init broken ?
>
> Not as far as I can see.
>
> > If I'm not mistaken, getprop will return the address and size of the
> > first resource and not the addresses of the first two resources.
>
> No, it'll get as much of the virtual-reg property as will fit in the
> buffer. There's no size in virtual-reg.
Ah right. Sorry about the misunderstanding.
> > What is virtual-reg used for ? To report the virtual address without
> > requiring a device tree walk ? Does it provide any information that
> > dt_xlate_reg can't find ?
>
> Yes, it tells you the virtual address when it's not an identity mapping.
> It's not currently used on CPM platforms, but might be used down the
> road with a QE device on 85xx.
Will the virtual-reg property on the muram node list the addresses of all
muram chunks or the address of the first chunk only ?
> >> Even the end of the first reg resource would be OK.
> >
> > If I use the end of the first resource, can I assume it spans 0x0000
> > - 0x8000 to set the default tx BD address in Kconfig ?
>
> No, especially seeing as it doesn't on any existing boards. :-)
I still need a default value :-) It obviously won't work for all boards.
> You could set the default to just before 0x2000 with board-specific
> exceptions, though.
We're getting a bit lost. I'll try to summarize the discussion.
- The muram node has a reg property that lists the offsets and sizes of all
muram chunks, and an optional virtual-reg property that lists the virtual
address of all chunks/the first chunk only.
- From the above information I can locate a section of muram at the end of the
first chunk (easy) or at the end of the muram (not really difficult, just a
bit more complex, especially if chunks are not sorted by their start
address).
- Kconfig needs a default address for the tx BD. This depends on the
allocation strategy (end of first chunk vs. end of last chunk). Is there some
consistent default across QE devices ?
--
Laurent Pinchart
CSE Semaphore Belgium
Chaussée de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
F +32 (2) 387 42 75
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
^ permalink raw reply
* Using FEC on a MPC5200 with default PHY configuration
From: Wolfgang Grandegger @ 2008-03-31 9:20 UTC (permalink / raw)
To: ppc-dev
Hello,
is it possible to use the FEC on a MPC5200 with the default hardware PHY
configuration. I mean running the link with a default speed without
handling or even touching the PHY like U-Boot does. I removed the PHY
entries from the DTS file and disabled CONFIG_FEC_MPC52xx_MDIO but it
did not work.
Any help is appreciated, TIA.
Wolfgang.
^ permalink raw reply
* Re: Using FEC on a MPC5200 with default PHY configuration
From: Wolfgang Grandegger @ 2008-03-31 9:44 UTC (permalink / raw)
To: Wolfgang Grandegger; +Cc: ppc-dev
In-Reply-To: <47F0ACC7.9080709@grandegger.com>
Wolfgang Grandegger wrote:
> Hello,
>
> is it possible to use the FEC on a MPC5200 with the default hardware PHY
> configuration. I mean running the link with a default speed without
> handling or even touching the PHY like U-Boot does. I removed the PHY
> entries from the DTS file and disabled CONFIG_FEC_MPC52xx_MDIO but it
> did not work.
To be more precise, I want to support a 3-Port managed switch with PHY
from Micrel using the direct switch link.
TIA.
Wolfgang.
^ permalink raw reply
* RE: Xilinx LLTEMAC driver issues
From: Magnus Hjorth @ 2008-03-31 11:10 UTC (permalink / raw)
To: 'rza1'; +Cc: linuxppc-embedded, 'John Linn', 'git'
In-Reply-To: <47F0AB74.4070802@so-logic.net>
Deactivating checksum offloading helped a lot! I still have some packet =
loss and not the best performance (TFTP transfer about 100 kbyte/s) but =
at least it works.=20
Thanks!
//Magnus
> -----Original Message-----
> From: rza1 [mailto:rza1@so-logic.net]
> Sent: den 31 mars 2008 11:14
> To: Magnus Hjorth
> Cc: John Linn; git; linuxppc-embedded@ozlabs.org
> Subject: Re: Xilinx LLTEMAC driver issues
>=20
> Hi Magnus,
>=20
> 1.
> I am using nearly the same versions then you and got the same problems
> too ;-).
> I think there are some problems with the checksum offloading.
> Try to sniff the some packages (e.g. wireshark)...
> For me ICMP (ping) worked but udp and tcp not (because off a wrong
> checksum in the transport layer).
> A quick solution is to just deactivate checksum offloading.
>=20
> 2.
> I remember some problems with Virtex-4 presamples too.
> There where problems with the hard-temac wrapper. You had to use =
1.00.a
> and not b version.
> But I don't have these problems with the EDK 9.2sp2/ISE9.2sp3 anymore.
>=20
> all the best,
> Robert
>=20
> Magnus Hjorth wrote:
> > Hi John,
> >
> > Thanks for the very fast reply! Right now I'm not at work so I don't
> > have the board or EDK here to test anything.
> >
> > I'm using checksum offload, but I don't know if DRE is enabled or =
not. I
> > can't recall seeing any setting to enable/disable DRE..
> >
> > A few things that crossed my mind:
> >
> > Last year I did a design with EDK 8.2, back then there was an issue =
with
> > the ML403 boards having an old revision of the FPGA which wasn't
> > compatible with some versions of the IP core. There are no such =
version
> > issues with the xps_ll_temac?
> >
> > I don't think that I had phy-addr set in the DTS file. Will test =
that on
> > Monday.
> >
> > Best regards,
> > Magnus
> >
> >
> > On Sat, 2008-03-29 at 07:58 -0600, John Linn wrote:
> >
> >> Hi Magnus,
> >>
> >> Sorry to hear you're having problems with it.
> >>
> >> I am doing testing on an ML405 which is the same board but with a =
bigger
> FPGA, but with ppc arch and I don't see this issue. I have done =
limited testing
> with powerpc arch and the LL TEMAC, but I didn't see this issue there =
either.
> Powerpc arch is definitely less mature in my experience than the ppc =
arch. I'll
> do a quick test with my powerpc arch and make sure again I'm not =
seeing it.
> >>
> >> My kernel is from the Xilinx Git tree, but there have been a number =
of
> changes we have pushed out so I don't know how long ago you pulled =
from the Git
> tree.
> >>
> >> My EDK project is 10.1 so it's a little newer. I am using LL TEMAC =
1.01a so
> it's a little newer. I reviewed the change log for the LL TEMAC and =
don't see
> any big problems that were fixed in the newer versions, more new =
features. I'll
> check with some others here to see if I missed something there.
> >>
> >> I am using DMA also, but no DRE or checksum offload. You didn't =
say anything
> about those. I'm going to insert my mhs file that describes my system =
to let you
> compare your system configuration. It's not clear to me yet if you =
have a h/w or
> s/w problem.
> >>
> >> I'll also insert some of my device tree with the LL TEMAC so you =
can compare
> (ignore 16550 stuff as we are still working on that).
> >>
> >> Since you can't ping reliably I would probably focus on that since =
it's
> simpler than the other issues you're seeing.
> >>
> >> Thanks,
> >> John
> >>
> >>
> >>
> >> #
> =
#########################################################################=
#####
> >> # Created by Base System Builder Wizard for Xilinx EDK 10.1.1 Build
> EDK_K_SP1.1
> >> # Thu Feb 14 14:11:12 2008
> >> # Target Board: Xilinx Virtex 4 ML405 Evaluation Platform Rev 1
> >> # Family: virtex4
> >> # Device: xc4vfx20
> >> # Package: ff672
> >> # Speed Grade: -10
> >> # Processor: ppc405_0
> >> # Processor clock frequency: 300.00 MHz
> >> # Bus clock frequency: 100.00 MHz
> >> # On Chip Memory : 8 KB
> >> # Total Off Chip Memory : 128 MB
> >> # - DDR_SDRAM =3D 128 MB
> >> #
> =
#########################################################################=
#####
> >> PARAMETER VERSION =3D 2.1.0
> >>
> >>
> >> PORT fpga_0_RS232_Uart_sin_pin =3D fpga_0_RS232_Uart_sin, DIR =3D =
I
> >> PORT fpga_0_RS232_Uart_sout_pin =3D fpga_0_RS232_Uart_sout, DIR =
=3D O
> >> PORT fpga_0_LEDs_4Bit_GPIO_IO_pin =3D fpga_0_LEDs_4Bit_GPIO_IO, =
DIR =3D IO, VEC
> =3D [0:3]
> >> PORT fpga_0_IIC_EEPROM_Scl_pin =3D fpga_0_IIC_EEPROM_Scl, DIR =3D =
IO
> >> PORT fpga_0_IIC_EEPROM_Sda_pin =3D fpga_0_IIC_EEPROM_Sda, DIR =3D =
IO
> >> PORT fpga_0_SysACE_CompactFlash_SysACE_CLK_pin =3D
> fpga_0_SysACE_CompactFlash_SysACE_CLK, DIR =3D I
> >> PORT fpga_0_SysACE_CompactFlash_SysACE_MPA_pin =3D
> fpga_0_SysACE_CompactFlash_SysACE_MPA, DIR =3D O, VEC =3D [6:1]
> >> PORT fpga_0_SysACE_CompactFlash_SysACE_MPD_pin =3D
> fpga_0_SysACE_CompactFlash_SysACE_MPD, DIR =3D IO, VEC =3D [15:0]
> >> PORT fpga_0_SysACE_CompactFlash_SysACE_CEN_pin =3D
> fpga_0_SysACE_CompactFlash_SysACE_CEN, DIR =3D O
> >> PORT fpga_0_SysACE_CompactFlash_SysACE_OEN_pin =3D
> fpga_0_SysACE_CompactFlash_SysACE_OEN, DIR =3D O
> >> PORT fpga_0_SysACE_CompactFlash_SysACE_WEN_pin =3D
> fpga_0_SysACE_CompactFlash_SysACE_WEN, DIR =3D O
> >> PORT fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin =3D
> fpga_0_SysACE_CompactFlash_SysACE_MPIRQ, DIR =3D I
> >> PORT fpga_0_DDR_SDRAM_DDR_Clk_pin =3D fpga_0_DDR_SDRAM_DDR_Clk, =
DIR =3D O
> >> PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin =3D =
fpga_0_DDR_SDRAM_DDR_Clk_n, DIR =3D O
> >> PORT fpga_0_DDR_SDRAM_DDR_Addr_pin =3D fpga_0_DDR_SDRAM_DDR_Addr, =
DIR =3D O, VEC
> =3D [12:0]
> >> PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin =3D =
fpga_0_DDR_SDRAM_DDR_BankAddr, DIR
> =3D O, VEC =3D [1:0]
> >> PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin =3D =
fpga_0_DDR_SDRAM_DDR_CAS_n, DIR =3D O
> >> PORT fpga_0_DDR_SDRAM_DDR_CE_pin =3D fpga_0_DDR_SDRAM_DDR_CE, DIR =
=3D O
> >> PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin =3D fpga_0_DDR_SDRAM_DDR_CS_n, =
DIR =3D O
> >> PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin =3D =
fpga_0_DDR_SDRAM_DDR_RAS_n, DIR =3D O
> >> PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin =3D fpga_0_DDR_SDRAM_DDR_WE_n, =
DIR =3D O
> >> PORT fpga_0_DDR_SDRAM_DDR_DM_pin =3D fpga_0_DDR_SDRAM_DDR_DM, DIR =
=3D O, VEC =3D
> [3:0]
> >> PORT fpga_0_DDR_SDRAM_DDR_DQS =3D fpga_0_DDR_SDRAM_DDR_DQS, DIR =
=3D IO, VEC =3D
> [3:0]
> >> PORT fpga_0_DDR_SDRAM_DDR_DQ =3D fpga_0_DDR_SDRAM_DDR_DQ, DIR =3D =
IO, VEC =3D
> [31:0]
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_TXD_0, DIR =3D O, VEC =3D [7:0]
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0, DIR =3D O
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0, DIR =3D O
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0, DIR =3D O
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_RXD_0, DIR =3D I, VEC =3D [7:0]
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0, DIR =3D I
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0, DIR =3D I
> >> PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin =3D
> fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0, DIR =3D I
> >> PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin =3D
> fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0, DIR =3D I
> >> PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin =3D =
fpga_0_TriMode_MAC_GMII_MDIO_0,
> DIR =3D IO
> >> PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin =3D =
fpga_0_TriMode_MAC_GMII_MDC_0, DIR
> =3D O
> >> PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin =3D
> fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n, DIR =3D O
> >> PORT sys_clk_pin =3D dcm_clk_s, DIR =3D I, SIGIS =3D CLK, CLK_FREQ =
=3D 100000000
> >> PORT sys_rst_pin =3D sys_rst_s, DIR =3D I, RST_POLARITY =3D 0, =
SIGIS =3D RST
> >>
> >>
> >> BEGIN ppc405_virtex4
> >> PARAMETER INSTANCE =3D ppc405_0
> >> PARAMETER HW_VER =3D 2.01.a
> >> PARAMETER C_FASTEST_PLB_CLOCK =3D DPLB1
> >> PARAMETER C_IDCR_BASEADDR =3D 0b0100000000
> >> PARAMETER C_IDCR_HIGHADDR =3D 0b0111111111
> >> BUS_INTERFACE JTAGPPC =3D jtagppc_0_0
> >> BUS_INTERFACE IPLB0 =3D plb
> >> BUS_INTERFACE DPLB0 =3D plb
> >> BUS_INTERFACE IPLB1 =3D ppc405_0_iplb1
> >> BUS_INTERFACE DPLB1 =3D ppc405_0_dplb1
> >> BUS_INTERFACE RESETPPC =3D ppc_reset_bus
> >> PORT CPMC405CLOCK =3D proc_clk_s
> >> PORT EICC405EXTINPUTIRQ =3D EICC405EXTINPUTIRQ
> >> END
> >>
> >> BEGIN jtagppc_cntlr
> >> PARAMETER INSTANCE =3D jtagppc_0
> >> PARAMETER HW_VER =3D 2.01.a
> >> BUS_INTERFACE JTAGPPC0 =3D jtagppc_0_0
> >> END
> >>
> >> BEGIN plb_v46
> >> PARAMETER INSTANCE =3D plb
> >> PARAMETER C_DCR_INTFCE =3D 0
> >> PARAMETER C_NUM_CLK_PLB2OPB_REARB =3D 100
> >> PARAMETER HW_VER =3D 1.02.a
> >> PORT PLB_Clk =3D sys_clk_s
> >> PORT SYS_Rst =3D sys_bus_reset
> >> END
> >>
> >> BEGIN xps_bram_if_cntlr
> >> PARAMETER INSTANCE =3D xps_bram_if_cntlr_1
> >> PARAMETER HW_VER =3D 1.00.a
> >> PARAMETER C_SPLB_NATIVE_DWIDTH =3D 64
> >> PARAMETER C_BASEADDR =3D 0xffffe000
> >> PARAMETER C_HIGHADDR =3D 0xffffffff
> >> BUS_INTERFACE SPLB =3D plb
> >> BUS_INTERFACE PORTA =3D xps_bram_if_cntlr_1_port
> >> END
> >>
> >> BEGIN bram_block
> >> PARAMETER INSTANCE =3D plb_bram_if_cntlr_1_bram
> >> PARAMETER HW_VER =3D 1.00.a
> >> BUS_INTERFACE PORTA =3D xps_bram_if_cntlr_1_port
> >> END
> >>
> >> BEGIN xps_uart16550
> >> PARAMETER INSTANCE =3D RS232_Uart
> >> PARAMETER HW_VER =3D 2.00.a
> >> PARAMETER C_IS_A_16550 =3D 1
> >> PARAMETER C_BASEADDR =3D 0x83e00000
> >> PARAMETER C_HIGHADDR =3D 0x83e0ffff
> >> BUS_INTERFACE SPLB =3D plb
> >> PORT sin =3D fpga_0_RS232_Uart_sin
> >> PORT sout =3D fpga_0_RS232_Uart_sout
> >> PORT IP2INTC_Irpt =3D RS232_Uart_IP2INTC_Irpt
> >> END
> >>
> >> BEGIN xps_gpio
> >> PARAMETER INSTANCE =3D LEDs_4Bit
> >> PARAMETER HW_VER =3D 1.00.a
> >> PARAMETER C_INTERRUPT_PRESENT =3D 1
> >> PARAMETER C_GPIO_WIDTH =3D 4
> >> PARAMETER C_IS_DUAL =3D 0
> >> PARAMETER C_IS_BIDIR =3D 1
> >> PARAMETER C_ALL_INPUTS =3D 0
> >> PARAMETER C_BASEADDR =3D 0x81400000
> >> PARAMETER C_HIGHADDR =3D 0x8140ffff
> >> BUS_INTERFACE SPLB =3D plb
> >> PORT GPIO_IO =3D fpga_0_LEDs_4Bit_GPIO_IO
> >> PORT IP2INTC_Irpt =3D LEDs_4Bit_IP2INTC_Irpt
> >> END
> >>
> >> BEGIN xps_iic
> >> PARAMETER INSTANCE =3D IIC_EEPROM
> >> PARAMETER HW_VER =3D 2.00.a
> >> PARAMETER C_CLK_FREQ =3D 100000000
> >> PARAMETER C_IIC_FREQ =3D 100000
> >> PARAMETER C_TEN_BIT_ADR =3D 0
> >> PARAMETER C_BASEADDR =3D 0x81600000
> >> PARAMETER C_HIGHADDR =3D 0x8160ffff
> >> BUS_INTERFACE SPLB =3D plb
> >> PORT Scl =3D fpga_0_IIC_EEPROM_Scl
> >> PORT Sda =3D fpga_0_IIC_EEPROM_Sda
> >> PORT IIC2INTC_Irpt =3D IIC_EEPROM_IIC2INTC_Irpt
> >> END
> >>
> >> BEGIN xps_sysace
> >> PARAMETER INSTANCE =3D SysACE_CompactFlash
> >> PARAMETER HW_VER =3D 1.00.a
> >> PARAMETER C_MEM_WIDTH =3D 16
> >> PARAMETER C_BASEADDR =3D 0x83600000
> >> PARAMETER C_HIGHADDR =3D 0x8360ffff
> >> BUS_INTERFACE SPLB =3D plb
> >> PORT SysACE_CLK =3D fpga_0_SysACE_CompactFlash_SysACE_CLK
> >> PORT SysACE_MPA =3D fpga_0_SysACE_CompactFlash_SysACE_MPA_split
> >> PORT SysACE_MPD =3D fpga_0_SysACE_CompactFlash_SysACE_MPD
> >> PORT SysACE_CEN =3D fpga_0_SysACE_CompactFlash_SysACE_CEN
> >> PORT SysACE_OEN =3D fpga_0_SysACE_CompactFlash_SysACE_OEN
> >> PORT SysACE_WEN =3D fpga_0_SysACE_CompactFlash_SysACE_WEN
> >> PORT SysACE_MPIRQ =3D fpga_0_SysACE_CompactFlash_SysACE_MPIRQ
> >> PORT SysACE_IRQ =3D SysACE_CompactFlash_SysACE_IRQ
> >> END
> >>
> >> BEGIN mpmc
> >> PARAMETER INSTANCE =3D DDR_SDRAM
> >> PARAMETER HW_VER =3D 4.00.a
> >> PARAMETER C_NUM_PORTS =3D 3
> >> PARAMETER C_MEM_PARTNO =3D HYB25D512160BE-5
> >> PARAMETER C_MEM_DATA_WIDTH =3D 32
> >> PARAMETER C_MEM_DQS_WIDTH =3D 4
> >> PARAMETER C_MEM_DM_WIDTH =3D 4
> >> PARAMETER C_MEM_TYPE =3D DDR
> >> PARAMETER C_NUM_IDELAYCTRL =3D 2
> >> PARAMETER C_IDELAYCTRL_LOC =3D IDELAYCTRL_X0Y3-IDELAYCTRL_X0Y2
> >> PARAMETER C_PIM0_BASETYPE =3D 2
> >> PARAMETER C_PIM1_BASETYPE =3D 2
> >> PARAMETER C_PIM2_BASETYPE =3D 3
> >> PARAMETER C_MPMC_CLK0_PERIOD_PS =3D 10000
> >> PARAMETER C_SDMA2_PI2LL_CLK_RATIO =3D 1
> >> PARAMETER C_MPMC_BASEADDR =3D 0x00000000
> >> PARAMETER C_MPMC_HIGHADDR =3D 0x07ffffff
> >> PARAMETER C_SDMA_CTRL_BASEADDR =3D 0x84600000
> >> PARAMETER C_SDMA_CTRL_HIGHADDR =3D 0x8460ffff
> >> BUS_INTERFACE SPLB0 =3D ppc405_0_iplb1
> >> BUS_INTERFACE SPLB1 =3D ppc405_0_dplb1
> >> BUS_INTERFACE SDMA_LL2 =3D TriMode_MAC_GMII_LLINK0
> >> BUS_INTERFACE SDMA_CTRL2 =3D plb
> >> PORT DDR_Addr =3D fpga_0_DDR_SDRAM_DDR_Addr
> >> PORT DDR_BankAddr =3D fpga_0_DDR_SDRAM_DDR_BankAddr
> >> PORT DDR_CAS_n =3D fpga_0_DDR_SDRAM_DDR_CAS_n
> >> PORT DDR_CE =3D fpga_0_DDR_SDRAM_DDR_CE
> >> PORT DDR_CS_n =3D fpga_0_DDR_SDRAM_DDR_CS_n
> >> PORT DDR_RAS_n =3D fpga_0_DDR_SDRAM_DDR_RAS_n
> >> PORT DDR_WE_n =3D fpga_0_DDR_SDRAM_DDR_WE_n
> >> PORT DDR_DM =3D fpga_0_DDR_SDRAM_DDR_DM
> >> PORT DDR_DQS =3D fpga_0_DDR_SDRAM_DDR_DQS
> >> PORT DDR_DQ =3D fpga_0_DDR_SDRAM_DDR_DQ
> >> PORT DDR_Clk =3D fpga_0_DDR_SDRAM_DDR_Clk
> >> PORT DDR_Clk_n =3D fpga_0_DDR_SDRAM_DDR_Clk_n
> >> PORT MPMC_Clk0 =3D sys_clk_s
> >> PORT MPMC_Clk90 =3D DDR_SDRAM_mpmc_clk_90_s
> >> PORT SDMA2_Clk =3D sys_clk_s
> >> PORT MPMC_Clk_200MHz =3D clk_200mhz_s
> >> PORT MPMC_Rst =3D sys_periph_reset
> >> PORT SDMA2_Rx_IntOut =3D DDR_SDRAM_SDMA2_Rx_IntOut
> >> PORT SDMA2_Tx_IntOut =3D DDR_SDRAM_SDMA2_Tx_IntOut
> >> END
> >>
> >> BEGIN xps_ll_temac
> >> PARAMETER INSTANCE =3D TriMode_MAC_GMII
> >> PARAMETER HW_VER =3D 1.01.a
> >> PARAMETER C_SPLB_CLK_PERIOD_PS =3D 10000
> >> PARAMETER C_PHY_TYPE =3D 1
> >> PARAMETER C_NUM_IDELAYCTRL =3D 4
> >> PARAMETER C_IDELAYCTRL_LOC =3D IDELAYCTRL_X1Y1-IDELAYCTRL_X1Y3-
> IDELAYCTRL_X2Y2-IDELAYCTRL_X2Y3
> >> PARAMETER C_TEMAC_TYPE =3D 1
> >> PARAMETER C_BUS2CORE_CLK_RATIO =3D 1
> >> PARAMETER C_BASEADDR =3D 0x81c00000
> >> PARAMETER C_HIGHADDR =3D 0x81c0ffff
> >> BUS_INTERFACE SPLB =3D plb
> >> BUS_INTERFACE LLINK0 =3D TriMode_MAC_GMII_LLINK0
> >> PORT GMII_TXD_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TXD_0
> >> PORT GMII_TX_EN_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0
> >> PORT GMII_TX_ER_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0
> >> PORT GMII_TX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0
> >> PORT GMII_RXD_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RXD_0
> >> PORT GMII_RX_DV_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0
> >> PORT GMII_RX_ER_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0
> >> PORT GMII_RX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0
> >> PORT MII_TX_CLK_0 =3D fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0
> >> PORT MDIO_0 =3D fpga_0_TriMode_MAC_GMII_MDIO_0
> >> PORT MDC_0 =3D fpga_0_TriMode_MAC_GMII_MDC_0
> >> PORT TemacPhy_RST_n =3D fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n
> >> PORT GTX_CLK_0 =3D temac_clk_s
> >> PORT REFCLK =3D clk_200mhz_s
> >> PORT LlinkTemac0_CLK =3D sys_clk_s
> >> PORT TemacIntc0_Irpt =3D TriMode_MAC_GMII_TemacIntc0_Irpt
> >> END
> >>
> >> BEGIN util_bus_split
> >> PARAMETER INSTANCE =3D SysACE_CompactFlash_util_bus_split_0
> >> PARAMETER HW_VER =3D 1.00.a
> >> PARAMETER C_SIZE_IN =3D 7
> >> PARAMETER C_LEFT_POS =3D 0
> >> PARAMETER C_SPLIT =3D 6
> >> PORT Sig =3D fpga_0_SysACE_CompactFlash_SysACE_MPA_split
> >> PORT Out1 =3D fpga_0_SysACE_CompactFlash_SysACE_MPA
> >> END
> >>
> >> BEGIN plb_v46
> >> PARAMETER INSTANCE =3D ppc405_0_iplb1
> >> PARAMETER HW_VER =3D 1.02.a
> >> PORT PLB_Clk =3D sys_clk_s
> >> PORT SYS_Rst =3D sys_bus_reset
> >> END
> >>
> >> BEGIN plb_v46
> >> PARAMETER INSTANCE =3D ppc405_0_dplb1
> >> PARAMETER HW_VER =3D 1.02.a
> >> PORT PLB_Clk =3D sys_clk_s
> >> PORT SYS_Rst =3D sys_bus_reset
> >> END
> >>
> >> BEGIN clock_generator
> >> PARAMETER INSTANCE =3D clock_generator_0
> >> PARAMETER HW_VER =3D 2.00.a
> >> PARAMETER C_EXT_RESET_HIGH =3D 1
> >> PARAMETER C_CLKIN_FREQ =3D 100000000
> >> PARAMETER C_CLKOUT0_FREQ =3D 100000000
> >> PARAMETER C_CLKOUT0_BUF =3D TRUE
> >> PARAMETER C_CLKOUT0_PHASE =3D 0
> >> PARAMETER C_CLKOUT0_GROUP =3D DCM0
> >> PARAMETER C_CLKOUT1_FREQ =3D 100000000
> >> PARAMETER C_CLKOUT1_BUF =3D TRUE
> >> PARAMETER C_CLKOUT1_PHASE =3D 90
> >> PARAMETER C_CLKOUT1_GROUP =3D DCM0
> >> PARAMETER C_CLKOUT2_FREQ =3D 300000000
> >> PARAMETER C_CLKOUT2_BUF =3D TRUE
> >> PARAMETER C_CLKOUT2_PHASE =3D 0
> >> PARAMETER C_CLKOUT2_GROUP =3D DCM0
> >> PARAMETER C_CLKOUT3_FREQ =3D 200000000
> >> PARAMETER C_CLKOUT3_BUF =3D TRUE
> >> PARAMETER C_CLKOUT3_PHASE =3D 0
> >> PARAMETER C_CLKOUT3_GROUP =3D NONE
> >> PARAMETER C_CLKOUT4_FREQ =3D 125000000
> >> PARAMETER C_CLKOUT4_BUF =3D TRUE
> >> PARAMETER C_CLKOUT4_PHASE =3D 0
> >> PARAMETER C_CLKOUT4_GROUP =3D NONE
> >> PORT CLKOUT0 =3D sys_clk_s
> >> PORT CLKOUT1 =3D DDR_SDRAM_mpmc_clk_90_s
> >> PORT CLKOUT2 =3D proc_clk_s
> >> PORT CLKOUT3 =3D clk_200mhz_s
> >> PORT CLKOUT4 =3D temac_clk_s
> >> PORT CLKIN =3D dcm_clk_s
> >> PORT LOCKED =3D Dcm_all_locked
> >> PORT RST =3D net_gnd
> >> END
> >>
> >> BEGIN proc_sys_reset
> >> PARAMETER INSTANCE =3D proc_sys_reset_0
> >> PARAMETER HW_VER =3D 2.00.a
> >> PARAMETER C_EXT_RESET_HIGH =3D 0
> >> BUS_INTERFACE RESETPPC0 =3D ppc_reset_bus
> >> PORT Slowest_sync_clk =3D sys_clk_s
> >> PORT Dcm_locked =3D Dcm_all_locked
> >> PORT Ext_Reset_In =3D sys_rst_s
> >> PORT Bus_Struct_Reset =3D sys_bus_reset
> >> PORT Peripheral_Reset =3D sys_periph_reset
> >> END
> >>
> >> BEGIN xps_intc
> >> PARAMETER INSTANCE =3D xps_intc_0
> >> PARAMETER HW_VER =3D 1.00.a
> >> PARAMETER C_BASEADDR =3D 0x81800000
> >> PARAMETER C_HIGHADDR =3D 0x8180ffff
> >> BUS_INTERFACE SPLB =3D plb
> >> PORT Irq =3D EICC405EXTINPUTIRQ
> >> PORT Intr =3D RS232_Uart_IP2INTC_Irpt & LEDs_4Bit_IP2INTC_Irpt &
> IIC_EEPROM_IIC2INTC_Irpt & SysACE_CompactFlash_SysACE_IRQ &
> TriMode_MAC_GMII_TemacIntc0_Irpt & DDR_SDRAM_SDMA2_Rx_IntOut &
> DDR_SDRAM_SDMA2_Tx_IntOut
> >> END
> >>
> >>
> >>
> >> #address-cells =3D <1>;
> >> #size-cells =3D <1>;
> >> compatible =3D "xlnx,virtex";
> >> model =3D "testing";
> >> DDR_SDRAM: memory@0 {
> >> device_type =3D "memory";
> >> reg =3D < 0 8000000 >;
> >> } ;
> >> chosen {
> >> bootargs =3D "console=3DttyS0,9600 ip=3Don
> nfsroot=3D172.16.40.76:/v2pclients/jhl26,tcp";
> >> linux,stdout-path =3D "/plb@0/serial@83e00000";
> >> } ;
> >> cpus {
> >> #address-cells =3D <1>;
> >> #cpus =3D <1>;
> >> #size-cells =3D <0>;
> >> ppc405_0: cpu@0 {
> >> clock-frequency =3D <11e1a300>;
> >> compatible =3D "PowerPC,405", "ibm,ppc405";
> >> d-cache-line-size =3D <20>;
> >> d-cache-size =3D <4000>;
> >> device_type =3D "cpu";
> >> i-cache-line-size =3D <20>;
> >> i-cache-size =3D <4000>;
> >> model =3D "PowerPC,405";
> >> reg =3D <0>;
> >> timebase-frequency =3D <11e1a300>;
> >> xlnx,apu-control =3D <de00>;
> >> xlnx,apu-udi-1 =3D <a18983>;
> >> xlnx,apu-udi-2 =3D <a38983>;
> >> xlnx,apu-udi-3 =3D <a589c3>;
> >> xlnx,apu-udi-4 =3D <a789c3>;
> >> xlnx,apu-udi-5 =3D <a98c03>;
> >> xlnx,apu-udi-6 =3D <ab8c03>;
> >> xlnx,apu-udi-7 =3D <ad8c43>;
> >> xlnx,apu-udi-8 =3D <af8c43>;
> >> xlnx,deterministic-mult =3D <0>;
> >> xlnx,disable-operand-forwarding =3D <1>;
> >> xlnx,fastest-plb-clock =3D "DPLB0";
> >> xlnx,generate-plb-timespecs =3D <1>;
> >> xlnx,mmu-enable =3D <1>;
> >> xlnx,pvr-high =3D <0>;
> >> xlnx,pvr-low =3D <0>;
> >> } ;
> >> } ;
> >> plb: plb@0 {
> >> #address-cells =3D <1>;
> >> #size-cells =3D <1>;
> >> compatible =3D "xlnx,plb-v46-1.02.a";
> >> ranges ;
> >> IIC_EEPROM: i2c@81600000 {
> >> compatible =3D "xlnx,xps-iic-2.00.a";
> >> interrupt-parent =3D <&xps_intc_0>;
> >> interrupts =3D < 4 2 >;
> >> reg =3D < 81600000 10000 >;
> >> xlnx,clk-freq =3D <5f5e100>;
> >> xlnx,family =3D "virtex4";
> >> xlnx,gpo-width =3D <1>;
> >> xlnx,iic-freq =3D <186a0>;
> >> xlnx,scl-inertial-delay =3D <0>;
> >> xlnx,sda-inertial-delay =3D <0>;
> >> xlnx,ten-bit-adr =3D <0>;
> >> } ;
> >> LEDs_4Bit: gpio@81400000 {
> >> compatible =3D "xlnx,xps-gpio-1.00.a";
> >> interrupt-parent =3D <&xps_intc_0>;
> >> interrupts =3D < 5 2 >;
> >> reg =3D < 81400000 10000 >;
> >> xlnx,all-inputs =3D <0>;
> >> xlnx,all-inputs-2 =3D <0>;
> >> xlnx,dout-default =3D <0>;
> >> xlnx,dout-default-2 =3D <0>;
> >> xlnx,family =3D "virtex4";
> >> xlnx,gpio-width =3D <4>;
> >> xlnx,interrupt-present =3D <1>;
> >> xlnx,is-bidir =3D <1>;
> >> xlnx,is-bidir-2 =3D <1>;
> >> xlnx,is-dual =3D <0>;
> >> xlnx,tri-default =3D <ffffffff>;
> >> xlnx,tri-default-2 =3D <ffffffff>;
> >> } ;
> >> RS232_Uart: serial@83e00000 {
> >> compatible =3D "xlnx,xps-uart16550-2.00.a";
> >> // compatible =3D "ns16550";
> >> device_type =3D "serial";
> >> interrupt-parent =3D <&xps_intc_0>;
> >> interrupts =3D < 6 2 >;
> >> reg =3D < 83e00000 10000 >;
> >> current-speed =3D <d#9600>;
> >> clock-frequency =3D <d#100000000>; /* added
> by jhl */
> >> reg-shift =3D <2>;
> >> xlnx,family =3D "virtex4";
> >> xlnx,has-external-rclk =3D <0>;
> >> xlnx,has-external-xin =3D <0>;
> >> xlnx,is-a-16550 =3D <1>;
> >> } ;
> >> SysACE_CompactFlash: sysace@83600000 {
> >> compatible =3D "xlnx,xps-sysace-1.00.a";
> >> interrupt-parent =3D <&xps_intc_0>;
> >> interrupts =3D < 3 2 >;
> >> reg =3D < 83600000 10000 >;
> >> xlnx,family =3D "virtex4";
> >> xlnx,mem-width =3D <10>;
> >> } ;
> >> TriMode_MAC_GMII: xps-ll-temac@81c00000 {
> >> #address-cells =3D <1>;
> >> #size-cells =3D <1>;
> >> compatible =3D "xlnx,compound";
> >> ethernet@81c00000 {
> >> compatible =3D "xlnx,xps-ll-temac-
> 1.01.a";
> >> device_type =3D "network";
> >> interrupt-parent =3D
> <&xps_intc_0>;
> >> interrupts =3D < 2 2 >;
> >> llink-connected =3D <&PIM2>;
> >> local-mac-address =3D [ 02 00 00
> 00 00 01 ];
> >> reg =3D < 81c00000 40 >;
> >> xlnx,bus2core-clk-ratio =3D <1>;
> >> xlnx,phy-type =3D <1>;
> >> xlnx,phyaddr =3D <1>;
> >> xlnx,rxcsum =3D <0>;
> >> xlnx,rxfifo =3D <1000>;
> >> xlnx,temac-type =3D <1>;
> >> xlnx,txcsum =3D <0>;
> >> xlnx,txfifo =3D <1000>;
> >> } ;
> >> } ;
> >> mpmc@0 {
> >> #address-cells =3D <1>;
> >> #size-cells =3D <1>;
> >> compatible =3D "xlnx,mpmc-4.00.a";
> >> PIM2: sdma@84600100 {
> >> compatible =3D "xlnx,ll-dma-
> 1.00.a";
> >> interrupt-parent =3D
> <&xps_intc_0>;
> >> interrupts =3D < 1 2 0 2 >;
> >> reg =3D < 84600100 80 >;
> >> } ;
> >> } ;
> >> xps_bram_if_cntlr_1: xps-bram-if-cntlr@ffffe000 {
> >> compatible =3D "xlnx,xps-bram-if-cntlr-
> 1.00.a";
> >> reg =3D < ffffe000 2000 >;
> >> xlnx,family =3D "virtex4";
> >> } ;
> >> xps_intc_0: interrupt-controller@81800000 {
> >> #interrupt-cells =3D <2>;
> >> compatible =3D "xlnx,xps-intc-1.00.a";
> >> interrupt-controller ;
> >> reg =3D < 81800000 10000 >;
> >> xlnx,num-intr-inputs =3D <7>;
> >> } ;
> >> } ;
> >> ppc405_0_dplb1: plb@1 {
> >> #address-cells =3D <1>;
> >> #size-cells =3D <1>;
> >> compatible =3D "xlnx,plb-v46-1.02.a";
> >> ranges ;
> >> } ;
> >> } ;
> >>
> >>
> >>
> >> -----Original Message-----
> >> From: Magnus Hjorth [mailto:mh@omnisys.se]
> >> Sent: Saturday, March 29, 2008 6:54 AM
> >> To: git
> >> Cc: linuxppc-embedded@ozlabs.org
> >> Subject: Xilinx LLTEMAC driver issues
> >>
> >> Hi,
> >>
> >> I'm having some networking troubles with the Xilinx LLTEMAC driver =
from the
> >> Xilinx Linux git tree (powerpc arch) on an ML403 board. EDK9.2SP2,
> >> xps_ll_temac v1.00.b
> >>
> >> The weird thing is, that it sort of half works. It successfully =
makes a DHCP
> >> request and gets its IP address. I tried setting up a tftpd server, =
and I can
> >> see UDP requests coming in but the response doesn't seem to come =
out. I also
> >> tried running a TCP server on the board, and it can see and accept =
incoming
> >> connections but after that no data seems to get through. I can ping =
out and
> >> get around 40% packet loss.
> >>
> >> Looking at /proc/interrupts, I can see both TxDma interrupts and =
RxDma
> >> interrupts. No eth0 interrupts but that seems to be OK judging by =
the driver
> >> source comments. Ifconfig shows no collistions, no dropped packets, =
no
> errors,
> >> so the system seems to think that everything is OK.
> >>
> >> Clues anyone? I'm starting to run out of ideas...
> >>
> >> Best regards,
> >> Magnus
> >>
> >>
> >> --
> >>
> >> Magnus Hjorth, M.Sc.
> >> Omnisys Instruments AB
> >> Gruvgatan 8
> >> SE-421 30 V=C3=A4stra Fr=C3=B6lunda, SWEDEN
> >> Phone: +46 31 734 34 09
> >> Fax: +46 31 734 34 29
> >> http://www.omnisys.se
> >>
> >
> > _______________________________________________
> > Linuxppc-embedded mailing list
> > Linuxppc-embedded@ozlabs.org
> > https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* Re: [PATCH] powerpc/pseries/xcis: ansify
From: David Howells @ 2008-03-31 12:07 UTC (permalink / raw)
To: Al Viro; +Cc: linuxppc-dev, torvalds, linux-kernel
In-Reply-To: <E1JfRSo-00030J-LV@ZenIV.linux.org.uk>
Al Viro <viro@ftp.linux.org.uk> wrote:
> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Acked-by: David Howells <dhowells@redhat.com>
^ permalink raw reply
* Re: OF compatible MTD platform RAM driver ?
From: Segher Boessenkool @ 2008-03-31 12:21 UTC (permalink / raw)
To: Laurent Pinchart
Cc: ben, linux-mtd, Paul Mackerras, linuxppc-dev, David Gibson
In-Reply-To: <200803311021.28919.laurentp@cse-semaphore.com>
>> So, all in all, I think we should just give these "auxiliary memory"
>> devices a name of "ram" c.q. "rom", and some "reg", and that should
>> be all that is needed: the main memory probe stuff won't consider
>> these nodes, and the (platform) device probe code can do whatever it
>> wants (create mtd devices, I guess).
>
> Ok, I get your point. I'll prepare a new documentation patch; changes
> to
> physmap_of.c will go away.
Thanks.
> If I understand you correctly, there should be no "compatible"
> property on the
> ram and rom devices.
They aren't normally needed here, I think.
> Should the "non-volatile", "slow" and "static ram"
> properties still be expressed in the device tree ?
If those are useful. I'll need to see a proposed binding to form
an opinion on this, it's too vague now, sorry.
Segher
^ permalink raw reply
* [PATCH] mpc83xx SPI glitch
From: Mike Hench @ 2008-03-31 13:04 UTC (permalink / raw)
To: linuxppc-dev
dont write SPMODE reg unless mode changed.
it causes SPI to go hi-z momentarily
which can cause a spike on the CLK line
this is a problem in MMC where /CS is held asserted
across multiple transactions.
Signed-off-by: Mike Hench <mhench@elutions.com>
---
--- linux-2.6.25-rc5.orig/drivers/spi/spi_mpc83xx.c 2008-03-10
00:22:27.000000000 -0500
+++ linux-2.6.25-rc5/drivers/spi/spi_mpc83xx.c 2008-03-31
07:37:37.000000000 -0500
@@ -147,6 +147,7 @@
=20
if (value =3D=3D BITBANG_CS_ACTIVE) {
u32 regval =3D
mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
+ u32 regval0 =3D regval;
u32 len =3D spi->bits_per_word;
u8 pm;
=20
@@ -188,9 +189,16 @@
regval |=3D SPMODE_PM(pm);
}
=20
- /* Turn off SPI unit prior changing mode */
- mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
- mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
+ // dont write reg unless mode changed.
+ // it causes SPI to go hi-z momentarily
+ // which can cause a spike on the CLK line
+ // this is a problem in MMC where /CS is held asserted
+ // across multiple transactions.
+ if(regval !=3D regval0) {
+ /* Turn off SPI unit prior changing mode */
+ mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode,
0);
+ mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode,
regval);
+ }
if (mpc83xx_spi->activate_cs)
mpc83xx_spi->activate_cs(spi->chip_select, pol);
}
^ permalink raw reply
* [PATCH] Add idle power save for ppc 4xx
From: Jerone Young @ 2008-03-31 13:12 UTC (permalink / raw)
To: linuxppc-dev; +Cc: kvm-ppc-devel
# HG changeset patch
# User Jerone Young <jyoung5@us.ibm.com>
# Date 1206969060 18000
# Node ID 10aea37177130bbe5de7bee6ec06d9010bc5da1f
# Parent 1506aa38ddabb0bf73fff3ac3f3db5f9ef6458cc
Add idle power save for ppc 4xx
This patch sets the wait state MSR when power_save is called in cpu_idle loop for ppc4xx. This is mainly to help out virtualization solutions such as KVM. This way the virtualization soultions are able to tell if the guest kernel is idle.
I have tested this on hardware & KVM virtual guest.
Signed-off-by: Jerone Young <jyoung5@us.ibm.com>
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_GENERIC_TBSYNC) += smp-tbsy
obj-$(CONFIG_GENERIC_TBSYNC) += smp-tbsync.o
obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
obj-$(CONFIG_6xx) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o
+obj-$(CONFIG_4xx) += idle_4xx.o
obj-$(CONFIG_TAU) += tau_6xx.o
obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o \
swsusp_$(CONFIG_WORD_SIZE).o
diff --git a/arch/powerpc/kernel/idle_4xx.c b/arch/powerpc/kernel/idle_4xx.c
new file mode 100644
--- /dev/null
+++ b/arch/powerpc/kernel/idle_4xx.c
@@ -0,0 +1,24 @@
+/*
+ * This file contains the power_save function for 4xx CPUs
+ *
+ * added by Jerone Young <jyoung5@us.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/processor.h>
+#include <asm/machdep.h>
+
+void ppc4xx_idle()
+{
+ unsigned long msr_save;
+
+ /* set wait state MSR */
+ local_irq_enable();
+ msr_save = mfmsr();
+ mtmsr(msr_save|MSR_WE);
+ local_irq_disable();
+}
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -132,6 +132,10 @@ void __init machine_init(unsigned long d
if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
cpu_has_feature(CPU_FTR_CAN_NAP))
ppc_md.power_save = ppc6xx_idle;
+#endif
+
+#ifdef CONFIG_4xx
+ ppc_md.power_save = ppc4xx_idle;
#endif
if (ppc_md.progress)
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
--- a/include/asm-powerpc/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -266,6 +266,7 @@ extern void power4_idle(void);
extern void power4_idle(void);
extern void power4_cpu_offline_powersave(void);
extern void ppc6xx_idle(void);
+extern void ppc4xx_idle(void);
/*
* ppc_md contains a copy of the machine description structure for the
^ permalink raw reply
* Re: [PATCH] mpc83xx SPI glitch
From: Joakim Tjernlund @ 2008-03-31 13:23 UTC (permalink / raw)
To: Mike Hench; +Cc: linuxppc-dev
In-Reply-To: <6629C06B144F5C4098DFF95C4FF9DAF702BA1FA0@mailsrv.engagenet.com>
Mike
I already sent a patch some time ago, it addresses this bug and
alot more. See spi-devel-general
<spi-devel-general@lists.sourceforge.net>,
I am waiting for David B. to comment/apply it. If you want to see this
in 2.6.25 I suggest you remind 'David Brownell' <david-b@pacbell.net>
Jocke
On Mon, 2008-03-31 at 08:04 -0500, Mike Hench wrote:
> dont write SPMODE reg unless mode changed.
> it causes SPI to go hi-z momentarily
> which can cause a spike on the CLK line
> this is a problem in MMC where /CS is held asserted
> across multiple transactions.
>=20
> Signed-off-by: Mike Hench <mhench@elutions.com>
>=20
> ---
>=20
> --- linux-2.6.25-rc5.orig/drivers/spi/spi_mpc83xx.c 2008-03-10
> 00:22:27.000000000 -0500
> +++ linux-2.6.25-rc5/drivers/spi/spi_mpc83xx.c 2008-03-31
> 07:37:37.000000000 -0500
> @@ -147,6 +147,7 @@
> =20
> if (value =3D=3D BITBANG_CS_ACTIVE) {
> u32 regval =3D
> mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
> + u32 regval0 =3D regval;
> u32 len =3D spi->bits_per_word;
> u8 pm;
> =20
> @@ -188,9 +189,16 @@
> regval |=3D SPMODE_PM(pm);
> }
> =20
> - /* Turn off SPI unit prior changing mode */
> - mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
> - mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
> + // dont write reg unless mode changed.
> + // it causes SPI to go hi-z momentarily
> + // which can cause a spike on the CLK line
> + // this is a problem in MMC where /CS is held asserted
> + // across multiple transactions.
> + if(regval !=3D regval0) {
> + /* Turn off SPI unit prior changing mode */
> + mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode,
> 0);
> + mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode,
> regval);
> + }
> if (mpc83xx_spi->activate_cs)
> mpc83xx_spi->activate_cs(spi->chip_select, pol);
> }
>=20
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>=20
>=20
^ permalink raw reply
* Re: Using FEC on a MPC5200 with default PHY configuration
From: Grant Likely @ 2008-03-31 13:33 UTC (permalink / raw)
To: Wolfgang Grandegger; +Cc: ppc-dev
In-Reply-To: <47F0B26A.10801@grandegger.com>
On Mon, Mar 31, 2008 at 3:44 AM, Wolfgang Grandegger <wg@grandegger.com> wrote:
> Wolfgang Grandegger wrote:
> > Hello,
> >
> > is it possible to use the FEC on a MPC5200 with the default hardware PHY
> > configuration. I mean running the link with a default speed without
> > handling or even touching the PHY like U-Boot does. I removed the PHY
> > entries from the DTS file and disabled CONFIG_FEC_MPC52xx_MDIO but it
> > did not work.
>
> To be more precise, I want to support a 3-Port managed switch with PHY
> from Micrel using the direct switch link.
I'm actually working on this exact problem at the moment. I'll get a
patch out shortly to do so.
Cheers,
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* RE: U-boot + Linux 2.6 + Avnet FX12 MM (based on ML403 config)
From: John Linn @ 2008-03-31 14:22 UTC (permalink / raw)
To: Mirek23, linuxppc-embedded
In-Reply-To: <16384525.post@talk.nabble.com>
Hi Mirek,
Our Git server from Xilinx, git.xilinx.com, has a kernel that is 2.6.24
based if this helps.=20
All of my testing for Virtex 4 is on the ML405 board which is an FX20
device rather than an FX12, but the kernel configuration is pretty much
compatible.
Thanks,
John
-----Original Message-----
From: linuxppc-embedded-bounces+john.linn=3Dxilinx.com@ozlabs.org
[mailto:linuxppc-embedded-bounces+john.linn=3Dxilinx.com@ozlabs.org] On
Behalf Of Mirek23
Sent: Sunday, March 30, 2008 11:21 AM
To: linuxppc-embedded@ozlabs.org
Subject: Re: U-boot + Linux 2.6 + Avnet FX12 MM (based on ML403 config)
Hi Guillaume,
I was facing the same problem with my Avent (virtex 4 FX12) evaluation
board. Originally I have built successfully u-boot 1.2.0 and linux
2.6.21
but I was not able to boot kernel 2.6.21 from u-boot 1.2.0. Kernel
2.6.22
(uImage) onwards can be booted with u-boot 1.2 and higher. Currently I
use
u-boot 1.2.0 and kernel 2.6.23 without any problems. My recommendation
is to
use at least the kernel version 2.6.22 otherwise you will have kernel
panic
problem.
Best Regards
Mirek
Guillaume Berthelom wrote:
>=20
> Hi,
>=20
> I'm trying to port Linux 2.6 on Avnet FX12 MM board with U-Boot and
the
> help of xilinx ML403 config.
>=20
> I have generate my costum xparameters.h file with EDK 8.2i.
> I use ELDK 4.1 and Linux 2.6.20.x.
> I have modified ml403.h u-boot's config file to adapt it for my board
and
> I have no problem to boot u-boot.
> I use the right board_info structure from <asm/ppcboot.h> and not the
one
> in xilinx_ml403.h.
>=20
> When I load the zImage directly with xilinx xmd debugger, the kernel
start
> without problem (if I don't have KGDB or SERIAL_TEXT_DEBUG option in
my
> kernel config). But when I try to load the uImage with u-boot, the
kernel
> start but crach befor I can see something on output.
>=20
> The kernel start because I debug it and the platform_init is ok,
> setup_arch too and it crach after ppc4xx_setup_arch at
printk(KERN_INFO
> "Xilinx ML403 Reference System (Virtex-4 FX)\n") line when the kernel
> access in printk.c.
>=20
> I suppose the serial init have problem but I have no idea what is the
> cause of the problem. I use the opb_uart16550 IP in my Xilinx design
and
> the associat drivers in u-boot and linux.
>=20
> Thanks,
> Guillaume Berthelom
>=20
>=20
--=20
View this message in context:
http://www.nabble.com/U-boot-%2B-Linux-2.6-%2B-Avnet-FX12-MM-%28based-on
-ML403-config%29-tp10201070p16384525.html
Sent from the linuxppc-embedded mailing list archive at Nabble.com.
_______________________________________________
Linuxppc-embedded mailing list
Linuxppc-embedded@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-embedded
^ permalink raw reply
* JFFS2 root-fs
From: Georg Schardt @ 2008-03-31 14:33 UTC (permalink / raw)
To: linuxppc-embedded
In-Reply-To: <16306218.post@talk.nabble.com>
Hi all,
i ask this questions a few months ago but i still have no solution for
my problem :(
i try to boot linux with a root-fs from flash. i create a jffs2-image,
download it to flash and
the u-boot "ls" shows me all my files, so i think all is right with the
image.
BUT, the kernel hangs after mounting the rootfs:
[ 0.572527] physmap platform flash device: 00400000 at 04000000
[ 0.579205] physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank
[ 0.586062] Amd/Fujitsu Extended Query Table at 0x0041
[ 0.591456] number of CFI chips: 1
[ 0.594973] cfi_cmdset_0002: Disabling erase-suspend-program due to
code brokenness.
[ 0.602916] 4 cmdlinepart partitions found on MTD device physmap-flash.0
[ 0.609759] Creating 4 MTD partitions on "physmap-flash.0":
[ 0.615454] 0x00000000-0x00010000 : "env"
[ 0.619599] mtd: Giving out device 0 to env
[ 0.628166] 0x00010000-0x00030000 : "uboot"
[ 0.632563] mtd: Giving out device 1 to uboot
[ 0.641172] 0x00030000-0x00160000 : "kernel"
[ 0.645744] mtd: Giving out device 2 to kernel
[ 0.654372] 0x00160000-0x00400000 : "fs"
[ 0.658604] mtd: Giving out device 3 to fs
[ 0.666992] block2mtd: version $Revision: 1.30 $
[ 0.673341] mice: PS/2 mouse device common for all mice
[ 0.679193] TCP cubic registered
[ 0.683016] NET: Registered protocol family 1
[ 0.687619] NET: Registered protocol family 17
[ 0.696556] MTDSB: dev_name "/dev/root"
[ 0.700723] MTDSB: path_lookup() returned 0, inode c02ec290
[ 0.706515] MTDSB: New superblock for device 3 ("fs")
[ 2.386543] VFS: Mounted root (jffs2 filesystem).
[ 2.392022] Freeing unused kernel memory: 76k init
[ 2.397182] Warning: unable to open an initial console.
[ 2.416877] Kernel panic - not syncing: No init found. Try passing
init= option to kernel.
[ 2.427312] Rebooting in 180 seconds..
It seems to me, that the kernel does not find ANY file. because the
/dev/console file is in the image, but the initial console is not found too
any ideas and hints are appreciated
regars
georg
-------------------------------------------------------------------
-------------------------------------------------------------------
Forschungszentrum Jülich GmbH
52425 Jülich
Sitz der Gesellschaft: Jülich
Eingetragen im Handelsregister des Amtsgerichts Düren Nr. HR B 3498
Vorsitzende des Aufsichtsrats: MinDir'in Bärbel Brumme-Bothe
Geschäftsführung: Prof. Dr. Achim Bachem (Vorsitzender),
Dr. Ulrich Krafft (stellv. Vorsitzender), Prof. Dr. Harald Bolt,
Dr. Sebastian M. Schmidt
-------------------------------------------------------------------
-------------------------------------------------------------------
^ permalink raw reply
* [BUG] 2.6.24.4 - kernel bug at kernel/sched.c:5154!
From: Kamalesh Babulal @ 2008-03-31 14:52 UTC (permalink / raw)
To: kernel list; +Cc: linuxppc-dev, mingo, Dhaval Giani, Balbir Singh
Hi,
The 2.6.24.4 kernel panic's while booting up on powerpc, The kernel
was compiled with allmodconfig. (please let me know if the .config
file is needed)
[ 0.000000] Kernel command line: ro console=hvc0 rhgb quiet root=LABEL=/1 autobench_args: root=/dev/sda3 ABAT:1206964330
[ 0.103959] BUG: scheduling while atomic: kthreadd/2/0x0007431c
[ 0.104051] BUG: scheduling while atomic: kthreadd/3/0xbe118168
[ 0.104119] ------------[ cut here ]------------
[ 0.104127] kernel BUG at kernel/sched.c:5154!
cpu 0x0: Vector: 700 (Program Check) at [c0000001be11bd70]
pc: c000000000070b34: .migration_thread+0x64/0x31c
lr: c000000000093878: .kthread+0x78/0xc4
sp: c0000001be11bff0
msr: 8000000000029032
current = 0xc0000000ee0ed740
paca = 0xc000000000497500
pid = 3, comm = kthreadd
kernel BUG at kernel/sched.c:5154!
enter ? for help
[c0000001be11c0b0] c000000000093878 .kthread+0x78/0xc4
[c0000001be11c140] c00000000002906c .kernel_thread+0x4c/0x68
0:mon> r
R00 = 0000000000000001 R16 = 0000000000000000
R01 = c0000001be11bff0 R17 = 0000000000000000
R02 = c00000000053ab90 R18 = 0000000000000000
R03 = 0000000000000000 R19 = 4000000001c00000
R04 = c0000000ee0ed740 R20 = c000000000453218
R05 = 0000000000000000 R21 = 0000000002053488
R06 = c000000000497500 R22 = 00000000002c2000
R07 = c0000001be1181b0 R23 = c000000000453488
R08 = 0000000000000000 R24 = 0000000002053218
R09 = c0000000ee0ed73f R25 = 0000000000000000
R10 = fffffffffffffffc R26 = c0000000005d40f8
R11 = c000000000497500 R27 = c0000000005d00b0
R12 = c00000000002906c R28 = c0000001be0c3ca8
R13 = c000000000497500 R29 = c000000000685c00
R14 = 0000000000000000 R30 = c0000000004f7210
R15 = 0000000000000000 R31 = c00000000050c788
pc = c000000000070b34 .migration_thread+0x64/0x31c
lr = c000000000093878 .kthread+0x78/0xc4
msr = 8000000000029032 cr = 28000024
ctr = c000000000070ad0 xer = 0000000020000004 trap = 700
0:mon> t
[c0000001be11c0b0] c000000000093878 .kthread+0x78/0xc4
[c0000001be11c140] c00000000002906c .kernel_thread+0x4c/0x68
0:mon> S
msr = 8000000000001032 sprg0= 0000000000000000
pvr = 00000000003b0200 sprg1= c000000000497500
dec = 00000000c4ac67ed sprg2= c000000000497500
sp = c0000001be11b620 sprg3= c000000000497500
toc = c00000000053ab90 dar = 0000000000000000
0xc000000000070b34 is in migration_thread (kernel/sched.c:5154).
5149 {
5150 int cpu = (long)data;
5151 struct rq *rq;
5152
5153 rq = cpu_rq(cpu);
5154 BUG_ON(rq->migration_thread != current);
5155
5156 set_current_state(TASK_INTERRUPTIBLE);
5157 while (!kthread_should_stop()) {
5158 struct migration_req *req;
--
Thanks & Regards,
Kamalesh Babulal,
Linux Technology Center,
IBM, ISTL.
^ permalink raw reply
* Re: [PATCHv2 2/3] ep8248e: Reference SMC parameter RAM base in the device tree.
From: Scott Wood @ 2008-03-31 15:33 UTC (permalink / raw)
To: Laurent Pinchart; +Cc: linuxppc-dev
In-Reply-To: <200803311109.02422.laurentp@cse-semaphore.com>
On Mon, Mar 31, 2008 at 11:08:58AM +0200, Laurent Pinchart wrote:
> On Friday 28 March 2008 19:07, Scott Wood wrote:
> > Yes, it tells you the virtual address when it's not an identity mapping.
> > It's not currently used on CPM platforms, but might be used down the
> > road with a QE device on 85xx.
>
> Will the virtual-reg property on the muram node list the addresses of all
> muram chunks or the address of the first chunk only ?
It should list all the chunks. If you want the size of each chunk, just
look at the reg property.
> > >> Even the end of the first reg resource would be OK.
> > >
> > > If I use the end of the first resource, can I assume it spans 0x0000
> > > - 0x8000 to set the default tx BD address in Kconfig ?
> >
> > No, especially seeing as it doesn't on any existing boards. :-)
>
> I still need a default value :-) It obviously won't work for all boards.
Just before 0x8000 won't work for any board, because that area is
reserved on CPM2.
> > You could set the default to just before 0x2000 with board-specific
> > exceptions, though.
>
> We're getting a bit lost. I'll try to summarize the discussion.
>
> - The muram node has a reg property that lists the offsets and sizes of all
> muram chunks, and an optional virtual-reg property that lists the virtual
> address of all chunks/the first chunk only.
>
> - From the above information I can locate a section of muram at the end of the
> first chunk (easy) or at the end of the muram (not really difficult, just a
> bit more complex, especially if chunks are not sorted by their start
> address).
>
> - Kconfig needs a default address for the tx BD. This depends on the
> allocation strategy (end of first chunk vs. end of last chunk). Is there some
> consistent default across QE devices ?
0x2000 minus sizeof(...) would be a good default for CPM1 and CPM2 (8280
has its first chunk go up to 0x4000, but for some reason that didn't get
reflected in the dts for the one 8280 board in-tree).
-Scott
^ permalink raw reply
* [PATCH] [POWERPC] fsldma: Use compatiable binding as spec
From: Kumar Gala @ 2008-03-31 16:17 UTC (permalink / raw)
To: linuxppc-dev; +Cc: dan.j.williams, linux-kernel
Documentation/powerpc/booting-without-of.txt specifies the
compatiables we should bind to for this driver (elo, eloplus).
Use these instead of the extremely specific 'mpc8540' and 'mpc8349'
compatiables.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
Dan, if you don't have any issue with this I'll sent it via the powerpc
tree (since its not really about functionality).
- k
drivers/dma/fsldma.c | 8 ++++----
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 7269230..df16368 100644
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -1021,11 +1021,11 @@ const u32 mpc8349_dma_ip_feature = FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN;
static struct of_device_id of_fsl_dma_chan_ids[] = {
{
- .compatible = "fsl,mpc8540-dma-channel",
+ .compatible = "fsl,eloplus-dma-channel",
.data = (void *)&mpc8540_dma_ip_feature,
},
{
- .compatible = "fsl,mpc8349-dma-channel",
+ .compatible = "fsl,elo-dma-channel",
.data = (void *)&mpc8349_dma_ip_feature,
},
{}
@@ -1107,8 +1107,8 @@ err:
}
static struct of_device_id of_fsl_dma_ids[] = {
- { .compatible = "fsl,mpc8540-dma", },
- { .compatible = "fsl,mpc8349-dma", },
+ { .compatible = "fsl,eloplus-dma", },
+ { .compatible = "fsl,elo-dma", },
{}
};
--
1.5.4.1
^ permalink raw reply related
* v5 patch to add FSL DIU framebuffer driver
From: York Sun @ 2008-03-31 16:23 UTC (permalink / raw)
To: linux-fbdev-devel
Cc: a.p.zijlstra, linux-kernel, linuxppc-dev, scottwood, akpm
Thanks for the feedback from Scott and Anton. Here is the version 5 patch.
My previous patch didn't arrive at linux-fbdev-devel@lists.sourceforge.net.
Hopefully this issue has been fixed and more feedback from the mailing list.
Regards,
York
^ permalink raw reply
* [PATCH 2/2 v5] Add DIU platform code for MPC8610HPCD
From: York Sun @ 2008-03-31 16:23 UTC (permalink / raw)
To: linux-fbdev-devel
Cc: Timur Tabi, a.p.zijlstra, linux-kernel, linuxppc-dev, scottwood,
akpm, York Sun
In-Reply-To: <1206980605689-git-send-email-yorksun@freescale.com>
Add platform code to support Freescale DIU. The platform code includes
framebuffer memory allocation, pixel format, monitor port, etc.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
---
This patch addes platform support for Freescale DIU driver, targeting 2.6.26 kernel.
arch/powerpc/configs/mpc8610_hpcd_defconfig | 198 +++++++++++++++++++++++----
arch/powerpc/platforms/86xx/mpc8610_hpcd.c | 190 ++++++++++++++++++++++++--
arch/powerpc/sysdev/fsl_soc.c | 41 ++++++
arch/powerpc/sysdev/fsl_soc.h | 23 +++
4 files changed, 413 insertions(+), 39 deletions(-)
diff --git a/arch/powerpc/configs/mpc8610_hpcd_defconfig b/arch/powerpc/configs/mpc8610_hpcd_defconfig
index 2500ef4..98cef01 100644
--- a/arch/powerpc/configs/mpc8610_hpcd_defconfig
+++ b/arch/powerpc/configs/mpc8610_hpcd_defconfig
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24-rc4
-# Thu Dec 6 16:48:56 2007
+# Linux kernel version: 2.6.25-rc5
+# Tue Mar 25 16:10:42 2008
#
# CONFIG_PPC64 is not set
@@ -29,6 +29,7 @@ CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
CONFIG_IRQ_PER_CPU=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_ARCH_HAS_ILOG2_U32=y
@@ -65,16 +66,20 @@ CONFIG_LOCALVERSION=""
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
+CONFIG_GROUP_SCHED=y
# CONFIG_FAIR_GROUP_SCHED is not set
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -88,11 +93,13 @@ CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
+CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
@@ -100,6 +107,13 @@ CONFIG_SLUB_DEBUG=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
@@ -122,6 +136,7 @@ CONFIG_DEFAULT_DEADLINE=y
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="deadline"
+CONFIG_CLASSIC_RCU=y
#
# Platform support
@@ -130,14 +145,15 @@ CONFIG_DEFAULT_IOSCHED="deadline"
# CONFIG_PPC_82xx is not set
# CONFIG_PPC_83xx is not set
CONFIG_PPC_86xx=y
-# CONFIG_PPC_MPC52xx is not set
-# CONFIG_PPC_MPC5200 is not set
+# CONFIG_PPC_MPC512x is not set
+# CONFIG_PPC_MPC5121 is not set
# CONFIG_PPC_CELL is not set
# CONFIG_PPC_CELL_NATIVE is not set
# CONFIG_PQ2ADS is not set
# CONFIG_MPC8641_HPCN is not set
CONFIG_MPC8610_HPCD=y
CONFIG_MPC8610=y
+# CONFIG_IPIC is not set
CONFIG_MPIC=y
# CONFIG_MPIC_WEIRD is not set
# CONFIG_PPC_I8259 is not set
@@ -148,7 +164,6 @@ CONFIG_MPIC=y
# CONFIG_PPC_INDIRECT_IO is not set
# CONFIG_GENERIC_IOMAP is not set
# CONFIG_CPU_FREQ is not set
-# CONFIG_CPM2 is not set
# CONFIG_FSL_ULI1575 is not set
#
@@ -164,12 +179,16 @@ CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
# CONFIG_HZ_300 is not set
CONFIG_HZ_1000=y
CONFIG_HZ=1000
+# CONFIG_SCHED_HRTICK is not set
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
+# CONFIG_IOMMU_HELPER is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_SELECT_MEMORY_MODEL=y
@@ -188,10 +207,7 @@ CONFIG_VIRT_TO_BUS=y
CONFIG_PROC_DEVICETREE=y
# CONFIG_CMDLINE_BOOL is not set
# CONFIG_PM is not set
-CONFIG_SUSPEND_UP_POSSIBLE=y
-CONFIG_HIBERNATION_UP_POSSIBLE=y
# CONFIG_SECCOMP is not set
-# CONFIG_WANT_DEVICE_TREE is not set
CONFIG_ISA_DMA_API=y
#
@@ -243,6 +259,7 @@ CONFIG_XFRM=y
CONFIG_XFRM_USER=y
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
@@ -311,6 +328,7 @@ CONFIG_IPV6_SIT=y
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
@@ -357,7 +375,7 @@ CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=131072
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_ATA_OVER_ETH is not set
CONFIG_MISC_DEVICES=y
@@ -365,6 +383,8 @@ CONFIG_MISC_DEVICES=y
# CONFIG_EEPROM_93CX6 is not set
# CONFIG_SGI_IOC4 is not set
# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_HAVE_IDE=y
CONFIG_IDE=y
CONFIG_IDE_MAX_HWIFS=4
# CONFIG_BLK_DEV_IDE is not set
@@ -432,6 +452,7 @@ CONFIG_SCSI_LOWLEVEL=y
# CONFIG_SCSI_IPS is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_MVSAS is not set
# CONFIG_SCSI_STEX is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
@@ -462,6 +483,7 @@ CONFIG_SATA_AHCI=y
# CONFIG_SATA_VIA is not set
# CONFIG_SATA_VITESSE is not set
# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_FSL is not set
CONFIG_PATA_ALI=y
# CONFIG_PATA_AMD is not set
# CONFIG_PATA_ARTOP is not set
@@ -485,6 +507,7 @@ CONFIG_PATA_ALI=y
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OPTI is not set
@@ -518,7 +541,6 @@ CONFIG_DUMMY=y
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
-# CONFIG_IP1000 is not set
# CONFIG_ARCNET is not set
CONFIG_PHYLIB=y
@@ -534,6 +556,7 @@ CONFIG_PHYLIB=y
# CONFIG_SMSC_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
CONFIG_NET_ETHERNET=y
@@ -574,6 +597,7 @@ CONFIG_8139TOO_PIO=y
# CONFIG_8139TOO_TUNE_TWISTER is not set
# CONFIG_8139TOO_8129 is not set
# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
# CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set
@@ -585,6 +609,9 @@ CONFIG_NETDEV_1000=y
# CONFIG_DL2K is not set
# CONFIG_E1000 is not set
# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
@@ -610,6 +637,7 @@ CONFIG_NETDEV_10000=y
# CONFIG_NIU is not set
# CONFIG_MLX4_CORE is not set
# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
# CONFIG_TR is not set
#
@@ -623,7 +651,6 @@ CONFIG_NETDEV_10000=y
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
@@ -674,6 +701,7 @@ CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
#
# Serial drivers
@@ -748,14 +776,12 @@ CONFIG_I2C_MPC=y
#
# Miscellaneous I2C Chip support
#
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_M41T00 is not set
+# CONFIG_TPS65010 is not set
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
@@ -771,6 +797,7 @@ CONFIG_I2C_MPC=y
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
# CONFIG_WATCHDOG is not set
#
@@ -798,7 +825,56 @@ CONFIG_DAB=y
# CONFIG_DRM is not set
# CONFIG_VGASTATE is not set
CONFIG_VIDEO_OUTPUT_CONTROL=y
-# CONFIG_FB is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_OF is not set
+# CONFIG_FB_CT65550 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_VGA16 is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+CONFIG_FB_FSL_DIU=y
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_VIRTUAL is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
@@ -812,6 +888,16 @@ CONFIG_VIDEO_OUTPUT_CONTROL=y
CONFIG_VGA_CONSOLE=y
# CONFIG_VGACON_SOFT_SCROLLBACK is not set
CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
#
# Sound
@@ -859,6 +945,7 @@ CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_BT87X is not set
# CONFIG_SND_CA0106 is not set
# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
# CONFIG_SND_CS4281 is not set
# CONFIG_SND_CS46XX is not set
# CONFIG_SND_CS5530 is not set
@@ -884,6 +971,7 @@ CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_HDA_INTEL is not set
# CONFIG_SND_HDSP is not set
# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
# CONFIG_SND_ICE1712 is not set
# CONFIG_SND_ICE1724 is not set
# CONFIG_SND_INTEL8X0 is not set
@@ -901,6 +989,7 @@ CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_TRIDENT is not set
# CONFIG_SND_VIA82XX is not set
# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
# CONFIG_SND_VX222 is not set
# CONFIG_SND_YMFPCI is not set
@@ -929,6 +1018,10 @@ CONFIG_SND_SOC_MPC8610_HPCD=y
CONFIG_SND_SOC_CS4270=y
CONFIG_SND_SOC_CS4270_VD33_ERRATA=y
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HID_DEBUG is not set
@@ -942,16 +1035,14 @@ CONFIG_USB_ARCH_HAS_EHCI=y
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
-
-#
-# USB Gadget Support
-#
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_INFINIBAND is not set
# CONFIG_EDAC is not set
# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
#
# Userspace I/O
@@ -970,6 +1061,7 @@ CONFIG_EXT3_FS_XATTR=y
# CONFIG_EXT3_FS_SECURITY is not set
# CONFIG_EXT4DEV_FS is not set
CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
@@ -977,11 +1069,9 @@ CONFIG_FS_MBCACHE=y
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY is not set
# CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
@@ -1023,8 +1113,10 @@ CONFIG_TMPFS=y
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
@@ -1114,7 +1206,6 @@ CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
# CONFIG_DLM is not set
-# CONFIG_UCC_SLOW is not set
#
# Library routines
@@ -1130,7 +1221,7 @@ CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
-# CONFIG_INSTRUMENTATION is not set
+CONFIG_HAVE_LMB=y
#
# Kernel hacking
@@ -1140,7 +1231,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_SHIRQ=y
@@ -1149,6 +1240,7 @@ CONFIG_SCHED_DEBUG=y
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
@@ -1162,14 +1254,15 @@ CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
-CONFIG_FORCED_INLINING=y
# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_SAMPLES is not set
# CONFIG_DEBUG_STACKOVERFLOW is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_PAGEALLOC is not set
# CONFIG_DEBUGGER is not set
+# CONFIG_VIRQ_DEBUG is not set
# CONFIG_BDI_SWITCH is not set
# CONFIG_PPC_EARLY_DEBUG is not set
@@ -1179,5 +1272,50 @@ CONFIG_FORCED_INLINING=y
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_SEQIV is not set
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_WP512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
# CONFIG_PPC_CLOCK is not set
+CONFIG_PPC_LIB_RHEAP=y
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index 0b07485..12f9aa1 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -3,11 +3,12 @@
*
* Initial author: Xianghua Xiao <x.xiao@freescale.com>
* Recode: Jason Jin <jason.jin@freescale.com>
+ * York Sun <yorksun@freescale.com>
*
* Rewrite the interrupt routing. remove the 8259PIC support,
* All the integrated device in ULI use sideband interrupt.
*
- * Copyright 2007 Freescale Semiconductor Inc.
+ * Copyright 2008 Freescale Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -38,6 +39,8 @@
#include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h>
+static unsigned char *pixis_bdcfg0, *pixis_arch;
+
static struct of_device_id __initdata mpc8610_ids[] = {
{ .compatible = "fsl,mpc8610-immr", },
{}
@@ -52,8 +55,7 @@ static int __init mpc8610_declare_of_platform_devices(void)
}
machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
-void __init
-mpc86xx_hpcd_init_irq(void)
+void __init mpc86xx_hpcd_init_irq(void)
{
struct mpic *mpic1;
struct device_node *np;
@@ -161,12 +163,159 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, final_uli5288);
#endif /* CONFIG_PCI */
-static void __init
-mpc86xx_hpcd_setup_arch(void)
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+
+static u32 get_busfreq(void)
{
-#ifdef CONFIG_PCI
- struct device_node *np;
+ struct device_node *node;
+
+ u32 fs_busfreq = 0;
+ node = of_find_node_by_type(NULL, "cpu");
+ if (node) {
+ unsigned int size;
+ const unsigned int *prop =
+ of_get_property(node, "bus-frequency", &size);
+ if (prop)
+ fs_busfreq = *prop;
+ of_node_put(node);
+ };
+ return fs_busfreq;
+}
+
+unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
+ int monitor_port)
+{
+ static const unsigned long pixelformat[][3] = {
+ {0x88882317, 0x88083218, 0x65052119},
+ {0x88883316, 0x88082219, 0x65053118},
+ };
+ unsigned int pix_fmt, arch_monitor;
+
+ arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
+ /* DVI port for board version 0x01 */
+
+ if (bits_per_pixel == 32)
+ pix_fmt = pixelformat[arch_monitor][0];
+ else if (bits_per_pixel == 24)
+ pix_fmt = pixelformat[arch_monitor][1];
+ else if (bits_per_pixel == 16)
+ pix_fmt = pixelformat[arch_monitor][2];
+ else
+ pix_fmt = pixelformat[1][0];
+
+ return pix_fmt;
+}
+
+void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
+{
+ int i;
+ if (monitor_port == 2) { /* dual link LVDS */
+ for (i = 0; i < 256*3; i++)
+ gamma_table_base[i] = (gamma_table_base[i] << 2) |
+ ((gamma_table_base[i] >> 6) & 0x03);
+ }
+}
+
+void mpc8610hpcd_set_monitor_port(int monitor_port)
+{
+ static const u8 bdcfg[] = {0xBD, 0xB5, 0xA5};
+ if (monitor_port < 3)
+ *pixis_bdcfg0 = bdcfg[monitor_port];
+}
+
+void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
+{
+ u32 __iomem *clkdvdr;
+ u32 temp;
+ /* variables for pixel clock calcs */
+ ulong bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
+ ulong pixval;
+ long err;
+ int i;
+
+ clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
+ if (!clkdvdr) {
+ printk(KERN_ERR "Err: can't map clock divider register!\n");
+ return;
+ }
+
+ /* Pixel Clock configuration */
+ pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
+ speed_ccb = get_busfreq();
+
+ /* Calculate the pixel clock with the smallest error */
+ /* calculate the following in steps to avoid overflow */
+ pr_debug("DIU pixclock in ps - %d\n", pixclock);
+ temp = 1000000000/pixclock;
+ temp *= 1000;
+ pixclock = temp;
+ pr_debug("DIU pixclock freq - %u\n", pixclock);
+
+ temp = pixclock * 5 / 100;
+ pr_debug("deviation = %d\n", temp);
+ minpixclock = pixclock - temp;
+ maxpixclock = pixclock + temp;
+ pr_debug("DIU minpixclock - %lu\n", minpixclock);
+ pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
+ pixval = speed_ccb/pixclock;
+ pr_debug("DIU pixval = %lu\n", pixval);
+
+ err = 100000000;
+ bestval = pixval;
+ pr_debug("DIU bestval = %lu\n", bestval);
+
+ bestfreq = 0;
+ for (i = -1; i <= 1; i++) {
+ temp = speed_ccb / ((pixval+i) + 1);
+ pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
+ i, pixval, temp);
+ if ((temp < minpixclock) || (temp > maxpixclock))
+ pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
+ minpixclock, maxpixclock);
+ else if (abs(temp - pixclock) < err) {
+ pr_debug("Entered the else if block %d\n", i);
+ err = abs(temp - pixclock);
+ bestval = pixval+i;
+ bestfreq = temp;
+ }
+ }
+
+ pr_debug("DIU chose = %lx\n", bestval);
+ pr_debug("DIU error = %ld\n NomPixClk ", err);
+ pr_debug("DIU: Best Freq = %lx\n", bestfreq);
+ /* Modify PXCLK in GUTS CLKDVDR */
+ pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
+ temp = (*clkdvdr) & 0x2000FFFF;
+ *clkdvdr = temp; /* turn off clock */
+ *clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16);
+ pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
+ iounmap(clkdvdr);
+}
+
+ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
+{
+ return snprintf(buf, PAGE_SIZE,
+ "%c0 - DVI\n"
+ "%c1 - Single link LVDS\n"
+ "%c2 - Dual link LVDS\n",
+ monitor_port == 0 ? '*' : ' ',
+ monitor_port == 1 ? '*' : ' ',
+ monitor_port == 2 ? '*' : ' ');
+}
+
+int mpc8610hpcd_set_sysfs_monitor_port(int val)
+{
+ return val < 3 ? val : 0;
+}
+
#endif
+
+static void __init mpc86xx_hpcd_setup_arch(void)
+{
+ struct resource r;
+ struct device_node *np;
+ unsigned char *pixis;
+
if (ppc_md.progress)
ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
@@ -183,6 +332,30 @@ mpc86xx_hpcd_setup_arch(void)
}
}
#endif
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+ preallocate_diu_videomemory();
+ diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
+ diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
+ diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
+ diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
+ diu_ops.show_monitor_port = mpc8610hpcd_show_monitor_port;
+ diu_ops.set_sysfs_monitor_port = mpc8610hpcd_set_sysfs_monitor_port;
+#endif
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
+ if (np) {
+ of_address_to_resource(np, 0, &r);
+ of_node_put(np);
+ pixis = ioremap(r.start, 32);
+ if (!pixis) {
+ printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
+ return;
+ }
+ pixis_bdcfg0 = pixis + 8;
+ pixis_arch = pixis + 1;
+ } else
+ printk(KERN_ERR "Err: "
+ "can't find device node 'fsl,fpga-pixis'\n");
printk("MPC86xx HPCD board from Freescale Semiconductor\n");
}
@@ -200,8 +373,7 @@ static int __init mpc86xx_hpcd_probe(void)
return 0;
}
-long __init
-mpc86xx_time_init(void)
+long __init mpc86xx_time_init(void)
{
unsigned int temp;
diff --git a/arch/powerpc/sysdev/fsl_soc.c b/arch/powerpc/sysdev/fsl_soc.c
index 2c5388c..fdd77fc 100644
--- a/arch/powerpc/sysdev/fsl_soc.c
+++ b/arch/powerpc/sysdev/fsl_soc.c
@@ -1438,3 +1438,44 @@ void fsl_rstcr_restart(char *cmd)
while (1) ;
}
#endif
+
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+struct platform_diu_data_ops diu_ops = {
+ .diu_size = 1280 * 1024 * 4, /* default one 1280x1024 buffer */
+};
+EXPORT_SYMBOL(diu_ops);
+
+int __init preallocate_diu_videomemory(void)
+{
+ pr_debug("diu_size=%lu\n", diu_ops.diu_size);
+
+ diu_ops.diu_mem = __alloc_bootmem(diu_ops.diu_size, 8, 0);
+ if (!diu_ops.diu_mem) {
+ printk(KERN_ERR "fsl-diu: cannot allocate %lu bytes\n",
+ diu_ops.diu_size);
+ return -ENOMEM;
+ }
+
+ pr_debug("diu_mem=%p\n", diu_ops.diu_mem);
+
+ rh_init(&diu_ops.diu_rh_info, 4096, ARRAY_SIZE(diu_ops.diu_rh_block),
+ diu_ops.diu_rh_block);
+ return rh_attach_region(&diu_ops.diu_rh_info,
+ (unsigned long) diu_ops.diu_mem,
+ diu_ops.diu_size);
+}
+
+static int __init early_parse_diufb(char *p)
+{
+ if (!p)
+ return 1;
+
+ diu_ops.diu_size = _ALIGN_UP(memparse(p, &p), 8);
+
+ pr_debug("diu_size=%lu\n", diu_ops.diu_size);
+
+ return 0;
+}
+early_param("diufb", early_parse_diufb);
+
+#endif
diff --git a/arch/powerpc/sysdev/fsl_soc.h b/arch/powerpc/sysdev/fsl_soc.h
index 63e7db3..bdc6ca1 100644
--- a/arch/powerpc/sysdev/fsl_soc.h
+++ b/arch/powerpc/sysdev/fsl_soc.h
@@ -16,5 +16,28 @@ extern int fsl_spi_init(struct spi_board_info *board_infos,
void (*deactivate_cs)(u8 cs, u8 polarity));
extern void fsl_rstcr_restart(char *cmd);
+
+#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+#include <linux/bootmem.h>
+#include <asm/rheap.h>
+struct platform_diu_data_ops {
+ rh_block_t diu_rh_block[16];
+ rh_info_t diu_rh_info;
+ unsigned long diu_size;
+ void *diu_mem;
+
+ unsigned int (*get_pixel_format) (unsigned int bits_per_pixel,
+ int monitor_port);
+ void (*set_gamma_table) (int monitor_port, char *gamma_table_base);
+ void (*set_monitor_port) (int monitor_port);
+ void (*set_pixel_clock) (unsigned int pixclock);
+ ssize_t (*show_monitor_port) (int monitor_port, char *buf);
+ int (*set_sysfs_monitor_port) (int val);
+};
+
+extern struct platform_diu_data_ops diu_ops;
+int __init preallocate_diu_videomemory(void);
+#endif
+
#endif
#endif
--
1.5.2.2
^ permalink raw reply related
* [PATCH 1/2 v5] Driver for Freescale 8610 and 5121 DIU
From: York Sun @ 2008-03-31 16:23 UTC (permalink / raw)
To: linux-fbdev-devel
Cc: Timur Tabi, a.p.zijlstra, linux-kernel, linuxppc-dev, scottwood,
akpm, York Sun
In-Reply-To: <12069806051060-git-send-email-yorksun@freescale.com>
The following features are supported:
plane 0 works as a regular frame buffer, can be accessed by /dev/fb0
plane 1 has two AOIs (area of interest), can be accessed by /dev/fb1 and /dev/fb2
plane 2 has two AOIs, can be accessed by /dev/fb3 and /dev/fb4
Special ioctls support AOIs
All /dev/fb* can be used as regular frame buffer devices, except hardware change can
only be made through /dev/fb0. Changing pixel clock has no effect on other fbs.
Limitation of usage of AOIs:
AOIs on the same plane can not be horizonally overlapped
AOIs have horizonal order, i.e. AOI0 should be always on top of AOI1
AOIs can not beyond phisical display area. Application should check AOI geometry
before changing physical resolution on /dev/fb0
required command line parameters to preallocate memory for frame buffer
diufb=15M
optional command line parameters to set modes and monitor
video=fslfb:[resolution][,bpp][,monitor]
Syntax:
Resolution
xres x yres-bpp@refresh_rate, the -bpp and @refresh_rate are optional
eg, 1024x768, 1280x1024, 1280x1024-32, 1280x1024@60, 1280x1024-32@60, 1280x480-32@60
Bpp
bpp=32, bpp=24, or bpp=16
Monitor
monitor=0, monitor=1, monitor=2
0 is DVI
1 is Single link LVDS
2 is Double link LVDS
Note: switching monitor is a board feather, not DIU feather. MPC8610HPCD has three
monitor ports to swtich to. MPC5121ADS doesn't have additional monitor port. So switching
monirot port for MPC5121ADS has no effect.
If compiled as a module, it takes pamameters mode, bpp, monitor with the same syntax above.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Timur Tabi <timur@freescale.com>
---
This patch addes new feature of Freescale DIU driver, targeting 2.6.26 kernel.
Documentation/powerpc/booting-without-of.txt | 33 +
arch/powerpc/boot/dts/mpc8610_hpcd.dts | 12 +
drivers/video/Kconfig | 10 +
drivers/video/Makefile | 1 +
drivers/video/fsl-diu-fb.c | 1721 ++++++++++++++++++++++++++
drivers/video/fsl-diu-fb.h | 223 ++++
6 files changed, 2000 insertions(+), 0 deletions(-)
create mode 100644 drivers/video/fsl-diu-fb.c
create mode 100644 drivers/video/fsl-diu-fb.h
diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt
index 7b4e8a7..0c85500 100644
--- a/Documentation/powerpc/booting-without-of.txt
+++ b/Documentation/powerpc/booting-without-of.txt
@@ -2816,6 +2816,39 @@ platforms are moved over to use the flattened-device-tree model.
big-endian;
};
+ r) Freescale Display Interface Unit
+
+ The Freescale DIU is a LCD controller, with proper hardware, it can also
+ drive DVI monitors.
+
+ Required properties:
+ - compatible : should be "fsl-diu".
+ - reg : should contain at least address and length of the DIU register
+ set.
+ - Interrupts : one DIU interrupt should be describe here.
+
+ Example (MPC8610HPCD)
+ display@2c000 {
+ compatible = "fsl,diu";
+ reg = <0x2c000 100>;
+ interrupts = <72 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ s) Freescale on board FPGA
+
+ This is the memory-mapped registers for on board FPGA.
+
+ Required properities:
+ - compatible : should be "fsl,fpga-pixis".
+ - reg : should contain the address and the lenght of the FPPGA register
+ set.
+
+ Example (MPC8610HPCD)
+ board-control@e8000000 {
+ compatible = "fsl,fpga-pixis";
+ reg = <0xe8000000 32>;
+ };
More devices will be defined as this spec matures.
diff --git a/arch/powerpc/boot/dts/mpc8610_hpcd.dts b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
index 16c947b..1f2f1e0 100644
--- a/arch/powerpc/boot/dts/mpc8610_hpcd.dts
+++ b/arch/powerpc/boot/dts/mpc8610_hpcd.dts
@@ -45,6 +45,11 @@
reg = <0x00000000 0x20000000>; // 512M at 0x0
};
+ board-control@e8000000 {
+ compatible = "fsl,fpga-pixis";
+ reg = <0xe8000000 32>; // pixis at 0xe8000000
+ };
+
soc@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
@@ -104,6 +109,13 @@
interrupt-parent = <&mpic>;
};
+ display@2c000 {
+ compatible = "fsl,diu";
+ reg = <0x2c000 100>;
+ interrupts = <72 2>;
+ interrupt-parent = <&mpic>;
+ };
+
mpic: interrupt-controller@40000 {
clock-frequency = <0>;
interrupt-controller;
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index e0b0580..d9c6be4 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1779,6 +1779,16 @@ config FB_MBX_DEBUG
If unsure, say N.
+config FB_FSL_DIU
+ tristate "Freescale DIU framebuffer support"
+ depends on FB && FSL_SOC
+ select FB_CFB_FILLRECT
+ select FB_CFB_COPYAREA
+ select FB_CFB_IMAGEBLIT
+ select PPC_LIB_RHEAP
+ ---help---
+ Framebuffer driver for the Freescale SoC DIU
+
config FB_W100
tristate "W100 frame buffer support"
depends on FB && PXA_SHARPSL
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 03371c7..3b9a3ce 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -113,6 +113,7 @@ obj-$(CONFIG_FB_PS3) += ps3fb.o
obj-$(CONFIG_FB_SM501) += sm501fb.o
obj-$(CONFIG_FB_XILINX) += xilinxfb.o
obj-$(CONFIG_FB_OMAP) += omap/
+obj-$(CONFIG_FB_FSL_DIU) += fsl-diu-fb.o
# Platform or fallback drivers go here
obj-$(CONFIG_FB_UVESA) += uvesafb.o
diff --git a/drivers/video/fsl-diu-fb.c b/drivers/video/fsl-diu-fb.c
new file mode 100644
index 0000000..b50bb03
--- /dev/null
+++ b/drivers/video/fsl-diu-fb.c
@@ -0,0 +1,1721 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Freescale DIU Frame Buffer device driver
+ *
+ * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
+ * Paul Widmer <paul.widmer@freescale.com>
+ * Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ * York Sun <yorksun@freescale.com>
+ *
+ * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/fb.h>
+#include <linux/init.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/uaccess.h>
+#include <linux/vmalloc.h>
+
+#include <linux/of_platform.h>
+
+#include <sysdev/fsl_soc.h>
+#include "fsl-diu-fb.h"
+
+/*
+ * These parameters give default parameters
+ * for video output 1024x768,
+ * FIXME - change timing to proper amounts
+ * hsync 31.5kHz, vsync 60Hz
+ */
+static struct fb_videomode __devinitdata fsl_diu_default_mode = {
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 160,
+ .right_margin = 24,
+ .upper_margin = 29,
+ .lower_margin = 3,
+ .hsync_len = 136,
+ .vsync_len = 6,
+ .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+static struct fb_videomode __devinitdata fsl_diu_mode_db[] = {
+ {
+ .name = "1024x768-60",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 160,
+ .right_margin = 24,
+ .upper_margin = 29,
+ .lower_margin = 3,
+ .hsync_len = 136,
+ .vsync_len = 6,
+ .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+ },
+ {
+ .name = "1024x768-70",
+ .refresh = 70,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 16886,
+ .left_margin = 3,
+ .right_margin = 3,
+ .upper_margin = 2,
+ .lower_margin = 2,
+ .hsync_len = 40,
+ .vsync_len = 18,
+ .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+ },
+ {
+ .name = "1024x768-75",
+ .refresh = 75,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15009,
+ .left_margin = 3,
+ .right_margin = 3,
+ .upper_margin = 2,
+ .lower_margin = 2,
+ .hsync_len = 80,
+ .vsync_len = 32,
+ .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+ },
+ {
+ .name = "1280x1024-60",
+ .refresh = 60,
+ .xres = 1280,
+ .yres = 1024,
+ .pixclock = 9375,
+ .left_margin = 38,
+ .right_margin = 128,
+ .upper_margin = 2,
+ .lower_margin = 7,
+ .hsync_len = 216,
+ .vsync_len = 37,
+ .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+ },
+ {
+ .name = "1280x1024-70",
+ .refresh = 70,
+ .xres = 1280,
+ .yres = 1024,
+ .pixclock = 9380,
+ .left_margin = 6,
+ .right_margin = 6,
+ .upper_margin = 4,
+ .lower_margin = 4,
+ .hsync_len = 60,
+ .vsync_len = 94,
+ .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+ },
+ {
+ .name = "1280x1024-75",
+ .refresh = 75,
+ .xres = 1280,
+ .yres = 1024,
+ .pixclock = 9380,
+ .left_margin = 6,
+ .right_margin = 6,
+ .upper_margin = 4,
+ .lower_margin = 4,
+ .hsync_len = 60,
+ .vsync_len = 15,
+ .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+ },
+ {
+ .name = "320x240", /* for AOI only */
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = 15385,
+ .left_margin = 0,
+ .right_margin = 0,
+ .upper_margin = 0,
+ .lower_margin = 0,
+ .hsync_len = 0,
+ .vsync_len = 0,
+ .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+ },
+ {
+ .name = "1280x480-60",
+ .refresh = 60,
+ .xres = 1280,
+ .yres = 480,
+ .pixclock = 18939,
+ .left_margin = 353,
+ .right_margin = 47,
+ .upper_margin = 39,
+ .lower_margin = 4,
+ .hsync_len = 8,
+ .vsync_len = 2,
+ .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+ },
+};
+
+static char *fb_mode = "1024x768-32@60";
+static unsigned long default_bpp = 32;
+static int monitor_port;
+
+#if defined(CONFIG_NOT_COHERENT_CACHE)
+static u8 *coherence_data;
+static size_t coherence_data_size;
+static unsigned int d_cache_line_size;
+#endif
+
+static DEFINE_SPINLOCK(diu_lock);
+
+struct fsl_diu_data {
+ struct fb_info *fsl_diu_info[FSL_AOI_NUM - 1];
+ /*FSL_AOI_NUM has one dummy AOI */
+ struct device_attribute dev_attr;
+ struct diu_ad *dummy_ad;
+ void *dummy_aoi_virt;
+ unsigned int irq;
+ int fb_enabled;
+ int monitor_port;
+};
+
+struct mfb_info {
+ int index;
+ int type;
+ char *id;
+ int registered;
+ int blank;
+ unsigned long pseudo_palette[16];
+ struct diu_ad *ad;
+ int cursor_reset;
+ unsigned char g_alpha;
+ unsigned int count;
+ int x_aoi_d; /* aoi display x offset to physical screen */
+ int y_aoi_d; /* aoi display y offset to physical screen */
+ struct fsl_diu_data *parent;
+};
+
+
+static struct mfb_info mfb_template[] = {
+ { /* AOI 0 for plane 0 */
+ .index = 0,
+ .type = MFB_TYPE_OUTPUT,
+ .id = "Panel0",
+ .registered = 0,
+ .count = 0,
+ .x_aoi_d = 0,
+ .y_aoi_d = 0,
+ },
+ { /* AOI 0 for plane 1 */
+ .index = 1,
+ .type = MFB_TYPE_OUTPUT,
+ .id = "Panel1 AOI0",
+ .registered = 0,
+ .g_alpha = 0xff,
+ .count = 0,
+ .x_aoi_d = 0,
+ .y_aoi_d = 0,
+ },
+ { /* AOI 1 for plane 1 */
+ .index = 2,
+ .type = MFB_TYPE_OUTPUT,
+ .id = "Panel1 AOI1",
+ .registered = 0,
+ .g_alpha = 0xff,
+ .count = 0,
+ .x_aoi_d = 0,
+ .y_aoi_d = 480,
+ },
+ { /* AOI 0 for plane 2 */
+ .index = 3,
+ .type = MFB_TYPE_OUTPUT,
+ .id = "Panel2 AOI0",
+ .registered = 0,
+ .g_alpha = 0xff,
+ .count = 0,
+ .x_aoi_d = 640,
+ .y_aoi_d = 0,
+ },
+ { /* AOI 1 for plane 2 */
+ .index = 4,
+ .type = MFB_TYPE_OUTPUT,
+ .id = "Panel2 AOI1",
+ .registered = 0,
+ .g_alpha = 0xff,
+ .count = 0,
+ .x_aoi_d = 640,
+ .y_aoi_d = 480,
+ },
+};
+
+static struct diu_hw dr = {
+ .mode = MFB_MODE1,
+ .reg_lock = __SPIN_LOCK_UNLOCKED(diu_hw.reg_lock),
+};
+
+static struct diu_pool pool;
+
+/* To allocate memory for framebuffer. First try __get_free_pages(). If it
+ * fails, try rh_alloc. The reason is __get_free_pages() cannot allocate
+ * very large memory (more than 4MB). We don't want to allocate all memory
+ * in rheap since small memory allocation/deallocation will fragment the
+ * rheap and make the furture large allocation fail.
+ */
+
+void *fsl_diu_alloc(unsigned long size, phys_addr_t *phys)
+{
+ void *virt;
+
+ pr_debug("size=%lu\n", size);
+
+ virt = (void *)__get_free_pages(GFP_DMA | __GFP_ZERO, get_order(size));
+ if (virt) {
+ *phys = virt_to_phys(virt);
+ pr_debug("virt %p, phys=%llx\n", virt, (uint64_t) *phys);
+ return virt;
+ }
+ if (!diu_ops.diu_mem) {
+ printk(KERN_INFO "%s: no diu_mem."
+ " To reserve more memory, put 'diufb=15M' "
+ "in the command line\n", __func__);
+ return NULL;
+ }
+
+ virt = (void *)rh_alloc(&diu_ops.diu_rh_info, size, "DIU");
+ if (virt) {
+ *phys = virt_to_bus(virt);
+ memset(virt, 0, size);
+ }
+
+ pr_debug("rh virt=%p phys=%lx\n", virt, *phys);
+
+ return virt;
+}
+
+void fsl_diu_free(void *p, unsigned long size)
+{
+ pr_debug("p=%p size=%lu\n", p, size);
+
+ if (!p)
+ return;
+
+ if ((p >= diu_ops.diu_mem) &&
+ (p < (diu_ops.diu_mem + diu_ops.diu_size))) {
+ pr_debug("rh\n");
+ rh_free(&diu_ops.diu_rh_info, (unsigned long) p);
+ } else {
+ pr_debug("dma\n");
+ free_pages((unsigned long)p, get_order(size));
+ }
+}
+
+static int fsl_diu_enable_panel(struct fb_info *info)
+{
+ struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
+ struct diu *hw = dr.diu_reg;
+ struct diu_ad *ad = mfbi->ad;
+ struct fsl_diu_data *machine_data = mfbi->parent;
+ int res = 0;
+
+ pr_debug("enable_panel index %d\n", mfbi->index);
+ if (mfbi->type != MFB_TYPE_OFF) {
+ switch (mfbi->index) {
+ case 0: /* plane 0 */
+ if (hw->desc[0] != ad->paddr)
+ out_be32(&hw->desc[0], ad->paddr);
+ break;
+ case 1: /* plane 1 AOI 0 */
+ cmfbi = machine_data->fsl_diu_info[2]->par;
+ if (hw->desc[1] != ad->paddr) { /* AOI0 closed */
+ if (cmfbi->count > 0) /* AOI1 open */
+ ad->next_ad =
+ cpu_to_le32(cmfbi->ad->paddr);
+ else
+ ad->next_ad = 0;
+ out_be32(&hw->desc[1], ad->paddr);
+ }
+ break;
+ case 3: /* plane 2 AOI 0 */
+ cmfbi = machine_data->fsl_diu_info[4]->par;
+ if (hw->desc[2] != ad->paddr) { /* AOI0 closed */
+ if (cmfbi->count > 0) /* AOI1 open */
+ ad->next_ad =
+ cpu_to_le32(cmfbi->ad->paddr);
+ else
+ ad->next_ad = 0;
+ out_be32(&hw->desc[2], ad->paddr);
+ }
+ break;
+ case 2: /* plane 1 AOI 1 */
+ pmfbi = machine_data->fsl_diu_info[1]->par;
+ ad->next_ad = 0;
+ if (hw->desc[1] == machine_data->dummy_ad->paddr)
+ out_be32(&hw->desc[1], ad->paddr);
+ else /* AOI0 open */
+ pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
+ break;
+ case 4: /* plane 2 AOI 1 */
+ pmfbi = machine_data->fsl_diu_info[3]->par;
+ ad->next_ad = 0;
+ if (hw->desc[2] == machine_data->dummy_ad->paddr)
+ out_be32(&hw->desc[2], ad->paddr);
+ else /* AOI0 was open */
+ pmfbi->ad->next_ad = cpu_to_le32(ad->paddr);
+ break;
+ default:
+ res = -EINVAL;
+ break;
+ }
+ } else
+ res = -EINVAL;
+ return res;
+}
+
+static int fsl_diu_disable_panel(struct fb_info *info)
+{
+ struct mfb_info *pmfbi, *cmfbi, *mfbi = info->par;
+ struct diu *hw = dr.diu_reg;
+ struct diu_ad *ad = mfbi->ad;
+ struct fsl_diu_data *machine_data = mfbi->parent;
+ int res = 0;
+
+ switch (mfbi->index) {
+ case 0: /* plane 0 */
+ if (hw->desc[0] != machine_data->dummy_ad->paddr)
+ out_be32(&hw->desc[0],
+ machine_data->dummy_ad->paddr);
+ break;
+ case 1: /* plane 1 AOI 0 */
+ cmfbi = machine_data->fsl_diu_info[2]->par;
+ if (cmfbi->count > 0) /* AOI1 is open */
+ out_be32(&hw->desc[1], cmfbi->ad->paddr);
+ /* move AOI1 to the first */
+ else /* AOI1 was closed */
+ out_be32(&hw->desc[1],
+ machine_data->dummy_ad->paddr);
+ /* close AOI 0 */
+ break;
+ case 3: /* plane 2 AOI 0 */
+ cmfbi = machine_data->fsl_diu_info[4]->par;
+ if (cmfbi->count > 0) /* AOI1 is open */
+ out_be32(&hw->desc[2], cmfbi->ad->paddr);
+ /* move AOI1 to the first */
+ else /* AOI1 was closed */
+ out_be32(&hw->desc[2],
+ machine_data->dummy_ad->paddr);
+ /* close AOI 0 */
+ break;
+ case 2: /* plane 1 AOI 1 */
+ pmfbi = machine_data->fsl_diu_info[1]->par;
+ if (hw->desc[1] != ad->paddr) {
+ /* AOI1 is not the first in the chain */
+ if (pmfbi->count > 0)
+ /* AOI0 is open, must be the first */
+ pmfbi->ad->next_ad = 0;
+ } else /* AOI1 is the first in the chain */
+ out_be32(&hw->desc[1], machine_data->dummy_ad->paddr);
+ /* close AOI 1 */
+ break;
+ case 4: /* plane 2 AOI 1 */
+ pmfbi = machine_data->fsl_diu_info[3]->par;
+ if (hw->desc[2] != ad->paddr) {
+ /* AOI1 is not the first in the chain */
+ if (pmfbi->count > 0)
+ /* AOI0 is open, must be the first */
+ pmfbi->ad->next_ad = 0;
+ } else /* AOI1 is the first in the chain */
+ out_be32(&hw->desc[2], machine_data->dummy_ad->paddr);
+ /* close AOI 1 */
+ break;
+ default:
+ res = -EINVAL;
+ break;
+ }
+
+ return res;
+}
+
+static void enable_lcdc(struct fb_info *info)
+{
+ struct diu *hw = dr.diu_reg;
+ struct mfb_info *mfbi = info->par;
+ struct fsl_diu_data *machine_data = mfbi->parent;
+
+ if (!machine_data->fb_enabled) {
+ out_be32(&hw->diu_mode, dr.mode);
+ machine_data->fb_enabled++;
+ }
+}
+
+static void disable_lcdc(struct fb_info *info)
+{
+ struct diu *hw = dr.diu_reg;
+ struct mfb_info *mfbi = info->par;
+ struct fsl_diu_data *machine_data = mfbi->parent;
+
+ if (machine_data->fb_enabled) {
+ out_be32(&hw->diu_mode, 0);
+ machine_data->fb_enabled = 0;
+ }
+}
+
+static void adjust_aoi_size_position(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ struct mfb_info *lower_aoi_mfbi, *upper_aoi_mfbi, *mfbi = info->par;
+ struct fsl_diu_data *machine_data = mfbi->parent;
+ int available_height, upper_aoi_bottom, index = mfbi->index;
+ int lower_aoi_is_open, upper_aoi_is_open;
+ __u32 base_plane_width, base_plane_height, upper_aoi_height;
+
+ base_plane_width = machine_data->fsl_diu_info[0]->var.xres;
+ base_plane_height = machine_data->fsl_diu_info[0]->var.yres;
+
+ switch (index) {
+ case 0:
+ if (mfbi->x_aoi_d != 0)
+ mfbi->x_aoi_d = 0;
+ if (mfbi->y_aoi_d != 0)
+ mfbi->y_aoi_d = 0;
+ break;
+ case 1: /* AOI 0 */
+ case 3:
+ lower_aoi_mfbi = machine_data->fsl_diu_info[index+1]->par;
+ lower_aoi_is_open = lower_aoi_mfbi->count > 0 ? 1 : 0;
+ if (var->xres > base_plane_width)
+ var->xres = base_plane_width;
+ if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
+ mfbi->x_aoi_d = base_plane_width - var->xres;
+
+ if (lower_aoi_is_open)
+ available_height = lower_aoi_mfbi->y_aoi_d;
+ else
+ available_height = base_plane_height;
+ if (var->yres > available_height)
+ var->yres = available_height;
+ if ((mfbi->y_aoi_d + var->yres) > available_height)
+ mfbi->y_aoi_d = available_height - var->yres;
+ break;
+ case 2: /* AOI 1 */
+ case 4:
+ upper_aoi_mfbi = machine_data->fsl_diu_info[index-1]->par;
+ upper_aoi_height =
+ machine_data->fsl_diu_info[index-1]->var.yres;
+ upper_aoi_bottom = upper_aoi_mfbi->y_aoi_d + upper_aoi_height;
+ upper_aoi_is_open = upper_aoi_mfbi->count > 0 ? 1 : 0;
+ if (var->xres > base_plane_width)
+ var->xres = base_plane_width;
+ if ((mfbi->x_aoi_d + var->xres) > base_plane_width)
+ mfbi->x_aoi_d = base_plane_width - var->xres;
+ if (mfbi->y_aoi_d < 0)
+ mfbi->y_aoi_d = 0;
+ if (upper_aoi_is_open) {
+ if (mfbi->y_aoi_d < upper_aoi_bottom)
+ mfbi->y_aoi_d = upper_aoi_bottom;
+ available_height = base_plane_height
+ - upper_aoi_bottom;
+ } else
+ available_height = base_plane_height;
+ if (var->yres > available_height)
+ var->yres = available_height;
+ if ((mfbi->y_aoi_d + var->yres) > base_plane_height)
+ mfbi->y_aoi_d = base_plane_height - var->yres;
+ break;
+ }
+}
+/*
+ * Checks to see if the hardware supports the state requested by var passed
+ * in. This function does not alter the hardware state! If the var passed in
+ * is slightly off by what the hardware can support then we alter the var
+ * PASSED in to what we can do. If the hardware doesn't support mode change
+ * a -EINVAL will be returned by the upper layers.
+ */
+static int fsl_diu_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ unsigned long htotal, vtotal;
+
+ pr_debug("check_var xres: %d\n", var->xres);
+ pr_debug("check_var yres: %d\n", var->yres);
+
+ if (var->xres_virtual < var->xres)
+ var->xres_virtual = var->xres;
+ if (var->yres_virtual < var->yres)
+ var->yres_virtual = var->yres;
+
+ if (var->xoffset < 0)
+ var->xoffset = 0;
+
+ if (var->yoffset < 0)
+ var->yoffset = 0;
+
+ if (var->xoffset + info->var.xres > info->var.xres_virtual)
+ var->xoffset = info->var.xres_virtual - info->var.xres;
+
+ if (var->yoffset + info->var.yres > info->var.yres_virtual)
+ var->yoffset = info->var.yres_virtual - info->var.yres;
+
+ if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
+ (var->bits_per_pixel != 16))
+ var->bits_per_pixel = default_bpp;
+
+ switch (var->bits_per_pixel) {
+ case 16:
+ var->red.length = 5;
+ var->red.offset = 11;
+ var->red.msb_right = 0;
+
+ var->green.length = 6;
+ var->green.offset = 5;
+ var->green.msb_right = 0;
+
+ var->blue.length = 5;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ var->transp.msb_right = 0;
+ break;
+ case 24:
+ var->red.length = 8;
+ var->red.offset = 0;
+ var->red.msb_right = 0;
+
+ var->green.length = 8;
+ var->green.offset = 8;
+ var->green.msb_right = 0;
+
+ var->blue.length = 8;
+ var->blue.offset = 16;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 0;
+ var->transp.offset = 0;
+ var->transp.msb_right = 0;
+ break;
+ case 32:
+ var->red.length = 8;
+ var->red.offset = 16;
+ var->red.msb_right = 0;
+
+ var->green.length = 8;
+ var->green.offset = 8;
+ var->green.msb_right = 0;
+
+ var->blue.length = 8;
+ var->blue.offset = 0;
+ var->blue.msb_right = 0;
+
+ var->transp.length = 8;
+ var->transp.offset = 24;
+ var->transp.msb_right = 0;
+
+ break;
+ }
+ /* If the pixclock is below the minimum spec'd value then set to
+ * refresh rate for 60Hz since this is supported by most monitors.
+ * Refer to Documentation/fb/ for calculations.
+ */
+ if ((var->pixclock < MIN_PIX_CLK) || (var->pixclock > MAX_PIX_CLK)) {
+ htotal = var->xres + var->right_margin + var->hsync_len +
+ var->left_margin;
+ vtotal = var->yres + var->lower_margin + var->vsync_len +
+ var->upper_margin;
+ var->pixclock = (vtotal * htotal * 6UL) / 100UL;
+ var->pixclock = KHZ2PICOS(var->pixclock);
+ pr_debug("pixclock set for 60Hz refresh = %u ps\n",
+ var->pixclock);
+ }
+
+ var->height = -1;
+ var->width = -1;
+ var->grayscale = 0;
+
+ /* Copy nonstd field to/from sync for fbset usage */
+ var->sync |= var->nonstd;
+ var->nonstd |= var->sync;
+
+ adjust_aoi_size_position(var, info);
+ return 0;
+}
+
+static void set_fix(struct fb_info *info)
+{
+ struct fb_fix_screeninfo *fix = &info->fix;
+ struct fb_var_screeninfo *var = &info->var;
+ struct mfb_info *mfbi = info->par;
+
+ strncpy(fix->id, mfbi->id, strlen(mfbi->id));
+ fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
+ fix->type = FB_TYPE_PACKED_PIXELS;
+ fix->accel = FB_ACCEL_NONE;
+ fix->visual = FB_VISUAL_TRUECOLOR;
+ fix->xpanstep = 1;
+ fix->ypanstep = 1;
+}
+
+static void update_lcdc(struct fb_info *info)
+{
+ struct fb_var_screeninfo *var = &info->var;
+ struct mfb_info *mfbi = info->par;
+ struct fsl_diu_data *machine_data = mfbi->parent;
+ struct diu *hw;
+ int i, j;
+ char __iomem *cursor_base, *gamma_table_base;
+
+ u32 temp;
+
+ hw = dr.diu_reg;
+
+ if (mfbi->type == MFB_TYPE_OFF) {
+ fsl_diu_disable_panel(info);
+ return;
+ }
+
+ diu_ops.set_monitor_port(machine_data->monitor_port);
+ gamma_table_base = pool.gamma.vaddr;
+ cursor_base = pool.cursor.vaddr;
+ /* Prep for DIU init - gamma table, cursor table */
+
+ for (i = 0; i <= 2; i++)
+ for (j = 0; j <= 255; j++)
+ *gamma_table_base++ = j;
+
+ diu_ops.set_gamma_table(machine_data->monitor_port, pool.gamma.vaddr);
+
+ pr_debug("update-lcdc: HW - %p\n Disabling DIU\n", hw);
+ disable_lcdc(info);
+
+ /* Program DIU registers */
+
+ out_be32(&hw->gamma, pool.gamma.paddr);
+ out_be32(&hw->cursor, pool.cursor.paddr);
+
+ out_be32(&hw->bgnd, 0x007F7F7F); /* BGND */
+ out_be32(&hw->bgnd_wb, 0); /* BGND_WB */
+ out_be32(&hw->disp_size, (var->yres << 16 | var->xres));
+ /* DISP SIZE */
+ pr_debug("DIU xres: %d\n", var->xres);
+ pr_debug("DIU yres: %d\n", var->yres);
+
+ out_be32(&hw->wb_size, 0); /* WB SIZE */
+ out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */
+
+ /* Horizontal and vertical configuration register */
+ temp = var->left_margin << 22 | /* BP_H */
+ var->hsync_len << 11 | /* PW_H */
+ var->right_margin; /* FP_H */
+
+ out_be32(&hw->hsyn_para, temp);
+
+ temp = var->upper_margin << 22 | /* BP_V */
+ var->vsync_len << 11 | /* PW_V */
+ var->lower_margin; /* FP_V */
+
+ out_be32(&hw->vsyn_para, temp);
+
+ pr_debug("DIU right_margin - %d\n", var->right_margin);
+ pr_debug("DIU left_margin - %d\n", var->left_margin);
+ pr_debug("DIU hsync_len - %d\n", var->hsync_len);
+ pr_debug("DIU upper_margin - %d\n", var->upper_margin);
+ pr_debug("DIU lower_margin - %d\n", var->lower_margin);
+ pr_debug("DIU vsync_len - %d\n", var->vsync_len);
+ pr_debug("DIU HSYNC - 0x%08x\n", hw->hsyn_para);
+ pr_debug("DIU VSYNC - 0x%08x\n", hw->vsyn_para);
+
+ diu_ops.set_pixel_clock(var->pixclock);
+
+ out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */
+ out_be32(&hw->thresholds, 0x00037800); /* The Thresholds */
+ out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */
+ out_be32(&hw->plut, 0x01F5F666);
+
+ /* Enable the DIU */
+ enable_lcdc(info);
+}
+
+static int map_video_memory(struct fb_info *info)
+{
+ phys_addr_t phys;
+
+ pr_debug("info->var.xres_virtual = %d\n", info->var.xres_virtual);
+ pr_debug("info->var.yres_virtual = %d\n", info->var.yres_virtual);
+ pr_debug("info->fix.line_length = %d\n", info->fix.line_length);
+
+ info->fix.smem_len = info->fix.line_length * info->var.yres_virtual;
+ pr_debug("MAP_VIDEO_MEMORY: smem_len = %d\n", info->fix.smem_len);
+ info->screen_base = fsl_diu_alloc(info->fix.smem_len, &phys);
+ if (info->screen_base == 0) {
+ printk(KERN_ERR "Unable to allocate fb memory\n");
+ return -ENOMEM;
+ }
+ info->fix.smem_start = (unsigned long) phys;
+ info->screen_size = info->fix.smem_len;
+
+ pr_debug("Allocated fb @ paddr=0x%08lx, size=%d.\n",
+ info->fix.smem_start,
+ info->fix.smem_len);
+ pr_debug("screen base %p\n", info->screen_base);
+
+ return 0;
+}
+
+static void unmap_video_memory(struct fb_info *info)
+{
+ fsl_diu_free(info->screen_base, info->fix.smem_len);
+ info->screen_base = 0;
+ info->fix.smem_start = 0;
+ info->fix.smem_len = 0;
+}
+
+/*
+ * Using the fb_var_screeninfo in fb_info we set the resolution of this
+ * particular framebuffer. This function alters the fb_fix_screeninfo stored
+ * in fb_info. It does not alter var in fb_info since we are using that
+ * data. This means we depend on the data in var inside fb_info to be
+ * supported by the hardware. fsl_diu_check_var is always called before
+ * fsl_diu_set_par to ensure this.
+ */
+static int fsl_diu_set_par(struct fb_info *info)
+{
+ unsigned long len;
+ struct fb_var_screeninfo *var = &info->var;
+ struct mfb_info *mfbi = info->par;
+ struct fsl_diu_data *machine_data = mfbi->parent;
+ struct diu_ad *ad = mfbi->ad;
+ struct diu *hw;
+
+ hw = dr.diu_reg;
+
+ set_fix(info);
+ mfbi->cursor_reset = 1;
+
+ len = info->var.yres_virtual * info->fix.line_length;
+ /* Alloc & dealloc each time resolution/bpp change */
+ if (len != info->fix.smem_len) {
+ if (info->fix.smem_start)
+ unmap_video_memory(info);
+ pr_debug("SET PAR: smem_len = %d\n", info->fix.smem_len);
+
+ /* Memory allocation for framebuffer */
+ if (map_video_memory(info)) {
+ printk(KERN_ERR "Unable to allocate fb memory 1\n");
+ return -ENOMEM;
+ }
+ }
+
+ ad->pix_fmt =
+ diu_ops.get_pixel_format(var->bits_per_pixel,
+ machine_data->monitor_port);
+ ad->addr = cpu_to_le32(info->fix.smem_start);
+ ad->src_size_g_alpha = cpu_to_le32((var->yres << 12) |
+ var->xres) | mfbi->g_alpha;
+ /* fix me. AOI should not be greater than display size */
+ ad->aoi_size = cpu_to_le32((var->yres << 16) | var->xres);
+ ad->offset_xyi = 0;
+ ad->offset_xyd = cpu_to_le32((mfbi->y_aoi_d << 16) | mfbi->x_aoi_d);
+
+ /* Disable chroma keying function */
+ ad->ckmax_r = 0;
+ ad->ckmax_g = 0;
+ ad->ckmax_b = 0;
+
+ ad->ckmin_r = 255;
+ ad->ckmin_g = 255;
+ ad->ckmin_b = 255;
+
+ if (mfbi->index == 0)
+ update_lcdc(info);
+ return 0;
+}
+
+static inline __u32 CNVT_TOHW(__u32 val, __u32 width)
+{
+ return ((val<<width) + 0x7FFF - val)>>16;
+}
+
+/*
+ * Set a single color register. The values supplied have a 16 bit magnitude
+ * which needs to be scaled in this function for the hardware. Things to take
+ * into consideration are how many color registers, if any, are supported with
+ * the current color visual. With truecolor mode no color palettes are
+ * supported. Here a psuedo palette is created which we store the value in
+ * pseudo_palette in struct fb_info. For pseudocolor mode we have a limited
+ * color palette.
+ */
+static int fsl_diu_setcolreg(unsigned regno, unsigned red, unsigned green,
+ unsigned blue, unsigned transp, struct fb_info *info)
+{
+ int ret = 1;
+
+ /*
+ * If greyscale is true, then we convert the RGB value
+ * to greyscale no matter what visual we are using.
+ */
+ if (info->var.grayscale)
+ red = green = blue = (19595 * red + 38470 * green +
+ 7471 * blue) >> 16;
+ switch (info->fix.visual) {
+ case FB_VISUAL_TRUECOLOR:
+ /*
+ * 16-bit True Colour. We encode the RGB value
+ * according to the RGB bitfield information.
+ */
+ if (regno < 16) {
+ u32 *pal = info->pseudo_palette;
+ u32 v;
+
+ red = CNVT_TOHW(red, info->var.red.length);
+ green = CNVT_TOHW(green, info->var.green.length);
+ blue = CNVT_TOHW(blue, info->var.blue.length);
+ transp = CNVT_TOHW(transp, info->var.transp.length);
+
+ v = (red << info->var.red.offset) |
+ (green << info->var.green.offset) |
+ (blue << info->var.blue.offset) |
+ (transp << info->var.transp.offset);
+
+ pal[regno] = v;
+ ret = 0;
+ }
+ break;
+ case FB_VISUAL_STATIC_PSEUDOCOLOR:
+ case FB_VISUAL_PSEUDOCOLOR:
+ break;
+ }
+
+ return ret;
+}
+
+/*
+ * Pan (or wrap, depending on the `vmode' field) the display using the
+ * 'xoffset' and 'yoffset' fields of the 'var' structure. If the values
+ * don't fit, return -EINVAL.
+ */
+static int fsl_diu_pan_display(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ if ((info->var.xoffset == var->xoffset) &&
+ (info->var.yoffset == var->yoffset))
+ return 0; /* No change, do nothing */
+
+ if (var->xoffset < 0 || var->yoffset < 0
+ || var->xoffset + info->var.xres > info->var.xres_virtual
+ || var->yoffset + info->var.yres > info->var.yres_virtual)
+ return -EINVAL;
+
+ info->var.xoffset = var->xoffset;
+ info->var.yoffset = var->yoffset;
+
+ if (var->vmode & FB_VMODE_YWRAP)
+ info->var.vmode |= FB_VMODE_YWRAP;
+ else
+ info->var.vmode &= ~FB_VMODE_YWRAP;
+
+ return 0;
+}
+
+/*
+ * Blank the screen if blank_mode != 0, else unblank. Return 0 if blanking
+ * succeeded, != 0 if un-/blanking failed.
+ * blank_mode == 2: suspend vsync
+ * blank_mode == 3: suspend hsync
+ * blank_mode == 4: powerdown
+ */
+static int fsl_diu_blank(int blank_mode, struct fb_info *info)
+{
+ struct mfb_info *mfbi = info->par;
+
+ mfbi->blank = blank_mode;
+
+ switch (blank_mode) {
+ case FB_BLANK_VSYNC_SUSPEND:
+ case FB_BLANK_HSYNC_SUSPEND:
+ /* FIXME: fixes to enable_panel and enable lcdc needed */
+ case FB_BLANK_NORMAL:
+ /* fsl_diu_disable_panel(info);*/
+ break;
+ case FB_BLANK_POWERDOWN:
+ /* disable_lcdc(info); */
+ break;
+ case FB_BLANK_UNBLANK:
+ /* fsl_diu_enable_panel(info);*/
+ break;
+ }
+
+ return 0;
+}
+
+static int fsl_diu_ioctl(struct fb_info *info, unsigned int cmd,
+ unsigned long arg)
+{
+ struct mfb_info *mfbi = info->par;
+ struct diu_ad *ad = mfbi->ad;
+ struct mfb_chroma_key ck;
+ unsigned char global_alpha;
+ struct aoi_display_offset aoi_d;
+ __u32 pix_fmt;
+ void __user *buf = (void __user *)arg;
+
+ if (!arg)
+ return -EINVAL;
+ switch (cmd) {
+ case MFB_SET_PIXFMT:
+ if (copy_from_user(&pix_fmt, buf, sizeof(pix_fmt)))
+ return -EFAULT;
+ ad->pix_fmt = pix_fmt;
+ pr_debug("Set pixel format to 0x%08x\n", ad->pix_fmt);
+ break;
+ case MFB_GET_PIXFMT:
+ pix_fmt = ad->pix_fmt;
+ if (copy_to_user(buf, &pix_fmt, sizeof(pix_fmt)))
+ return -EFAULT;
+ pr_debug("get pixel format 0x%08x\n", ad->pix_fmt);
+ break;
+ case MFB_SET_AOID:
+ if (copy_from_user(&aoi_d, buf, sizeof(aoi_d)))
+ return -EFAULT;
+ mfbi->x_aoi_d = aoi_d.x_aoi_d;
+ mfbi->y_aoi_d = aoi_d.y_aoi_d;
+ pr_debug("set AOI display offset of index %d to (%d,%d)\n",
+ mfbi->index, aoi_d.x_aoi_d, aoi_d.y_aoi_d);
+ fsl_diu_check_var(&info->var, info);
+ fsl_diu_set_par(info);
+ break;
+ case MFB_GET_AOID:
+ aoi_d.x_aoi_d = mfbi->x_aoi_d;
+ aoi_d.y_aoi_d = mfbi->y_aoi_d;
+ if (copy_to_user(buf, &aoi_d, sizeof(aoi_d)))
+ return -EFAULT;
+ pr_debug("get AOI display offset of index %d (%d,%d)\n",
+ mfbi->index, aoi_d.x_aoi_d, aoi_d.y_aoi_d);
+ break;
+ case MFB_GET_ALPHA:
+ global_alpha = mfbi->g_alpha;
+ if (copy_to_user(buf, &global_alpha, sizeof(global_alpha)))
+ return -EFAULT;
+ pr_debug("get global alpha of index %d\n", mfbi->index);
+ break;
+ case MFB_SET_ALPHA:
+ /* set panel information */
+ if (copy_from_user(&global_alpha, buf, sizeof(global_alpha)))
+ return -EFAULT;
+ ad->src_size_g_alpha = (ad->src_size_g_alpha & (~0xff)) |
+ (global_alpha & 0xff);
+ mfbi->g_alpha = global_alpha;
+ pr_debug("set global alpha for index %d\n", mfbi->index);
+ break;
+ case MFB_SET_CHROMA_KEY:
+ /* set panel winformation */
+ if (copy_from_user(&ck, buf, sizeof(ck)))
+ return -EFAULT;
+
+ if (ck.enable &&
+ (ck.red_max < ck.red_min ||
+ ck.green_max < ck.green_min ||
+ ck.blue_max < ck.blue_min))
+ return -EINVAL;
+
+ if (!ck.enable) {
+ ad->ckmax_r = 0;
+ ad->ckmax_g = 0;
+ ad->ckmax_b = 0;
+ ad->ckmin_r = 255;
+ ad->ckmin_g = 255;
+ ad->ckmin_b = 255;
+ } else {
+ ad->ckmax_r = ck.red_max;
+ ad->ckmax_g = ck.green_max;
+ ad->ckmax_b = ck.blue_max;
+ ad->ckmin_r = ck.red_min;
+ ad->ckmin_g = ck.green_min;
+ ad->ckmin_b = ck.blue_min;
+ }
+ pr_debug("set chroma key\n");
+ break;
+ case FBIOGET_GWINFO:
+ if (mfbi->type == MFB_TYPE_OFF)
+ return -ENODEV;
+ /* get graphic window information */
+ if (copy_to_user(buf, ad, sizeof(*ad)))
+ return -EFAULT;
+ break;
+ case FBIOGET_HWCINFO:
+ pr_debug("FBIOGET_HWCINFO:0x%08x\n", FBIOGET_HWCINFO);
+ break;
+ case FBIOPUT_MODEINFO:
+ pr_debug("FBIOPUT_MODEINFO:0x%08x\n", FBIOPUT_MODEINFO);
+ break;
+ case FBIOGET_DISPINFO:
+ pr_debug("FBIOGET_DISPINFO:0x%08x\n", FBIOGET_DISPINFO);
+ break;
+
+ default:
+ printk(KERN_ERR "Unknown ioctl command (0x%08X)\n", cmd);
+ return -ENOIOCTLCMD;
+ }
+
+ return 0;
+}
+
+/* turn on fb if count == 1
+ */
+static int fsl_diu_open(struct fb_info *info, int user)
+{
+ struct mfb_info *mfbi = info->par;
+ int res = 0;
+
+ spin_lock(&diu_lock);
+ mfbi->count++;
+ if (mfbi->count == 1) {
+ pr_debug("open plane index %d\n", mfbi->index);
+ fsl_diu_check_var(&info->var, info);
+ res = fsl_diu_set_par(info);
+ if (res < 0)
+ mfbi->count--;
+ else {
+ res = fsl_diu_enable_panel(info);
+ if (res < 0)
+ mfbi->count--;
+ }
+ }
+
+ spin_unlock(&diu_lock);
+ return res;
+}
+
+/* turn off fb if count == 0
+ */
+static int fsl_diu_release(struct fb_info *info, int user)
+{
+ struct mfb_info *mfbi = info->par;
+ int res = 0;
+
+ spin_lock(&diu_lock);
+ mfbi->count--;
+ if (mfbi->count == 0) {
+ pr_debug("release plane index %d\n", mfbi->index);
+ res = fsl_diu_disable_panel(info);
+ if (res < 0)
+ mfbi->count++;
+ }
+ spin_unlock(&diu_lock);
+ return res;
+}
+
+static struct fb_ops fsl_diu_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = fsl_diu_check_var,
+ .fb_set_par = fsl_diu_set_par,
+ .fb_setcolreg = fsl_diu_setcolreg,
+ .fb_blank = fsl_diu_blank,
+ .fb_pan_display = fsl_diu_pan_display,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+ .fb_ioctl = fsl_diu_ioctl,
+ .fb_open = fsl_diu_open,
+ .fb_release = fsl_diu_release,
+};
+
+static int init_fbinfo(struct fb_info *info)
+{
+ struct mfb_info *mfbi = info->par;
+
+ info->device = NULL;
+ info->var.activate = FB_ACTIVATE_NOW;
+ info->fbops = &fsl_diu_ops;
+ info->flags = FBINFO_FLAG_DEFAULT;
+ info->pseudo_palette = &mfbi->pseudo_palette;
+
+ /* Allocate colormap */
+ fb_alloc_cmap(&info->cmap, 16, 0);
+ return 0;
+}
+
+static int install_fb(struct fb_info *info)
+{
+ int rc;
+ struct mfb_info *mfbi = info->par;
+ const char *aoi_mode, *init_aoi_mode = "320x240";
+
+ if (init_fbinfo(info))
+ return -EINVAL;
+
+ if (mfbi->index == 0) /* plane 0 */
+ aoi_mode = fb_mode;
+ else
+ aoi_mode = init_aoi_mode;
+ pr_debug("mode used = %s\n", aoi_mode);
+ rc = fb_find_mode(&info->var, info, aoi_mode, fsl_diu_mode_db,
+ ARRAY_SIZE(fsl_diu_mode_db), &fsl_diu_default_mode, default_bpp);
+
+ switch (rc) {
+ case 1:
+ pr_debug("using mode specified in @mode\n");
+ break;
+ case 2:
+ pr_debug("using mode specified in @mode "
+ "with ignored refresh rate\n");
+ break;
+ case 3:
+ pr_debug("using mode default mode\n");
+ break;
+ case 4:
+ pr_debug("using mode from list\n");
+ break;
+ default:
+ pr_debug("rc = %d\n", rc);
+ pr_debug("failed to find mode\n");
+ return -EINVAL;
+ break;
+ }
+
+ pr_debug("xres_virtual %d\n", info->var.xres_virtual);
+ pr_debug("bits_per_pixel %d\n", info->var.bits_per_pixel);
+
+ pr_debug("info->var.yres_virtual = %d\n", info->var.yres_virtual);
+ pr_debug("info->fix.line_length = %d\n", info->fix.line_length);
+
+ if (mfbi->type == MFB_TYPE_OFF)
+ mfbi->blank = FB_BLANK_NORMAL;
+ else
+ mfbi->blank = FB_BLANK_UNBLANK;
+
+ if (fsl_diu_check_var(&info->var, info)) {
+ printk(KERN_ERR "fb_check_var failed");
+ fb_dealloc_cmap(&info->cmap);
+ return -EINVAL;
+ }
+
+ if (fsl_diu_set_par(info)) {
+ printk(KERN_ERR "fb_set_par failed");
+ fb_dealloc_cmap(&info->cmap);
+ return -EINVAL;
+ }
+
+ if (register_framebuffer(info) < 0) {
+ printk(KERN_ERR "register_framebuffer failed");
+ unmap_video_memory(info);
+ fb_dealloc_cmap(&info->cmap);
+ return -EINVAL;
+ }
+
+ mfbi->registered = 1;
+ printk(KERN_INFO "fb%d: %s fb device registered successfully.\n",
+ info->node, info->fix.id);
+
+ return 0;
+}
+
+static void __exit uninstall_fb(struct fb_info *info)
+{
+ struct mfb_info *mfbi = info->par;
+
+ if (!mfbi->registered)
+ return;
+
+ unregister_framebuffer(info);
+ unmap_video_memory(info);
+ if (&info->cmap)
+ fb_dealloc_cmap(&info->cmap);
+
+ mfbi->registered = 0;
+}
+
+static irqreturn_t fsl_diu_isr(int irq, void *dev_id)
+{
+ struct diu *hw = dr.diu_reg;
+ unsigned int status = in_be32(&hw->int_status);
+
+ if (status) {
+ /* This is the workaround for underrun */
+ if (status & INT_UNDRUN) {
+ out_be32(&hw->diu_mode, 0);
+ pr_debug("Err: DIU occurs underrun!\n");
+ udelay(1);
+ out_be32(&hw->diu_mode, 1);
+ }
+#if defined(CONFIG_NOT_COHERENT_CACHE)
+ else if (status & INT_VSYNC) {
+ unsigned int i;
+ for (i = 0; i < coherence_data_size;
+ i += d_cache_line_size)
+ __asm__ __volatile__ (
+ "dcbz 0, %[input]"
+ ::[input]"r"(&coherence_data[i]));
+ }
+#endif
+ return IRQ_HANDLED;
+ }
+ return IRQ_NONE;
+}
+
+static int request_irq_local(int irq)
+{
+ unsigned long status, ints;
+ struct diu *hw;
+ int ret;
+
+ hw = dr.diu_reg;
+
+ /* Read to clear the status */
+ status = in_be32(&hw->int_status);
+
+ ret = request_irq(irq, fsl_diu_isr, 0, "diu", 0);
+ if (ret)
+ pr_info("Request diu IRQ failed.\n");
+ else {
+ ints = INT_PARERR | INT_LS_BF_VS;
+#if !defined(CONFIG_NOT_COHERENT_CACHE)
+ ints |= INT_VSYNC;
+#endif
+ if (dr.mode == MFB_MODE2 || dr.mode == MFB_MODE3)
+ ints |= INT_VSYNC_WB;
+
+ /* Read to clear the status */
+ status = in_be32(&hw->int_status);
+ out_be32(&hw->int_mask, ints);
+ }
+ return ret;
+}
+
+static void free_irq_local(int irq)
+{
+ struct diu *hw = dr.diu_reg;
+
+ /* Disable all LCDC interrupt */
+ out_be32(&hw->int_mask, 0x1f);
+
+ free_irq(irq, 0);
+}
+
+#ifdef CONFIG_PM
+/*
+ * Power management hooks. Note that we won't be called from IRQ context,
+ * unlike the blank functions above, so we may sleep.
+ */
+static int fsl_diu_suspend(struct of_device *dev, pm_message_t state)
+{
+ struct fsl_diu_data *machine_data;
+
+ machine_data = dev_get_drvdata(&ofdev->dev);
+ disable_lcdc(machine_data->fsl_diu_info[0]);
+
+ return 0;
+}
+
+static int fsl_diu_resume(struct of_device *dev)
+{
+ struct fsl_diu_data *machine_data;
+
+ machine_data = dev_get_drvdata(&ofdev->dev);
+ enable_lcdc(machine_data->fsl_diu_info[0]);
+
+ return 0;
+}
+
+#else
+#define fsl_diu_suspend NULL
+#define fsl_diu_resume NULL
+#endif /* CONFIG_PM */
+
+/* Align to 64-bit(8-byte), 32-byte, etc. */
+static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align)
+{
+ u32 offset, ssize;
+ u32 mask;
+ dma_addr_t paddr = 0;
+
+ ssize = size + bytes_align;
+ buf->vaddr = dma_alloc_coherent(0, ssize, &paddr, GFP_DMA | __GFP_ZERO);
+ if (!buf->vaddr)
+ return -ENOMEM;
+
+ buf->paddr = (__u32) paddr;
+
+ mask = bytes_align - 1;
+ offset = (u32)buf->paddr & mask;
+ if (offset) {
+ buf->offset = bytes_align - offset;
+ buf->paddr = (u32)buf->paddr + offset;
+ } else
+ buf->offset = 0;
+ return 0;
+}
+
+static void free_buf(struct diu_addr *buf, u32 size, u32 bytes_align)
+{
+ dma_free_coherent(0, size + bytes_align,
+ buf->vaddr, (buf->paddr - buf->offset));
+ return;
+}
+
+static ssize_t store_monitor(struct device *device,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int old_monitor_port;
+ unsigned long val;
+ struct fsl_diu_data *machine_data =
+ container_of(attr, struct fsl_diu_data, dev_attr);
+
+ if (strict_strtoul(buf, 10, &val))
+ return 0;
+
+ old_monitor_port = machine_data->monitor_port;
+ machine_data->monitor_port = diu_ops.set_sysfs_monitor_port(val);
+
+ if (old_monitor_port != machine_data->monitor_port) {
+ /* All AOIs need adjust pixel format
+ * fsl_diu_set_par only change the pixsel format here
+ * unlikely to fail. */
+ fsl_diu_set_par(machine_data->fsl_diu_info[0]);
+ fsl_diu_set_par(machine_data->fsl_diu_info[1]);
+ fsl_diu_set_par(machine_data->fsl_diu_info[2]);
+ fsl_diu_set_par(machine_data->fsl_diu_info[3]);
+ fsl_diu_set_par(machine_data->fsl_diu_info[4]);
+ }
+ return count;
+}
+
+static ssize_t show_monitor(struct device *device,
+ struct device_attribute *attr, char *buf)
+{
+ struct fsl_diu_data *machine_data =
+ container_of(attr, struct fsl_diu_data, dev_attr);
+ return diu_ops.show_monitor_port(machine_data->monitor_port, buf);
+}
+
+static int fsl_diu_probe(struct of_device *ofdev,
+ const struct of_device_id *match)
+{
+ struct device_node *np = ofdev->node;
+ struct mfb_info *mfbi;
+ phys_addr_t dummy_ad_addr;
+ int ret, i, error = 0;
+ struct resource res;
+ struct fsl_diu_data *machine_data;
+
+ machine_data = kzalloc(sizeof(struct fsl_diu_data), GFP_KERNEL);
+ if (!machine_data)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++) {
+ machine_data->fsl_diu_info[i] =
+ framebuffer_alloc(sizeof(struct mfb_info), &ofdev->dev);
+ if (!machine_data->fsl_diu_info[i]) {
+ dev_err(&ofdev->dev, "cannot allocate memory\n");
+ ret = -ENOMEM;
+ goto error2;
+ }
+ mfbi = machine_data->fsl_diu_info[i]->par;
+ memcpy(mfbi, &mfb_template[i], sizeof(struct mfb_info));
+ mfbi->parent = machine_data;
+ }
+
+ ret = of_address_to_resource(np, 0, &res);
+ if (ret) {
+ dev_err(&ofdev->dev, "could not obtain DIU address\n");
+ goto error;
+ }
+ if (!res.start) {
+ dev_err(&ofdev->dev, "invalid DIU address\n");
+ goto error;
+ }
+ dev_dbg(&ofdev->dev, "%s, res.start: 0x%08x\n", __func__, res.start);
+
+ dr.diu_reg = ioremap(res.start, sizeof(struct diu));
+ if (!dr.diu_reg) {
+ dev_err(&ofdev->dev, "Err: can't map DIU registers!\n");
+ ret = -EFAULT;
+ goto error2;
+ }
+
+ out_be32(&dr.diu_reg->diu_mode, 0); /* disable DIU anyway*/
+
+ /* Get the IRQ of the DIU */
+ machine_data->irq = irq_of_parse_and_map(np, 0);
+
+ if (!machine_data->irq) {
+ dev_err(&ofdev->dev, "could not get DIU IRQ\n");
+ ret = -EINVAL;
+ goto error;
+ }
+ machine_data->monitor_port = monitor_port;
+
+ /* Area descriptor memory pool aligns to 64-bit boundary */
+ if (allocate_buf(&pool.ad, sizeof(struct diu_ad) * FSL_AOI_NUM, 8))
+ return -ENOMEM;
+
+ /* Get memory for Gamma Table - 32-byte aligned memory */
+ if (allocate_buf(&pool.gamma, 768, 32)) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ /* For performance, cursor bitmap buffer aligns to 32-byte boundary */
+ if (allocate_buf(&pool.cursor, MAX_CURS * MAX_CURS * 2, 32)) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
+ i = ARRAY_SIZE(machine_data->fsl_diu_info);
+ machine_data->dummy_ad = (struct diu_ad *)
+ ((u32)pool.ad.vaddr + pool.ad.offset) + i;
+ machine_data->dummy_ad->paddr = pool.ad.paddr +
+ i * sizeof(struct diu_ad);
+ machine_data->dummy_aoi_virt = fsl_diu_alloc(64, &dummy_ad_addr);
+ if (!machine_data->dummy_aoi_virt) {
+ ret = -ENOMEM;
+ goto error;
+ }
+ machine_data->dummy_ad->addr = cpu_to_le32(dummy_ad_addr);
+ machine_data->dummy_ad->pix_fmt = 0x88882317;
+ machine_data->dummy_ad->src_size_g_alpha = cpu_to_le32((4 << 12) | 4);
+ machine_data->dummy_ad->aoi_size = cpu_to_le32((4 << 16) | 2);
+ machine_data->dummy_ad->offset_xyi = 0;
+ machine_data->dummy_ad->offset_xyd = 0;
+ machine_data->dummy_ad->next_ad = 0;
+
+ out_be32(&dr.diu_reg->desc[0], machine_data->dummy_ad->paddr);
+ out_be32(&dr.diu_reg->desc[1], machine_data->dummy_ad->paddr);
+ out_be32(&dr.diu_reg->desc[2], machine_data->dummy_ad->paddr);
+
+ for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++) {
+ machine_data->fsl_diu_info[i]->fix.smem_start = 0;
+ mfbi = machine_data->fsl_diu_info[i]->par;
+ mfbi->ad = (struct diu_ad *)((u32)pool.ad.vaddr
+ + pool.ad.offset) + i;
+ mfbi->ad->paddr = pool.ad.paddr + i * sizeof(struct diu_ad);
+ ret = install_fb(machine_data->fsl_diu_info[i]);
+ if (ret) {
+ dev_err(&ofdev->dev,
+ "Failed to register framebuffer %d\n",
+ i);
+ goto error;
+ }
+ }
+
+ if (request_irq_local(machine_data->irq)) {
+ dev_err(machine_data->fsl_diu_info[0]->dev,
+ "could not request irq for diu.");
+ goto error;
+ }
+
+ machine_data->dev_attr.attr.name = "monitor";
+ machine_data->dev_attr.attr.mode = S_IRUGO|S_IWUSR;
+ machine_data->dev_attr.show = show_monitor;
+ machine_data->dev_attr.store = store_monitor;
+ error = device_create_file(machine_data->fsl_diu_info[0]->dev,
+ &machine_data->dev_attr);
+ if (error) {
+ dev_err(machine_data->fsl_diu_info[0]->dev,
+ "could not create sysfs %s file\n",
+ machine_data->dev_attr.attr.name);
+ }
+
+ dev_set_drvdata(&ofdev->dev, machine_data);
+ return 0;
+
+error:
+ for (i = ARRAY_SIZE(machine_data->fsl_diu_info);
+ i > 0; i--)
+ uninstall_fb(machine_data->fsl_diu_info[i - 1]);
+ if (pool.ad.vaddr)
+ free_buf(&pool.ad, sizeof(struct diu_ad) * FSL_AOI_NUM, 8);
+ if (pool.gamma.vaddr)
+ free_buf(&pool.gamma, 768, 32);
+ if (pool.cursor.vaddr)
+ free_buf(&pool.cursor, MAX_CURS * MAX_CURS * 2, 32);
+ if (machine_data->dummy_aoi_virt)
+ fsl_diu_free(machine_data->dummy_aoi_virt, 64);
+ iounmap(dr.diu_reg);
+
+error2:
+ for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++)
+ if (machine_data->fsl_diu_info[i])
+ framebuffer_release(machine_data->fsl_diu_info[i]);
+ kfree(machine_data);
+
+ return ret;
+}
+
+
+static int fsl_diu_remove(struct of_device *ofdev)
+{
+ struct fsl_diu_data *machine_data;
+ int i;
+
+ machine_data = dev_get_drvdata(&ofdev->dev);
+ disable_lcdc(machine_data->fsl_diu_info[0]);
+ free_irq_local(machine_data->irq);
+ for (i = ARRAY_SIZE(machine_data->fsl_diu_info); i > 0; i--)
+ uninstall_fb(machine_data->fsl_diu_info[i - 1]);
+ if (pool.ad.vaddr)
+ free_buf(&pool.ad, sizeof(struct diu_ad) * FSL_AOI_NUM, 8);
+ if (pool.gamma.vaddr)
+ free_buf(&pool.gamma, 768, 32);
+ if (pool.cursor.vaddr)
+ free_buf(&pool.cursor, MAX_CURS * MAX_CURS * 2, 32);
+ if (machine_data->dummy_aoi_virt)
+ fsl_diu_free(machine_data->dummy_aoi_virt, 64);
+ iounmap(dr.diu_reg);
+ for (i = 0; i < ARRAY_SIZE(machine_data->fsl_diu_info); i++)
+ if (machine_data->fsl_diu_info[i])
+ framebuffer_release(machine_data->fsl_diu_info[i]);
+ kfree(machine_data);
+
+ return 0;
+}
+
+#ifndef MODULE
+static int __init fsl_diu_setup(char *options)
+{
+ char *opt;
+ unsigned long val;
+
+ if (!options || !*options)
+ return 0;
+
+ while ((opt = strsep(&options, ",")) != NULL) {
+ if (!*opt)
+ continue;
+ if (!strncmp(opt, "monitor=", 8)) {
+ if (!strict_strtoul(opt + 8, 10, &val) && (val <= 2))
+ monitor_port = val;
+ } else if (!strncmp(opt, "bpp=", 4)) {
+ if (!strict_strtoul(opt + 4, 10, &val))
+ default_bpp = val;
+ } else
+ fb_mode = opt;
+ }
+
+ return 0;
+}
+#endif
+
+static struct of_device_id fsl_diu_match[] = {
+ {
+ .compatible = "fsl,diu",
+ },
+ {}
+};
+MODULE_DEVICE_TABLE(of, fsl_diu_match);
+
+static struct of_platform_driver fsl_diu_driver = {
+ .owner = THIS_MODULE,
+ .name = "fsl_diu",
+ .match_table = fsl_diu_match,
+ .probe = fsl_diu_probe,
+ .remove = fsl_diu_remove,
+ .suspend = fsl_diu_suspend,
+ .resume = fsl_diu_resume,
+};
+
+static int __init fsl_diu_init(void)
+{
+#ifdef CONFIG_NOT_COHERENT_CACHE
+ struct device_node *np;
+ const u32 *prop;
+#endif
+ int ret;
+#ifndef MODULE
+ char *option;
+
+ /*
+ * For kernel boot options (in 'video=xxxfb:<options>' format)
+ */
+ if (fb_get_options("fslfb", &option))
+ return -ENODEV;
+ fsl_diu_setup(option);
+#endif
+ printk(KERN_INFO "Freescale DIU driver\n");
+
+#ifdef CONFIG_NOT_COHERENT_CACHE
+ np = of_find_node_by_type(NULL, "cpu");
+ if (!np) {
+ printk(KERN_ERR "Err: can't find device node 'cpu'\n");
+ return -ENODEV;
+ }
+
+ prop = of_get_property(np, "d-cache-size", NULL);
+ if (prop == NULL)
+ return -ENODEV;
+
+ /* Freescale PLRU requires 13/8 times the cache size to do a proper
+ displacement flush
+ */
+ coherence_data_size = *prop * 13;
+ coherence_data_size /= 8;
+
+ prop = of_get_property(np, "d-cache-line-size", NULL);
+ if (prop == NULL)
+ return -ENODEV;
+ d_cache_line_size = *prop;
+
+ of_node_put(np);
+ coherence_data = vmalloc(coherence_data_size);
+ if (!coherence_data)
+ return -ENOMEM;
+#endif
+ ret = of_register_platform_driver(&fsl_diu_driver);
+ if (ret) {
+ printk(KERN_ERR
+ "fsl-diu: failed to register platform driver\n");
+#if defined(CONFIG_NOT_COHERENT_CACHE)
+ vfree(coherence_data);
+#endif
+ iounmap(dr.diu_reg);
+ }
+ return ret;
+}
+
+static void __exit fsl_diu_exit(void)
+{
+ of_unregister_platform_driver(&fsl_diu_driver);
+#if defined(CONFIG_NOT_COHERENT_CACHE)
+ vfree(coherence_data);
+#endif
+}
+
+module_init(fsl_diu_init);
+module_exit(fsl_diu_exit);
+
+MODULE_AUTHOR("York Sun <yorksun@freescale.com>");
+MODULE_DESCRIPTION("Freescale DIU framebuffer driver");
+MODULE_LICENSE("GPL");
+
+module_param_named(mode, fb_mode, charp, 0);
+MODULE_PARM_DESC(mode,
+ "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
+module_param_named(bpp, default_bpp, ulong, 0);
+MODULE_PARM_DESC(bpp, "Specify bit-per-pixel if not specified mode");
+module_param_named(monitor, monitor_port, int, 0);
+MODULE_PARM_DESC(monitor,
+ "Specify the monitor port (0, 1 or 2) if supported by the platform");
+
diff --git a/drivers/video/fsl-diu-fb.h b/drivers/video/fsl-diu-fb.h
new file mode 100644
index 0000000..fc295d7
--- /dev/null
+++ b/drivers/video/fsl-diu-fb.h
@@ -0,0 +1,223 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Freescale DIU Frame Buffer device driver
+ *
+ * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
+ * Paul Widmer <paul.widmer@freescale.com>
+ * Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
+ * York Sun <yorksun@freescale.com>
+ *
+ * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __FSL_DIU_FB_H__
+#define __FSL_DIU_FB_H__
+
+/* Arbitrary threshold to determine the allocation method
+ * See mpc8610fb_set_par(), map_video_memory(), and unmap_video_memory()
+ */
+#define MEM_ALLOC_THRESHOLD (1024*768*4+32)
+/* Minimum value that the pixel clock can be set to in pico seconds
+ * This is determined by platform clock/3 where the minimum platform
+ * clock is 533MHz. This gives 5629 pico seconds.
+ */
+#define MIN_PIX_CLK 5629
+#define MAX_PIX_CLK 96096
+
+#include <linux/types.h>
+
+struct mfb_alpha {
+ int enable;
+ int alpha;
+};
+
+struct mfb_chroma_key {
+ int enable;
+ __u8 red_max;
+ __u8 green_max;
+ __u8 blue_max;
+ __u8 red_min;
+ __u8 green_min;
+ __u8 blue_min;
+};
+
+struct aoi_display_offset {
+ int x_aoi_d;
+ int y_aoi_d;
+};
+
+#define MFB_SET_CHROMA_KEY _IOW('M', 1, struct mfb_chroma_key)
+#define MFB_WAIT_FOR_VSYNC _IOW('F', 0x20, u_int32_t)
+#define MFB_SET_BRIGHTNESS _IOW('M', 3, __u8)
+
+#define MFB_SET_ALPHA 0x80014d00
+#define MFB_GET_ALPHA 0x40014d00
+#define MFB_SET_AOID 0x80084d04
+#define MFB_GET_AOID 0x40084d04
+#define MFB_SET_PIXFMT 0x80014d08
+#define MFB_GET_PIXFMT 0x40014d08
+
+#define FBIOGET_GWINFO 0x46E0
+#define FBIOPUT_GWINFO 0x46E1
+
+#ifdef __KERNEL__
+#include <linux/spinlock.h>
+
+/*
+ * These are the fields of area descriptor(in DDR memory) for every plane
+ */
+struct diu_ad {
+ /* Word 0(32-bit) in DDR memory */
+/* __u16 comp; */
+/* __u16 pixel_s:2; */
+/* __u16 pallete:1; */
+/* __u16 red_c:2; */
+/* __u16 green_c:2; */
+/* __u16 blue_c:2; */
+/* __u16 alpha_c:3; */
+/* __u16 byte_f:1; */
+/* __u16 res0:3; */
+
+ __be32 pix_fmt; /* hard coding pixel format */
+
+ /* Word 1(32-bit) in DDR memory */
+ __le32 addr;
+
+ /* Word 2(32-bit) in DDR memory */
+/* __u32 delta_xs:11; */
+/* __u32 res1:1; */
+/* __u32 delta_ys:11; */
+/* __u32 res2:1; */
+/* __u32 g_alpha:8; */
+ __le32 src_size_g_alpha;
+
+ /* Word 3(32-bit) in DDR memory */
+/* __u32 delta_xi:11; */
+/* __u32 res3:5; */
+/* __u32 delta_yi:11; */
+/* __u32 res4:3; */
+/* __u32 flip:2; */
+ __le32 aoi_size;
+
+ /* Word 4(32-bit) in DDR memory */
+ /*__u32 offset_xi:11;
+ __u32 res5:5;
+ __u32 offset_yi:11;
+ __u32 res6:5;
+ */
+ __le32 offset_xyi;
+
+ /* Word 5(32-bit) in DDR memory */
+ /*__u32 offset_xd:11;
+ __u32 res7:5;
+ __u32 offset_yd:11;
+ __u32 res8:5; */
+ __le32 offset_xyd;
+
+
+ /* Word 6(32-bit) in DDR memory */
+ __u8 ckmax_r;
+ __u8 ckmax_g;
+ __u8 ckmax_b;
+ __u8 res9;
+
+ /* Word 7(32-bit) in DDR memory */
+ __u8 ckmin_r;
+ __u8 ckmin_g;
+ __u8 ckmin_b;
+ __u8 res10;
+/* __u32 res10:8; */
+
+ /* Word 8(32-bit) in DDR memory */
+ __le32 next_ad;
+
+ /* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
+ __u32 paddr;
+} __attribute__ ((packed));
+
+/* DIU register map */
+struct diu {
+ __be32 desc[3];
+ __be32 gamma;
+ __be32 pallete;
+ __be32 cursor;
+ __be32 curs_pos;
+ __be32 diu_mode;
+ __be32 bgnd;
+ __be32 bgnd_wb;
+ __be32 disp_size;
+ __be32 wb_size;
+ __be32 wb_mem_addr;
+ __be32 hsyn_para;
+ __be32 vsyn_para;
+ __be32 syn_pol;
+ __be32 thresholds;
+ __be32 int_status;
+ __be32 int_mask;
+ __be32 colorbar[8];
+ __be32 filling;
+ __be32 plut;
+} __attribute__ ((packed));
+
+struct diu_hw {
+ struct diu *diu_reg;
+ spinlock_t reg_lock;
+
+ __u32 mode; /* DIU operation mode */
+};
+
+struct diu_addr {
+ __u8 __iomem *vaddr; /* Virtual address */
+ dma_addr_t paddr; /* Physical address */
+ __u32 offset;
+};
+
+struct diu_pool {
+ struct diu_addr ad;
+ struct diu_addr gamma;
+ struct diu_addr pallete;
+ struct diu_addr cursor;
+};
+
+#define FSL_DIU_BASE_OFFSET 0x2C000 /* Offset of DIU */
+#define INT_LCDC 64 /* DIU interrupt number */
+
+#define FSL_AOI_NUM 6 /* 5 AOIs and one dummy AOI */
+ /* 1 for plane 0, 2 for plane 1&2 each */
+
+/* Minimum X and Y resolutions */
+#define MIN_XRES 64
+#define MIN_YRES 64
+
+/* HW cursor parameters */
+#define MAX_CURS 32
+
+/* Modes of operation of DIU */
+#define MFB_MODE0 0 /* DIU off */
+#define MFB_MODE1 1 /* All three planes output to display */
+#define MFB_MODE2 2 /* Plane 1 to display, planes 2+3 written back*/
+#define MFB_MODE3 3 /* All three planes written back to memory */
+#define MFB_MODE4 4 /* Color bar generation */
+
+/* INT_STATUS/INT_MASK field descriptions */
+#define INT_VSYNC 0x01 /* Vsync interrupt */
+#define INT_VSYNC_WB 0x02 /* Vsync interrupt for write back operation */
+#define INT_UNDRUN 0x04 /* Under run exception interrupt */
+#define INT_PARERR 0x08 /* Display parameters error interrupt */
+#define INT_LS_BF_VS 0x10 /* Lines before vsync. interrupt */
+
+/* Panels'operation modes */
+#define MFB_TYPE_OUTPUT 0 /* Panel output to display */
+#define MFB_TYPE_OFF 1 /* Panel off */
+#define MFB_TYPE_WB 2 /* Panel written back to memory */
+#define MFB_TYPE_TEST 3 /* Panel generate color bar */
+
+#endif /* __KERNEL__ */
+#endif /* __FSL_DIU_FB_H__ */
--
1.5.2.2
^ permalink raw reply related
* Re: [kvm-ppc-devel] [PATCH] Add idle power save for ppc 4xx
From: Hollis Blanchard @ 2008-03-31 16:27 UTC (permalink / raw)
To: Jerone Young; +Cc: kvm-ppc-devel, linuxppc-dev
In-Reply-To: <10aea37177130bbe5de7.1206969157@thinkpadL>
On Mon, 2008-03-31 at 08:12 -0500, Jerone Young wrote:
> # HG changeset patch
> # User Jerone Young <jyoung5@us.ibm.com>
> # Date 1206969060 18000
> # Node ID 10aea37177130bbe5de7bee6ec06d9010bc5da1f
> # Parent 1506aa38ddabb0bf73fff3ac3f3db5f9ef6458cc
> Add idle power save for ppc 4xx
>
> This patch sets the wait state MSR when power_save is called in
> cpu_idle loop for ppc4xx. This is mainly to help out virtualization
> solutions such as KVM. This way the virtualization soultions are able
> to tell if the guest kernel is idle.
>
> I have tested this on hardware & KVM virtual guest.
>
> Signed-off-by: Jerone Young <jyoung5@us.ibm.com>
>
> diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
> --- a/arch/powerpc/kernel/Makefile
> +++ b/arch/powerpc/kernel/Makefile
> @@ -39,6 +39,7 @@ obj-$(CONFIG_GENERIC_TBSYNC) += smp-tbsy
> obj-$(CONFIG_GENERIC_TBSYNC) += smp-tbsync.o
> obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
> obj-$(CONFIG_6xx) += idle_6xx.o l2cr_6xx.o cpu_setup_6xx.o
> +obj-$(CONFIG_4xx) += idle_4xx.o
> obj-$(CONFIG_TAU) += tau_6xx.o
> obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o \
> swsusp_$(CONFIG_WORD_SIZE).o
> diff --git a/arch/powerpc/kernel/idle_4xx.c b/arch/powerpc/kernel/idle_4xx.c
> new file mode 100644
> --- /dev/null
> +++ b/arch/powerpc/kernel/idle_4xx.c
> @@ -0,0 +1,24 @@
> +/*
> + * This file contains the power_save function for 4xx CPUs
> + *
> + * added by Jerone Young <jyoung5@us.ibm.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +
> +#include <asm/processor.h>
> +#include <asm/machdep.h>
> +
> +void ppc4xx_idle()
void ppc4xx_idle(void)
> +{
> + unsigned long msr_save;
> +
> + /* set wait state MSR */
> + local_irq_enable();
> + msr_save = mfmsr();
> + mtmsr(msr_save|MSR_WE);
Why don't you |MSR_WE|MSR_EE at the same time?
> + local_irq_disable();
> +}
None of the other power_save() implementations need this. In fact many
of them don't even seem to return; they just loop around mtmsr.
> diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
> --- a/arch/powerpc/kernel/setup_32.c
> +++ b/arch/powerpc/kernel/setup_32.c
> @@ -132,6 +132,10 @@ void __init machine_init(unsigned long d
> if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
> cpu_has_feature(CPU_FTR_CAN_NAP))
> ppc_md.power_save = ppc6xx_idle;
> +#endif
> +
> +#ifdef CONFIG_4xx
> + ppc_md.power_save = ppc4xx_idle;
> #endif
>
> if (ppc_md.progress)
This belongs in the platform setup code.
--
Hollis Blanchard
IBM Linux Technology Center
^ permalink raw reply
* Re: [PATCH 4/9] [POWERPC] mv64x60: Fix FDT compatible names: mv64x60 => mv64360
From: Dale Farnsworth @ 2008-03-31 16:33 UTC (permalink / raw)
To: Olof Johansson; +Cc: linuxppc-dev, paulus
In-Reply-To: <20080329215753.GA27226@lixom.net>
On Sat, Mar 29, 2008 at 04:57:53PM -0500, Olof Johansson wrote:
> On Fri, Mar 28, 2008 at 04:47:04PM -0700, Dale Farnsworth wrote:
> > From: Mark A. Greer <mgreer@mvista.com>
> >
> > Compatible names should refer to a specific version of the hardware,
> > without wildcards. Change each instance of mv64x60 to mv64360, which
> > is the oldest version we currently support.
>
> Actually, it's normal to have more than one compatible field, from
> specific to generic. So it should make sense to have both (with the
> 64360 entry first).
Sure it's normal to have multiple entries. But it's not correct to
have names that refer to a range of models, such as mv64x60. We're
replacing it with a name referring to the oldest specific model, mv64360.
We can add additional entries later if the need arises.
-Dale
^ permalink raw reply
* Re: [PATCH] [POWERPC] fsldma: Use compatiable binding as spec
From: Dan Williams @ 2008-03-31 16:37 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, linux-kernel
In-Reply-To: <Pine.LNX.4.64.0803311115540.5470@blarg.am.freescale.net>
On Mon, Mar 31, 2008 at 9:17 AM, Kumar Gala <galak@kernel.crashing.org> wrote:
> Documentation/powerpc/booting-without-of.txt specifies the
> compatiables we should bind to for this driver (elo, eloplus).
> Use these instead of the extremely specific 'mpc8540' and 'mpc8349'
> compatiables.
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> ---
>
> Dan, if you don't have any issue with this I'll sent it via the powerpc
> tree (since its not really about functionality).
>
Acked-by: Dan Williams <dan.j.williams@intel.com>
^ permalink raw reply
* Re: [PATCH 6/9] [POWERPC] prpmc2800: clean up dts properties
From: Dale Farnsworth @ 2008-03-31 16:43 UTC (permalink / raw)
To: Olof Johansson, linuxppc-dev, paulus
In-Reply-To: <20080330101128.GA20077@localhost.localdomain>
On Sun, Mar 30, 2008 at 09:11:28PM +1100, David Gibson wrote:
> On Sat, Mar 29, 2008 at 04:59:42PM -0500, Olof Johansson wrote:
> > On Fri, Mar 28, 2008 at 04:49:00PM -0700, Dale Farnsworth wrote:
> > > From: Mark A. Greer <mgreer@mvista.com>
> > >
> > > Remove several unused (or software config only) properties.
> > > Rename marvel node to "soc". Technically, it's not an SOC,
> > > but its organization is the same as an SOC. Also, rename the
> > > "block-index" property to "cell-index" to conform to current
> > > practice.
> >
> > I see this rename as purely misleading. It isn't an soc, so it shouldn't
> > be named as such. Call it system-controller or something. Pretty much
> > any other name is better. :-)
>
> I agree. system-controller, host-bridge, north-bridge, maybe, but not
> soc. With current conventions, the node name is primarily for the
> benefit of human readers, so if it misleads it has failed entirely in
> its purpose.
I'm convinced. I'll change it to system-controller.
However, I can't resist pointing out that in the existing devtrees
with a "soc" node, the name is also misleading. That node doesn't
refer to the SOC itself, but to the part of the SOC containing the
peripherals. Whether the system is implemented on one or two chips
is an implementation detail irrelevant to the drivers or device tree.
-Dale
^ permalink raw reply
* [PATCHv3 4/4] cpm2: Reset the CPM when early debugging is not enabled.
From: Laurent Pinchart @ 2008-03-31 16:37 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Scott Wood
In-Reply-To: <200803311834.42327.laurentp@cse-semaphore.com>
[-- Attachment #1: Type: text/plain, Size: 1046 bytes --]
Similarly to what is done for PQ1-based platforms, this patch resets the
PQ2 Communication Processor Module in cpm2_reset() when early debugging is
not enabled. This helps avoiding conflicts when the boot loader configured
the CPM in an unexpected way.
Signed-off-by: Laurent Pinchart <laurentp@cse-semaphore.com>
---
arch/powerpc/sysdev/cpm2.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/sysdev/cpm2.c b/arch/powerpc/sysdev/cpm2.c
index 7be7112..57ed1a4 100644
--- a/arch/powerpc/sysdev/cpm2.c
+++ b/arch/powerpc/sysdev/cpm2.c
@@ -80,6 +80,12 @@ void __init cpm2_reset(void)
/* Tell everyone where the comm processor resides.
*/
cpmp = &cpm2_immr->im_cpm;
+
+#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
+ /* Reset the CPM.
+ */
+ cpm_command(CPM_CR_RST, 0);
+#endif
}
static DEFINE_SPINLOCK(cmd_lock);
--
1.5.0
--
Laurent Pinchart
CSE Semaphore Belgium
Chaussée de Bruxelles, 732A
B-1410 Waterloo
Belgium
T +32 (2) 387 42 59
F +32 (2) 387 42 75
[-- Attachment #2: Type: application/pgp-signature, Size: 189 bytes --]
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