* Re: [PATCH] Do not inline putprops function
From: M. Mohan Kumar @ 2009-08-07 14:35 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, Neil Horman, Simon Horman, kexec, miltonm
In-Reply-To: <1249568660.20200.23.camel@concordia>
Hi,
After enabling EARLY_DEBUG (and DEBUG in some of the files in
arch/powerpc/kernel directory), without forcing the dtstruct variable to 8
byte alignment:
# ./kexec -e
Starting new kernel
console [udbg0] enabled
-> early_setup(), dt_ptr: 0x7723000
-> early_init_devtree(c000000007723000)
Invalid tag 5 scanning flattened device tree !
search "chosen", depth: 0, uname:
Invalid tag 5 scanning flattened device tree !
dt_root_size_cells = 2
dt_root_addr_cells = 2
Invalid tag 5 scanning flattened device tree !
reserving: 128c000 -> 5ec1f7
reserving: 7734000 -> 8cc000
reserving: 7723000 -> f698
Phys. mem: 0
-> move_device_tree
<- move_device_tree
Scanning CPUs ...
Invalid tag 5 scanning flattened device tree !
<- early_init_devtree()
Probing machine type ...
pSeries ...
No suitable machine found !
So device-tree is getting corrupted when dtstruct variable is not aligned to
8 byte variable. This problem is not seen with gcc-3.4. Is it compiler
issue? or bug in the code.
Regards,
M. Mohan Kumar.
On Fri, Aug 07, 2009 at 12:24:20AM +1000, Michael Ellerman wrote:
> On Wed, 2009-08-05 at 22:19 +0530, M. Mohan Kumar wrote:
> > Hi,
> >
> > When I align the dtstruct variable to 8 bytes, I am able to invoke kdump.
> >
> > When the line
> > static unsigned dtstruct[TREEWORDS], *dt;
> > changed to
> > static unsigned dtstruct[TREEWORDS] __attribute__ ((aligned (8))), *dt;
> >
> > kexec-tool works.
>
> Hmm, odd.
>
> Can you check how it's aligned without your change? ie. in the original
> binary, is it 4 byte aligned?
>
> When you make the change, is the only thing that changes in the binary
> the alignedness of dtstruct, or does it cause other things to move
> around?
>
> I don't think an unaligned dt blob should have any effect on the kernel,
> ie. it should copy it in fine, but I'd have to look at the code.
>
> cheers
^ permalink raw reply
* RE: [PATCH][v2][powerpc/85xx] P2020RDB Platform Support Added
From: Aggrwal Poonam-B10812 @ 2009-08-07 14:35 UTC (permalink / raw)
To: Felix Radensky; +Cc: linuxppc-dev
In-Reply-To: <4A7C0BF5.8010503@embedded-sol.com>
=20
> -----Original Message-----
> From: Felix Radensky [mailto:felix@embedded-sol.com]=20
> Sent: Friday, August 07, 2009 4:42 PM
> To: Aggrwal Poonam-B10812
> Cc: linuxppc-dev@ozlabs.org
> Subject: Re: [PATCH][v2][powerpc/85xx] P2020RDB Platform Support Added
>=20
> Hi, Poonam
>=20
> See some more comments below.
>=20
> Poonam Aggrwal wrote:
> > Adds P2020RDB basic support in linux.
> > Overview of P2020RDB platform
> > - DDR
> > DDR2 1G
> > - NOR Flash
> > 16MByte
> > - NAND Flash
> > 32MByte
> > - 3 Ethernet interfaces
> > 1) etSEC1
> > - RGMII
> > - connected to a 5 port Vitesse Switch(VSC7385)
> > - Switch is memory mapped through eLBC interface(CS#2)
> > - IRQ1
> > 2) etSEC2
> > - SGMII
> > - connected to VSC8221
> > - IRQ2
> > 3) etSEC3
> > - RGMII
> > - connected to VSC8641
> > - IRQ3
> > - 2 1X PCIe interfaces
> > - SD/MMC ,USB
> > - SPI EEPROM
> > - Serial I2C EEPROM
> >=20
> > Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> > ---
> > based on=20
> > http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
> > incorporated Felix feedback regarding the partition names.
> > fixed the vitesse switch ranges entry in device tree.
> > arch/powerpc/boot/dts/p2020rdb.dts | 586=20
> +++++++++++++++++++++++++++++
> > arch/powerpc/configs/mpc85xx_defconfig | 1 +
> > arch/powerpc/platforms/85xx/Kconfig | 9 +
> > arch/powerpc/platforms/85xx/Makefile | 3 +-
> > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 141 +++++++
> > 5 files changed, 739 insertions(+), 1 deletions(-) create mode=20
> > 100644 arch/powerpc/boot/dts/p2020rdb.dts
> > create mode 100644 arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> >=20
> > diff --git a/arch/powerpc/boot/dts/p2020rdb.dts=20
> > b/arch/powerpc/boot/dts/p2020rdb.dts
> > new file mode 100644
> > index 0000000..617029f
> > --- /dev/null
> > +++ b/arch/powerpc/boot/dts/p2020rdb.dts
> > @@ -0,0 +1,586 @@
> > +/*
> > + * P2020 RDB Device Tree Source
> > + *
> > + * Copyright 2009 Freescale Semiconductor Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or=20
> > +modify it
> > + * under the terms of the GNU General Public License as=20
> published=20
> > +by the
> > + * Free Software Foundation; either version 2 of the License, or=20
> > +(at your
> > + * option) any later version.
> > + */
> > +
> > +/dts-v1/;
> > +/ {
> > + model =3D "fsl,P2020";
> > + compatible =3D "fsl,P2020RDB";
> > + #address-cells =3D <2>;
> > + #size-cells =3D <2>;
> > +
> > + aliases {
> > + ethernet0 =3D &enet0;
> > + ethernet1 =3D &enet1;
> > + ethernet2 =3D &enet2;
> > + serial0 =3D &serial0;
> > + serial1 =3D &serial1;
> > + pci0 =3D &pci0;
> > + pci1 =3D &pci1;
> > + };
> > +
> > + cpus {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > +
> > + PowerPC,P2020@0 {
> > + device_type =3D "cpu";
> > + reg =3D <0x0>;
> > + next-level-cache =3D <&L2>;
> > + };
> > +
> > + PowerPC,P2020@1 {
> > + device_type =3D "cpu";
> > + reg =3D <0x1>;
> > + next-level-cache =3D <&L2>;
> > + };
> > + };
> > +
> > + memory {
> > + device_type =3D "memory";
> > + };
> > +
> > + localbus@ffe05000 {
> > + #address-cells =3D <2>;
> > + #size-cells =3D <1>;
> > + compatible =3D "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
> > + reg =3D <0 0xffe05000 0 0x1000>;
> > + interrupts =3D <19 2>;
> > + interrupt-parent =3D <&mpic>;
> > +
> > + /* NOR and NAND Flashes */
> > + ranges =3D <0x0 0x0 0x0 0xef000000 0x01000000
> > + 0x1 0x0 0x0 0xffa00000 0x00040000
> > + 0x2 0x0 0x0 0xffb00000 0x00020000>;
> > +
> > + nor@0,0 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "cfi-flash";
> > + reg =3D <0x0 0x0 0x1000000>;
> > + bank-width =3D <2>;
> > + device-width =3D <1>;
> > +
> > + partition@0 {
> > + /* This location must not be altered */
> > + /* 256KB for Vitesse 7385=20
> Switch firmware */
> > + reg =3D <0x0 0x00040000>;
> > + label =3D "NOR (RO) Vitesse-7385=20
> Firmware";
> > + read-only;
> > + };
> > +
> > + partition@40000 {
> > + /* 256KB for DTB Image */
> > + reg =3D <0x00040000 0x00040000>;
> > + label =3D "NOR (RO) DTB Image";
> > + read-only;
> > + };
> > +
> > + partition@80000 {
> > + /* 3.5 MB for Linux Kernel Image */
> > + reg =3D <0x00080000 0x00380000>;
> > + label =3D "NOR (RO) Linux Kernel Image";
> > + read-only;
> > + };
> > +
> > + partition@400000 {
> > + /* 11MB for JFFS2 based Root=20
> file System */
> > + reg =3D <0x00400000 0x00b00000>;
> > + label =3D "NOR (RW) JFFS2 Root=20
> File System";
> > + };
> > +
> > + partition@f00000 {
> > + /* This location must not be altered */
> > + /* 512KB for u-boot Bootloader Image */
> > + /* 512KB for u-boot Environment=20
> Variables */
> > + reg =3D <0x00f00000 0x00100000>;
> > + label =3D "NOR (RO) U-Boot Image";
> > + read-only;
> > + };
> > + };
> > +
> > + nand@1,0 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "fsl,p2020-fcm-nand",
> > + "fsl,elbc-fcm-nand";
> > + reg =3D <0x1 0x0 0x40000>;
> > +
> > + u-boot@0 {
> > + /* This location must not be altered */
> > + /* 1MB for u-boot Bootloader Image */
> > + reg =3D <0x0 0x00100000>;
> > + label =3D "NAND (RO) U-Boot Image";
> > + read-only;
> > + };
> > +
> > + dtb@100000 {
> > + /* 1MB for DTB Image */
> > + reg =3D <0x00100000 0x00100000>;
> > + label =3D "NAND (RO) DTB Image";
> > + read-only;
> > + };
> > +
> > + uImage@200000 {
> > + /* 4MB for Linux Kernel Image */
> > + reg =3D <0x00200000 0x00400000>;
> > + label =3D "NAND (RO) Linux Kernel Image";
> > + read-only;
> > + };
> > +
> > + rfs@600000 {
> > + /* 4MB for Compressed Root file=20
> System Image */
> > + reg =3D <0x00600000 0x00400000>;
> > + label =3D "NAND (RO) Compressed=20
> RFS Image";
> > + read-only;
> > + };
> > +
> > + jffs2@a00000 {
> > + /* 7MB for JFFS2 based Root=20
> file System */
> > + reg =3D <0x00a00000 0x00700000>;
> > + label =3D "NAND (RW) JFFS2 Root=20
> File System";
> > + };
> > +
> > + user@1100000 {
> > + /* 15MB for JFFS2 based Root=20
> file System */
> > + reg =3D <0x01100000 0x00f00000>;
> > + label =3D "NAND (RW) Writable User area";
> > + };
> > + };
>=20
> NAND partitions should also be declared using new syntax.
Of course, some goof up happened while sending.
>=20
>=20
> > +
> > + L2switch@2,0 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "vitesse-7385";
> > + reg =3D <0x2 0x0 0x20000>;
> > + };
> > +
> > + };
> > +
> > + soc@ffe00000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + device_type =3D "soc";
> > + compatible =3D "fsl,p2020-immr", "simple-bus";
> > + ranges =3D <0x0 0x0 0xffe00000 0x100000>;
> > + bus-frequency =3D <0>; // Filled out by uboot.
> > +
> > + ecm-law@0 {
> > + compatible =3D "fsl,ecm-law";
> > + reg =3D <0x0 0x1000>;
> > + fsl,num-laws =3D <12>;
> > + };
> > +
> > + ecm@1000 {
> > + compatible =3D "fsl,p2020-ecm", "fsl,ecm";
> > + reg =3D <0x1000 0x1000>;
> > + interrupts =3D <17 2>;
> > + interrupt-parent =3D <&mpic>;
> > + };
> > +
> > + memory-controller@2000 {
> > + compatible =3D "fsl,p2020-memory-controller";
> > + reg =3D <0x2000 0x1000>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <18 2>;
> > + };
> > +
> > + i2c@3000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + cell-index =3D <0>;
> > + compatible =3D "fsl-i2c";
> > + reg =3D <0x3000 0x100>;
> > + interrupts =3D <43 2>;
> > + interrupt-parent =3D <&mpic>;
> > + dfsrr;
> > + rtc@68 {
> > + compatible =3D "dallas,ds1339";
> > + reg =3D <0x68>;
> > + };
> > + };
> > +
> > + i2c@3100 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + cell-index =3D <1>;
> > + compatible =3D "fsl-i2c";
> > + reg =3D <0x3100 0x100>;
> > + interrupts =3D <43 2>;
> > + interrupt-parent =3D <&mpic>;
> > + dfsrr;
> > + };
> > +
> > + serial0: serial@4500 {
> > + cell-index =3D <0>;
> > + device_type =3D "serial";
> > + compatible =3D "ns16550";
> > + reg =3D <0x4500 0x100>;
> > + clock-frequency =3D <0>;
> > + interrupts =3D <42 2>;
> > + interrupt-parent =3D <&mpic>;
> > + };
> > +
> > + serial1: serial@4600 {
> > + cell-index =3D <1>;
> > + device_type =3D "serial";
> > + compatible =3D "ns16550";
> > + reg =3D <0x4600 0x100>;
> > + clock-frequency =3D <0>;
> > + interrupts =3D <42 2>;
> > + interrupt-parent =3D <&mpic>;
> > + };
> > +
> > + spi@7000 {
> > + cell-index =3D <0>;
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + compatible =3D "fsl,espi";
> > + reg =3D <0x7000 0x1000>;
> > + interrupts =3D <59 0x2>;
> > + interrupt-parent =3D <&mpic>;
> > + mode =3D "cpu";
> > +
> > + fsl_m25p80@0 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "fsl,espi-flash";
> > + reg =3D <0>;
> > + linux,modalias =3D "fsl_m25p80";
> > + modal =3D "s25sl128b";
> > + spi-max-frequency =3D <50000000>;
> > + mode =3D <0>;
> > +
> > + partition@0 {
> > + /* 512KB for u-boot=20
> Bootloader Image */
> > + reg =3D <0x0 0x00080000>;
> > + label =3D "SPI (RO) U-Boot Image";
> > + read-only;
> > + };
> > +
> > + partition@80000 {
> > + /* 512KB for DTB Image */
> > + reg =3D <0x00080000 0x00080000>;
> > + label =3D "SPI (RO) DTB Image";
> > + read-only;
> > + };
> > +
> > + partition@100000 {
> > + /* 4MB for Linux Kernel Image */
> > + reg =3D <0x00100000 0x00400000>;
> > + label =3D "SPI (RO) Linux=20
> Kernel Image";
> > + read-only;
> > + };
> > +
> > + partition@500000 {
> > + /* 4MB for Compressed=20
> RFS Image */
> > + reg =3D <0x00500000 0x00400000>;
> > + label =3D "SPI (RO)=20
> Compressed RFS Image";
> > + read-only;
> > + };
> > +
> > + partition@900000 {
> > + /* 7MB for JFFS2 based RFS */
> > + reg =3D <0x00900000 0x00700000>;
> > + label =3D "SPI (RW) JFFS2 RFS";
> > + };
> > + };
> > + };
> > +
> > + dma@c300 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "fsl,eloplus-dma";
> > + reg =3D <0xc300 0x4>;
> > + ranges =3D <0x0 0xc100 0x200>;
> > + cell-index =3D <1>;
> > + dma-channel@0 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x0 0x80>;
> > + cell-index =3D <0>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <76 2>;
> > + };
> > + dma-channel@80 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x80 0x80>;
> > + cell-index =3D <1>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <77 2>;
> > + };
> > + dma-channel@100 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x100 0x80>;
> > + cell-index =3D <2>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <78 2>;
> > + };
> > + dma-channel@180 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x180 0x80>;
> > + cell-index =3D <3>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <79 2>;
> > + };
> > + };
> > +
> > + gpio: gpio-controller@f000 {
> > + #gpio-cells =3D <2>;
> > + compatible =3D "fsl,mpc8572-gpio";
> > + reg =3D <0xf000 0x100>;
> > + interrupts =3D <47 0x2>;
> > + interrupt-parent =3D <&mpic>;
> > + gpio-controller;
> > + };
> > +
> > + L2: l2-cache-controller@20000 {
> > + compatible =3D "fsl,p2020-l2-cache-controller";
> > + reg =3D <0x20000 0x1000>;
> > + cache-line-size =3D <32>; // 32 bytes
> > + cache-size =3D <0x80000>; // L2,512K
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <16 2>;
> > + };
> > +
> > + dma@21300 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "fsl,eloplus-dma";
> > + reg =3D <0x21300 0x4>;
> > + ranges =3D <0x0 0x21100 0x200>;
> > + cell-index =3D <0>;
> > + dma-channel@0 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x0 0x80>;
> > + cell-index =3D <0>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <20 2>;
> > + };
> > + dma-channel@80 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x80 0x80>;
> > + cell-index =3D <1>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <21 2>;
> > + };
> > + dma-channel@100 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x100 0x80>;
> > + cell-index =3D <2>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <22 2>;
> > + };
> > + dma-channel@180 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x180 0x80>;
> > + cell-index =3D <3>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <23 2>;
> > + };
> > + };
> > +
> > + usb@22000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + compatible =3D "fsl-usb2-dr";
> > + reg =3D <0x22000 0x1000>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <28 0x2>;
> > + phy_type =3D "ulpi";
> > + };
> > +
> > + enet0: ethernet@24000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + cell-index =3D <0>;
> > + device_type =3D "network";
> > + model =3D "eTSEC";
> > + compatible =3D "gianfar";
> > + reg =3D <0x24000 0x1000>;
> > + ranges =3D <0x0 0x24000 0x1000>;
> > + local-mac-address =3D [ 00 00 00 00 00 00 ];
> > + interrupts =3D <29 2 30 2 34 2>;
> > + interrupt-parent =3D <&mpic>;
> > + fixed-link =3D <1 1 1000 0 0>;
> > + phy-connection-type =3D "rgmii-id";
> > +
> > + mdio@520 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + compatible =3D "fsl,gianfar-mdio";
> > + reg =3D <0x520 0x20>;
> > +
> > + phy0: ethernet-phy@0 {
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <3 1>;
> > + reg =3D <0x0>;
> > + };
> > + phy1: ethernet-phy@1 {
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <3 1>;
> > + reg =3D <0x1>;
> > + };
> > + };
> > + };
> > +
> > + enet1: ethernet@25000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + cell-index =3D <1>;
> > + device_type =3D "network";
> > + model =3D "eTSEC";
> > + compatible =3D "gianfar";
> > + reg =3D <0x25000 0x1000>;
> > + ranges =3D <0x0 0x25000 0x1000>;
> > + local-mac-address =3D [ 00 00 00 00 00 00 ];
> > + interrupts =3D <35 2 36 2 40 2>;
> > + interrupt-parent =3D <&mpic>;
> > + tbi-handle =3D <&tbi0>;
> > + phy-handle =3D <&phy0>;
> > + phy-connection-type =3D "sgmii";
> > +
> > + mdio@520 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + compatible =3D "fsl,gianfar-tbi";
> > + reg =3D <0x520 0x20>;
> > +
> > + tbi0: tbi-phy@11 {
> > + reg =3D <0x11>;
> > + device_type =3D "tbi-phy";
> > + };
> > + };
> > + };
> > +
> > + enet2: ethernet@26000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + cell-index =3D <2>;
> > + device_type =3D "network";
> > + model =3D "eTSEC";
> > + compatible =3D "gianfar";
> > + reg =3D <0x26000 0x1000>;
> > + ranges =3D <0x0 0x26000 0x1000>;
> > + local-mac-address =3D [ 00 00 00 00 00 00 ];
> > + interrupts =3D <31 2 32 2 33 2>;
> > + interrupt-parent =3D <&mpic>;
> > + phy-handle =3D <&phy1>;
> > + phy-connection-type =3D "rgmii-id";
> > + };
> > +
>=20
> Shouldn't mdio node be associated with enet2 ?
On the P2020 SOC mdio signals for enet1 are coming out and connected to
the PHYs on the board. All PHYs are supposed to use this as MDIO bus.
>=20
>=20
> > + sdhci@2e000 {
> > + compatible =3D "fsl,p2020-esdhc", "fsl,esdhc";
> > + reg =3D <0x2e000 0x1000>;
> > + interrupts =3D <72 0x2>;
> > + interrupt-parent =3D <&mpic>;
> > + /* Filled in by U-Boot */
> > + clock-frequency =3D <0>;
> > + };
> > +
> > + crypto@30000 {
> > + compatible =3D "fsl,sec3.1",=20
> "fsl,sec3.0", "fsl,sec2.4",
> > + "fsl,sec2.2",=20
> "fsl,sec2.1", "fsl,sec2.0";
> > + reg =3D <0x30000 0x10000>;
> > + interrupts =3D <45 2 58 2>;
> > + interrupt-parent =3D <&mpic>;
> > + fsl,num-channels =3D <4>;
> > + fsl,channel-fifo-len =3D <24>;
> > + fsl,exec-units-mask =3D <0xbfe>;
> > + fsl,descriptor-types-mask =3D <0x3ab0ebf>;
> > + };
> > +
> > + mpic: pic@40000 {
> > + interrupt-controller;
> > + #address-cells =3D <0>;
> > + #interrupt-cells =3D <2>;
> > + reg =3D <0x40000 0x40000>;
> > + compatible =3D "chrp,open-pic";
> > + device_type =3D "open-pic";
> > + };
> > +
> > + msi@41600 {
> > + compatible =3D "fsl,p2020-msi", "fsl,mpic-msi";
> > + reg =3D <0x41600 0x80>;
> > + msi-available-ranges =3D <0 0x100>;
> > + interrupts =3D <
> > + 0xe0 0
> > + 0xe1 0
> > + 0xe2 0
> > + 0xe3 0
> > + 0xe4 0
> > + 0xe5 0
> > + 0xe6 0
> > + 0xe7 0>;
> > + interrupt-parent =3D <&mpic>;
> > + };
> > +
> > + global-utilities@e0000 { //global utilities block
> > + compatible =3D "fsl,p2020-guts";
> > + reg =3D <0xe0000 0x1000>;
> > + fsl,has-rstcr;
> > + };
> > + };
> > +
> > + pci0: pcie@ffe09000 {
> > + compatible =3D "fsl,mpc8548-pcie";
> > + device_type =3D "pci";
> > + #interrupt-cells =3D <1>;
> > + #size-cells =3D <2>;
> > + #address-cells =3D <3>;
> > + reg =3D <0 0xffe09000 0 0x1000>;
> > + bus-range =3D <0 255>;
> > + ranges =3D <0x2000000 0x0 0xa0000000 0 0xa0000000=20
> 0x0 0x20000000
> > + 0x1000000 0x0 0x00000000 0 0xffc30000=20
> 0x0 0x10000>;
> > + clock-frequency =3D <33333333>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <25 2>;
> > + pcie@0 {
> > + reg =3D <0x0 0x0 0x0 0x0 0x0>;
> > + #size-cells =3D <2>;
> > + #address-cells =3D <3>;
> > + device_type =3D "pci";
> > + ranges =3D <0x2000000 0x0 0xa0000000
> > + 0x2000000 0x0 0xa0000000
> > + 0x0 0x20000000
> > +
> > + 0x1000000 0x0 0x0
> > + 0x1000000 0x0 0x0
> > + 0x0 0x100000>;
> > + };
> > + };
> > +
> > + pci1: pcie@ffe0a000 {
> > + compatible =3D "fsl,mpc8548-pcie";
> > + device_type =3D "pci";
> > + #interrupt-cells =3D <1>;
> > + #size-cells =3D <2>;
> > + #address-cells =3D <3>;
> > + reg =3D <0 0xffe0a000 0 0x1000>;
> > + bus-range =3D <0 255>;
> > + ranges =3D <0x2000000 0x0 0xc0000000 0 0xc0000000=20
> 0x0 0x20000000
> > + 0x1000000 0x0 0x00000000 0 0xffc20000=20
> 0x0 0x10000>;
> > + clock-frequency =3D <33333333>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <26 2>;
> > + pcie@0 {
> > + reg =3D <0x0 0x0 0x0 0x0 0x0>;
> > + #size-cells =3D <2>;
> > + #address-cells =3D <3>;
> > + device_type =3D "pci";
> > + ranges =3D <0x2000000 0x0 0xc0000000
> > + 0x2000000 0x0 0xc0000000
> > + 0x0 0x20000000
> > +
> > + 0x1000000 0x0 0x0
> > + 0x1000000 0x0 0x0
> > + 0x0 0x100000>;
> > + };
> > + };
> > +};
> > diff --git a/arch/powerpc/configs/mpc85xx_defconfig=20
> b/arch/powerpc/configs/mpc85xx_defconfig
> > index c162724..dc4819c 100644
> > --- a/arch/powerpc/configs/mpc85xx_defconfig
> > +++ b/arch/powerpc/configs/mpc85xx_defconfig
> > @@ -189,6 +189,7 @@ CONFIG_MPC85xx_CDS=3Dy
> > CONFIG_MPC85xx_MDS=3Dy
> > CONFIG_MPC8536_DS=3Dy
> > CONFIG_MPC85xx_DS=3Dy
> > +CONFIG_MPC85xx_RDB=3Dy
> > CONFIG_SOCRATES=3Dy
> > CONFIG_KSI8560=3Dy
> > CONFIG_STX_GP3=3Dy
> > diff --git a/arch/powerpc/platforms/85xx/Kconfig=20
> b/arch/powerpc/platforms/85xx/Kconfig
> > index a9b4166..d3a975e 100644
> > --- a/arch/powerpc/platforms/85xx/Kconfig
> > +++ b/arch/powerpc/platforms/85xx/Kconfig
> > @@ -55,6 +55,15 @@ config MPC85xx_DS
> > help
> > This option enables support for the MPC85xx DS=20
> (MPC8544 DS) board
> > =20
> > +config MPC85xx_RDB
> > + bool "Freescale MPC85xx RDB"
> > + select PPC_I8259
> > + select DEFAULT_UIMAGE
> > + select FSL_ULI1575
> > + select SWIOTLB
> > + help
> > + This option enables support for the MPC85xx RDB=20
> (P2020 RDB) board
> > +
> > config SOCRATES
> > bool "Socrates"
> > select DEFAULT_UIMAGE
> > diff --git a/arch/powerpc/platforms/85xx/Makefile=20
> b/arch/powerpc/platforms/85xx/Makefile
> > index 835733f..4efcc63 100644
> > --- a/arch/powerpc/platforms/85xx/Makefile
> > +++ b/arch/powerpc/platforms/85xx/Makefile
> > @@ -9,10 +9,11 @@ obj-$(CONFIG_MPC85xx_CDS) +=3D mpc85xx_cds.o
> > obj-$(CONFIG_MPC8536_DS) +=3D mpc8536_ds.o
> > obj-$(CONFIG_MPC85xx_DS) +=3D mpc85xx_ds.o
> > obj-$(CONFIG_MPC85xx_MDS) +=3D mpc85xx_mds.o
> > +obj-$(CONFIG_MPC85xx_RDB) +=3D mpc85xx_rdb.o
> > obj-$(CONFIG_STX_GP3) +=3D stx_gp3.o
> > obj-$(CONFIG_TQM85xx) +=3D tqm85xx.o
> > obj-$(CONFIG_SBC8560) +=3D sbc8560.o
> > obj-$(CONFIG_SBC8548) +=3D sbc8548.o
> > obj-$(CONFIG_SOCRATES) +=3D socrates.o socrates_fpga_pic.o
> > obj-$(CONFIG_KSI8560) +=3D ksi8560.o
> > -obj-$(CONFIG_XES_MPC85xx) +=3D xes_mpc85xx.o
> > \ No newline at end of file
> > +obj-$(CONFIG_XES_MPC85xx) +=3D xes_mpc85xx.o
> > diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c=20
> b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> > new file mode 100644
> > index 0000000..c8468de
> > --- /dev/null
> > +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> > @@ -0,0 +1,141 @@
> > +/*
> > + * MPC85xx RDB Board Setup
> > + *
> > + * Copyright 2009 Freescale Semiconductor Inc.
> > + *
> > + * This program is free software; you can redistribute it=20
> and/or modify it
> > + * under the terms of the GNU General Public License as=20
> published by the
> > + * Free Software Foundation; either version 2 of the =20
> License, or (at your
> > + * option) any later version.
> > + */
> > +
> > +#include <linux/stddef.h>
> > +#include <linux/kernel.h>
> > +#include <linux/pci.h>
> > +#include <linux/kdev_t.h>
> > +#include <linux/delay.h>
> > +#include <linux/seq_file.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/of_platform.h>
> > +
> > +#include <asm/system.h>
> > +#include <asm/time.h>
> > +#include <asm/machdep.h>
> > +#include <asm/pci-bridge.h>
> > +#include <mm/mmu_decl.h>
> > +#include <asm/prom.h>
> > +#include <asm/udbg.h>
> > +#include <asm/mpic.h>
> > +
> > +#include <sysdev/fsl_soc.h>
> > +#include <sysdev/fsl_pci.h>
> > +
> > +#undef DEBUG
> > +
> > +#ifdef DEBUG
> > +#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt,=20
> __func__, ## args)
> > +#else
> > +#define DBG(fmt, args...)
> > +#endif
> > +
> > +
> > +void __init mpc85xx_rdb_pic_init(void)
> > +{
> > + struct mpic *mpic;
> > + struct resource r;
> > + struct device_node *np;
> > +
> > + np =3D of_find_node_by_type(NULL, "open-pic");
> > + if (np =3D=3D NULL) {
> > + printk(KERN_ERR "Could not find open-pic node\n");
> > + return;
> > + }
> > +
> > + if (of_address_to_resource(np, 0, &r)) {
> > + printk(KERN_ERR "Failed to map mpic register space\n");
> > + of_node_put(np);
> > + return;
> > + }
> > +
> > + mpic =3D mpic_alloc(np, r.start,
> > + MPIC_PRIMARY | MPIC_WANTS_RESET |
> > + MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
> > + MPIC_SINGLE_DEST_CPU,
> > + 0, 256, " OpenPIC ");
> > +
> > + BUG_ON(mpic =3D=3D NULL);
> > + of_node_put(np);
> > +
> > + mpic_init(mpic);
> > +
> > +}
> > +
> > +/*
> > + * Setup the architecture
> > + */
> > +#ifdef CONFIG_SMP
> > +extern void __init mpc85xx_smp_init(void);
> > +#endif
> > +static void __init mpc85xx_rdb_setup_arch(void)
> > +{
> > +#ifdef CONFIG_PCI
> > + struct device_node *np;
> > +#endif
> > +
> > + if (ppc_md.progress)
> > + ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
> > +
> > +#ifdef CONFIG_PCI
> > + for_each_node_by_type(np, "pci") {
> > + if (of_device_is_compatible(np, "fsl,mpc8548-pcie"))
> > + fsl_add_bridge(np, 0);
> > + }
> > +
> > +#endif
> > +
> > +#ifdef CONFIG_SMP
> > + mpc85xx_smp_init();
> > +#endif
> > +
> > + printk(KERN_INFO "MPC85xx RDB board from Freescale=20
> Semiconductor\n");
> > +}
> > +
> > +static struct of_device_id __initdata mpc85xxrdb_ids[] =3D {
> > + { .type =3D "soc", },
> > + { .compatible =3D "soc", },
> > + { .compatible =3D "simple-bus", },
> > + { .compatible =3D "gianfar", },
> > + {},
> > +};
> > +
> > +static int __init mpc85xxrdb_publish_devices(void)
> > +{
> > + return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);
> > +}
> > +machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);
> > +
> > +/*
> > + * Called very early, device-tree isn't unflattened
> > + */
> > +static int __init p2020_rdb_probe(void)
> > +{
> > + unsigned long root =3D of_get_flat_dt_root();
> > +
> > + if (of_flat_dt_is_compatible(root, "fsl,P2020RDB"))
> > + return 1;
> > + return 0;
> > +}
> > +
> > +define_machine(p2020_rdb) {
> > + .name =3D "P2020 RDB",
> > + .probe =3D p2020_rdb_probe,
> > + .setup_arch =3D mpc85xx_rdb_setup_arch,
> > + .init_IRQ =3D mpc85xx_rdb_pic_init,
> > +#ifdef CONFIG_PCI
> > + .pcibios_fixup_bus =3D fsl_pcibios_fixup_bus,
> > +#endif
> > + .get_irq =3D mpic_get_irq,
> > + .restart =3D fsl_rstcr_restart,
> > + .calibrate_decr =3D generic_calibrate_decr,
> > + .progress =3D udbg_progress,
> > +};
>=20
^ permalink raw reply
* 5121 cache handling.
From: Kenneth Johansson @ 2009-08-07 12:53 UTC (permalink / raw)
To: linuxppc-dev
on 5121 there is a e300 core that unfortunately is connected to the rest
of the SOC with a bus that do not support coherency.
solution for many driver has been to use uncached memory. But for the
framebuffer that is not going to work as the performance impact of doing
graphics operations on uncached memory is to large.
currently the "solution" is to flush the cache in the interrupt
handler.
#if defined(CONFIG_NOT_COHERENT_CACHE)
int i;
unsigned int *ptr;
ptr = coherence_data;
for (i = 0; i < 1024*8; i++)
*ptr++ = 0;
#endif
Now this apparently is not enough on a e300 core that has a PLRU cache
replacement algorithm. but what is the optimal solution?
should not the framebuffer be marked as cache write through. that is the
W bit should be set in the tlb mapping. Why is this not done ? is that
feature also not working on 5121 ??
if this manual handling needs to be done what is best.
do it like now but over 52KB memory basically throwing out anything in
the cache in the process regardless if it was needed or not.
or do it carefully over just the framebuffer memory.
problem with doing it over just the framebuffer is that a 1024x768
buffer is 98304 cache lines it's going to take a considerable time to
do. how many cycles does it take per cache line if we never get a hit ??
3cycles at 400MHz gives 4.5milisec/sec or 4-5% overhead
1024*768*4/32*3*(1/400000000)*60
.04423680000000000000
52kB on the other hand is only 1664 lines but is obviously going to have
to do a lot of actual memory writes also for any modified cache line and
later a lot of reads to read back what was evicted.
^ permalink raw reply
* Re: [PATCH][v2][powerpc/85xx] P2020RDB Platform Support Added
From: Felix Radensky @ 2009-08-07 11:11 UTC (permalink / raw)
To: Poonam Aggrwal; +Cc: linuxppc-dev
In-Reply-To: <1249633286-21663-1-git-send-email-poonam.aggrwal@freescale.com>
Hi, Poonam
See some more comments below.
Poonam Aggrwal wrote:
> Adds P2020RDB basic support in linux.
> Overview of P2020RDB platform
> - DDR
> DDR2 1G
> - NOR Flash
> 16MByte
> - NAND Flash
> 32MByte
> - 3 Ethernet interfaces
> 1) etSEC1
> - RGMII
> - connected to a 5 port Vitesse Switch(VSC7385)
> - Switch is memory mapped through eLBC interface(CS#2)
> - IRQ1
> 2) etSEC2
> - SGMII
> - connected to VSC8221
> - IRQ2
> 3) etSEC3
> - RGMII
> - connected to VSC8641
> - IRQ3
> - 2 1X PCIe interfaces
> - SD/MMC ,USB
> - SPI EEPROM
> - Serial I2C EEPROM
>
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> ---
> based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
> incorporated Felix feedback regarding the partition names.
> fixed the vitesse switch ranges entry in device tree.
> arch/powerpc/boot/dts/p2020rdb.dts | 586 +++++++++++++++++++++++++++++
> arch/powerpc/configs/mpc85xx_defconfig | 1 +
> arch/powerpc/platforms/85xx/Kconfig | 9 +
> arch/powerpc/platforms/85xx/Makefile | 3 +-
> arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 141 +++++++
> 5 files changed, 739 insertions(+), 1 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/p2020rdb.dts
> create mode 100644 arch/powerpc/platforms/85xx/mpc85xx_rdb.c
>
> diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
> new file mode 100644
> index 0000000..617029f
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/p2020rdb.dts
> @@ -0,0 +1,586 @@
> +/*
> + * P2020 RDB Device Tree Source
> + *
> + * Copyright 2009 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/dts-v1/;
> +/ {
> + model = "fsl,P2020";
> + compatible = "fsl,P2020RDB";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + ethernet0 = &enet0;
> + ethernet1 = &enet1;
> + ethernet2 = &enet2;
> + serial0 = &serial0;
> + serial1 = &serial1;
> + pci0 = &pci0;
> + pci1 = &pci1;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + PowerPC,P2020@0 {
> + device_type = "cpu";
> + reg = <0x0>;
> + next-level-cache = <&L2>;
> + };
> +
> + PowerPC,P2020@1 {
> + device_type = "cpu";
> + reg = <0x1>;
> + next-level-cache = <&L2>;
> + };
> + };
> +
> + memory {
> + device_type = "memory";
> + };
> +
> + localbus@ffe05000 {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
> + reg = <0 0xffe05000 0 0x1000>;
> + interrupts = <19 2>;
> + interrupt-parent = <&mpic>;
> +
> + /* NOR and NAND Flashes */
> + ranges = <0x0 0x0 0x0 0xef000000 0x01000000
> + 0x1 0x0 0x0 0xffa00000 0x00040000
> + 0x2 0x0 0x0 0xffb00000 0x00020000>;
> +
> + nor@0,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "cfi-flash";
> + reg = <0x0 0x0 0x1000000>;
> + bank-width = <2>;
> + device-width = <1>;
> +
> + partition@0 {
> + /* This location must not be altered */
> + /* 256KB for Vitesse 7385 Switch firmware */
> + reg = <0x0 0x00040000>;
> + label = "NOR (RO) Vitesse-7385 Firmware";
> + read-only;
> + };
> +
> + partition@40000 {
> + /* 256KB for DTB Image */
> + reg = <0x00040000 0x00040000>;
> + label = "NOR (RO) DTB Image";
> + read-only;
> + };
> +
> + partition@80000 {
> + /* 3.5 MB for Linux Kernel Image */
> + reg = <0x00080000 0x00380000>;
> + label = "NOR (RO) Linux Kernel Image";
> + read-only;
> + };
> +
> + partition@400000 {
> + /* 11MB for JFFS2 based Root file System */
> + reg = <0x00400000 0x00b00000>;
> + label = "NOR (RW) JFFS2 Root File System";
> + };
> +
> + partition@f00000 {
> + /* This location must not be altered */
> + /* 512KB for u-boot Bootloader Image */
> + /* 512KB for u-boot Environment Variables */
> + reg = <0x00f00000 0x00100000>;
> + label = "NOR (RO) U-Boot Image";
> + read-only;
> + };
> + };
> +
> + nand@1,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,p2020-fcm-nand",
> + "fsl,elbc-fcm-nand";
> + reg = <0x1 0x0 0x40000>;
> +
> + u-boot@0 {
> + /* This location must not be altered */
> + /* 1MB for u-boot Bootloader Image */
> + reg = <0x0 0x00100000>;
> + label = "NAND (RO) U-Boot Image";
> + read-only;
> + };
> +
> + dtb@100000 {
> + /* 1MB for DTB Image */
> + reg = <0x00100000 0x00100000>;
> + label = "NAND (RO) DTB Image";
> + read-only;
> + };
> +
> + uImage@200000 {
> + /* 4MB for Linux Kernel Image */
> + reg = <0x00200000 0x00400000>;
> + label = "NAND (RO) Linux Kernel Image";
> + read-only;
> + };
> +
> + rfs@600000 {
> + /* 4MB for Compressed Root file System Image */
> + reg = <0x00600000 0x00400000>;
> + label = "NAND (RO) Compressed RFS Image";
> + read-only;
> + };
> +
> + jffs2@a00000 {
> + /* 7MB for JFFS2 based Root file System */
> + reg = <0x00a00000 0x00700000>;
> + label = "NAND (RW) JFFS2 Root File System";
> + };
> +
> + user@1100000 {
> + /* 15MB for JFFS2 based Root file System */
> + reg = <0x01100000 0x00f00000>;
> + label = "NAND (RW) Writable User area";
> + };
> + };
NAND partitions should also be declared using new syntax.
> +
> + L2switch@2,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "vitesse-7385";
> + reg = <0x2 0x0 0x20000>;
> + };
> +
> + };
> +
> + soc@ffe00000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "soc";
> + compatible = "fsl,p2020-immr", "simple-bus";
> + ranges = <0x0 0x0 0xffe00000 0x100000>;
> + bus-frequency = <0>; // Filled out by uboot.
> +
> + ecm-law@0 {
> + compatible = "fsl,ecm-law";
> + reg = <0x0 0x1000>;
> + fsl,num-laws = <12>;
> + };
> +
> + ecm@1000 {
> + compatible = "fsl,p2020-ecm", "fsl,ecm";
> + reg = <0x1000 0x1000>;
> + interrupts = <17 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + memory-controller@2000 {
> + compatible = "fsl,p2020-memory-controller";
> + reg = <0x2000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <18 2>;
> + };
> +
> + i2c@3000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cell-index = <0>;
> + compatible = "fsl-i2c";
> + reg = <0x3000 0x100>;
> + interrupts = <43 2>;
> + interrupt-parent = <&mpic>;
> + dfsrr;
> + rtc@68 {
> + compatible = "dallas,ds1339";
> + reg = <0x68>;
> + };
> + };
> +
> + i2c@3100 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cell-index = <1>;
> + compatible = "fsl-i2c";
> + reg = <0x3100 0x100>;
> + interrupts = <43 2>;
> + interrupt-parent = <&mpic>;
> + dfsrr;
> + };
> +
> + serial0: serial@4500 {
> + cell-index = <0>;
> + device_type = "serial";
> + compatible = "ns16550";
> + reg = <0x4500 0x100>;
> + clock-frequency = <0>;
> + interrupts = <42 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + serial1: serial@4600 {
> + cell-index = <1>;
> + device_type = "serial";
> + compatible = "ns16550";
> + reg = <0x4600 0x100>;
> + clock-frequency = <0>;
> + interrupts = <42 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + spi@7000 {
> + cell-index = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,espi";
> + reg = <0x7000 0x1000>;
> + interrupts = <59 0x2>;
> + interrupt-parent = <&mpic>;
> + mode = "cpu";
> +
> + fsl_m25p80@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,espi-flash";
> + reg = <0>;
> + linux,modalias = "fsl_m25p80";
> + modal = "s25sl128b";
> + spi-max-frequency = <50000000>;
> + mode = <0>;
> +
> + partition@0 {
> + /* 512KB for u-boot Bootloader Image */
> + reg = <0x0 0x00080000>;
> + label = "SPI (RO) U-Boot Image";
> + read-only;
> + };
> +
> + partition@80000 {
> + /* 512KB for DTB Image */
> + reg = <0x00080000 0x00080000>;
> + label = "SPI (RO) DTB Image";
> + read-only;
> + };
> +
> + partition@100000 {
> + /* 4MB for Linux Kernel Image */
> + reg = <0x00100000 0x00400000>;
> + label = "SPI (RO) Linux Kernel Image";
> + read-only;
> + };
> +
> + partition@500000 {
> + /* 4MB for Compressed RFS Image */
> + reg = <0x00500000 0x00400000>;
> + label = "SPI (RO) Compressed RFS Image";
> + read-only;
> + };
> +
> + partition@900000 {
> + /* 7MB for JFFS2 based RFS */
> + reg = <0x00900000 0x00700000>;
> + label = "SPI (RW) JFFS2 RFS";
> + };
> + };
> + };
> +
> + dma@c300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,eloplus-dma";
> + reg = <0xc300 0x4>;
> + ranges = <0x0 0xc100 0x200>;
> + cell-index = <1>;
> + dma-channel@0 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x0 0x80>;
> + cell-index = <0>;
> + interrupt-parent = <&mpic>;
> + interrupts = <76 2>;
> + };
> + dma-channel@80 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x80 0x80>;
> + cell-index = <1>;
> + interrupt-parent = <&mpic>;
> + interrupts = <77 2>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x100 0x80>;
> + cell-index = <2>;
> + interrupt-parent = <&mpic>;
> + interrupts = <78 2>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x180 0x80>;
> + cell-index = <3>;
> + interrupt-parent = <&mpic>;
> + interrupts = <79 2>;
> + };
> + };
> +
> + gpio: gpio-controller@f000 {
> + #gpio-cells = <2>;
> + compatible = "fsl,mpc8572-gpio";
> + reg = <0xf000 0x100>;
> + interrupts = <47 0x2>;
> + interrupt-parent = <&mpic>;
> + gpio-controller;
> + };
> +
> + L2: l2-cache-controller@20000 {
> + compatible = "fsl,p2020-l2-cache-controller";
> + reg = <0x20000 0x1000>;
> + cache-line-size = <32>; // 32 bytes
> + cache-size = <0x80000>; // L2,512K
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +
> + dma@21300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,eloplus-dma";
> + reg = <0x21300 0x4>;
> + ranges = <0x0 0x21100 0x200>;
> + cell-index = <0>;
> + dma-channel@0 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x0 0x80>;
> + cell-index = <0>;
> + interrupt-parent = <&mpic>;
> + interrupts = <20 2>;
> + };
> + dma-channel@80 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x80 0x80>;
> + cell-index = <1>;
> + interrupt-parent = <&mpic>;
> + interrupts = <21 2>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x100 0x80>;
> + cell-index = <2>;
> + interrupt-parent = <&mpic>;
> + interrupts = <22 2>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x180 0x80>;
> + cell-index = <3>;
> + interrupt-parent = <&mpic>;
> + interrupts = <23 2>;
> + };
> + };
> +
> + usb@22000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl-usb2-dr";
> + reg = <0x22000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <28 0x2>;
> + phy_type = "ulpi";
> + };
> +
> + enet0: ethernet@24000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + cell-index = <0>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "gianfar";
> + reg = <0x24000 0x1000>;
> + ranges = <0x0 0x24000 0x1000>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupts = <29 2 30 2 34 2>;
> + interrupt-parent = <&mpic>;
> + fixed-link = <1 1 1000 0 0>;
> + phy-connection-type = "rgmii-id";
> +
> + mdio@520 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,gianfar-mdio";
> + reg = <0x520 0x20>;
> +
> + phy0: ethernet-phy@0 {
> + interrupt-parent = <&mpic>;
> + interrupts = <3 1>;
> + reg = <0x0>;
> + };
> + phy1: ethernet-phy@1 {
> + interrupt-parent = <&mpic>;
> + interrupts = <3 1>;
> + reg = <0x1>;
> + };
> + };
> + };
> +
> + enet1: ethernet@25000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + cell-index = <1>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "gianfar";
> + reg = <0x25000 0x1000>;
> + ranges = <0x0 0x25000 0x1000>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupts = <35 2 36 2 40 2>;
> + interrupt-parent = <&mpic>;
> + tbi-handle = <&tbi0>;
> + phy-handle = <&phy0>;
> + phy-connection-type = "sgmii";
> +
> + mdio@520 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,gianfar-tbi";
> + reg = <0x520 0x20>;
> +
> + tbi0: tbi-phy@11 {
> + reg = <0x11>;
> + device_type = "tbi-phy";
> + };
> + };
> + };
> +
> + enet2: ethernet@26000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + cell-index = <2>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "gianfar";
> + reg = <0x26000 0x1000>;
> + ranges = <0x0 0x26000 0x1000>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupts = <31 2 32 2 33 2>;
> + interrupt-parent = <&mpic>;
> + phy-handle = <&phy1>;
> + phy-connection-type = "rgmii-id";
> + };
> +
Shouldn't mdio node be associated with enet2 ?
> + sdhci@2e000 {
> + compatible = "fsl,p2020-esdhc", "fsl,esdhc";
> + reg = <0x2e000 0x1000>;
> + interrupts = <72 0x2>;
> + interrupt-parent = <&mpic>;
> + /* Filled in by U-Boot */
> + clock-frequency = <0>;
> + };
> +
> + crypto@30000 {
> + compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
> + "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
> + reg = <0x30000 0x10000>;
> + interrupts = <45 2 58 2>;
> + interrupt-parent = <&mpic>;
> + fsl,num-channels = <4>;
> + fsl,channel-fifo-len = <24>;
> + fsl,exec-units-mask = <0xbfe>;
> + fsl,descriptor-types-mask = <0x3ab0ebf>;
> + };
> +
> + mpic: pic@40000 {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + reg = <0x40000 0x40000>;
> + compatible = "chrp,open-pic";
> + device_type = "open-pic";
> + };
> +
> + msi@41600 {
> + compatible = "fsl,p2020-msi", "fsl,mpic-msi";
> + reg = <0x41600 0x80>;
> + msi-available-ranges = <0 0x100>;
> + interrupts = <
> + 0xe0 0
> + 0xe1 0
> + 0xe2 0
> + 0xe3 0
> + 0xe4 0
> + 0xe5 0
> + 0xe6 0
> + 0xe7 0>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + global-utilities@e0000 { //global utilities block
> + compatible = "fsl,p2020-guts";
> + reg = <0xe0000 0x1000>;
> + fsl,has-rstcr;
> + };
> + };
> +
> + pci0: pcie@ffe09000 {
> + compatible = "fsl,mpc8548-pcie";
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + reg = <0 0xffe09000 0 0x1000>;
> + bus-range = <0 255>;
> + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
> + 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
> + clock-frequency = <33333333>;
> + interrupt-parent = <&mpic>;
> + interrupts = <25 2>;
> + pcie@0 {
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + device_type = "pci";
> + ranges = <0x2000000 0x0 0xa0000000
> + 0x2000000 0x0 0xa0000000
> + 0x0 0x20000000
> +
> + 0x1000000 0x0 0x0
> + 0x1000000 0x0 0x0
> + 0x0 0x100000>;
> + };
> + };
> +
> + pci1: pcie@ffe0a000 {
> + compatible = "fsl,mpc8548-pcie";
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + reg = <0 0xffe0a000 0 0x1000>;
> + bus-range = <0 255>;
> + ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
> + 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
> + clock-frequency = <33333333>;
> + interrupt-parent = <&mpic>;
> + interrupts = <26 2>;
> + pcie@0 {
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + device_type = "pci";
> + ranges = <0x2000000 0x0 0xc0000000
> + 0x2000000 0x0 0xc0000000
> + 0x0 0x20000000
> +
> + 0x1000000 0x0 0x0
> + 0x1000000 0x0 0x0
> + 0x0 0x100000>;
> + };
> + };
> +};
> diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
> index c162724..dc4819c 100644
> --- a/arch/powerpc/configs/mpc85xx_defconfig
> +++ b/arch/powerpc/configs/mpc85xx_defconfig
> @@ -189,6 +189,7 @@ CONFIG_MPC85xx_CDS=y
> CONFIG_MPC85xx_MDS=y
> CONFIG_MPC8536_DS=y
> CONFIG_MPC85xx_DS=y
> +CONFIG_MPC85xx_RDB=y
> CONFIG_SOCRATES=y
> CONFIG_KSI8560=y
> CONFIG_STX_GP3=y
> diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
> index a9b4166..d3a975e 100644
> --- a/arch/powerpc/platforms/85xx/Kconfig
> +++ b/arch/powerpc/platforms/85xx/Kconfig
> @@ -55,6 +55,15 @@ config MPC85xx_DS
> help
> This option enables support for the MPC85xx DS (MPC8544 DS) board
>
> +config MPC85xx_RDB
> + bool "Freescale MPC85xx RDB"
> + select PPC_I8259
> + select DEFAULT_UIMAGE
> + select FSL_ULI1575
> + select SWIOTLB
> + help
> + This option enables support for the MPC85xx RDB (P2020 RDB) board
> +
> config SOCRATES
> bool "Socrates"
> select DEFAULT_UIMAGE
> diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
> index 835733f..4efcc63 100644
> --- a/arch/powerpc/platforms/85xx/Makefile
> +++ b/arch/powerpc/platforms/85xx/Makefile
> @@ -9,10 +9,11 @@ obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
> obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o
> obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
> obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
> +obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
> obj-$(CONFIG_STX_GP3) += stx_gp3.o
> obj-$(CONFIG_TQM85xx) += tqm85xx.o
> obj-$(CONFIG_SBC8560) += sbc8560.o
> obj-$(CONFIG_SBC8548) += sbc8548.o
> obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
> obj-$(CONFIG_KSI8560) += ksi8560.o
> -obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
> \ No newline at end of file
> +obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> new file mode 100644
> index 0000000..c8468de
> --- /dev/null
> +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> @@ -0,0 +1,141 @@
> +/*
> + * MPC85xx RDB Board Setup
> + *
> + * Copyright 2009 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +#include <linux/stddef.h>
> +#include <linux/kernel.h>
> +#include <linux/pci.h>
> +#include <linux/kdev_t.h>
> +#include <linux/delay.h>
> +#include <linux/seq_file.h>
> +#include <linux/interrupt.h>
> +#include <linux/of_platform.h>
> +
> +#include <asm/system.h>
> +#include <asm/time.h>
> +#include <asm/machdep.h>
> +#include <asm/pci-bridge.h>
> +#include <mm/mmu_decl.h>
> +#include <asm/prom.h>
> +#include <asm/udbg.h>
> +#include <asm/mpic.h>
> +
> +#include <sysdev/fsl_soc.h>
> +#include <sysdev/fsl_pci.h>
> +
> +#undef DEBUG
> +
> +#ifdef DEBUG
> +#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
> +#else
> +#define DBG(fmt, args...)
> +#endif
> +
> +
> +void __init mpc85xx_rdb_pic_init(void)
> +{
> + struct mpic *mpic;
> + struct resource r;
> + struct device_node *np;
> +
> + np = of_find_node_by_type(NULL, "open-pic");
> + if (np == NULL) {
> + printk(KERN_ERR "Could not find open-pic node\n");
> + return;
> + }
> +
> + if (of_address_to_resource(np, 0, &r)) {
> + printk(KERN_ERR "Failed to map mpic register space\n");
> + of_node_put(np);
> + return;
> + }
> +
> + mpic = mpic_alloc(np, r.start,
> + MPIC_PRIMARY | MPIC_WANTS_RESET |
> + MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
> + MPIC_SINGLE_DEST_CPU,
> + 0, 256, " OpenPIC ");
> +
> + BUG_ON(mpic == NULL);
> + of_node_put(np);
> +
> + mpic_init(mpic);
> +
> +}
> +
> +/*
> + * Setup the architecture
> + */
> +#ifdef CONFIG_SMP
> +extern void __init mpc85xx_smp_init(void);
> +#endif
> +static void __init mpc85xx_rdb_setup_arch(void)
> +{
> +#ifdef CONFIG_PCI
> + struct device_node *np;
> +#endif
> +
> + if (ppc_md.progress)
> + ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
> +
> +#ifdef CONFIG_PCI
> + for_each_node_by_type(np, "pci") {
> + if (of_device_is_compatible(np, "fsl,mpc8548-pcie"))
> + fsl_add_bridge(np, 0);
> + }
> +
> +#endif
> +
> +#ifdef CONFIG_SMP
> + mpc85xx_smp_init();
> +#endif
> +
> + printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
> +}
> +
> +static struct of_device_id __initdata mpc85xxrdb_ids[] = {
> + { .type = "soc", },
> + { .compatible = "soc", },
> + { .compatible = "simple-bus", },
> + { .compatible = "gianfar", },
> + {},
> +};
> +
> +static int __init mpc85xxrdb_publish_devices(void)
> +{
> + return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);
> +}
> +machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);
> +
> +/*
> + * Called very early, device-tree isn't unflattened
> + */
> +static int __init p2020_rdb_probe(void)
> +{
> + unsigned long root = of_get_flat_dt_root();
> +
> + if (of_flat_dt_is_compatible(root, "fsl,P2020RDB"))
> + return 1;
> + return 0;
> +}
> +
> +define_machine(p2020_rdb) {
> + .name = "P2020 RDB",
> + .probe = p2020_rdb_probe,
> + .setup_arch = mpc85xx_rdb_setup_arch,
> + .init_IRQ = mpc85xx_rdb_pic_init,
> +#ifdef CONFIG_PCI
> + .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
> +#endif
> + .get_irq = mpic_get_irq,
> + .restart = fsl_rstcr_restart,
> + .calibrate_decr = generic_calibrate_decr,
> + .progress = udbg_progress,
> +};
^ permalink raw reply
* Re: MPC8313 performance evaluation
From: Lutz Jaenicke @ 2009-08-07 11:02 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20090807105654.GA20678@lutz.bln.innominate.local>
On Fri, Aug 07, 2009 at 12:56:54PM +0200, Lutz Jaenicke wrote:
> On Fri, Aug 07, 2009 at 04:08:50PM +0800, Liu Dave-R63238 wrote:
> >
> > > Some discussion with the the freescale rep. lead to the CSB frequency
> > > of the 8313 (166MHz) being significantly lower than that of the 8343.
> > > Is the CSB the critical point here?
> >
> > I believe the CSB is critical point here. They are right.
>
> This indeed indicates that the CSB is the limiting factor.
> Until a few days ago I have not even been aware of the CSB being a
> performance critical component. All of the nice powerpoints explaining
> the processors and used for comparing different families shown by the
> Freescale Rep include the core frequencies and the DRAM interface
> and frequency but do not even mention the CSB...
Having this said, is there any good white paper to be read about it?
For firewall usage there are different influence factors:
* Ethernet interfaces (DMA to/from DRAM via CSB!?)
* CPU processing for the firewall rules (code/data to/from DRAM closely
related to cache size or misses)
Hence I would like to understand better the impact of the different
components.
(If only available under NDA I can also contact my Freescale Rep but
having public source always makes things easier.)
Best regards,
Lutz
--
Dr.-Ing. Lutz Jänicke
CTO
Innominate Security Technologies AG /protecting industrial networks/
tel: +49.30.921028-200
fax: +49.30.921028-020
Rudower Chaussee 13
D-12489 Berlin, Germany
www.innominate.com
Register Court: AG Charlottenburg, HR B 81603
Management Board: Dirk Seewald
Chairman of the Supervisory Board: Volker Bibelhausen
^ permalink raw reply
* Re: MPC8313 performance evaluation
From: Lutz Jaenicke @ 2009-08-07 10:56 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <D7CCA83BB0796C49BC0BB53B6AB1208956D03F@zch01exm21.fsl.freescale.net>
On Fri, Aug 07, 2009 at 04:08:50PM +0800, Liu Dave-R63238 wrote:
>
> > Some discussion with the the freescale rep. lead to the CSB frequency
> > of the 8313 (166MHz) being significantly lower than that of the 8343.
> > Is the CSB the critical point here?
>
> I believe the CSB is critical point here. They are right.
I have performed some additional measurements with other multiplier/divider
settings
Previous values with CSB=166MHz
> >> With the MPC8313 I get a significantly lower value:
> >> MPC8313@250MHz 12500fps
> >> MPC8313@333MHz 14500fps
> >> MPC8313@416MHz 15500fps (333MHz type, overclocked)
New value with CSB=200MHz (overclocked)
MPC8313@400MHz 17500fps
This indeed indicates that the CSB is the limiting factor.
Until a few days ago I have not even been aware of the CSB being a
performance critical component. All of the nice powerpoints explaining
the processors and used for comparing different families shown by the
Freescale Rep include the core frequencies and the DRAM interface
and frequency but do not even mention the CSB...
> > Note: the IXP42x uses an internal bus speed of 133MHz and operates
> > at frame rates similar to the 8343...
>
> It is possible, IXP42x has the differenet SoC architecture with 83xx.
That is very true indeed, then XScale (ARM) based IXP42x does have
a completely different implementation.
Best regards,
Lutz
--
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CTO
Innominate Security Technologies AG /protecting industrial networks/
tel: +49.30.921028-200
fax: +49.30.921028-020
Rudower Chaussee 13
D-12489 Berlin, Germany
www.innominate.com
Register Court: AG Charlottenburg, HR B 81603
Management Board: Dirk Seewald
Chairman of the Supervisory Board: Volker Bibelhausen
^ permalink raw reply
* Linux booting problem
From: Sumesh Kaana @ 2009-08-07 9:02 UTC (permalink / raw)
To: linuxppc-dev
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Hi all,
I am trying to boot linux kernel (2.6.30) on a custom built board.I am using simple ppc platform and attached are my dts file and boot log..
I've 26Mb of RAM,UART and UIC with powerpc 440x5 processor.Kernel Image size is less than 1 mb.
cgc,skybeam board is added in arch/powerpc/platforms/44x/ppc44x_simple.c
device tree file as bellow:----------------------------
/dts-v1/;
/ { model = "cgc,skybeam"; compatible = "cgc,skybeam"; #address-cells = <1>; #size-cells = <1>; dcr-parent = <&SKYBEAM_PPC>; chosen { bootargs = "console=ttyS0 root=/dev/ram"; linux,stdout-path = "/plb/serial@02080000"; } ; aliases { serial0 = &STD_UART; } ; memory { device_type = "memory"; reg = < 0x0 0x01A00000 >; } ; cpus { #address-cells = <1>; #size-cells = <0>; SKYBEAM_PPC: cpu@0 { device_type = "cpu"; #address-cells = <1>; #size-cells = <1>; reg = <0>; clock-frequency = <25000000>; compatible = "PowerPC,440", "ibm,ppc440"; d-cache-line-size = <0x20>; d-cache-size = <0x8000>; dcr-access-method = "native"; dcr-controller ; i-cache-line-size = <0x20>; i-cache-size = <0x8000>; model = "PowerPC,440"; timebase-frequency = <25000000>; } ; } ; UIC0: interrupt-controller0 { compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <0>; dcr-reg = <0x1c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; }; PLB: plb { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges ; STD_UART: serial@02080000 { device_type = "serial"; compatible = "ns16550"; reg = <0x02080000 0x00000008>; virtual-reg = <0x02080000>; clock-frequency = <125000000>; current-speed = <9600>; interrupt-parent = <&UIC0>; interrupts = <0x5 0x4>; } ; } ;} ;
boot log is as below:---------------------
zImage starting: loaded at 0x00400000 (sp: 0x004deeb0)Allocating 0x1dad84 bytes for kernel ...gunzipping (0x00000000 <- 0x0040c000:0x004dd3fc)...done 0x1c31cc bytes
Linux/PowerPC load: console=ttyS0 root=/dev/ramFinalizing device tree... flat tree at 0x4eb300Debug print:This worksDebug print:############!!!!###########Memory hole size: 0MB
Unable to handle kernel paging request for data at address 0x01a00000Faulting instruction address: 0xc0011434Oops: Kernel access of bad area, sig: 11 [#1]PREEMPT PowerPC 44x PlatformModules linked in:NIP: c0011434 LR: c010dcb0 CTR: 00000001REGS: c01bfe60 TRAP: 0300 Not tainted (2.6.30)MSR: 00021000 <ME,CE> CR: 22000024 XER: 20000000DEAR: 01a00000, ESR: 00000000TASK = c01a94b8[0] 'swapper' THREAD: c01be000GPR00: fffffff4 c01bff10 c01a94b8 01a00000 019fffff 0000000c c01958b0 00000000GPR08: 00000037 c0110000 00000042 00003fff 22000022 00000000 fffff104 00000000GPR16: 00000000 00000000 00000000 00000000 00000000 00000000 c010d750 c01958b0GPR24: 0000000c 00000000 c01a1dfc 01a00000 c01a1dfc 00003fff 0000000c 00000000NIP [c0011434] strlen+0x4/0x18LR [c010dcb0] match_token+0x1a0/0x228Call Trace:[c01bff50] [c01962f4] free_area_init_nodes+0x48/0x3a0[c01bff80] [c0191738] paging_init+0x80/0xa0[c01bffb0] [c01909b4] setup_arch+0x1c4/0x1dc[c01bffc0] [c018c648] start_kernel+0x54/0x288[c01bfff0] [c0000200] skpinv+0x190/0x1ccInstruction dump:4d820020 7ca903a6 38a3ffff 3884ffff 8c650001 2c830000 8c040001 7c6018514d860020 4102ffec 4e800020 3883ffff <8c040001> 2c000000 4082fff8 7c632050---[ end trace 31fd0ba7d8756001 ]---Kernel panic - not syncing: Attempted to kill the idle task!Call Trace:[c01bfd40] [c0005d5c] show_stack+0x4c/0x16c (unreliable)[c01bfd80] [c002f174] panic+0xa0/0x168[c01bfdd0] [c0032eb0] do_exit+0x61c/0x638[c01bfe10] [c000b60c] kernel_bad_stack+0x0/0x4c[c01bfe40] [c000f328] bad_page_fault+0x90/0xd8[c01bfe50] [c000e19c] handle_page_fault+0x7c/0x80[c01bff10] [00000000] (null)[c01bff50] [c01962f4] free_area_init_nodes+0x48/0x3a0[c01bff80] [c0191738] paging_init+0x80/0xa0[c01bffb0] [c01909b4] setup_arch+0x1c4/0x1dc[c01bffc0] [c018c648] start_kernel+0x54/0x288[c01bfff0] [c0000200] skpinv+0x190/0x1ccRebooting in 180 seconds..
Can anyone tell what would be the problem..?
thanks,Sumesh.
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^ permalink raw reply
* Re: Question about powerpc branch instructions
From: Benjamin Herrenschmidt @ 2009-08-07 8:52 UTC (permalink / raw)
To: HongWoo Lee; +Cc: linuxppc-dev
In-Reply-To: <4A7BEA04.7030006@gmail.com>
On Fri, 2009-08-07 at 17:47 +0900, HongWoo Lee wrote:
> #1: Is there any special reason to concatenate 0b00 ? Why 0b00 ??
Because instructions have to be aligned on 4 bytes boundaries ?
> #2: Is b similar to the jmp in x86 ? and bl is similar to the call in x86 ?
I'm not totally familiar with x86 but I "sounds" like it, though of
course they can be (ab)used in some more subtle ways.
Cheers,
Ben.
> Thanks in advance.
>
> HongWoo.
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Question about powerpc branch instructions
From: HongWoo Lee @ 2009-08-07 8:47 UTC (permalink / raw)
To: linuxppc-dev
Hi~
I want to know about bl instruction and the difference between branch
instructions.
I found this code segment.
{{{
....
bl go_to_real
insrdi r18, r19, 32, 0
....
}}}
And I found the explanation about branch instructions in PowerISA 2.06
document.
{{{
b target_addr (AA=0 LK=0)
ba target_addr (AA=1 LK=0)
bl target_addr (AA=0 LK=1)
bla target_addr (AA=1 LK=1)
If AA=0 then the branch target address is the sum of LI || 0b00
sign-extended and the address of this instruction,
with the high-order 32 bits of the branch target address set to 0 in
32-bit mode.
If AA=1 then the branch target address is the value LI || 0b00
sign-extended,
with the high-order 32 bits of the branch target address set to 0 in
32-bit mode.
If LK=1 then the effective address of the instruction following the
Branch instruction is placed into the Link Register.
}}}
Questions
#1: Is there any special reason to concatenate 0b00 ? Why 0b00 ??
#2: Is b similar to the jmp in x86 ? and bl is similar to the call in x86 ?
Thanks in advance.
HongWoo.
^ permalink raw reply
* [PATCH][v2][powerpc/85xx] P2020RDB Platform Support Added
From: Poonam Aggrwal @ 2009-08-07 8:21 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Poonam Aggrwal
Adds P2020RDB basic support in linux.
Overview of P2020RDB platform
- DDR
DDR2 1G
- NOR Flash
16MByte
- NAND Flash
32MByte
- 3 Ethernet interfaces
1) etSEC1
- RGMII
- connected to a 5 port Vitesse Switch(VSC7385)
- Switch is memory mapped through eLBC interface(CS#2)
- IRQ1
2) etSEC2
- SGMII
- connected to VSC8221
- IRQ2
3) etSEC3
- RGMII
- connected to VSC8641
- IRQ3
- 2 1X PCIe interfaces
- SD/MMC ,USB
- SPI EEPROM
- Serial I2C EEPROM
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
---
based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
incorporated Felix feedback regarding the partition names.
fixed the vitesse switch ranges entry in device tree.
arch/powerpc/boot/dts/p2020rdb.dts | 586 +++++++++++++++++++++++++++++
arch/powerpc/configs/mpc85xx_defconfig | 1 +
arch/powerpc/platforms/85xx/Kconfig | 9 +
arch/powerpc/platforms/85xx/Makefile | 3 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 141 +++++++
5 files changed, 739 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p2020rdb.dts
create mode 100644 arch/powerpc/platforms/85xx/mpc85xx_rdb.c
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
new file mode 100644
index 0000000..617029f
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -0,0 +1,586 @@
+/*
+ * P2020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = "fsl,P2020";
+ compatible = "fsl,P2020RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,P2020@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,P2020@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ localbus@ffe05000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xffe05000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+
+ /* NOR and NAND Flashes */
+ ranges = <0x0 0x0 0x0 0xef000000 0x01000000
+ 0x1 0x0 0x0 0xffa00000 0x00040000
+ 0x2 0x0 0x0 0xffb00000 0x00020000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x1000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = <0x0 0x00040000>;
+ label = "NOR (RO) Vitesse-7385 Firmware";
+ read-only;
+ };
+
+ partition@40000 {
+ /* 256KB for DTB Image */
+ reg = <0x00040000 0x00040000>;
+ label = "NOR (RO) DTB Image";
+ read-only;
+ };
+
+ partition@80000 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = <0x00080000 0x00380000>;
+ label = "NOR (RO) Linux Kernel Image";
+ read-only;
+ };
+
+ partition@400000 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = <0x00400000 0x00b00000>;
+ label = "NOR (RW) JFFS2 Root File System";
+ };
+
+ partition@f00000 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = <0x00f00000 0x00100000>;
+ label = "NOR (RO) U-Boot Image";
+ read-only;
+ };
+ };
+
+ nand@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p2020-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x1 0x0 0x40000>;
+
+ u-boot@0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = <0x0 0x00100000>;
+ label = "NAND (RO) U-Boot Image";
+ read-only;
+ };
+
+ dtb@100000 {
+ /* 1MB for DTB Image */
+ reg = <0x00100000 0x00100000>;
+ label = "NAND (RO) DTB Image";
+ read-only;
+ };
+
+ uImage@200000 {
+ /* 4MB for Linux Kernel Image */
+ reg = <0x00200000 0x00400000>;
+ label = "NAND (RO) Linux Kernel Image";
+ read-only;
+ };
+
+ rfs@600000 {
+ /* 4MB for Compressed Root file System Image */
+ reg = <0x00600000 0x00400000>;
+ label = "NAND (RO) Compressed RFS Image";
+ read-only;
+ };
+
+ jffs2@a00000 {
+ /* 7MB for JFFS2 based Root file System */
+ reg = <0x00a00000 0x00700000>;
+ label = "NAND (RW) JFFS2 Root File System";
+ };
+
+ user@1100000 {
+ /* 15MB for JFFS2 based Root file System */
+ reg = <0x01100000 0x00f00000>;
+ label = "NAND (RW) Writable User area";
+ };
+ };
+
+ L2switch@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "vitesse-7385";
+ reg = <0x2 0x0 0x20000>;
+ };
+
+ };
+
+ soc@ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p2020-immr", "simple-bus";
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,p2020-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,p2020-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ spi@7000 {
+ cell-index = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,espi";
+ reg = <0x7000 0x1000>;
+ interrupts = <59 0x2>;
+ interrupt-parent = <&mpic>;
+ mode = "cpu";
+
+ fsl_m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,espi-flash";
+ reg = <0>;
+ linux,modalias = "fsl_m25p80";
+ modal = "s25sl128b";
+ spi-max-frequency = <50000000>;
+ mode = <0>;
+
+ partition@0 {
+ /* 512KB for u-boot Bootloader Image */
+ reg = <0x0 0x00080000>;
+ label = "SPI (RO) U-Boot Image";
+ read-only;
+ };
+
+ partition@80000 {
+ /* 512KB for DTB Image */
+ reg = <0x00080000 0x00080000>;
+ label = "SPI (RO) DTB Image";
+ read-only;
+ };
+
+ partition@100000 {
+ /* 4MB for Linux Kernel Image */
+ reg = <0x00100000 0x00400000>;
+ label = "SPI (RO) Linux Kernel Image";
+ read-only;
+ };
+
+ partition@500000 {
+ /* 4MB for Compressed RFS Image */
+ reg = <0x00500000 0x00400000>;
+ label = "SPI (RO) Compressed RFS Image";
+ read-only;
+ };
+
+ partition@900000 {
+ /* 7MB for JFFS2 based RFS */
+ reg = <0x00900000 0x00700000>;
+ label = "SPI (RW) JFFS2 RFS";
+ };
+ };
+ };
+
+ dma@c300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0xc300 0x4>;
+ ranges = <0x0 0xc100 0x200>;
+ cell-index = <1>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <76 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <77 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <78 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <79 2>;
+ };
+ };
+
+ gpio: gpio-controller@f000 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x100>;
+ interrupts = <47 0x2>;
+ interrupt-parent = <&mpic>;
+ gpio-controller;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,p2020-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x80000>; // L2,512K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ usb@22000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x22000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <28 0x2>;
+ phy_type = "ulpi";
+ };
+
+ enet0: ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ fixed-link = <1 1 1000 0 0>;
+ phy-connection-type = "rgmii-id";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x1>;
+ };
+ };
+ };
+
+ enet1: ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "sgmii";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet2: ethernet@26000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <2>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x26000 0x1000>;
+ ranges = <0x0 0x26000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <31 2 32 2 33 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ sdhci@2e000 {
+ compatible = "fsl,p2020-esdhc", "fsl,esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <72 0x2>;
+ interrupt-parent = <&mpic>;
+ /* Filled in by U-Boot */
+ clock-frequency = <0>;
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+ "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xbfe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi@41600 {
+ compatible = "fsl,p2020-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,p2020-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci0: pcie@ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe09000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <25 2>;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe0a000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <26 2>;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+};
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index c162724..dc4819c 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -189,6 +189,7 @@ CONFIG_MPC85xx_CDS=y
CONFIG_MPC85xx_MDS=y
CONFIG_MPC8536_DS=y
CONFIG_MPC85xx_DS=y
+CONFIG_MPC85xx_RDB=y
CONFIG_SOCRATES=y
CONFIG_KSI8560=y
CONFIG_STX_GP3=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index a9b4166..d3a975e 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -55,6 +55,15 @@ config MPC85xx_DS
help
This option enables support for the MPC85xx DS (MPC8544 DS) board
+config MPC85xx_RDB
+ bool "Freescale MPC85xx RDB"
+ select PPC_I8259
+ select DEFAULT_UIMAGE
+ select FSL_ULI1575
+ select SWIOTLB
+ help
+ This option enables support for the MPC85xx RDB (P2020 RDB) board
+
config SOCRATES
bool "Socrates"
select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 835733f..4efcc63 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -9,10 +9,11 @@ obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o
obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
+obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
obj-$(CONFIG_STX_GP3) += stx_gp3.o
obj-$(CONFIG_TQM85xx) += tqm85xx.o
obj-$(CONFIG_SBC8560) += sbc8560.o
obj-$(CONFIG_SBC8548) += sbc8548.o
obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
obj-$(CONFIG_KSI8560) += ksi8560.o
-obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
\ No newline at end of file
+obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
new file mode 100644
index 0000000..c8468de
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -0,0 +1,141 @@
+/*
+ * MPC85xx RDB Board Setup
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
+#else
+#define DBG(fmt, args...)
+#endif
+
+
+void __init mpc85xx_rdb_pic_init(void)
+{
+ struct mpic *mpic;
+ struct resource r;
+ struct device_node *np;
+
+ np = of_find_node_by_type(NULL, "open-pic");
+ if (np == NULL) {
+ printk(KERN_ERR "Could not find open-pic node\n");
+ return;
+ }
+
+ if (of_address_to_resource(np, 0, &r)) {
+ printk(KERN_ERR "Failed to map mpic register space\n");
+ of_node_put(np);
+ return;
+ }
+
+ mpic = mpic_alloc(np, r.start,
+ MPIC_PRIMARY | MPIC_WANTS_RESET |
+ MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+ MPIC_SINGLE_DEST_CPU,
+ 0, 256, " OpenPIC ");
+
+ BUG_ON(mpic == NULL);
+ of_node_put(np);
+
+ mpic_init(mpic);
+
+}
+
+/*
+ * Setup the architecture
+ */
+#ifdef CONFIG_SMP
+extern void __init mpc85xx_smp_init(void);
+#endif
+static void __init mpc85xx_rdb_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+ struct device_node *np;
+#endif
+
+ if (ppc_md.progress)
+ ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+ for_each_node_by_type(np, "pci") {
+ if (of_device_is_compatible(np, "fsl,mpc8548-pcie"))
+ fsl_add_bridge(np, 0);
+ }
+
+#endif
+
+#ifdef CONFIG_SMP
+ mpc85xx_smp_init();
+#endif
+
+ printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
+}
+
+static struct of_device_id __initdata mpc85xxrdb_ids[] = {
+ { .type = "soc", },
+ { .compatible = "soc", },
+ { .compatible = "simple-bus", },
+ { .compatible = "gianfar", },
+ {},
+};
+
+static int __init mpc85xxrdb_publish_devices(void)
+{
+ return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);
+}
+machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p2020_rdb_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, "fsl,P2020RDB"))
+ return 1;
+ return 0;
+}
+
+define_machine(p2020_rdb) {
+ .name = "P2020 RDB",
+ .probe = p2020_rdb_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.5.6.3
^ permalink raw reply related
* RE: MPC8313 performance evaluation
From: Liu Dave-R63238 @ 2009-08-07 8:08 UTC (permalink / raw)
To: Lutz Jaenicke, linuxppc-dev
In-Reply-To: <20090806180035.GA19088@lutz.bln.innominate.local>
> Some discussion with the the freescale rep. lead to the CSB frequency
> of the 8313 (166MHz) being significantly lower than that of the 8343.
> Is the CSB the critical point here?
I believe the CSB is critical point here. They are right.
> Note: the IXP42x uses an internal bus speed of 133MHz and operates
> at frame rates similar to the 8343...
It is possible, IXP42x has the differenet SoC architecture with 83xx.
^ permalink raw reply
* RE: MPC8313 performance evaluation
From: Liu Dave-R63238 @ 2009-08-07 8:05 UTC (permalink / raw)
To: Lutz Jaenicke, linuxppc-dev
In-Reply-To: <20090807074801.GA19763@lutz.bln.innominate.local>
> > On Aug 6, 2009, at 1:00 PM, Lutz Jaenicke wrote:
> >> With the MPC8343@400MHz I get a throughput of approx.=20
> 24500 frames/s
> >> using the predefined firewall rules.
>=20
> >> With the MPC8313 I get a significantly lower value:
> >> MPC8313@250MHz 12500fps
> >> MPC8313@333MHz 14500fps
> >> MPC8313@416MHz 15500fps (333MHz type, overclocked)
>=20
> > What DDR frequencies (and width) are you running the 8343=20
> vs 8313 at. =20
> > This can have a significant impact on performance.
>=20
> The 8343 is running DDR2 32bit at 266MHz (CSB 266MHz)
> The 8313 is running DDR2 32bit at 333MHz (CSB 166MHz)
>=20
> The test were performed with 128byte frames so that the overall
> bandwidth needed is far below even 100Mbit/s.
The CSB bus freq is key for the throught.
CSB freq of 8313 is lower than 8343, it will cause the performance
degrade.
^ permalink raw reply
* Re: MPC8313 performance evaluation
From: Lutz Jaenicke @ 2009-08-07 7:48 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <8731B515-14B1-4580-A196-75E57543C3F9@kernel.crashing.org>
On Thu, Aug 06, 2009 at 02:16:55PM -0500, Kumar Gala wrote:
>
> On Aug 6, 2009, at 1:00 PM, Lutz Jaenicke wrote:
>> With the MPC8343@400MHz I get a throughput of approx. 24500 frames/s
>> using the predefined firewall rules.
>> With the MPC8313 I get a significantly lower value:
>> MPC8313@250MHz 12500fps
>> MPC8313@333MHz 14500fps
>> MPC8313@416MHz 15500fps (333MHz type, overclocked)
> What DDR frequencies (and width) are you running the 8343 vs 8313 at.
> This can have a significant impact on performance.
The 8343 is running DDR2 32bit at 266MHz (CSB 266MHz)
The 8313 is running DDR2 32bit at 333MHz (CSB 166MHz)
The test were performed with 128byte frames so that the overall
bandwidth needed is far below even 100Mbit/s.
Best regards,
Lutz
--
Dr.-Ing. Lutz Jänicke
CTO
Innominate Security Technologies AG /protecting industrial networks/
tel: +49.30.921028-200
fax: +49.30.921028-020
Rudower Chaussee 13
D-12489 Berlin, Germany
www.innominate.com
Register Court: AG Charlottenburg, HR B 81603
Management Board: Dirk Seewald
Chairman of the Supervisory Board: Volker Bibelhausen
^ permalink raw reply
* Re: [PATCH 1/3] arch/powerpc: Add kmalloc NULL tests
From: Julia Lawall @ 2009-08-07 7:00 UTC (permalink / raw)
To: Daniel K.; +Cc: kernel-janitors, paulus, linux-kernel, linuxppc-dev
In-Reply-To: <4A7BCAF1.5070605@uw.no>
From: Julia Lawall <julia@diku.dk>
Check that the result of kmalloc/kzalloc is not NULL before dereferencing it.
The semantic match that finds this problem is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@@
expression *x;
identifier f;
constant char *C;
@@
x = \(kmalloc\|kcalloc\|kzalloc\)(...);
... when != x == NULL
when != x != NULL
when != (x || ...)
(
kfree(x)
|
f(...,C,...,x,...)
|
*f(...,x,...)
|
*x->f
)
// </smpl>
Signed-off-by: Julia Lawall <julia@diku.dk>
---
arch/powerpc/sysdev/fsl_rio.c | 18 ++++++++++++++----
1 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index cbb3bed..757a83f 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -1057,6 +1057,10 @@ int fsl_rio_setup(struct of_device *dev)
law_start, law_size);
ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
+ if (!ops) {
+ rc = -ENOMEM;
+ goto err_ops;
+ }
ops->lcread = fsl_local_config_read;
ops->lcwrite = fsl_local_config_write;
ops->cread = fsl_rio_config_read;
@@ -1064,6 +1068,10 @@ int fsl_rio_setup(struct of_device *dev)
ops->dsend = fsl_rio_doorbell_send;
port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
+ if (!port) {
+ rc = -ENOMEM;
+ goto err_port;
+ }
port->id = 0;
port->index = 0;
@@ -1071,7 +1079,7 @@ int fsl_rio_setup(struct of_device *dev)
if (!priv) {
printk(KERN_ERR "Can't alloc memory for 'priv'\n");
rc = -ENOMEM;
- goto err;
+ goto err_priv;
}
INIT_LIST_HEAD(&port->dbells);
@@ -1169,11 +1177,13 @@ int fsl_rio_setup(struct of_device *dev)
return 0;
err:
- if (priv)
- iounmap(priv->regs_win);
- kfree(ops);
+ iounmap(priv->regs_win);
kfree(priv);
+err_priv:
kfree(port);
+err_port:
+ kfree(ops);
+err_ops:
return rc;
}
^ permalink raw reply related
* Re: [PATCH 1/3] arch/powerpc: Add kmalloc NULL tests
From: Julia Lawall @ 2009-08-07 6:51 UTC (permalink / raw)
To: Daniel K.; +Cc: kernel-janitors, paulus, linux-kernel, linuxppc-dev
In-Reply-To: <4A7BCAF1.5070605@uw.no>
On Fri, 7 Aug 2009, Daniel K. wrote:
> Julia Lawall wrote:
> > --- a/arch/powerpc/sysdev/fsl_rio.c
> > +++ b/arch/powerpc/sysdev/fsl_rio.c
> > @@ -1057,6 +1057,10 @@ int fsl_rio_setup(struct of_device *dev)
> > law_start, law_size);
> >
> > ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
> > + if (!ops) {
> > + rc = -ENOMEM;
> > + goto err_ops;
> > + }
> > ops->lcread = fsl_local_config_read;
> > ops->lcwrite = fsl_local_config_write;
> > ops->cread = fsl_rio_config_read;
> > @@ -1064,6 +1068,10 @@ int fsl_rio_setup(struct of_device *dev)
> > ops->dsend = fsl_rio_doorbell_send;
> >
> > port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
> > + if (!port) {
> > + rc = -ENOMEM;
> > + goto err_port;
> > + }
> > port->id = 0;
> > port->index = 0;
> >
> > @@ -1071,7 +1079,7 @@ int fsl_rio_setup(struct of_device *dev)
> > if (!priv) {
> > printk(KERN_ERR "Can't alloc memory for 'priv'\n");
> > rc = -ENOMEM;
> > - goto err;
> > + goto err_priv;
> > }
> >
> > INIT_LIST_HEAD(&port->dbells);
> > @@ -1169,13 +1177,15 @@ int fsl_rio_setup(struct of_device *dev)
> >
> > return 0;
> > err:
> > - if (priv)
> > - iounmap(priv->regs_win);
> > - kfree(ops);
> > + iounmap(priv->regs_win);
> > +err_priv:
> > kfree(priv);
> > +err_port:
> > kfree(port);
> > +err_ops:
> > + kfree(ops);
> > return rc;
>
> There seems to be a goto-off-by-one error here.
>
> If xxxx = kxalloc() fails, you goto err_xxxx, and do a kfree(xxxx) where xxxx
> is
> already proven to be NULL.
>
> Is there a reason for this that eludes me?
No, I messed up... I will fix it.
julia
> I'd expect that last hunk to look something like
>
> @@ -1169,13 +1177,15 @@ int fsl_rio_setup(struct of_device *dev)
>
> return 0;
> err:
> - if (priv)
> - iounmap(priv->regs_win);
> - kfree(ops);
> + iounmap(priv->regs_win);
> kfree(priv);
> +err_priv:
> kfree(port);
> +err_port:
> + kfree(ops);
> +err_ops:
> return rc;
> }
>
>
> Daniel K.
> --
> To unsubscribe from this list: send the line "unsubscribe kernel-janitors" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* Re: [PATCH 1/3] arch/powerpc: Add kmalloc NULL tests
From: Daniel K. @ 2009-08-07 6:34 UTC (permalink / raw)
To: Julia Lawall; +Cc: kernel-janitors, paulus, linux-kernel, linuxppc-dev
In-Reply-To: <Pine.LNX.4.64.0908062203380.19100@ask.diku.dk>
Julia Lawall wrote:
> --- a/arch/powerpc/sysdev/fsl_rio.c
> +++ b/arch/powerpc/sysdev/fsl_rio.c
> @@ -1057,6 +1057,10 @@ int fsl_rio_setup(struct of_device *dev)
> law_start, law_size);
>
> ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL);
> + if (!ops) {
> + rc = -ENOMEM;
> + goto err_ops;
> + }
> ops->lcread = fsl_local_config_read;
> ops->lcwrite = fsl_local_config_write;
> ops->cread = fsl_rio_config_read;
> @@ -1064,6 +1068,10 @@ int fsl_rio_setup(struct of_device *dev)
> ops->dsend = fsl_rio_doorbell_send;
>
> port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
> + if (!port) {
> + rc = -ENOMEM;
> + goto err_port;
> + }
> port->id = 0;
> port->index = 0;
>
> @@ -1071,7 +1079,7 @@ int fsl_rio_setup(struct of_device *dev)
> if (!priv) {
> printk(KERN_ERR "Can't alloc memory for 'priv'\n");
> rc = -ENOMEM;
> - goto err;
> + goto err_priv;
> }
>
> INIT_LIST_HEAD(&port->dbells);
> @@ -1169,13 +1177,15 @@ int fsl_rio_setup(struct of_device *dev)
>
> return 0;
> err:
> - if (priv)
> - iounmap(priv->regs_win);
> - kfree(ops);
> + iounmap(priv->regs_win);
> +err_priv:
> kfree(priv);
> +err_port:
> kfree(port);
> +err_ops:
> + kfree(ops);
> return rc;
There seems to be a goto-off-by-one error here.
If xxxx = kxalloc() fails, you goto err_xxxx, and do a kfree(xxxx) where xxxx is
already proven to be NULL.
Is there a reason for this that eludes me?
I'd expect that last hunk to look something like
@@ -1169,13 +1177,15 @@ int fsl_rio_setup(struct of_device *dev)
return 0;
err:
- if (priv)
- iounmap(priv->regs_win);
- kfree(ops);
+ iounmap(priv->regs_win);
kfree(priv);
+err_priv:
kfree(port);
+err_port:
+ kfree(ops);
+err_ops:
return rc;
}
Daniel K.
^ permalink raw reply
* [PATCH v3 2/2] 82xx, mgcoge: update defconfig for 2.6.32
From: Heiko Schocher @ 2009-08-07 6:41 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, david
In-Reply-To: <40E28EF5-215D-4D69-B44E-CD3145652F9B@kernel.crashing.org>
- add I2C support
- add FCC1 and FCC2 support
Signed-off-by: Heiko Schocher <hs@denx.de>
---
- against git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
next branch
- checked with checkpatch.pl:
$ ./scripts/checkpatch.pl 0001-82xx-mgcoge-update-defconfig-for-2.6.32.patch
total: 0 errors, 0 warnings, 134 lines checked
0001-82xx-mgcoge-update-defconfig-for-2.6.32.patch has no obvious style problems and is ready for submission.
$
- changes since v1
- Add comments from David Gibson
removed 2 "device_type" entries
- Add comment from Kumar Gala
splittet into 2 patches (seperated defconfig patch)
- changes since v2
- based against kumars tree, next branch
arch/powerpc/configs/mgcoge_defconfig | 86 ++++++++++++++++++++++++++++++--
1 files changed, 80 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/configs/mgcoge_defconfig b/arch/powerpc/configs/mgcoge_defconfig
index e9491c1..30b68bf 100644
--- a/arch/powerpc/configs/mgcoge_defconfig
+++ b/arch/powerpc/configs/mgcoge_defconfig
@@ -1,7 +1,7 @@
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc4
-# Wed Jul 29 23:31:51 2009
+# Linux kernel version: 2.6.31-rc5
+# Fri Aug 7 08:19:15 2009
#
# CONFIG_PPC64 is not set
@@ -158,6 +158,7 @@ CONFIG_BASE_SMALL=0
# CONFIG_MODULES is not set
CONFIG_BLOCK=y
CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
# CONFIG_BLK_DEV_INTEGRITY is not set
#
@@ -506,6 +507,7 @@ CONFIG_MTD_PHYSMAP_OF=y
# CONFIG_MTD_UBI is not set
CONFIG_OF_DEVICE=y
CONFIG_OF_GPIO=y
+CONFIG_OF_I2C=y
CONFIG_OF_MDIO=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
@@ -582,7 +584,8 @@ CONFIG_PHYLIB=y
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
CONFIG_FIXED_PHY=y
-# CONFIG_MDIO_BITBANG is not set
+CONFIG_MDIO_BITBANG=y
+# CONFIG_MDIO_GPIO is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_MACE is not set
@@ -608,8 +611,8 @@ CONFIG_MII=y
# CONFIG_ATL2 is not set
CONFIG_FS_ENET=y
CONFIG_FS_ENET_HAS_SCC=y
-# CONFIG_FS_ENET_HAS_FCC is not set
-# CONFIG_FS_ENET_MDIO_FCC is not set
+CONFIG_FS_ENET_HAS_FCC=y
+CONFIG_FS_ENET_MDIO_FCC=y
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
# CONFIG_TR is not set
@@ -680,7 +683,68 @@ CONFIG_HW_RANDOM=y
# CONFIG_APPLICOM is not set
# CONFIG_RAW_DRIVER is not set
CONFIG_DEVPORT=y
-# CONFIG_I2C is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# Mac SMBus host controller drivers
+#
+# CONFIG_I2C_POWERMAC is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_CPM=y
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_MPC is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+
+#
+# Graphics adapter I2C/DDC channel drivers
+#
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_PCF8575 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
# CONFIG_SPI is not set
#
@@ -699,6 +763,9 @@ CONFIG_GPIOLIB=y
#
# I2C GPIO expanders:
#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
#
# PCI GPIO expanders:
@@ -727,7 +794,14 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
--
1.6.0.6
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply related
* Re: [PATCH v2 2/2] 82xx, mgcoge: update defconfig for 2.6.32
From: Heiko Schocher @ 2009-08-07 5:58 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, david
In-Reply-To: <40E28EF5-215D-4D69-B44E-CD3145652F9B@kernel.crashing.org>
Hello Kumar,
Kumar Gala wrote:
> On Aug 3, 2009, at 2:35 AM, Heiko Schocher wrote:
>
>> - add I2C support
>> - add FCC1 and FCC2 support
>>
>> Signed-off-by: Heiko Schocher <hs@denx.de>
>> ---
>> - against git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
>> next branch
>> - checked with checkpatch.pl:
>> $ ./scripts/checkpatch.pl
>> 0002-82xx-mgcoge-update-defconfig-for-2.6.32.patch
>> total: 0 errors, 0 warnings, 381 lines checked
>
> I had problems applying this to my 'next' branch
Ups, Sorry, I based this patchset against:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git
^^^^
I make a patch against your next branch ...
bye
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply
* Re: 2.6.31-rc5-git2 crash [net/core/flow.c:flow_cache_new_hashrnd]
From: Tony Breeds @ 2009-08-07 3:49 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: netdev, David Miller, linuxppc-dev
In-Reply-To: <1249614835.24311.11.camel@pasglop>
On Fri, Aug 07, 2009 at 01:13:54PM +1000, Benjamin Herrenschmidt wrote:
> I think Tony did yes. Not sure what's the status with the "enterprise"
> distros.
It's fixed in F11 and F12 (thanks to dwmw2), it's in my for-1.3.15 branch for
yaboot. We're working on updateing the version in the enterprise, we'll see
what the next release holds.
Yours Tony
^ permalink raw reply
* Re: 2.6.31-rc5-git2 crash [net/core/flow.c:flow_cache_new_hashrnd]
From: Benjamin Herrenschmidt @ 2009-08-07 3:13 UTC (permalink / raw)
To: Josh Boyer; +Cc: netdev, David Miller, linuxppc-dev
In-Reply-To: <20090807025454.GL3095@hansolo.jdub.homelinux.org>
On Thu, 2009-08-06 at 22:54 -0400, Josh Boyer wrote:
> On Fri, Aug 07, 2009 at 08:23:05AM +1000, Benjamin Herrenschmidt wrote:
> >On Wed, 2009-08-05 at 00:15 +1000, Michael Ellerman wrote:
> >
> >> > c000000000600000 00001010 .long 0x1010
> >> > 0:mon>
> >> > c000000000600004 00000008 .long 0x8
> >> > c000000000600008 00001013 .long 0x1013
> >> > c00000000060000c 0000000f .long 0xf
> >> > c000000000600010 7961626f rldimi. r1,r11,44,41
> >> > c000000000600014 6f740000 xoris r20,r27,0
> >> > c000000000600018 00101600 .long 0x101600
> >> > c00000000060001c 00000c00 .long 0xc00
> >> > c000000000600020 00000400 .long 0x400
> >> > c000000000600024 00101100 .long 0x101100
> >> > c000000000600028 000008e9 .long 0x8e9
> >
> >BTW. Corruption looks like bi_recs... ie, broken yaboot. This was fixed
> >recently, yaboot would eventually crap over the kernel for certain sizes
> >of the kernel image.
> >
> >0x1010 = BI_FIRST
> >0x1013 = BI_BOOTLOADER_ID followed by 0x7961626f6f74 which is
> >"yaboot" :-)
> >0x1016 = BI_MACHTYPE
>
> I know we fixed it in Fedora for F11/F12. Did it get fixed upstream?
I think Tony did yes. Not sure what's the status with the "enterprise"
distros.
Cheers,
Ben.
^ permalink raw reply
* Please pull from 'next' branch
From: Kumar Gala @ 2009-08-07 3:09 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: linuxppc-dev
Please pull from 'next' branch of
master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc.git next
to receive the following updates:
arch/powerpc/boot/dts/gef_sbc310.dts | 64 +++-
arch/powerpc/boot/dts/mgcoge.dts | 53 +++
arch/powerpc/boot/dts/mpc8377_rdb.dts | 2
arch/powerpc/boot/dts/mpc8377_wlan.dts | 464 +++++++++++++++++++++++++++++
arch/powerpc/boot/dts/mpc8378_rdb.dts | 2
arch/powerpc/boot/dts/mpc8379_rdb.dts | 2
arch/powerpc/boot/dts/mpc8536ds.dts | 32 +-
arch/powerpc/boot/dts/mpc8536ds_36b.dts | 467 ++++++++++++++++++++++++++++++
arch/powerpc/boot/dts/mpc8548cds.dts | 20 +
arch/powerpc/mm/fsl_booke_mmu.c | 2
arch/powerpc/platforms/82xx/mgcoge.c | 69 +++-
arch/powerpc/platforms/83xx/Kconfig | 4
arch/powerpc/platforms/83xx/mpc837x_rdb.c | 28 +
arch/powerpc/platforms/83xx/mpc83xx.h | 4
arch/powerpc/platforms/86xx/gef_ppc9a.c | 37 +-
arch/powerpc/sysdev/fsl_rio.c | 18 -
arch/powerpc/sysdev/ipic.c | 7
arch/powerpc/sysdev/qe_lib/qe_ic.c | 5
18 files changed, 1219 insertions(+), 61 deletions(-)
Anton Vorontsov (3):
powerpc/83xx: Add support for MPC8377E-WLAN boards
powerpc/85xx: Add support for I2C EEPROMs on MPC8548CDS boards
powerpc/83xx: Add eSDHC support for MPC837xE-RDB/WLAN boards
Heiko Schocher (1):
powerpc/82xx: mgcoge - updates for 2.6.32
Julia Lawall (3):
powerpc/fsl_rio: Add kmalloc NULL tests
powerpc/ipic: introduce missing kfree
powerpc/qe: introduce missing kfree
Kumar Gala (2):
powerpc/85xx: Move mpc8536ds.dts to address-cells/size-cells = <2>
powerpc/85xx: Added 36-bit physical device tree for mpc8572ds board
Martyn Welch (3):
powerpc/86xx: Correct reading of information presented in cpuinfo
powerpc/86xx: Enable XMC site on GE Fanuc SBC310
powerpc/86xx: Update GE Fanuc sbc310 DTS
Roel Kluin (1):
powerpc/fsl-booke: read buffer overflow
Sebastian Andrzej Siewior (1):
powerpc/ipic: unmask all interrupt sources
^ permalink raw reply
* Re: 2.6.31-rc5-git2 crash [net/core/flow.c:flow_cache_new_hashrnd]
From: Josh Boyer @ 2009-08-07 2:54 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: netdev, David Miller, linuxppc-dev
In-Reply-To: <1249597385.24311.10.camel@pasglop>
On Fri, Aug 07, 2009 at 08:23:05AM +1000, Benjamin Herrenschmidt wrote:
>On Wed, 2009-08-05 at 00:15 +1000, Michael Ellerman wrote:
>
>> > c000000000600000 00001010 .long 0x1010
>> > 0:mon>
>> > c000000000600004 00000008 .long 0x8
>> > c000000000600008 00001013 .long 0x1013
>> > c00000000060000c 0000000f .long 0xf
>> > c000000000600010 7961626f rldimi. r1,r11,44,41
>> > c000000000600014 6f740000 xoris r20,r27,0
>> > c000000000600018 00101600 .long 0x101600
>> > c00000000060001c 00000c00 .long 0xc00
>> > c000000000600020 00000400 .long 0x400
>> > c000000000600024 00101100 .long 0x101100
>> > c000000000600028 000008e9 .long 0x8e9
>
>BTW. Corruption looks like bi_recs... ie, broken yaboot. This was fixed
>recently, yaboot would eventually crap over the kernel for certain sizes
>of the kernel image.
>
>0x1010 = BI_FIRST
>0x1013 = BI_BOOTLOADER_ID followed by 0x7961626f6f74 which is
>"yaboot" :-)
>0x1016 = BI_MACHTYPE
I know we fixed it in Fedora for F11/F12. Did it get fixed upstream?
josh
^ permalink raw reply
* Re: [PATCH v2] powerpc/86xx: Update GE Fanuc sbc310 DTS
From: Kumar Gala @ 2009-08-07 2:45 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev, Martyn Welch
In-Reply-To: <B8CD6A65-59B6-402E-97DC-8A29929585A2@kernel.crashing.org>
On Aug 6, 2009, at 9:38 PM, Kumar Gala wrote:
>
> On Jul 30, 2009, at 3:13 AM, Martyn Welch wrote:
>
>> Update GE Fanuc DTS to match the alterations suggested during the
>> merge of
>> the ppc9a DTS in commit 740d36ae6344f38c4da64c2ede765d7d2dd1f132
>>
>> Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com>
>> ---
>>
>> v2: Fixed run on message.
>>
>> Kumar: I think the problem may be that this patch depends on a
>> previous patch:
>>
>> http://patchwork.ozlabs.org/patch/29335/
>>
>> Martyn
>>
>> arch/powerpc/boot/dts/gef_sbc310.dts | 29 ++++++++++++
>> +----------------
>> 1 files changed, 13 insertions(+), 16 deletions(-)
>
> applied to next
>
> For some reason in my tree the extra line at the end had already
> been removed.
Ignore this, I see what you meant by the earlier patch...
- k
^ permalink raw reply
* Re: [PATCH] powerpc/86xx: Enable XMC site on GE Fanuc SBC310
From: Kumar Gala @ 2009-08-07 2:44 UTC (permalink / raw)
To: Martyn Welch; +Cc: linuxppc-dev
In-Reply-To: <20090630143238.10798.9863.stgit@ES-J7S4D2J.amer.consind.ge.com>
On Jun 30, 2009, at 9:32 AM, Martyn Welch wrote:
> This patch enables the XMC (PCIe daughter card) site on the SBC310.
> STG enter the description for the patch above.
>
> Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com>
> ---
>
> arch/powerpc/boot/dts/gef_sbc310.dts | 37 +++++++++++++++++++++++++
> +++++++++
> 1 files changed, 37 insertions(+), 0 deletions(-)
applied to next.
- k
^ permalink raw reply
* Re: [PATCH] powerpc/86xx: Correct reading of information presented in cpuinfo
From: Kumar Gala @ 2009-08-07 2:44 UTC (permalink / raw)
To: Martyn Welch; +Cc: linuxppc-dev
In-Reply-To: <20090630143226.10778.29002.stgit@ES-J7S4D2J.amer.consind.ge.com>
On Jun 30, 2009, at 9:32 AM, Martyn Welch wrote:
> /proc/cpuinfo should be showing the boards revision and the revision
> of the FPGA fitted. The functions currently used to access this
> information as incorrect.
>
> Additionally the VME geographical address of the PPC9A and it's
> status as system contoller are available in the board registers.
> Show these in cpuinfo.
>
> Signed-off-by: Martyn Welch <martyn.welch@gefanuc.com>
> ---
>
> arch/powerpc/platforms/86xx/gef_ppc9a.c | 37 ++++++++++++++++++++++
> +++------
> 1 files changed, 30 insertions(+), 7 deletions(-)
applied to next.
(Fixed the comment formatting to wrap properly)
- k
^ permalink raw reply
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