* Re: [PATCH 3/4] sdhci-of: Fix high-speed cards recognition
From: Anton Vorontsov @ 2009-08-07 18:43 UTC (permalink / raw)
To: David Vrabel
Cc: Ben Dooks, sdhci-devel, linux-kernel, linuxppc-dev, Andrew Morton,
Pierre Ossman
In-Reply-To: <4A7C5FAB.2020304@csr.com>
On Fri, Aug 07, 2009 at 06:08:59PM +0100, David Vrabel wrote:
> Anton Vorontsov wrote:
> > eSDHC fails to recognize some SDHS cards, throwing timeout errors:
> >
> > mmc0: error -110 whilst initialising SD card
> >
> > That's because we calculate timeout value in a wrong way: on eSDHC
> > hosts the timeout clock is derivied from the SD clock, which is set
> > dynamically.
>
> I've seen an reference design for an SDHC controller do this also.
Thanks for the information!
> > +/* Controller has dynamic timeout clock management */
> > +#define SDHCI_QUIRK_DYNAMIC_TIMEOUT_CLOCK (1<<24)
>
> This comment and define would be better if it matched terms used in the
> spec. Suggest:
>
> /* Controller uses SDCLK instead of TMCLK for data timeouts. */
> #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 24)
Yeah, if it's somewhat common scheme, then it makes sense to name the
quirk that way.
Thanks,
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply
* [PATCH] Use clock freqency from the device tree to calculate correct MPC5200 PSC clock.
From: Jon Smirl @ 2009-08-07 18:41 UTC (permalink / raw)
To: grant.likely, Linuxppc-dev
Use clock freqency from the device tree to calculate correct MPC5200 PSC clock.
Previous code had errors or used a constant. This versions computes
the right clock based on the xtal and register settings.
---
arch/powerpc/include/asm/mpc52xx.h | 2 +-
arch/powerpc/platforms/52xx/mpc52xx_common.c | 26 ++++++++++++++++++++++++--
drivers/spi/mpc52xx_psc_spi.c | 8 +-------
sound/soc/fsl/mpc5200_psc_i2s.c | 11 +----------
4 files changed, 27 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/include/asm/mpc52xx.h b/arch/powerpc/include/asm/mpc52xx.h
index cadd398..1ca8a0e 100644
--- a/arch/powerpc/include/asm/mpc52xx.h
+++ b/arch/powerpc/include/asm/mpc52xx.h
@@ -285,7 +285,7 @@ struct mpc52xx_rtc {
extern void mpc5200_setup_xlb_arbiter(void);
extern void mpc52xx_declare_of_platform_devices(void);
extern void mpc52xx_map_common_devices(void);
-extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
+extern int mpc52xx_set_psc_clkdiv(int psc_id, int freq);
extern unsigned int mpc52xx_get_xtal_freq(struct device_node *node);
extern void mpc52xx_restart(char *cmd);
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_common.c b/arch/powerpc/platforms/52xx/mpc52xx_common.c
index a46bad0..f81fb03 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_common.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_common.c
@@ -110,6 +110,8 @@ static struct of_device_id mpc52xx_cdm_ids[] __initdata = {
{}
};
+static u32 fsystem; /* fsystem clock on mpc5200 */
+
/**
* mpc52xx_map_common_devices: iomap devices required by common code
*/
@@ -117,6 +119,7 @@ void __init
mpc52xx_map_common_devices(void)
{
struct device_node *np;
+ u32 val;
/* mpc52xx_wdt is mapped here and used in mpc52xx_restart,
* possibly from a interrupt context. wdt is only implement
@@ -133,8 +136,16 @@ mpc52xx_map_common_devices(void)
/* Clock Distribution Module, used by PSC clock setting function */
np = of_find_matching_node(NULL, mpc52xx_cdm_ids);
+ fsystem = mpc5xxx_get_bus_frequency(np);
mpc52xx_cdm = of_iomap(np, 0);
of_node_put(np);
+
+ /* compute fsystem, it is either 4 or 8 times the bus freq */
+ val = in_be32(&mpc52xx_cdm->rstcfg);
+ if (val & (1 << 5))
+ fsystem *= 8;
+ else
+ fsystem *= 4;
}
/**
@@ -143,17 +154,28 @@ mpc52xx_map_common_devices(void)
* @psc_id: id of psc port; must be 1,2,3 or 6
* @clkdiv: clock divider value to put into CDM PSC register.
*/
-int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv)
+int mpc52xx_set_psc_clkdiv(int psc_id, int freq)
{
unsigned long flags;
u16 __iomem *reg;
u32 val;
- u32 mask;
+ u32 mask, clkdiv, err;
u32 mclken_div;
if (!mpc52xx_cdm)
return -ENODEV;
+ /* figure out the closest frequency the hardware can make */
+ clkdiv = fsystem / freq;
+ err = fsystem % freq;
+ if (err > freq / 2)
+ clkdiv++;
+ /* hardware is not very flexible, there will be significant error */
+ /* frequency error = fsystem / clkdiv - freq; */
+
+ /* hardware adds one to the divisor */
+ clkdiv -= 1;
+
mclken_div = 0x8000 | (clkdiv & 0x1FF);
switch (psc_id) {
case 1: reg = &mpc52xx_cdm->mclken_div_psc1; mask = 0x20; break;
diff --git a/drivers/spi/mpc52xx_psc_spi.c b/drivers/spi/mpc52xx_psc_spi.c
index d2a04d6..5c8e621 100644
--- a/drivers/spi/mpc52xx_psc_spi.c
+++ b/drivers/spi/mpc52xx_psc_spi.c
@@ -33,7 +33,6 @@
struct mpc52xx_psc_spi {
/* fsl_spi_platform data */
void (*cs_control)(struct spi_device *spi, bool on);
- u32 sysclk;
/* driver internal data */
struct mpc52xx_psc __iomem *psc;
@@ -313,12 +312,9 @@ static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
{
struct mpc52xx_psc __iomem *psc = mps->psc;
struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
- u32 mclken_div;
int ret = 0;
- /* default sysclk is 512MHz */
- mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
- mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
+ mpc52xx_set_psc_clkdiv(psc_id, MCLK);
/* Reset the PSC into a known state */
out_8(&psc->command, MPC52xx_PSC_RST_RX);
@@ -383,12 +379,10 @@ static int __init mpc52xx_psc_spi_do_probe(struct of_device *op, u32 regaddr,
dev_warn(&op->dev, "probe called without platform data, no "
"cs_control function will be called\n");
mps->cs_control = NULL;
- mps->sysclk = 0;
master->bus_num = bus_num;
master->num_chipselect = 255;
} else {
mps->cs_control = pdata->cs_control;
- mps->sysclk = pdata->sysclk;
master->bus_num = pdata->bus_num;
master->num_chipselect = pdata->max_chipselect;
}
diff --git a/sound/soc/fsl/mpc5200_psc_i2s.c b/sound/soc/fsl/mpc5200_psc_i2s.c
index c58fcde..8de4719 100644
--- a/sound/soc/fsl/mpc5200_psc_i2s.c
+++ b/sound/soc/fsl/mpc5200_psc_i2s.c
@@ -115,7 +115,6 @@ static int psc_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int dir)
{
struct psc_dma *psc_dma = cpu_dai->private_data;
- int clkdiv, err;
dev_dbg(psc_dma->dev, "psc_i2s_set_sysclk(cpu_dai=%p, freq=%u, dir=%i)\n",
cpu_dai, freq, dir);
@@ -128,15 +127,7 @@ static int psc_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
psc_dma->sicr &= ~MPC52xx_PSC_SICR_CELLSLAVE;
psc_dma->sicr |= MPC52xx_PSC_SICR_GENCLK;
- clkdiv = ppc_proc_freq / freq;
- err = ppc_proc_freq % freq;
- if (err > freq / 2)
- clkdiv++;
-
- dev_dbg(psc_dma->dev, "psc_i2s_set_sysclk(clkdiv %d freq error=%ldHz)\n",
- clkdiv, (ppc_proc_freq / clkdiv - freq));
-
- return mpc52xx_set_psc_clkdiv(psc_dma->id + 1, clkdiv);
+ return mpc52xx_set_psc_clkdiv(psc_dma->id + 1, freq);
}
}
return 0;
^ permalink raw reply related
* Re: [PATCH 0/4] sdhci-of: Some fixes for high-speed and 4-bit SD cards
From: Anton Vorontsov @ 2009-08-07 18:41 UTC (permalink / raw)
To: Andrew Morton
Cc: linuxppc-dev, Ben Dooks, Pierre Ossman, linux-kernel, sdhci-devel
In-Reply-To: <20090807163940.GA29192@oksana.dev.rtsoft.ru>
On Fri, Aug 07, 2009 at 08:39:40PM +0400, Anton Vorontsov wrote:
> Hi all,
>
> Finally I've got a bunch of SD cards to test eSDHC in various ways,
> and more importantly now I have a lot of SDHS cards. ;-)
>
> So, here are few fixes that make eSDHC work flawlessly on MPC83xx
> SOCs with all SD and MMC cards that I have.
>
> On MPC85xx (namely MPC8536 and MPC8569) SOCs there is one issue:
> the cards can be detected and read just fine, but writing doesn't
> work (no interrupts received). I'm currently investigating this.
Solved. It appears that eSDHC on MPC85xx has a normal write-protect
reporting. And eSDHC actually checks the WP pin, thus doesn't let
anybody to do any writes... I'll make some additional patches and
will send v2 soon.
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply
* Re: PSC clock divider
From: Grant Likely @ 2009-08-07 18:29 UTC (permalink / raw)
To: Jon Smirl; +Cc: linuxppc-dev
In-Reply-To: <9e4733910908070934se43b2a9lfe72e89e0e247ea3@mail.gmail.com>
On Fri, Aug 7, 2009 at 10:34 AM, Jon Smirl<jonsmirl@gmail.com> wrote:
> On Fri, Aug 7, 2009 at 12:15 PM, Grant Likely<grant.likely@secretlab.ca> wrote:
>>> Should I modify mpc52xx_set_psc_clkdiv() to take in a frequency and
>>> them move this code into mpc52xx_common.c? That allows the sysclk
>>> parameter to be eliminated for SPI.
>>
>> Yes, please do.
>
> Can mpc5xxx_clocks.c be eliminated and this function:
>
> mpc5xxx_get_bus_frequency(struct device_node *node)
>
> be moved into mpc52cc_common.c?
No. mpc5xxx_get_bus_frequency is not mpc5200 specific. It is used by
mpc5121 also.
g.
--
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* Re: [PATCH 3/4] sdhci-of: Fix high-speed cards recognition
From: David Vrabel @ 2009-08-07 17:08 UTC (permalink / raw)
To: Anton Vorontsov
Cc: Ben Dooks, sdhci-devel, linux-kernel, linuxppc-dev, Andrew Morton,
Pierre Ossman
In-Reply-To: <20090807165015.GB524@oksana.dev.rtsoft.ru>
Anton Vorontsov wrote:
> eSDHC fails to recognize some SDHS cards, throwing timeout errors:
>
> mmc0: error -110 whilst initialising SD card
>
> That's because we calculate timeout value in a wrong way: on eSDHC
> hosts the timeout clock is derivied from the SD clock, which is set
> dynamically.
I've seen an reference design for an SDHC controller do this also.
> +/* Controller has dynamic timeout clock management */
> +#define SDHCI_QUIRK_DYNAMIC_TIMEOUT_CLOCK (1<<24)
This comment and define would be better if it matched terms used in the
spec. Suggest:
/* Controller uses SDCLK instead of TMCLK for data timeouts. */
#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 24)
David
--
David Vrabel, Senior Software Engineer, Drivers
CSR, Churchill House, Cambridge Business Park, Tel: +44 (0)1223 692562
Cowley Road, Cambridge, CB4 0WZ http://www.csr.com/
'member of the CSR plc group of companies. CSR plc registered in England and Wales, registered number 4187346, registered office Churchill House, Cambridge Business Park, Cowley Road, Cambridge, CB4 0WZ, United Kingdom'
^ permalink raw reply
* [PATCH 4/4] sdhci-of: Cleanup eSDHC's set_clock() a little bit
From: Anton Vorontsov @ 2009-08-07 16:50 UTC (permalink / raw)
To: Andrew Morton
Cc: Ben Dooks, linux-kernel, sdhci-devel, linuxppc-dev, Pierre Ossman
In-Reply-To: <20090807163940.GA29192@oksana.dev.rtsoft.ru>
- Get rid of incomprehensible "if { for { if } }" construction for the
exponential divisor calculation. The first if statement isn't correct
at all, since it should check for "host->max_clk / pre_div / 16 >
clock". The error doesn't cause any bugs because the check in the for
loop does the right thing, and so the outer check becomes useless;
- For the linear divisor do the same: a single while statement is more
readable than for + if construction;
- Add dev_dbg() that prints desired and actual clock frequency.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
drivers/mmc/host/sdhci-of.c | 19 ++++++++-----------
1 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of.c
index b6ff2e8..bbdd468 100644
--- a/drivers/mmc/host/sdhci-of.c
+++ b/drivers/mmc/host/sdhci-of.c
@@ -120,8 +120,8 @@ static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
{
- int div;
int pre_div = 2;
+ int div = 1;
clrbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
@@ -129,17 +129,14 @@ static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
if (clock == 0)
goto out;
- if (host->max_clk / 16 > clock) {
- for (; pre_div < 256; pre_div *= 2) {
- if (host->max_clk / pre_div < clock * 16)
- break;
- }
- }
+ while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
+ pre_div *= 2;
- for (div = 1; div <= 16; div++) {
- if (host->max_clk / (div * pre_div) <= clock)
- break;
- }
+ while (host->max_clk / pre_div / div > clock && div < 16)
+ div++;
+
+ dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
+ clock, host->max_clk / pre_div / div);
pre_div >>= 1;
div--;
--
1.6.3.3
^ permalink raw reply related
* [PATCH 3/4] sdhci-of: Fix high-speed cards recognition
From: Anton Vorontsov @ 2009-08-07 16:50 UTC (permalink / raw)
To: Andrew Morton
Cc: Ben Dooks, linux-kernel, sdhci-devel, linuxppc-dev, Pierre Ossman
In-Reply-To: <20090807163940.GA29192@oksana.dev.rtsoft.ru>
eSDHC fails to recognize some SDHS cards, throwing timeout errors:
mmc0: error -110 whilst initialising SD card
That's because we calculate timeout value in a wrong way: on eSDHC
hosts the timeout clock is derivied from the SD clock, which is set
dynamically.
This patch fixes the issue by introducing and implementing
DYNAMIC_TIMEOUT_CLOCK quirk for sdhci-of driver.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
drivers/mmc/host/sdhci-of.c | 5 ++---
drivers/mmc/host/sdhci.c | 4 ++++
drivers/mmc/host/sdhci.h | 2 ++
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of.c
index 8440fd9..b6ff2e8 100644
--- a/drivers/mmc/host/sdhci-of.c
+++ b/drivers/mmc/host/sdhci-of.c
@@ -174,9 +174,7 @@ static unsigned int esdhc_get_min_clock(struct sdhci_host *host)
static unsigned int esdhc_get_timeout_clock(struct sdhci_host *host)
{
- struct sdhci_of_host *of_host = sdhci_priv(host);
-
- return of_host->clock / 1000;
+ return host->clock / 1000;
}
static struct sdhci_of_data sdhci_esdhc = {
@@ -185,6 +183,7 @@ static struct sdhci_of_data sdhci_esdhc = {
SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
SDHCI_QUIRK_NO_BUSY_IRQ |
SDHCI_QUIRK_NONSTANDARD_CLOCK |
+ SDHCI_QUIRK_DYNAMIC_TIMEOUT_CLOCK |
SDHCI_QUIRK_PIO_NEEDS_DELAY |
SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET |
SDHCI_QUIRK_NO_CARD_NO_RESET,
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index fc96f8c..0f273fe 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -591,6 +591,10 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
target_timeout = data->timeout_ns / 1000 +
data->timeout_clks / host->clock;
+ if (host->quirks & SDHCI_QUIRK_DYNAMIC_TIMEOUT_CLOCK &&
+ host->ops->get_timeout_clock)
+ host->timeout_clk = host->ops->get_timeout_clock(host);
+
/*
* Figure out needed cycles.
* We do this in steps in order to fit inside a 32 bit int.
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c77e9ff..44b1dcc 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -232,6 +232,8 @@ struct sdhci_host {
#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
/* Controller needs 10ms delay between applying power and clock */
#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
+/* Controller has dynamic timeout clock management */
+#define SDHCI_QUIRK_DYNAMIC_TIMEOUT_CLOCK (1<<24)
int irq; /* Device IRQ */
void __iomem * ioaddr; /* Mapped address */
--
1.6.3.3
^ permalink raw reply related
* [PATCH 2/4] sdhci-of: Avoid writing reserved bits into host control register
From: Anton Vorontsov @ 2009-08-07 16:49 UTC (permalink / raw)
To: Andrew Morton
Cc: Ben Dooks, linux-kernel, sdhci-devel, linuxppc-dev, Pierre Ossman
In-Reply-To: <20090807163940.GA29192@oksana.dev.rtsoft.ru>
SDHCI core tries to write HISPD bit into the host control register,
but the eSDHC controllers don't have that bit, and that causes
all sorts of misbehaviour when using 4-bit mode capable SD cards.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
drivers/mmc/host/sdhci-of.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of.c
index 92b5667..8440fd9 100644
--- a/drivers/mmc/host/sdhci-of.c
+++ b/drivers/mmc/host/sdhci-of.c
@@ -48,6 +48,8 @@ struct sdhci_of_host {
#define ESDHC_CLOCK_HCKEN 0x00000002
#define ESDHC_CLOCK_IPGEN 0x00000001
+#define ESDHC_HOST_CONTROL_RES 0x05
+
static u32 esdhc_readl(struct sdhci_host *host, int reg)
{
return in_be32(host->ioaddr + reg);
@@ -109,6 +111,10 @@ static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
int base = reg & ~0x3;
int shift = (reg & 0x3) * 8;
+ /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
+ if (reg == SDHCI_HOST_CONTROL)
+ val &= ~ESDHC_HOST_CONTROL_RES;
+
clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
}
--
1.6.3.3
^ permalink raw reply related
* [PATCH 1/4] sdhci-of: Fix SD clock calculation
From: Anton Vorontsov @ 2009-08-07 16:40 UTC (permalink / raw)
To: Andrew Morton
Cc: Ben Dooks, linux-kernel, sdhci-devel, linuxppc-dev, Pierre Ossman
In-Reply-To: <20090807163940.GA29192@oksana.dev.rtsoft.ru>
Linear divisor's values in a register start at 0 (zero means
"divide by 1"). Before this patch the code didn't account that
fact, so SD cards were running underclocked.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
drivers/mmc/host/sdhci-of.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of.c b/drivers/mmc/host/sdhci-of.c
index 9088443..92b5667 100644
--- a/drivers/mmc/host/sdhci-of.c
+++ b/drivers/mmc/host/sdhci-of.c
@@ -136,6 +136,7 @@ static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
}
pre_div >>= 1;
+ div--;
setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
--
1.6.3.3
^ permalink raw reply related
* Re: PSC clock divider
From: Jon Smirl @ 2009-08-07 16:34 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev
In-Reply-To: <fa686aa40908070915x7e04cbb8ofccd106230d5f76c@mail.gmail.com>
On Fri, Aug 7, 2009 at 12:15 PM, Grant Likely<grant.likely@secretlab.ca> wrote:
>> Should I modify mpc52xx_set_psc_clkdiv() to take in a frequency and
>> them move this code into mpc52xx_common.c? That allows the sysclk
>> parameter to be eliminated for SPI.
>
> Yes, please do.
Can mpc5xxx_clocks.c be eliminated and this function:
mpc5xxx_get_bus_frequency(struct device_node *node)
be moved into mpc52cc_common.c?
--
Jon Smirl
jonsmirl@gmail.com
^ permalink raw reply
* [PATCH 0/4] sdhci-of: Some fixes for high-speed and 4-bit SD cards
From: Anton Vorontsov @ 2009-08-07 16:39 UTC (permalink / raw)
To: Andrew Morton
Cc: Ben Dooks, linux-kernel, sdhci-devel, linuxppc-dev, Pierre Ossman
Hi all,
Finally I've got a bunch of SD cards to test eSDHC in various ways,
and more importantly now I have a lot of SDHS cards. ;-)
So, here are few fixes that make eSDHC work flawlessly on MPC83xx
SOCs with all SD and MMC cards that I have.
On MPC85xx (namely MPC8536 and MPC8569) SOCs there is one issue:
the cards can be detected and read just fine, but writing doesn't
work (no interrupts received). I'm currently investigating this.
Thanks,
--
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2
^ permalink raw reply
* Re: PSC clock divider
From: Grant Likely @ 2009-08-07 16:15 UTC (permalink / raw)
To: Jon Smirl; +Cc: linuxppc-dev
In-Reply-To: <9e4733910908070903p539b8987p8351df5b3d328fdd@mail.gmail.com>
On Fri, Aug 7, 2009 at 10:03 AM, Jon Smirl<jonsmirl@gmail.com> wrote:
> mpc52xx_set_psc_clkdiv() has problems. It take the clk divider as a
> parameter. But this divisor is not always gettting calculated
> correctly. My code in i2s was doing it wrong.
>
> Take this snippet from the SPI driver, it just assumes a fsystem of
> 512Mhz. fsystem is 533Mhz on my boards.
>
> =A0 =A0 =A0 =A0/* default sysclk is 512MHz */
> =A0 =A0 =A0 =A0mclken_div =3D (mps->sysclk ? mps->sysclk : 512000000) / M=
CLK;
> =A0 =A0 =A0 =A0mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
>
> Is it also not accounting for the hardware adding one to the divisor.
>
> I've change i2s to this:
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (!fsystem) {
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0np =3D of_=
find_matching_node(NULL, mpc52xx_cdm_ids);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0mpc52xx_cd=
m =3D of_iomap(np, 0);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0fsystem =
=3D mpc5xxx_get_bus_frequency(np);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0of_node_pu=
t(np);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0val =3D in=
_be32(&mpc52xx_cdm->rstcfg);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (val & =
(1 << 5))
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0fsystem *=3D 8;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0else
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0fsystem *=3D 4;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0iounmap(mp=
c52xx_cdm);
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0}
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0clkdiv =3D fsystem / freq;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0err =3D fsystem % freq;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0if (err > freq / 2)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0clkdiv++;
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0dev_dbg(psc_dma->dev, "psc=
_i2s_set_sysclk(clkdiv %d freq error=3D%dHz)\n",
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0clkdiv, (fsystem / clkdiv - freq));
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* PSC is 1-6 */
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Hardware adds 1 to divi=
sor */
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0return mpc52xx_set_psc_clk=
div(psc_dma->id + 1, clkdiv - 1);
>
>
> Should I modify mpc52xx_set_psc_clkdiv() to take in a frequency and
> them move this code into mpc52xx_common.c? That allows the sysclk
> parameter to be eliminated for SPI.
Yes, please do.
g.
--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply
* PSC clock divider
From: Jon Smirl @ 2009-08-07 16:03 UTC (permalink / raw)
To: linuxppc-dev, Grant Likely
mpc52xx_set_psc_clkdiv() has problems. It take the clk divider as a
parameter. But this divisor is not always gettting calculated
correctly. My code in i2s was doing it wrong.
Take this snippet from the SPI driver, it just assumes a fsystem of
512Mhz. fsystem is 533Mhz on my boards.
/* default sysclk is 512MHz */
mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
Is it also not accounting for the hardware adding one to the divisor.
I've change i2s to this:
if (!fsystem) {
np = of_find_matching_node(NULL, mpc52xx_cdm_ids);
mpc52xx_cdm = of_iomap(np, 0);
fsystem = mpc5xxx_get_bus_frequency(np);
of_node_put(np);
val = in_be32(&mpc52xx_cdm->rstcfg);
if (val & (1 << 5))
fsystem *= 8;
else
fsystem *= 4;
iounmap(mpc52xx_cdm);
}
clkdiv = fsystem / freq;
err = fsystem % freq;
if (err > freq / 2)
clkdiv++;
dev_dbg(psc_dma->dev, "psc_i2s_set_sysclk(clkdiv %d freq error=%dHz)\n",
clkdiv, (fsystem / clkdiv - freq));
/* PSC is 1-6 */
/* Hardware adds 1 to divisor */
return mpc52xx_set_psc_clkdiv(psc_dma->id + 1, clkdiv - 1);
Should I modify mpc52xx_set_psc_clkdiv() to take in a frequency and
them move this code into mpc52xx_common.c? That allows the sysclk
parameter to be eliminated for SPI.
--
Jon Smirl
jonsmirl@gmail.com
^ permalink raw reply
* Re: sequoia: The final kernel image would overwrite the device tree
From: Geert Uytterhoeven @ 2009-08-07 15:48 UTC (permalink / raw)
To: Benjamin Herrenschmidt; +Cc: Linux/PPC Development
In-Reply-To: <alpine.LRH.2.00.0907281524510.29006@vixen.sonytel.be>
On Tue, 28 Jul 2009, Geert Uytterhoeven wrote:
> Current kernel (2.6.31-rc4) fails to boot on sequoia:
>
> | ## Booting image at 00100000 ...
> | Image Name: Linux-2.6.31-rc4-00003-g52c6890-
> | Image Type: PowerPC Linux Kernel Image (gzip compressed)
> | Data Size: 1680490 Bytes = 1.6 MB
> | Load Address: 00400000
> | Entry Point: 00400458
> | Verifying Checksum ... OK
> | Uncompressing Kernel Image ... OK
> | CPU clock-frequency <- 0x27bc86a4 (667MHz)
> | CPU timebase-frequency <- 0x27bc86a4 (667MHz)
> | /plb: clock-frequency <- 9ef21a9 (167MHz)
> | /plb/opb: clock-frequency <- 4f790d4 (83MHz)
> | /plb/opb/ebc: clock-frequency <- 34fb5e3 (56MHz)
> | /plb/opb/serial@ef600300: clock-frequency <- a8c000 (11MHz)
> | /plb/opb/serial@ef600400: clock-frequency <- a8c000 (11MHz)
> | /plb/opb/serial@ef600500: clock-frequency <- 42ecac (4MHz)
> | /plb/opb/serial@ef600600: clock-frequency <- 42ecac (4MHz)
> | Memory <- <0x0 0x0 0xffff000> (255MB)
> | ethernet0: local-mac-address <- 00:10:ec:00:f1:df
> | ethernet1: local-mac-address <- 00:10:ec:80:f1:df
> |
> | zImage starting: loaded at 0x00400000 (sp: 0x0ff2ba18)
> | Allocating 0x85e77c bytes for kernel ...
> | The final kernel image would overwrite the device tree?
>
> Git bisect told me the bad guy is:
>
> | commit 5d38902c483881645ba16058cffaa478b81e5cfa
> | Author: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> | Date: Wed Jun 17 17:43:59 2009 +0000
> |
> | powerpc: Add irqtrace support for 32-bit powerpc
>
> However, disabling CONFIG_PROVE_LOCKING also fixes the problem.
I did some more investigations.
If CONFIG_PROVE_LOCKING is not set:
| zImage starting: loaded at 0x00400000 (sp: 0x0ff2b670)
| Allocating 0x74a764 bytes for kernel ...
| platform_ops.vmlinux_alloc = 0x00000000
| _end = 0x78e000
| gunzipping (0x00000000 <- 0x0040e000:0x00781b34)...done 0x360460 bytes
and the rest of the kernel boots (note: it hangs later on with "BUG: spinlock
lockup on CPU#0, swapper/1, cf8b6908" with today's kernel, will look into
that later).
However, nm says _end = c074b000?
If CONFIG_PROVE_LOCKING=y:
| zImage starting: loaded at 0x00400000 (sp: 0x0ff2ba18)
| Allocating 0x85e784 bytes for kernel ...
| platform_ops.vmlinux_alloc = 0x00000000
| _end = 0x792000
| The final kernel image would overwrite the device tree?
and it reboots.
However, nm says _end = c085f000.
So in both cases _end is not correct in arch/powerpc/boot/main.c:prep_kernel()?
But depending on CONFIG_PROVE_LOCKING, the test for
((unsigned long)_end < ei.memsize) gives different results, and the kernel
boots or doesn't boot?
With kind regards,
Geert Uytterhoeven
Software Architect
Techsoft Centre
Technology and Software Centre Europe
The Corporate Village · Da Vincilaan 7-D1 · B-1935 Zaventem · Belgium
Phone: +32 (0)2 700 8453
Fax: +32 (0)2 700 8622
E-mail: Geert.Uytterhoeven@sonycom.com
Internet: http://www.sony-europe.com/
A division of Sony Europe (Belgium) N.V.
VAT BE 0413.825.160 · RPR Brussels
Fortis · BIC GEBABEBB · IBAN BE41293037680010
^ permalink raw reply
* [v3][PATCH][powerpc/85xx] P2020RDB Platform Support Added
From: Poonam Aggrwal @ 2009-08-07 15:35 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Poonam Aggrwal
Adds P2020RDB basic support in linux.
Overview of P2020RDB platform
- DDR
DDR2 1G
- NOR Flash
16MByte
- NAND Flash
32MByte
- 3 Ethernet interfaces
1) etSEC1
- RGMII
- connected to a 5 port Vitesse Switch(VSC7385)
- Switch is memory mapped through eLBC interface(CS#2)
- IRQ1
2) etSEC2
- SGMII
- connected to VSC8221
- IRQ2
3) etSEC3
- RGMII
- connected to VSC8641
- IRQ3
- 2 1X PCIe interfaces
- SD/MMC ,USB
- SPI EEPROM
- Serial I2C EEPROM
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
---
based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
Incorporated more feedback from Felix
arch/powerpc/boot/dts/p2020rdb.dts | 586 +++++++++++++++++++++++++++++
arch/powerpc/configs/mpc85xx_defconfig | 1 +
arch/powerpc/platforms/85xx/Kconfig | 9 +
arch/powerpc/platforms/85xx/Makefile | 3 +-
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 141 +++++++
5 files changed, 739 insertions(+), 1 deletions(-)
create mode 100644 arch/powerpc/boot/dts/p2020rdb.dts
create mode 100644 arch/powerpc/platforms/85xx/mpc85xx_rdb.c
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
new file mode 100644
index 0000000..da4cb0d
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -0,0 +1,586 @@
+/*
+ * P2020 RDB Device Tree Source
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = "fsl,P2020";
+ compatible = "fsl,P2020RDB";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ serial0 = &serial0;
+ serial1 = &serial1;
+ pci0 = &pci0;
+ pci1 = &pci1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ PowerPC,P2020@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ next-level-cache = <&L2>;
+ };
+
+ PowerPC,P2020@1 {
+ device_type = "cpu";
+ reg = <0x1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ localbus@ffe05000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
+ reg = <0 0xffe05000 0 0x1000>;
+ interrupts = <19 2>;
+ interrupt-parent = <&mpic>;
+
+ /* NOR and NAND Flashes */
+ ranges = <0x0 0x0 0x0 0xef000000 0x01000000
+ 0x1 0x0 0x0 0xffa00000 0x00040000
+ 0x2 0x0 0x0 0xffb00000 0x00020000>;
+
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "cfi-flash";
+ reg = <0x0 0x0 0x1000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 256KB for Vitesse 7385 Switch firmware */
+ reg = <0x0 0x00040000>;
+ label = "NOR (RO) Vitesse-7385 Firmware";
+ read-only;
+ };
+
+ partition@40000 {
+ /* 256KB for DTB Image */
+ reg = <0x00040000 0x00040000>;
+ label = "NOR (RO) DTB Image";
+ read-only;
+ };
+
+ partition@80000 {
+ /* 3.5 MB for Linux Kernel Image */
+ reg = <0x00080000 0x00380000>;
+ label = "NOR (RO) Linux Kernel Image";
+ read-only;
+ };
+
+ partition@400000 {
+ /* 11MB for JFFS2 based Root file System */
+ reg = <0x00400000 0x00b00000>;
+ label = "NOR (RW) JFFS2 Root File System";
+ };
+
+ partition@f00000 {
+ /* This location must not be altered */
+ /* 512KB for u-boot Bootloader Image */
+ /* 512KB for u-boot Environment Variables */
+ reg = <0x00f00000 0x00100000>;
+ label = "NOR (RO) U-Boot Image";
+ read-only;
+ };
+ };
+
+ nand@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,p2020-fcm-nand",
+ "fsl,elbc-fcm-nand";
+ reg = <0x1 0x0 0x40000>;
+
+ partition@0 {
+ /* This location must not be altered */
+ /* 1MB for u-boot Bootloader Image */
+ reg = <0x0 0x00100000>;
+ label = "NAND (RO) U-Boot Image";
+ read-only;
+ };
+
+ partition@100000 {
+ /* 1MB for DTB Image */
+ reg = <0x00100000 0x00100000>;
+ label = "NAND (RO) DTB Image";
+ read-only;
+ };
+
+ partition@200000 {
+ /* 4MB for Linux Kernel Image */
+ reg = <0x00200000 0x00400000>;
+ label = "NAND (RO) Linux Kernel Image";
+ read-only;
+ };
+
+ partition@600000 {
+ /* 4MB for Compressed Root file System Image */
+ reg = <0x00600000 0x00400000>;
+ label = "NAND (RO) Compressed RFS Image";
+ read-only;
+ };
+
+ partition@a00000 {
+ /* 7MB for JFFS2 based Root file System */
+ reg = <0x00a00000 0x00700000>;
+ label = "NAND (RW) JFFS2 Root File System";
+ };
+
+ partition@1100000 {
+ /* 15MB for JFFS2 based Root file System */
+ reg = <0x01100000 0x00f00000>;
+ label = "NAND (RW) Writable User area";
+ };
+ };
+
+ L2switch@2,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "vitesse-7385";
+ reg = <0x2 0x0 0x20000>;
+ };
+
+ };
+
+ soc@ffe00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "fsl,p2020-immr", "simple-bus";
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+ bus-frequency = <0>; // Filled out by uboot.
+
+ ecm-law@0 {
+ compatible = "fsl,ecm-law";
+ reg = <0x0 0x1000>;
+ fsl,num-laws = <12>;
+ };
+
+ ecm@1000 {
+ compatible = "fsl,p2020-ecm", "fsl,ecm";
+ reg = <0x1000 0x1000>;
+ interrupts = <17 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ memory-controller@2000 {
+ compatible = "fsl,p2020-memory-controller";
+ reg = <0x2000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <18 2>;
+ };
+
+ i2c@3000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl-i2c";
+ reg = <0x3000 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+ };
+
+ i2c@3100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+ compatible = "fsl-i2c";
+ reg = <0x3100 0x100>;
+ interrupts = <43 2>;
+ interrupt-parent = <&mpic>;
+ dfsrr;
+ };
+
+ serial0: serial@4500 {
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ serial1: serial@4600 {
+ cell-index = <1>;
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x4600 0x100>;
+ clock-frequency = <0>;
+ interrupts = <42 2>;
+ interrupt-parent = <&mpic>;
+ };
+
+ spi@7000 {
+ cell-index = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,espi";
+ reg = <0x7000 0x1000>;
+ interrupts = <59 0x2>;
+ interrupt-parent = <&mpic>;
+ mode = "cpu";
+
+ fsl_m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,espi-flash";
+ reg = <0>;
+ linux,modalias = "fsl_m25p80";
+ modal = "s25sl128b";
+ spi-max-frequency = <50000000>;
+ mode = <0>;
+
+ partition@0 {
+ /* 512KB for u-boot Bootloader Image */
+ reg = <0x0 0x00080000>;
+ label = "SPI (RO) U-Boot Image";
+ read-only;
+ };
+
+ partition@80000 {
+ /* 512KB for DTB Image */
+ reg = <0x00080000 0x00080000>;
+ label = "SPI (RO) DTB Image";
+ read-only;
+ };
+
+ partition@100000 {
+ /* 4MB for Linux Kernel Image */
+ reg = <0x00100000 0x00400000>;
+ label = "SPI (RO) Linux Kernel Image";
+ read-only;
+ };
+
+ partition@500000 {
+ /* 4MB for Compressed RFS Image */
+ reg = <0x00500000 0x00400000>;
+ label = "SPI (RO) Compressed RFS Image";
+ read-only;
+ };
+
+ partition@900000 {
+ /* 7MB for JFFS2 based RFS */
+ reg = <0x00900000 0x00700000>;
+ label = "SPI (RW) JFFS2 RFS";
+ };
+ };
+ };
+
+ dma@c300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0xc300 0x4>;
+ ranges = <0x0 0xc100 0x200>;
+ cell-index = <1>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <76 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <77 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <78 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <79 2>;
+ };
+ };
+
+ gpio: gpio-controller@f000 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8572-gpio";
+ reg = <0xf000 0x100>;
+ interrupts = <47 0x2>;
+ interrupt-parent = <&mpic>;
+ gpio-controller;
+ };
+
+ L2: l2-cache-controller@20000 {
+ compatible = "fsl,p2020-l2-cache-controller";
+ reg = <0x20000 0x1000>;
+ cache-line-size = <32>; // 32 bytes
+ cache-size = <0x80000>; // L2,512K
+ interrupt-parent = <&mpic>;
+ interrupts = <16 2>;
+ };
+
+ dma@21300 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "fsl,eloplus-dma";
+ reg = <0x21300 0x4>;
+ ranges = <0x0 0x21100 0x200>;
+ cell-index = <0>;
+ dma-channel@0 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x0 0x80>;
+ cell-index = <0>;
+ interrupt-parent = <&mpic>;
+ interrupts = <20 2>;
+ };
+ dma-channel@80 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x80 0x80>;
+ cell-index = <1>;
+ interrupt-parent = <&mpic>;
+ interrupts = <21 2>;
+ };
+ dma-channel@100 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x100 0x80>;
+ cell-index = <2>;
+ interrupt-parent = <&mpic>;
+ interrupts = <22 2>;
+ };
+ dma-channel@180 {
+ compatible = "fsl,eloplus-dma-channel";
+ reg = <0x180 0x80>;
+ cell-index = <3>;
+ interrupt-parent = <&mpic>;
+ interrupts = <23 2>;
+ };
+ };
+
+ usb@22000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl-usb2-dr";
+ reg = <0x22000 0x1000>;
+ interrupt-parent = <&mpic>;
+ interrupts = <28 0x2>;
+ phy_type = "ulpi";
+ };
+
+ enet0: ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <0>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x24000 0x1000>;
+ ranges = <0x0 0x24000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <29 2 30 2 34 2>;
+ interrupt-parent = <&mpic>;
+ fixed-link = <1 1 1000 0 0>;
+ phy-connection-type = "rgmii-id";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-mdio";
+ reg = <0x520 0x20>;
+
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x0>;
+ };
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&mpic>;
+ interrupts = <3 1>;
+ reg = <0x1>;
+ };
+ };
+ };
+
+ enet1: ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <1>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x25000 0x1000>;
+ ranges = <0x0 0x25000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <35 2 36 2 40 2>;
+ interrupt-parent = <&mpic>;
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "sgmii";
+
+ mdio@520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,gianfar-tbi";
+ reg = <0x520 0x20>;
+
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+ };
+
+ enet2: ethernet@26000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cell-index = <2>;
+ device_type = "network";
+ model = "eTSEC";
+ compatible = "gianfar";
+ reg = <0x26000 0x1000>;
+ ranges = <0x0 0x26000 0x1000>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ interrupts = <31 2 32 2 33 2>;
+ interrupt-parent = <&mpic>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "rgmii-id";
+ };
+
+ sdhci@2e000 {
+ compatible = "fsl,p2020-esdhc", "fsl,esdhc";
+ reg = <0x2e000 0x1000>;
+ interrupts = <72 0x2>;
+ interrupt-parent = <&mpic>;
+ /* Filled in by U-Boot */
+ clock-frequency = <0>;
+ };
+
+ crypto@30000 {
+ compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
+ "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
+ reg = <0x30000 0x10000>;
+ interrupts = <45 2 58 2>;
+ interrupt-parent = <&mpic>;
+ fsl,num-channels = <4>;
+ fsl,channel-fifo-len = <24>;
+ fsl,exec-units-mask = <0xbfe>;
+ fsl,descriptor-types-mask = <0x3ab0ebf>;
+ };
+
+ mpic: pic@40000 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x40000 0x40000>;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ };
+
+ msi@41600 {
+ compatible = "fsl,p2020-msi", "fsl,mpic-msi";
+ reg = <0x41600 0x80>;
+ msi-available-ranges = <0 0x100>;
+ interrupts = <
+ 0xe0 0
+ 0xe1 0
+ 0xe2 0
+ 0xe3 0
+ 0xe4 0
+ 0xe5 0
+ 0xe6 0
+ 0xe7 0>;
+ interrupt-parent = <&mpic>;
+ };
+
+ global-utilities@e0000 { //global utilities block
+ compatible = "fsl,p2020-guts";
+ reg = <0xe0000 0x1000>;
+ fsl,has-rstcr;
+ };
+ };
+
+ pci0: pcie@ffe09000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe09000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <25 2>;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ compatible = "fsl,mpc8548-pcie";
+ device_type = "pci";
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <0 0xffe0a000 0 0x1000>;
+ bus-range = <0 255>;
+ ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
+ clock-frequency = <33333333>;
+ interrupt-parent = <&mpic>;
+ interrupts = <26 2>;
+ pcie@0 {
+ reg = <0x0 0x0 0x0 0x0 0x0>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ device_type = "pci";
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+};
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index c162724..dc4819c 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -189,6 +189,7 @@ CONFIG_MPC85xx_CDS=y
CONFIG_MPC85xx_MDS=y
CONFIG_MPC8536_DS=y
CONFIG_MPC85xx_DS=y
+CONFIG_MPC85xx_RDB=y
CONFIG_SOCRATES=y
CONFIG_KSI8560=y
CONFIG_STX_GP3=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index a9b4166..d3a975e 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -55,6 +55,15 @@ config MPC85xx_DS
help
This option enables support for the MPC85xx DS (MPC8544 DS) board
+config MPC85xx_RDB
+ bool "Freescale MPC85xx RDB"
+ select PPC_I8259
+ select DEFAULT_UIMAGE
+ select FSL_ULI1575
+ select SWIOTLB
+ help
+ This option enables support for the MPC85xx RDB (P2020 RDB) board
+
config SOCRATES
bool "Socrates"
select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 835733f..9098aea 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -9,10 +9,11 @@ obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o
obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
+obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
obj-$(CONFIG_STX_GP3) += stx_gp3.o
obj-$(CONFIG_TQM85xx) += tqm85xx.o
obj-$(CONFIG_SBC8560) += sbc8560.o
obj-$(CONFIG_SBC8548) += sbc8548.o
obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
obj-$(CONFIG_KSI8560) += ksi8560.o
-obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
\ No newline at end of file
+obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
new file mode 100644
index 0000000..c8468de
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -0,0 +1,141 @@
+/*
+ * MPC85xx RDB Board Setup
+ *
+ * Copyright 2009 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
+#else
+#define DBG(fmt, args...)
+#endif
+
+
+void __init mpc85xx_rdb_pic_init(void)
+{
+ struct mpic *mpic;
+ struct resource r;
+ struct device_node *np;
+
+ np = of_find_node_by_type(NULL, "open-pic");
+ if (np == NULL) {
+ printk(KERN_ERR "Could not find open-pic node\n");
+ return;
+ }
+
+ if (of_address_to_resource(np, 0, &r)) {
+ printk(KERN_ERR "Failed to map mpic register space\n");
+ of_node_put(np);
+ return;
+ }
+
+ mpic = mpic_alloc(np, r.start,
+ MPIC_PRIMARY | MPIC_WANTS_RESET |
+ MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+ MPIC_SINGLE_DEST_CPU,
+ 0, 256, " OpenPIC ");
+
+ BUG_ON(mpic == NULL);
+ of_node_put(np);
+
+ mpic_init(mpic);
+
+}
+
+/*
+ * Setup the architecture
+ */
+#ifdef CONFIG_SMP
+extern void __init mpc85xx_smp_init(void);
+#endif
+static void __init mpc85xx_rdb_setup_arch(void)
+{
+#ifdef CONFIG_PCI
+ struct device_node *np;
+#endif
+
+ if (ppc_md.progress)
+ ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+ for_each_node_by_type(np, "pci") {
+ if (of_device_is_compatible(np, "fsl,mpc8548-pcie"))
+ fsl_add_bridge(np, 0);
+ }
+
+#endif
+
+#ifdef CONFIG_SMP
+ mpc85xx_smp_init();
+#endif
+
+ printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
+}
+
+static struct of_device_id __initdata mpc85xxrdb_ids[] = {
+ { .type = "soc", },
+ { .compatible = "soc", },
+ { .compatible = "simple-bus", },
+ { .compatible = "gianfar", },
+ {},
+};
+
+static int __init mpc85xxrdb_publish_devices(void)
+{
+ return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);
+}
+machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p2020_rdb_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, "fsl,P2020RDB"))
+ return 1;
+ return 0;
+}
+
+define_machine(p2020_rdb) {
+ .name = "P2020 RDB",
+ .probe = p2020_rdb_probe,
+ .setup_arch = mpc85xx_rdb_setup_arch,
+ .init_IRQ = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
--
1.5.6.5
^ permalink raw reply related
* Re: ethernet phy attached to wrong driver
From: Detlev Zundel @ 2009-08-07 14:57 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <4A797655.6060205@gersys.de>
Hi Stefan,
> I'm having trouble with my Ethernet device on a TQM5200 based board with
> LXT971 Phy. I'm running U-Boot 2009.03 and a Kernel 2.6.30.
>
> When doing a ping under U-Boot before booting into Linux, Ethernet works
> fine in Linux also. Dmesg reads:
> [ 262.369444] net eth0: Using PHY at MDIO address 0
> [ 263.265903] net eth0: attached phy 0 to driver LXT971
>
> But if I start Linux without prior use of the fec under U-Boot, Ethernet
> is not working in Linux. The wrong drivers seems to be attached to the
> phy. Dmesg reads:
> [ 2.068285] net eth0: Using PHY at MDIO address 0
> [ 2.964774] net eth0: attached phy 0 to driver Generic PHY
> ^^^^^^^^^^^
> Is there a bootarg to tell linux which driver to use? Any ideas what I'm
> doing wrong?
I cannot reproduce this problem with a tqm5200/stk52xx combination.
Linux always happily uses a genric PHY, irrelevant if I use networking
in U-Boot.
Cheers
Detlev
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu@denx.de
^ permalink raw reply
* Re: [PATCH] Do not inline putprops function
From: M. Mohan Kumar @ 2009-08-07 14:54 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, Neil Horman, Simon Horman, kexec, miltonm
In-Reply-To: <20090807143549.GA3110@in.ibm.com>
On Fri, Aug 07, 2009 at 08:05:49PM +0530, M. Mohan Kumar wrote:
> Hi,
>
> After enabling EARLY_DEBUG (and DEBUG in some of the files in
> arch/powerpc/kernel directory), without forcing the dtstruct variable to 8
> byte alignment:
>
> # ./kexec -e
> Starting new kernel
> console [udbg0] enabled
> -> early_setup(), dt_ptr: 0x7723000
> -> early_init_devtree(c000000007723000)
> Invalid tag 5 scanning flattened device tree !
> search "chosen", depth: 0, uname:
> Invalid tag 5 scanning flattened device tree !
> dt_root_size_cells = 2
> dt_root_addr_cells = 2
> Invalid tag 5 scanning flattened device tree !
> reserving: 128c000 -> 5ec1f7
> reserving: 7734000 -> 8cc000
> reserving: 7723000 -> f698
> Phys. mem: 0
> -> move_device_tree
> <- move_device_tree
> Scanning CPUs ...
> Invalid tag 5 scanning flattened device tree !
> <- early_init_devtree()
> Probing machine type ...
> pSeries ...
> No suitable machine found !
>
>
> So device-tree is getting corrupted when dtstruct variable is not aligned to
> 8 byte variable. This problem is not seen with gcc-3.4. Is it compiler
> issue? or bug in the code.
>
I tried writing the device tree to a binary file with and without dt_len and
compared the files after hexdump:
0000 0001 2f00 0000 0000 0003 0000 0004 0000 0001 2f00 0000 0000 0003 0000 0004
0000 0000 0000 0002 0000 0003 0000 0004 0000 0000 0000 0002 0000 0003 0000 0004
0000 000f 0000 0002 0000 0003 0000 0004 0000 000f 0000 0002 0000 0003 0000 0004
0000 001b 3ef1 4800 0000 0003 0000 000d 0000 001b 3ef1 4800 0000 0003 0000 000d
0000 002b 0000 0000 4942 4d2c 3931 3135 | 0000 002b 4942 4d2c 3931 3135 2d35 3035
2d35 3035 0000 0000 0000 0003 0000 0005 | 0000 0000 0000 0003 0000 0005 0000 0036
Regards,
M. Mohan Kumar
>
> On Fri, Aug 07, 2009 at 12:24:20AM +1000, Michael Ellerman wrote:
> > On Wed, 2009-08-05 at 22:19 +0530, M. Mohan Kumar wrote:
> > > Hi,
> > >
> > > When I align the dtstruct variable to 8 bytes, I am able to invoke kdump.
> > >
> > > When the line
> > > static unsigned dtstruct[TREEWORDS], *dt;
> > > changed to
> > > static unsigned dtstruct[TREEWORDS] __attribute__ ((aligned (8))), *dt;
> > >
> > > kexec-tool works.
> >
> > Hmm, odd.
> >
> > Can you check how it's aligned without your change? ie. in the original
> > binary, is it 4 byte aligned?
> >
> > When you make the change, is the only thing that changes in the binary
> > the alignedness of dtstruct, or does it cause other things to move
> > around?
> >
> > I don't think an unaligned dt blob should have any effect on the kernel,
> > ie. it should copy it in fine, but I'd have to look at the code.
> >
> > cheers
>
>
>
> _______________________________________________
> kexec mailing list
> kexec@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kexec
^ permalink raw reply
* Re: [PATCH] Do not inline putprops function
From: M. Mohan Kumar @ 2009-08-07 14:35 UTC (permalink / raw)
To: Michael Ellerman; +Cc: linuxppc-dev, Neil Horman, Simon Horman, kexec, miltonm
In-Reply-To: <1249568660.20200.23.camel@concordia>
Hi,
After enabling EARLY_DEBUG (and DEBUG in some of the files in
arch/powerpc/kernel directory), without forcing the dtstruct variable to 8
byte alignment:
# ./kexec -e
Starting new kernel
console [udbg0] enabled
-> early_setup(), dt_ptr: 0x7723000
-> early_init_devtree(c000000007723000)
Invalid tag 5 scanning flattened device tree !
search "chosen", depth: 0, uname:
Invalid tag 5 scanning flattened device tree !
dt_root_size_cells = 2
dt_root_addr_cells = 2
Invalid tag 5 scanning flattened device tree !
reserving: 128c000 -> 5ec1f7
reserving: 7734000 -> 8cc000
reserving: 7723000 -> f698
Phys. mem: 0
-> move_device_tree
<- move_device_tree
Scanning CPUs ...
Invalid tag 5 scanning flattened device tree !
<- early_init_devtree()
Probing machine type ...
pSeries ...
No suitable machine found !
So device-tree is getting corrupted when dtstruct variable is not aligned to
8 byte variable. This problem is not seen with gcc-3.4. Is it compiler
issue? or bug in the code.
Regards,
M. Mohan Kumar.
On Fri, Aug 07, 2009 at 12:24:20AM +1000, Michael Ellerman wrote:
> On Wed, 2009-08-05 at 22:19 +0530, M. Mohan Kumar wrote:
> > Hi,
> >
> > When I align the dtstruct variable to 8 bytes, I am able to invoke kdump.
> >
> > When the line
> > static unsigned dtstruct[TREEWORDS], *dt;
> > changed to
> > static unsigned dtstruct[TREEWORDS] __attribute__ ((aligned (8))), *dt;
> >
> > kexec-tool works.
>
> Hmm, odd.
>
> Can you check how it's aligned without your change? ie. in the original
> binary, is it 4 byte aligned?
>
> When you make the change, is the only thing that changes in the binary
> the alignedness of dtstruct, or does it cause other things to move
> around?
>
> I don't think an unaligned dt blob should have any effect on the kernel,
> ie. it should copy it in fine, but I'd have to look at the code.
>
> cheers
^ permalink raw reply
* RE: [PATCH][v2][powerpc/85xx] P2020RDB Platform Support Added
From: Aggrwal Poonam-B10812 @ 2009-08-07 14:35 UTC (permalink / raw)
To: Felix Radensky; +Cc: linuxppc-dev
In-Reply-To: <4A7C0BF5.8010503@embedded-sol.com>
=20
> -----Original Message-----
> From: Felix Radensky [mailto:felix@embedded-sol.com]=20
> Sent: Friday, August 07, 2009 4:42 PM
> To: Aggrwal Poonam-B10812
> Cc: linuxppc-dev@ozlabs.org
> Subject: Re: [PATCH][v2][powerpc/85xx] P2020RDB Platform Support Added
>=20
> Hi, Poonam
>=20
> See some more comments below.
>=20
> Poonam Aggrwal wrote:
> > Adds P2020RDB basic support in linux.
> > Overview of P2020RDB platform
> > - DDR
> > DDR2 1G
> > - NOR Flash
> > 16MByte
> > - NAND Flash
> > 32MByte
> > - 3 Ethernet interfaces
> > 1) etSEC1
> > - RGMII
> > - connected to a 5 port Vitesse Switch(VSC7385)
> > - Switch is memory mapped through eLBC interface(CS#2)
> > - IRQ1
> > 2) etSEC2
> > - SGMII
> > - connected to VSC8221
> > - IRQ2
> > 3) etSEC3
> > - RGMII
> > - connected to VSC8641
> > - IRQ3
> > - 2 1X PCIe interfaces
> > - SD/MMC ,USB
> > - SPI EEPROM
> > - Serial I2C EEPROM
> >=20
> > Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> > ---
> > based on=20
> > http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
> > incorporated Felix feedback regarding the partition names.
> > fixed the vitesse switch ranges entry in device tree.
> > arch/powerpc/boot/dts/p2020rdb.dts | 586=20
> +++++++++++++++++++++++++++++
> > arch/powerpc/configs/mpc85xx_defconfig | 1 +
> > arch/powerpc/platforms/85xx/Kconfig | 9 +
> > arch/powerpc/platforms/85xx/Makefile | 3 +-
> > arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 141 +++++++
> > 5 files changed, 739 insertions(+), 1 deletions(-) create mode=20
> > 100644 arch/powerpc/boot/dts/p2020rdb.dts
> > create mode 100644 arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> >=20
> > diff --git a/arch/powerpc/boot/dts/p2020rdb.dts=20
> > b/arch/powerpc/boot/dts/p2020rdb.dts
> > new file mode 100644
> > index 0000000..617029f
> > --- /dev/null
> > +++ b/arch/powerpc/boot/dts/p2020rdb.dts
> > @@ -0,0 +1,586 @@
> > +/*
> > + * P2020 RDB Device Tree Source
> > + *
> > + * Copyright 2009 Freescale Semiconductor Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or=20
> > +modify it
> > + * under the terms of the GNU General Public License as=20
> published=20
> > +by the
> > + * Free Software Foundation; either version 2 of the License, or=20
> > +(at your
> > + * option) any later version.
> > + */
> > +
> > +/dts-v1/;
> > +/ {
> > + model =3D "fsl,P2020";
> > + compatible =3D "fsl,P2020RDB";
> > + #address-cells =3D <2>;
> > + #size-cells =3D <2>;
> > +
> > + aliases {
> > + ethernet0 =3D &enet0;
> > + ethernet1 =3D &enet1;
> > + ethernet2 =3D &enet2;
> > + serial0 =3D &serial0;
> > + serial1 =3D &serial1;
> > + pci0 =3D &pci0;
> > + pci1 =3D &pci1;
> > + };
> > +
> > + cpus {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > +
> > + PowerPC,P2020@0 {
> > + device_type =3D "cpu";
> > + reg =3D <0x0>;
> > + next-level-cache =3D <&L2>;
> > + };
> > +
> > + PowerPC,P2020@1 {
> > + device_type =3D "cpu";
> > + reg =3D <0x1>;
> > + next-level-cache =3D <&L2>;
> > + };
> > + };
> > +
> > + memory {
> > + device_type =3D "memory";
> > + };
> > +
> > + localbus@ffe05000 {
> > + #address-cells =3D <2>;
> > + #size-cells =3D <1>;
> > + compatible =3D "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
> > + reg =3D <0 0xffe05000 0 0x1000>;
> > + interrupts =3D <19 2>;
> > + interrupt-parent =3D <&mpic>;
> > +
> > + /* NOR and NAND Flashes */
> > + ranges =3D <0x0 0x0 0x0 0xef000000 0x01000000
> > + 0x1 0x0 0x0 0xffa00000 0x00040000
> > + 0x2 0x0 0x0 0xffb00000 0x00020000>;
> > +
> > + nor@0,0 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "cfi-flash";
> > + reg =3D <0x0 0x0 0x1000000>;
> > + bank-width =3D <2>;
> > + device-width =3D <1>;
> > +
> > + partition@0 {
> > + /* This location must not be altered */
> > + /* 256KB for Vitesse 7385=20
> Switch firmware */
> > + reg =3D <0x0 0x00040000>;
> > + label =3D "NOR (RO) Vitesse-7385=20
> Firmware";
> > + read-only;
> > + };
> > +
> > + partition@40000 {
> > + /* 256KB for DTB Image */
> > + reg =3D <0x00040000 0x00040000>;
> > + label =3D "NOR (RO) DTB Image";
> > + read-only;
> > + };
> > +
> > + partition@80000 {
> > + /* 3.5 MB for Linux Kernel Image */
> > + reg =3D <0x00080000 0x00380000>;
> > + label =3D "NOR (RO) Linux Kernel Image";
> > + read-only;
> > + };
> > +
> > + partition@400000 {
> > + /* 11MB for JFFS2 based Root=20
> file System */
> > + reg =3D <0x00400000 0x00b00000>;
> > + label =3D "NOR (RW) JFFS2 Root=20
> File System";
> > + };
> > +
> > + partition@f00000 {
> > + /* This location must not be altered */
> > + /* 512KB for u-boot Bootloader Image */
> > + /* 512KB for u-boot Environment=20
> Variables */
> > + reg =3D <0x00f00000 0x00100000>;
> > + label =3D "NOR (RO) U-Boot Image";
> > + read-only;
> > + };
> > + };
> > +
> > + nand@1,0 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "fsl,p2020-fcm-nand",
> > + "fsl,elbc-fcm-nand";
> > + reg =3D <0x1 0x0 0x40000>;
> > +
> > + u-boot@0 {
> > + /* This location must not be altered */
> > + /* 1MB for u-boot Bootloader Image */
> > + reg =3D <0x0 0x00100000>;
> > + label =3D "NAND (RO) U-Boot Image";
> > + read-only;
> > + };
> > +
> > + dtb@100000 {
> > + /* 1MB for DTB Image */
> > + reg =3D <0x00100000 0x00100000>;
> > + label =3D "NAND (RO) DTB Image";
> > + read-only;
> > + };
> > +
> > + uImage@200000 {
> > + /* 4MB for Linux Kernel Image */
> > + reg =3D <0x00200000 0x00400000>;
> > + label =3D "NAND (RO) Linux Kernel Image";
> > + read-only;
> > + };
> > +
> > + rfs@600000 {
> > + /* 4MB for Compressed Root file=20
> System Image */
> > + reg =3D <0x00600000 0x00400000>;
> > + label =3D "NAND (RO) Compressed=20
> RFS Image";
> > + read-only;
> > + };
> > +
> > + jffs2@a00000 {
> > + /* 7MB for JFFS2 based Root=20
> file System */
> > + reg =3D <0x00a00000 0x00700000>;
> > + label =3D "NAND (RW) JFFS2 Root=20
> File System";
> > + };
> > +
> > + user@1100000 {
> > + /* 15MB for JFFS2 based Root=20
> file System */
> > + reg =3D <0x01100000 0x00f00000>;
> > + label =3D "NAND (RW) Writable User area";
> > + };
> > + };
>=20
> NAND partitions should also be declared using new syntax.
Of course, some goof up happened while sending.
>=20
>=20
> > +
> > + L2switch@2,0 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "vitesse-7385";
> > + reg =3D <0x2 0x0 0x20000>;
> > + };
> > +
> > + };
> > +
> > + soc@ffe00000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + device_type =3D "soc";
> > + compatible =3D "fsl,p2020-immr", "simple-bus";
> > + ranges =3D <0x0 0x0 0xffe00000 0x100000>;
> > + bus-frequency =3D <0>; // Filled out by uboot.
> > +
> > + ecm-law@0 {
> > + compatible =3D "fsl,ecm-law";
> > + reg =3D <0x0 0x1000>;
> > + fsl,num-laws =3D <12>;
> > + };
> > +
> > + ecm@1000 {
> > + compatible =3D "fsl,p2020-ecm", "fsl,ecm";
> > + reg =3D <0x1000 0x1000>;
> > + interrupts =3D <17 2>;
> > + interrupt-parent =3D <&mpic>;
> > + };
> > +
> > + memory-controller@2000 {
> > + compatible =3D "fsl,p2020-memory-controller";
> > + reg =3D <0x2000 0x1000>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <18 2>;
> > + };
> > +
> > + i2c@3000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + cell-index =3D <0>;
> > + compatible =3D "fsl-i2c";
> > + reg =3D <0x3000 0x100>;
> > + interrupts =3D <43 2>;
> > + interrupt-parent =3D <&mpic>;
> > + dfsrr;
> > + rtc@68 {
> > + compatible =3D "dallas,ds1339";
> > + reg =3D <0x68>;
> > + };
> > + };
> > +
> > + i2c@3100 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + cell-index =3D <1>;
> > + compatible =3D "fsl-i2c";
> > + reg =3D <0x3100 0x100>;
> > + interrupts =3D <43 2>;
> > + interrupt-parent =3D <&mpic>;
> > + dfsrr;
> > + };
> > +
> > + serial0: serial@4500 {
> > + cell-index =3D <0>;
> > + device_type =3D "serial";
> > + compatible =3D "ns16550";
> > + reg =3D <0x4500 0x100>;
> > + clock-frequency =3D <0>;
> > + interrupts =3D <42 2>;
> > + interrupt-parent =3D <&mpic>;
> > + };
> > +
> > + serial1: serial@4600 {
> > + cell-index =3D <1>;
> > + device_type =3D "serial";
> > + compatible =3D "ns16550";
> > + reg =3D <0x4600 0x100>;
> > + clock-frequency =3D <0>;
> > + interrupts =3D <42 2>;
> > + interrupt-parent =3D <&mpic>;
> > + };
> > +
> > + spi@7000 {
> > + cell-index =3D <0>;
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + compatible =3D "fsl,espi";
> > + reg =3D <0x7000 0x1000>;
> > + interrupts =3D <59 0x2>;
> > + interrupt-parent =3D <&mpic>;
> > + mode =3D "cpu";
> > +
> > + fsl_m25p80@0 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "fsl,espi-flash";
> > + reg =3D <0>;
> > + linux,modalias =3D "fsl_m25p80";
> > + modal =3D "s25sl128b";
> > + spi-max-frequency =3D <50000000>;
> > + mode =3D <0>;
> > +
> > + partition@0 {
> > + /* 512KB for u-boot=20
> Bootloader Image */
> > + reg =3D <0x0 0x00080000>;
> > + label =3D "SPI (RO) U-Boot Image";
> > + read-only;
> > + };
> > +
> > + partition@80000 {
> > + /* 512KB for DTB Image */
> > + reg =3D <0x00080000 0x00080000>;
> > + label =3D "SPI (RO) DTB Image";
> > + read-only;
> > + };
> > +
> > + partition@100000 {
> > + /* 4MB for Linux Kernel Image */
> > + reg =3D <0x00100000 0x00400000>;
> > + label =3D "SPI (RO) Linux=20
> Kernel Image";
> > + read-only;
> > + };
> > +
> > + partition@500000 {
> > + /* 4MB for Compressed=20
> RFS Image */
> > + reg =3D <0x00500000 0x00400000>;
> > + label =3D "SPI (RO)=20
> Compressed RFS Image";
> > + read-only;
> > + };
> > +
> > + partition@900000 {
> > + /* 7MB for JFFS2 based RFS */
> > + reg =3D <0x00900000 0x00700000>;
> > + label =3D "SPI (RW) JFFS2 RFS";
> > + };
> > + };
> > + };
> > +
> > + dma@c300 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "fsl,eloplus-dma";
> > + reg =3D <0xc300 0x4>;
> > + ranges =3D <0x0 0xc100 0x200>;
> > + cell-index =3D <1>;
> > + dma-channel@0 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x0 0x80>;
> > + cell-index =3D <0>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <76 2>;
> > + };
> > + dma-channel@80 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x80 0x80>;
> > + cell-index =3D <1>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <77 2>;
> > + };
> > + dma-channel@100 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x100 0x80>;
> > + cell-index =3D <2>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <78 2>;
> > + };
> > + dma-channel@180 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x180 0x80>;
> > + cell-index =3D <3>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <79 2>;
> > + };
> > + };
> > +
> > + gpio: gpio-controller@f000 {
> > + #gpio-cells =3D <2>;
> > + compatible =3D "fsl,mpc8572-gpio";
> > + reg =3D <0xf000 0x100>;
> > + interrupts =3D <47 0x2>;
> > + interrupt-parent =3D <&mpic>;
> > + gpio-controller;
> > + };
> > +
> > + L2: l2-cache-controller@20000 {
> > + compatible =3D "fsl,p2020-l2-cache-controller";
> > + reg =3D <0x20000 0x1000>;
> > + cache-line-size =3D <32>; // 32 bytes
> > + cache-size =3D <0x80000>; // L2,512K
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <16 2>;
> > + };
> > +
> > + dma@21300 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + compatible =3D "fsl,eloplus-dma";
> > + reg =3D <0x21300 0x4>;
> > + ranges =3D <0x0 0x21100 0x200>;
> > + cell-index =3D <0>;
> > + dma-channel@0 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x0 0x80>;
> > + cell-index =3D <0>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <20 2>;
> > + };
> > + dma-channel@80 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x80 0x80>;
> > + cell-index =3D <1>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <21 2>;
> > + };
> > + dma-channel@100 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x100 0x80>;
> > + cell-index =3D <2>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <22 2>;
> > + };
> > + dma-channel@180 {
> > + compatible =3D "fsl,eloplus-dma-channel";
> > + reg =3D <0x180 0x80>;
> > + cell-index =3D <3>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <23 2>;
> > + };
> > + };
> > +
> > + usb@22000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + compatible =3D "fsl-usb2-dr";
> > + reg =3D <0x22000 0x1000>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <28 0x2>;
> > + phy_type =3D "ulpi";
> > + };
> > +
> > + enet0: ethernet@24000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + cell-index =3D <0>;
> > + device_type =3D "network";
> > + model =3D "eTSEC";
> > + compatible =3D "gianfar";
> > + reg =3D <0x24000 0x1000>;
> > + ranges =3D <0x0 0x24000 0x1000>;
> > + local-mac-address =3D [ 00 00 00 00 00 00 ];
> > + interrupts =3D <29 2 30 2 34 2>;
> > + interrupt-parent =3D <&mpic>;
> > + fixed-link =3D <1 1 1000 0 0>;
> > + phy-connection-type =3D "rgmii-id";
> > +
> > + mdio@520 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + compatible =3D "fsl,gianfar-mdio";
> > + reg =3D <0x520 0x20>;
> > +
> > + phy0: ethernet-phy@0 {
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <3 1>;
> > + reg =3D <0x0>;
> > + };
> > + phy1: ethernet-phy@1 {
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <3 1>;
> > + reg =3D <0x1>;
> > + };
> > + };
> > + };
> > +
> > + enet1: ethernet@25000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + cell-index =3D <1>;
> > + device_type =3D "network";
> > + model =3D "eTSEC";
> > + compatible =3D "gianfar";
> > + reg =3D <0x25000 0x1000>;
> > + ranges =3D <0x0 0x25000 0x1000>;
> > + local-mac-address =3D [ 00 00 00 00 00 00 ];
> > + interrupts =3D <35 2 36 2 40 2>;
> > + interrupt-parent =3D <&mpic>;
> > + tbi-handle =3D <&tbi0>;
> > + phy-handle =3D <&phy0>;
> > + phy-connection-type =3D "sgmii";
> > +
> > + mdio@520 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <0>;
> > + compatible =3D "fsl,gianfar-tbi";
> > + reg =3D <0x520 0x20>;
> > +
> > + tbi0: tbi-phy@11 {
> > + reg =3D <0x11>;
> > + device_type =3D "tbi-phy";
> > + };
> > + };
> > + };
> > +
> > + enet2: ethernet@26000 {
> > + #address-cells =3D <1>;
> > + #size-cells =3D <1>;
> > + cell-index =3D <2>;
> > + device_type =3D "network";
> > + model =3D "eTSEC";
> > + compatible =3D "gianfar";
> > + reg =3D <0x26000 0x1000>;
> > + ranges =3D <0x0 0x26000 0x1000>;
> > + local-mac-address =3D [ 00 00 00 00 00 00 ];
> > + interrupts =3D <31 2 32 2 33 2>;
> > + interrupt-parent =3D <&mpic>;
> > + phy-handle =3D <&phy1>;
> > + phy-connection-type =3D "rgmii-id";
> > + };
> > +
>=20
> Shouldn't mdio node be associated with enet2 ?
On the P2020 SOC mdio signals for enet1 are coming out and connected to
the PHYs on the board. All PHYs are supposed to use this as MDIO bus.
>=20
>=20
> > + sdhci@2e000 {
> > + compatible =3D "fsl,p2020-esdhc", "fsl,esdhc";
> > + reg =3D <0x2e000 0x1000>;
> > + interrupts =3D <72 0x2>;
> > + interrupt-parent =3D <&mpic>;
> > + /* Filled in by U-Boot */
> > + clock-frequency =3D <0>;
> > + };
> > +
> > + crypto@30000 {
> > + compatible =3D "fsl,sec3.1",=20
> "fsl,sec3.0", "fsl,sec2.4",
> > + "fsl,sec2.2",=20
> "fsl,sec2.1", "fsl,sec2.0";
> > + reg =3D <0x30000 0x10000>;
> > + interrupts =3D <45 2 58 2>;
> > + interrupt-parent =3D <&mpic>;
> > + fsl,num-channels =3D <4>;
> > + fsl,channel-fifo-len =3D <24>;
> > + fsl,exec-units-mask =3D <0xbfe>;
> > + fsl,descriptor-types-mask =3D <0x3ab0ebf>;
> > + };
> > +
> > + mpic: pic@40000 {
> > + interrupt-controller;
> > + #address-cells =3D <0>;
> > + #interrupt-cells =3D <2>;
> > + reg =3D <0x40000 0x40000>;
> > + compatible =3D "chrp,open-pic";
> > + device_type =3D "open-pic";
> > + };
> > +
> > + msi@41600 {
> > + compatible =3D "fsl,p2020-msi", "fsl,mpic-msi";
> > + reg =3D <0x41600 0x80>;
> > + msi-available-ranges =3D <0 0x100>;
> > + interrupts =3D <
> > + 0xe0 0
> > + 0xe1 0
> > + 0xe2 0
> > + 0xe3 0
> > + 0xe4 0
> > + 0xe5 0
> > + 0xe6 0
> > + 0xe7 0>;
> > + interrupt-parent =3D <&mpic>;
> > + };
> > +
> > + global-utilities@e0000 { //global utilities block
> > + compatible =3D "fsl,p2020-guts";
> > + reg =3D <0xe0000 0x1000>;
> > + fsl,has-rstcr;
> > + };
> > + };
> > +
> > + pci0: pcie@ffe09000 {
> > + compatible =3D "fsl,mpc8548-pcie";
> > + device_type =3D "pci";
> > + #interrupt-cells =3D <1>;
> > + #size-cells =3D <2>;
> > + #address-cells =3D <3>;
> > + reg =3D <0 0xffe09000 0 0x1000>;
> > + bus-range =3D <0 255>;
> > + ranges =3D <0x2000000 0x0 0xa0000000 0 0xa0000000=20
> 0x0 0x20000000
> > + 0x1000000 0x0 0x00000000 0 0xffc30000=20
> 0x0 0x10000>;
> > + clock-frequency =3D <33333333>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <25 2>;
> > + pcie@0 {
> > + reg =3D <0x0 0x0 0x0 0x0 0x0>;
> > + #size-cells =3D <2>;
> > + #address-cells =3D <3>;
> > + device_type =3D "pci";
> > + ranges =3D <0x2000000 0x0 0xa0000000
> > + 0x2000000 0x0 0xa0000000
> > + 0x0 0x20000000
> > +
> > + 0x1000000 0x0 0x0
> > + 0x1000000 0x0 0x0
> > + 0x0 0x100000>;
> > + };
> > + };
> > +
> > + pci1: pcie@ffe0a000 {
> > + compatible =3D "fsl,mpc8548-pcie";
> > + device_type =3D "pci";
> > + #interrupt-cells =3D <1>;
> > + #size-cells =3D <2>;
> > + #address-cells =3D <3>;
> > + reg =3D <0 0xffe0a000 0 0x1000>;
> > + bus-range =3D <0 255>;
> > + ranges =3D <0x2000000 0x0 0xc0000000 0 0xc0000000=20
> 0x0 0x20000000
> > + 0x1000000 0x0 0x00000000 0 0xffc20000=20
> 0x0 0x10000>;
> > + clock-frequency =3D <33333333>;
> > + interrupt-parent =3D <&mpic>;
> > + interrupts =3D <26 2>;
> > + pcie@0 {
> > + reg =3D <0x0 0x0 0x0 0x0 0x0>;
> > + #size-cells =3D <2>;
> > + #address-cells =3D <3>;
> > + device_type =3D "pci";
> > + ranges =3D <0x2000000 0x0 0xc0000000
> > + 0x2000000 0x0 0xc0000000
> > + 0x0 0x20000000
> > +
> > + 0x1000000 0x0 0x0
> > + 0x1000000 0x0 0x0
> > + 0x0 0x100000>;
> > + };
> > + };
> > +};
> > diff --git a/arch/powerpc/configs/mpc85xx_defconfig=20
> b/arch/powerpc/configs/mpc85xx_defconfig
> > index c162724..dc4819c 100644
> > --- a/arch/powerpc/configs/mpc85xx_defconfig
> > +++ b/arch/powerpc/configs/mpc85xx_defconfig
> > @@ -189,6 +189,7 @@ CONFIG_MPC85xx_CDS=3Dy
> > CONFIG_MPC85xx_MDS=3Dy
> > CONFIG_MPC8536_DS=3Dy
> > CONFIG_MPC85xx_DS=3Dy
> > +CONFIG_MPC85xx_RDB=3Dy
> > CONFIG_SOCRATES=3Dy
> > CONFIG_KSI8560=3Dy
> > CONFIG_STX_GP3=3Dy
> > diff --git a/arch/powerpc/platforms/85xx/Kconfig=20
> b/arch/powerpc/platforms/85xx/Kconfig
> > index a9b4166..d3a975e 100644
> > --- a/arch/powerpc/platforms/85xx/Kconfig
> > +++ b/arch/powerpc/platforms/85xx/Kconfig
> > @@ -55,6 +55,15 @@ config MPC85xx_DS
> > help
> > This option enables support for the MPC85xx DS=20
> (MPC8544 DS) board
> > =20
> > +config MPC85xx_RDB
> > + bool "Freescale MPC85xx RDB"
> > + select PPC_I8259
> > + select DEFAULT_UIMAGE
> > + select FSL_ULI1575
> > + select SWIOTLB
> > + help
> > + This option enables support for the MPC85xx RDB=20
> (P2020 RDB) board
> > +
> > config SOCRATES
> > bool "Socrates"
> > select DEFAULT_UIMAGE
> > diff --git a/arch/powerpc/platforms/85xx/Makefile=20
> b/arch/powerpc/platforms/85xx/Makefile
> > index 835733f..4efcc63 100644
> > --- a/arch/powerpc/platforms/85xx/Makefile
> > +++ b/arch/powerpc/platforms/85xx/Makefile
> > @@ -9,10 +9,11 @@ obj-$(CONFIG_MPC85xx_CDS) +=3D mpc85xx_cds.o
> > obj-$(CONFIG_MPC8536_DS) +=3D mpc8536_ds.o
> > obj-$(CONFIG_MPC85xx_DS) +=3D mpc85xx_ds.o
> > obj-$(CONFIG_MPC85xx_MDS) +=3D mpc85xx_mds.o
> > +obj-$(CONFIG_MPC85xx_RDB) +=3D mpc85xx_rdb.o
> > obj-$(CONFIG_STX_GP3) +=3D stx_gp3.o
> > obj-$(CONFIG_TQM85xx) +=3D tqm85xx.o
> > obj-$(CONFIG_SBC8560) +=3D sbc8560.o
> > obj-$(CONFIG_SBC8548) +=3D sbc8548.o
> > obj-$(CONFIG_SOCRATES) +=3D socrates.o socrates_fpga_pic.o
> > obj-$(CONFIG_KSI8560) +=3D ksi8560.o
> > -obj-$(CONFIG_XES_MPC85xx) +=3D xes_mpc85xx.o
> > \ No newline at end of file
> > +obj-$(CONFIG_XES_MPC85xx) +=3D xes_mpc85xx.o
> > diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c=20
> b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> > new file mode 100644
> > index 0000000..c8468de
> > --- /dev/null
> > +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> > @@ -0,0 +1,141 @@
> > +/*
> > + * MPC85xx RDB Board Setup
> > + *
> > + * Copyright 2009 Freescale Semiconductor Inc.
> > + *
> > + * This program is free software; you can redistribute it=20
> and/or modify it
> > + * under the terms of the GNU General Public License as=20
> published by the
> > + * Free Software Foundation; either version 2 of the =20
> License, or (at your
> > + * option) any later version.
> > + */
> > +
> > +#include <linux/stddef.h>
> > +#include <linux/kernel.h>
> > +#include <linux/pci.h>
> > +#include <linux/kdev_t.h>
> > +#include <linux/delay.h>
> > +#include <linux/seq_file.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/of_platform.h>
> > +
> > +#include <asm/system.h>
> > +#include <asm/time.h>
> > +#include <asm/machdep.h>
> > +#include <asm/pci-bridge.h>
> > +#include <mm/mmu_decl.h>
> > +#include <asm/prom.h>
> > +#include <asm/udbg.h>
> > +#include <asm/mpic.h>
> > +
> > +#include <sysdev/fsl_soc.h>
> > +#include <sysdev/fsl_pci.h>
> > +
> > +#undef DEBUG
> > +
> > +#ifdef DEBUG
> > +#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt,=20
> __func__, ## args)
> > +#else
> > +#define DBG(fmt, args...)
> > +#endif
> > +
> > +
> > +void __init mpc85xx_rdb_pic_init(void)
> > +{
> > + struct mpic *mpic;
> > + struct resource r;
> > + struct device_node *np;
> > +
> > + np =3D of_find_node_by_type(NULL, "open-pic");
> > + if (np =3D=3D NULL) {
> > + printk(KERN_ERR "Could not find open-pic node\n");
> > + return;
> > + }
> > +
> > + if (of_address_to_resource(np, 0, &r)) {
> > + printk(KERN_ERR "Failed to map mpic register space\n");
> > + of_node_put(np);
> > + return;
> > + }
> > +
> > + mpic =3D mpic_alloc(np, r.start,
> > + MPIC_PRIMARY | MPIC_WANTS_RESET |
> > + MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
> > + MPIC_SINGLE_DEST_CPU,
> > + 0, 256, " OpenPIC ");
> > +
> > + BUG_ON(mpic =3D=3D NULL);
> > + of_node_put(np);
> > +
> > + mpic_init(mpic);
> > +
> > +}
> > +
> > +/*
> > + * Setup the architecture
> > + */
> > +#ifdef CONFIG_SMP
> > +extern void __init mpc85xx_smp_init(void);
> > +#endif
> > +static void __init mpc85xx_rdb_setup_arch(void)
> > +{
> > +#ifdef CONFIG_PCI
> > + struct device_node *np;
> > +#endif
> > +
> > + if (ppc_md.progress)
> > + ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
> > +
> > +#ifdef CONFIG_PCI
> > + for_each_node_by_type(np, "pci") {
> > + if (of_device_is_compatible(np, "fsl,mpc8548-pcie"))
> > + fsl_add_bridge(np, 0);
> > + }
> > +
> > +#endif
> > +
> > +#ifdef CONFIG_SMP
> > + mpc85xx_smp_init();
> > +#endif
> > +
> > + printk(KERN_INFO "MPC85xx RDB board from Freescale=20
> Semiconductor\n");
> > +}
> > +
> > +static struct of_device_id __initdata mpc85xxrdb_ids[] =3D {
> > + { .type =3D "soc", },
> > + { .compatible =3D "soc", },
> > + { .compatible =3D "simple-bus", },
> > + { .compatible =3D "gianfar", },
> > + {},
> > +};
> > +
> > +static int __init mpc85xxrdb_publish_devices(void)
> > +{
> > + return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);
> > +}
> > +machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);
> > +
> > +/*
> > + * Called very early, device-tree isn't unflattened
> > + */
> > +static int __init p2020_rdb_probe(void)
> > +{
> > + unsigned long root =3D of_get_flat_dt_root();
> > +
> > + if (of_flat_dt_is_compatible(root, "fsl,P2020RDB"))
> > + return 1;
> > + return 0;
> > +}
> > +
> > +define_machine(p2020_rdb) {
> > + .name =3D "P2020 RDB",
> > + .probe =3D p2020_rdb_probe,
> > + .setup_arch =3D mpc85xx_rdb_setup_arch,
> > + .init_IRQ =3D mpc85xx_rdb_pic_init,
> > +#ifdef CONFIG_PCI
> > + .pcibios_fixup_bus =3D fsl_pcibios_fixup_bus,
> > +#endif
> > + .get_irq =3D mpic_get_irq,
> > + .restart =3D fsl_rstcr_restart,
> > + .calibrate_decr =3D generic_calibrate_decr,
> > + .progress =3D udbg_progress,
> > +};
>=20
^ permalink raw reply
* 5121 cache handling.
From: Kenneth Johansson @ 2009-08-07 12:53 UTC (permalink / raw)
To: linuxppc-dev
on 5121 there is a e300 core that unfortunately is connected to the rest
of the SOC with a bus that do not support coherency.
solution for many driver has been to use uncached memory. But for the
framebuffer that is not going to work as the performance impact of doing
graphics operations on uncached memory is to large.
currently the "solution" is to flush the cache in the interrupt
handler.
#if defined(CONFIG_NOT_COHERENT_CACHE)
int i;
unsigned int *ptr;
ptr = coherence_data;
for (i = 0; i < 1024*8; i++)
*ptr++ = 0;
#endif
Now this apparently is not enough on a e300 core that has a PLRU cache
replacement algorithm. but what is the optimal solution?
should not the framebuffer be marked as cache write through. that is the
W bit should be set in the tlb mapping. Why is this not done ? is that
feature also not working on 5121 ??
if this manual handling needs to be done what is best.
do it like now but over 52KB memory basically throwing out anything in
the cache in the process regardless if it was needed or not.
or do it carefully over just the framebuffer memory.
problem with doing it over just the framebuffer is that a 1024x768
buffer is 98304 cache lines it's going to take a considerable time to
do. how many cycles does it take per cache line if we never get a hit ??
3cycles at 400MHz gives 4.5milisec/sec or 4-5% overhead
1024*768*4/32*3*(1/400000000)*60
.04423680000000000000
52kB on the other hand is only 1664 lines but is obviously going to have
to do a lot of actual memory writes also for any modified cache line and
later a lot of reads to read back what was evicted.
^ permalink raw reply
* Re: [PATCH][v2][powerpc/85xx] P2020RDB Platform Support Added
From: Felix Radensky @ 2009-08-07 11:11 UTC (permalink / raw)
To: Poonam Aggrwal; +Cc: linuxppc-dev
In-Reply-To: <1249633286-21663-1-git-send-email-poonam.aggrwal@freescale.com>
Hi, Poonam
See some more comments below.
Poonam Aggrwal wrote:
> Adds P2020RDB basic support in linux.
> Overview of P2020RDB platform
> - DDR
> DDR2 1G
> - NOR Flash
> 16MByte
> - NAND Flash
> 32MByte
> - 3 Ethernet interfaces
> 1) etSEC1
> - RGMII
> - connected to a 5 port Vitesse Switch(VSC7385)
> - Switch is memory mapped through eLBC interface(CS#2)
> - IRQ1
> 2) etSEC2
> - SGMII
> - connected to VSC8221
> - IRQ2
> 3) etSEC3
> - RGMII
> - connected to VSC8641
> - IRQ3
> - 2 1X PCIe interfaces
> - SD/MMC ,USB
> - SPI EEPROM
> - Serial I2C EEPROM
>
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> ---
> based on http://www.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
> incorporated Felix feedback regarding the partition names.
> fixed the vitesse switch ranges entry in device tree.
> arch/powerpc/boot/dts/p2020rdb.dts | 586 +++++++++++++++++++++++++++++
> arch/powerpc/configs/mpc85xx_defconfig | 1 +
> arch/powerpc/platforms/85xx/Kconfig | 9 +
> arch/powerpc/platforms/85xx/Makefile | 3 +-
> arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 141 +++++++
> 5 files changed, 739 insertions(+), 1 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/p2020rdb.dts
> create mode 100644 arch/powerpc/platforms/85xx/mpc85xx_rdb.c
>
> diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
> new file mode 100644
> index 0000000..617029f
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/p2020rdb.dts
> @@ -0,0 +1,586 @@
> +/*
> + * P2020 RDB Device Tree Source
> + *
> + * Copyright 2009 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/dts-v1/;
> +/ {
> + model = "fsl,P2020";
> + compatible = "fsl,P2020RDB";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + aliases {
> + ethernet0 = &enet0;
> + ethernet1 = &enet1;
> + ethernet2 = &enet2;
> + serial0 = &serial0;
> + serial1 = &serial1;
> + pci0 = &pci0;
> + pci1 = &pci1;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + PowerPC,P2020@0 {
> + device_type = "cpu";
> + reg = <0x0>;
> + next-level-cache = <&L2>;
> + };
> +
> + PowerPC,P2020@1 {
> + device_type = "cpu";
> + reg = <0x1>;
> + next-level-cache = <&L2>;
> + };
> + };
> +
> + memory {
> + device_type = "memory";
> + };
> +
> + localbus@ffe05000 {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
> + reg = <0 0xffe05000 0 0x1000>;
> + interrupts = <19 2>;
> + interrupt-parent = <&mpic>;
> +
> + /* NOR and NAND Flashes */
> + ranges = <0x0 0x0 0x0 0xef000000 0x01000000
> + 0x1 0x0 0x0 0xffa00000 0x00040000
> + 0x2 0x0 0x0 0xffb00000 0x00020000>;
> +
> + nor@0,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "cfi-flash";
> + reg = <0x0 0x0 0x1000000>;
> + bank-width = <2>;
> + device-width = <1>;
> +
> + partition@0 {
> + /* This location must not be altered */
> + /* 256KB for Vitesse 7385 Switch firmware */
> + reg = <0x0 0x00040000>;
> + label = "NOR (RO) Vitesse-7385 Firmware";
> + read-only;
> + };
> +
> + partition@40000 {
> + /* 256KB for DTB Image */
> + reg = <0x00040000 0x00040000>;
> + label = "NOR (RO) DTB Image";
> + read-only;
> + };
> +
> + partition@80000 {
> + /* 3.5 MB for Linux Kernel Image */
> + reg = <0x00080000 0x00380000>;
> + label = "NOR (RO) Linux Kernel Image";
> + read-only;
> + };
> +
> + partition@400000 {
> + /* 11MB for JFFS2 based Root file System */
> + reg = <0x00400000 0x00b00000>;
> + label = "NOR (RW) JFFS2 Root File System";
> + };
> +
> + partition@f00000 {
> + /* This location must not be altered */
> + /* 512KB for u-boot Bootloader Image */
> + /* 512KB for u-boot Environment Variables */
> + reg = <0x00f00000 0x00100000>;
> + label = "NOR (RO) U-Boot Image";
> + read-only;
> + };
> + };
> +
> + nand@1,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,p2020-fcm-nand",
> + "fsl,elbc-fcm-nand";
> + reg = <0x1 0x0 0x40000>;
> +
> + u-boot@0 {
> + /* This location must not be altered */
> + /* 1MB for u-boot Bootloader Image */
> + reg = <0x0 0x00100000>;
> + label = "NAND (RO) U-Boot Image";
> + read-only;
> + };
> +
> + dtb@100000 {
> + /* 1MB for DTB Image */
> + reg = <0x00100000 0x00100000>;
> + label = "NAND (RO) DTB Image";
> + read-only;
> + };
> +
> + uImage@200000 {
> + /* 4MB for Linux Kernel Image */
> + reg = <0x00200000 0x00400000>;
> + label = "NAND (RO) Linux Kernel Image";
> + read-only;
> + };
> +
> + rfs@600000 {
> + /* 4MB for Compressed Root file System Image */
> + reg = <0x00600000 0x00400000>;
> + label = "NAND (RO) Compressed RFS Image";
> + read-only;
> + };
> +
> + jffs2@a00000 {
> + /* 7MB for JFFS2 based Root file System */
> + reg = <0x00a00000 0x00700000>;
> + label = "NAND (RW) JFFS2 Root File System";
> + };
> +
> + user@1100000 {
> + /* 15MB for JFFS2 based Root file System */
> + reg = <0x01100000 0x00f00000>;
> + label = "NAND (RW) Writable User area";
> + };
> + };
NAND partitions should also be declared using new syntax.
> +
> + L2switch@2,0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "vitesse-7385";
> + reg = <0x2 0x0 0x20000>;
> + };
> +
> + };
> +
> + soc@ffe00000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + device_type = "soc";
> + compatible = "fsl,p2020-immr", "simple-bus";
> + ranges = <0x0 0x0 0xffe00000 0x100000>;
> + bus-frequency = <0>; // Filled out by uboot.
> +
> + ecm-law@0 {
> + compatible = "fsl,ecm-law";
> + reg = <0x0 0x1000>;
> + fsl,num-laws = <12>;
> + };
> +
> + ecm@1000 {
> + compatible = "fsl,p2020-ecm", "fsl,ecm";
> + reg = <0x1000 0x1000>;
> + interrupts = <17 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + memory-controller@2000 {
> + compatible = "fsl,p2020-memory-controller";
> + reg = <0x2000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <18 2>;
> + };
> +
> + i2c@3000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cell-index = <0>;
> + compatible = "fsl-i2c";
> + reg = <0x3000 0x100>;
> + interrupts = <43 2>;
> + interrupt-parent = <&mpic>;
> + dfsrr;
> + rtc@68 {
> + compatible = "dallas,ds1339";
> + reg = <0x68>;
> + };
> + };
> +
> + i2c@3100 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cell-index = <1>;
> + compatible = "fsl-i2c";
> + reg = <0x3100 0x100>;
> + interrupts = <43 2>;
> + interrupt-parent = <&mpic>;
> + dfsrr;
> + };
> +
> + serial0: serial@4500 {
> + cell-index = <0>;
> + device_type = "serial";
> + compatible = "ns16550";
> + reg = <0x4500 0x100>;
> + clock-frequency = <0>;
> + interrupts = <42 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + serial1: serial@4600 {
> + cell-index = <1>;
> + device_type = "serial";
> + compatible = "ns16550";
> + reg = <0x4600 0x100>;
> + clock-frequency = <0>;
> + interrupts = <42 2>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + spi@7000 {
> + cell-index = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,espi";
> + reg = <0x7000 0x1000>;
> + interrupts = <59 0x2>;
> + interrupt-parent = <&mpic>;
> + mode = "cpu";
> +
> + fsl_m25p80@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,espi-flash";
> + reg = <0>;
> + linux,modalias = "fsl_m25p80";
> + modal = "s25sl128b";
> + spi-max-frequency = <50000000>;
> + mode = <0>;
> +
> + partition@0 {
> + /* 512KB for u-boot Bootloader Image */
> + reg = <0x0 0x00080000>;
> + label = "SPI (RO) U-Boot Image";
> + read-only;
> + };
> +
> + partition@80000 {
> + /* 512KB for DTB Image */
> + reg = <0x00080000 0x00080000>;
> + label = "SPI (RO) DTB Image";
> + read-only;
> + };
> +
> + partition@100000 {
> + /* 4MB for Linux Kernel Image */
> + reg = <0x00100000 0x00400000>;
> + label = "SPI (RO) Linux Kernel Image";
> + read-only;
> + };
> +
> + partition@500000 {
> + /* 4MB for Compressed RFS Image */
> + reg = <0x00500000 0x00400000>;
> + label = "SPI (RO) Compressed RFS Image";
> + read-only;
> + };
> +
> + partition@900000 {
> + /* 7MB for JFFS2 based RFS */
> + reg = <0x00900000 0x00700000>;
> + label = "SPI (RW) JFFS2 RFS";
> + };
> + };
> + };
> +
> + dma@c300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,eloplus-dma";
> + reg = <0xc300 0x4>;
> + ranges = <0x0 0xc100 0x200>;
> + cell-index = <1>;
> + dma-channel@0 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x0 0x80>;
> + cell-index = <0>;
> + interrupt-parent = <&mpic>;
> + interrupts = <76 2>;
> + };
> + dma-channel@80 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x80 0x80>;
> + cell-index = <1>;
> + interrupt-parent = <&mpic>;
> + interrupts = <77 2>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x100 0x80>;
> + cell-index = <2>;
> + interrupt-parent = <&mpic>;
> + interrupts = <78 2>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x180 0x80>;
> + cell-index = <3>;
> + interrupt-parent = <&mpic>;
> + interrupts = <79 2>;
> + };
> + };
> +
> + gpio: gpio-controller@f000 {
> + #gpio-cells = <2>;
> + compatible = "fsl,mpc8572-gpio";
> + reg = <0xf000 0x100>;
> + interrupts = <47 0x2>;
> + interrupt-parent = <&mpic>;
> + gpio-controller;
> + };
> +
> + L2: l2-cache-controller@20000 {
> + compatible = "fsl,p2020-l2-cache-controller";
> + reg = <0x20000 0x1000>;
> + cache-line-size = <32>; // 32 bytes
> + cache-size = <0x80000>; // L2,512K
> + interrupt-parent = <&mpic>;
> + interrupts = <16 2>;
> + };
> +
> + dma@21300 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,eloplus-dma";
> + reg = <0x21300 0x4>;
> + ranges = <0x0 0x21100 0x200>;
> + cell-index = <0>;
> + dma-channel@0 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x0 0x80>;
> + cell-index = <0>;
> + interrupt-parent = <&mpic>;
> + interrupts = <20 2>;
> + };
> + dma-channel@80 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x80 0x80>;
> + cell-index = <1>;
> + interrupt-parent = <&mpic>;
> + interrupts = <21 2>;
> + };
> + dma-channel@100 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x100 0x80>;
> + cell-index = <2>;
> + interrupt-parent = <&mpic>;
> + interrupts = <22 2>;
> + };
> + dma-channel@180 {
> + compatible = "fsl,eloplus-dma-channel";
> + reg = <0x180 0x80>;
> + cell-index = <3>;
> + interrupt-parent = <&mpic>;
> + interrupts = <23 2>;
> + };
> + };
> +
> + usb@22000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl-usb2-dr";
> + reg = <0x22000 0x1000>;
> + interrupt-parent = <&mpic>;
> + interrupts = <28 0x2>;
> + phy_type = "ulpi";
> + };
> +
> + enet0: ethernet@24000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + cell-index = <0>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "gianfar";
> + reg = <0x24000 0x1000>;
> + ranges = <0x0 0x24000 0x1000>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupts = <29 2 30 2 34 2>;
> + interrupt-parent = <&mpic>;
> + fixed-link = <1 1 1000 0 0>;
> + phy-connection-type = "rgmii-id";
> +
> + mdio@520 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,gianfar-mdio";
> + reg = <0x520 0x20>;
> +
> + phy0: ethernet-phy@0 {
> + interrupt-parent = <&mpic>;
> + interrupts = <3 1>;
> + reg = <0x0>;
> + };
> + phy1: ethernet-phy@1 {
> + interrupt-parent = <&mpic>;
> + interrupts = <3 1>;
> + reg = <0x1>;
> + };
> + };
> + };
> +
> + enet1: ethernet@25000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + cell-index = <1>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "gianfar";
> + reg = <0x25000 0x1000>;
> + ranges = <0x0 0x25000 0x1000>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupts = <35 2 36 2 40 2>;
> + interrupt-parent = <&mpic>;
> + tbi-handle = <&tbi0>;
> + phy-handle = <&phy0>;
> + phy-connection-type = "sgmii";
> +
> + mdio@520 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,gianfar-tbi";
> + reg = <0x520 0x20>;
> +
> + tbi0: tbi-phy@11 {
> + reg = <0x11>;
> + device_type = "tbi-phy";
> + };
> + };
> + };
> +
> + enet2: ethernet@26000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + cell-index = <2>;
> + device_type = "network";
> + model = "eTSEC";
> + compatible = "gianfar";
> + reg = <0x26000 0x1000>;
> + ranges = <0x0 0x26000 0x1000>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupts = <31 2 32 2 33 2>;
> + interrupt-parent = <&mpic>;
> + phy-handle = <&phy1>;
> + phy-connection-type = "rgmii-id";
> + };
> +
Shouldn't mdio node be associated with enet2 ?
> + sdhci@2e000 {
> + compatible = "fsl,p2020-esdhc", "fsl,esdhc";
> + reg = <0x2e000 0x1000>;
> + interrupts = <72 0x2>;
> + interrupt-parent = <&mpic>;
> + /* Filled in by U-Boot */
> + clock-frequency = <0>;
> + };
> +
> + crypto@30000 {
> + compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
> + "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
> + reg = <0x30000 0x10000>;
> + interrupts = <45 2 58 2>;
> + interrupt-parent = <&mpic>;
> + fsl,num-channels = <4>;
> + fsl,channel-fifo-len = <24>;
> + fsl,exec-units-mask = <0xbfe>;
> + fsl,descriptor-types-mask = <0x3ab0ebf>;
> + };
> +
> + mpic: pic@40000 {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + reg = <0x40000 0x40000>;
> + compatible = "chrp,open-pic";
> + device_type = "open-pic";
> + };
> +
> + msi@41600 {
> + compatible = "fsl,p2020-msi", "fsl,mpic-msi";
> + reg = <0x41600 0x80>;
> + msi-available-ranges = <0 0x100>;
> + interrupts = <
> + 0xe0 0
> + 0xe1 0
> + 0xe2 0
> + 0xe3 0
> + 0xe4 0
> + 0xe5 0
> + 0xe6 0
> + 0xe7 0>;
> + interrupt-parent = <&mpic>;
> + };
> +
> + global-utilities@e0000 { //global utilities block
> + compatible = "fsl,p2020-guts";
> + reg = <0xe0000 0x1000>;
> + fsl,has-rstcr;
> + };
> + };
> +
> + pci0: pcie@ffe09000 {
> + compatible = "fsl,mpc8548-pcie";
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + reg = <0 0xffe09000 0 0x1000>;
> + bus-range = <0 255>;
> + ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
> + 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
> + clock-frequency = <33333333>;
> + interrupt-parent = <&mpic>;
> + interrupts = <25 2>;
> + pcie@0 {
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + device_type = "pci";
> + ranges = <0x2000000 0x0 0xa0000000
> + 0x2000000 0x0 0xa0000000
> + 0x0 0x20000000
> +
> + 0x1000000 0x0 0x0
> + 0x1000000 0x0 0x0
> + 0x0 0x100000>;
> + };
> + };
> +
> + pci1: pcie@ffe0a000 {
> + compatible = "fsl,mpc8548-pcie";
> + device_type = "pci";
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + reg = <0 0xffe0a000 0 0x1000>;
> + bus-range = <0 255>;
> + ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
> + 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
> + clock-frequency = <33333333>;
> + interrupt-parent = <&mpic>;
> + interrupts = <26 2>;
> + pcie@0 {
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + device_type = "pci";
> + ranges = <0x2000000 0x0 0xc0000000
> + 0x2000000 0x0 0xc0000000
> + 0x0 0x20000000
> +
> + 0x1000000 0x0 0x0
> + 0x1000000 0x0 0x0
> + 0x0 0x100000>;
> + };
> + };
> +};
> diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
> index c162724..dc4819c 100644
> --- a/arch/powerpc/configs/mpc85xx_defconfig
> +++ b/arch/powerpc/configs/mpc85xx_defconfig
> @@ -189,6 +189,7 @@ CONFIG_MPC85xx_CDS=y
> CONFIG_MPC85xx_MDS=y
> CONFIG_MPC8536_DS=y
> CONFIG_MPC85xx_DS=y
> +CONFIG_MPC85xx_RDB=y
> CONFIG_SOCRATES=y
> CONFIG_KSI8560=y
> CONFIG_STX_GP3=y
> diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
> index a9b4166..d3a975e 100644
> --- a/arch/powerpc/platforms/85xx/Kconfig
> +++ b/arch/powerpc/platforms/85xx/Kconfig
> @@ -55,6 +55,15 @@ config MPC85xx_DS
> help
> This option enables support for the MPC85xx DS (MPC8544 DS) board
>
> +config MPC85xx_RDB
> + bool "Freescale MPC85xx RDB"
> + select PPC_I8259
> + select DEFAULT_UIMAGE
> + select FSL_ULI1575
> + select SWIOTLB
> + help
> + This option enables support for the MPC85xx RDB (P2020 RDB) board
> +
> config SOCRATES
> bool "Socrates"
> select DEFAULT_UIMAGE
> diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
> index 835733f..4efcc63 100644
> --- a/arch/powerpc/platforms/85xx/Makefile
> +++ b/arch/powerpc/platforms/85xx/Makefile
> @@ -9,10 +9,11 @@ obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
> obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o
> obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
> obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
> +obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
> obj-$(CONFIG_STX_GP3) += stx_gp3.o
> obj-$(CONFIG_TQM85xx) += tqm85xx.o
> obj-$(CONFIG_SBC8560) += sbc8560.o
> obj-$(CONFIG_SBC8548) += sbc8548.o
> obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
> obj-$(CONFIG_KSI8560) += ksi8560.o
> -obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
> \ No newline at end of file
> +obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
> diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> new file mode 100644
> index 0000000..c8468de
> --- /dev/null
> +++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
> @@ -0,0 +1,141 @@
> +/*
> + * MPC85xx RDB Board Setup
> + *
> + * Copyright 2009 Freescale Semiconductor Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +#include <linux/stddef.h>
> +#include <linux/kernel.h>
> +#include <linux/pci.h>
> +#include <linux/kdev_t.h>
> +#include <linux/delay.h>
> +#include <linux/seq_file.h>
> +#include <linux/interrupt.h>
> +#include <linux/of_platform.h>
> +
> +#include <asm/system.h>
> +#include <asm/time.h>
> +#include <asm/machdep.h>
> +#include <asm/pci-bridge.h>
> +#include <mm/mmu_decl.h>
> +#include <asm/prom.h>
> +#include <asm/udbg.h>
> +#include <asm/mpic.h>
> +
> +#include <sysdev/fsl_soc.h>
> +#include <sysdev/fsl_pci.h>
> +
> +#undef DEBUG
> +
> +#ifdef DEBUG
> +#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
> +#else
> +#define DBG(fmt, args...)
> +#endif
> +
> +
> +void __init mpc85xx_rdb_pic_init(void)
> +{
> + struct mpic *mpic;
> + struct resource r;
> + struct device_node *np;
> +
> + np = of_find_node_by_type(NULL, "open-pic");
> + if (np == NULL) {
> + printk(KERN_ERR "Could not find open-pic node\n");
> + return;
> + }
> +
> + if (of_address_to_resource(np, 0, &r)) {
> + printk(KERN_ERR "Failed to map mpic register space\n");
> + of_node_put(np);
> + return;
> + }
> +
> + mpic = mpic_alloc(np, r.start,
> + MPIC_PRIMARY | MPIC_WANTS_RESET |
> + MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
> + MPIC_SINGLE_DEST_CPU,
> + 0, 256, " OpenPIC ");
> +
> + BUG_ON(mpic == NULL);
> + of_node_put(np);
> +
> + mpic_init(mpic);
> +
> +}
> +
> +/*
> + * Setup the architecture
> + */
> +#ifdef CONFIG_SMP
> +extern void __init mpc85xx_smp_init(void);
> +#endif
> +static void __init mpc85xx_rdb_setup_arch(void)
> +{
> +#ifdef CONFIG_PCI
> + struct device_node *np;
> +#endif
> +
> + if (ppc_md.progress)
> + ppc_md.progress("mpc85xx_rdb_setup_arch()", 0);
> +
> +#ifdef CONFIG_PCI
> + for_each_node_by_type(np, "pci") {
> + if (of_device_is_compatible(np, "fsl,mpc8548-pcie"))
> + fsl_add_bridge(np, 0);
> + }
> +
> +#endif
> +
> +#ifdef CONFIG_SMP
> + mpc85xx_smp_init();
> +#endif
> +
> + printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
> +}
> +
> +static struct of_device_id __initdata mpc85xxrdb_ids[] = {
> + { .type = "soc", },
> + { .compatible = "soc", },
> + { .compatible = "simple-bus", },
> + { .compatible = "gianfar", },
> + {},
> +};
> +
> +static int __init mpc85xxrdb_publish_devices(void)
> +{
> + return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);
> +}
> +machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);
> +
> +/*
> + * Called very early, device-tree isn't unflattened
> + */
> +static int __init p2020_rdb_probe(void)
> +{
> + unsigned long root = of_get_flat_dt_root();
> +
> + if (of_flat_dt_is_compatible(root, "fsl,P2020RDB"))
> + return 1;
> + return 0;
> +}
> +
> +define_machine(p2020_rdb) {
> + .name = "P2020 RDB",
> + .probe = p2020_rdb_probe,
> + .setup_arch = mpc85xx_rdb_setup_arch,
> + .init_IRQ = mpc85xx_rdb_pic_init,
> +#ifdef CONFIG_PCI
> + .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
> +#endif
> + .get_irq = mpic_get_irq,
> + .restart = fsl_rstcr_restart,
> + .calibrate_decr = generic_calibrate_decr,
> + .progress = udbg_progress,
> +};
^ permalink raw reply
* Re: MPC8313 performance evaluation
From: Lutz Jaenicke @ 2009-08-07 11:02 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <20090807105654.GA20678@lutz.bln.innominate.local>
On Fri, Aug 07, 2009 at 12:56:54PM +0200, Lutz Jaenicke wrote:
> On Fri, Aug 07, 2009 at 04:08:50PM +0800, Liu Dave-R63238 wrote:
> >
> > > Some discussion with the the freescale rep. lead to the CSB frequency
> > > of the 8313 (166MHz) being significantly lower than that of the 8343.
> > > Is the CSB the critical point here?
> >
> > I believe the CSB is critical point here. They are right.
>
> This indeed indicates that the CSB is the limiting factor.
> Until a few days ago I have not even been aware of the CSB being a
> performance critical component. All of the nice powerpoints explaining
> the processors and used for comparing different families shown by the
> Freescale Rep include the core frequencies and the DRAM interface
> and frequency but do not even mention the CSB...
Having this said, is there any good white paper to be read about it?
For firewall usage there are different influence factors:
* Ethernet interfaces (DMA to/from DRAM via CSB!?)
* CPU processing for the firewall rules (code/data to/from DRAM closely
related to cache size or misses)
Hence I would like to understand better the impact of the different
components.
(If only available under NDA I can also contact my Freescale Rep but
having public source always makes things easier.)
Best regards,
Lutz
--
Dr.-Ing. Lutz Jänicke
CTO
Innominate Security Technologies AG /protecting industrial networks/
tel: +49.30.921028-200
fax: +49.30.921028-020
Rudower Chaussee 13
D-12489 Berlin, Germany
www.innominate.com
Register Court: AG Charlottenburg, HR B 81603
Management Board: Dirk Seewald
Chairman of the Supervisory Board: Volker Bibelhausen
^ permalink raw reply
* Re: MPC8313 performance evaluation
From: Lutz Jaenicke @ 2009-08-07 10:56 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <D7CCA83BB0796C49BC0BB53B6AB1208956D03F@zch01exm21.fsl.freescale.net>
On Fri, Aug 07, 2009 at 04:08:50PM +0800, Liu Dave-R63238 wrote:
>
> > Some discussion with the the freescale rep. lead to the CSB frequency
> > of the 8313 (166MHz) being significantly lower than that of the 8343.
> > Is the CSB the critical point here?
>
> I believe the CSB is critical point here. They are right.
I have performed some additional measurements with other multiplier/divider
settings
Previous values with CSB=166MHz
> >> With the MPC8313 I get a significantly lower value:
> >> MPC8313@250MHz 12500fps
> >> MPC8313@333MHz 14500fps
> >> MPC8313@416MHz 15500fps (333MHz type, overclocked)
New value with CSB=200MHz (overclocked)
MPC8313@400MHz 17500fps
This indeed indicates that the CSB is the limiting factor.
Until a few days ago I have not even been aware of the CSB being a
performance critical component. All of the nice powerpoints explaining
the processors and used for comparing different families shown by the
Freescale Rep include the core frequencies and the DRAM interface
and frequency but do not even mention the CSB...
> > Note: the IXP42x uses an internal bus speed of 133MHz and operates
> > at frame rates similar to the 8343...
>
> It is possible, IXP42x has the differenet SoC architecture with 83xx.
That is very true indeed, then XScale (ARM) based IXP42x does have
a completely different implementation.
Best regards,
Lutz
--
Dr.-Ing. Lutz Jänicke
CTO
Innominate Security Technologies AG /protecting industrial networks/
tel: +49.30.921028-200
fax: +49.30.921028-020
Rudower Chaussee 13
D-12489 Berlin, Germany
www.innominate.com
Register Court: AG Charlottenburg, HR B 81603
Management Board: Dirk Seewald
Chairman of the Supervisory Board: Volker Bibelhausen
^ permalink raw reply
* Linux booting problem
From: Sumesh Kaana @ 2009-08-07 9:02 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 4525 bytes --]
Hi all,
I am trying to boot linux kernel (2.6.30) on a custom built board.I am using simple ppc platform and attached are my dts file and boot log..
I've 26Mb of RAM,UART and UIC with powerpc 440x5 processor.Kernel Image size is less than 1 mb.
cgc,skybeam board is added in arch/powerpc/platforms/44x/ppc44x_simple.c
device tree file as bellow:----------------------------
/dts-v1/;
/ { model = "cgc,skybeam"; compatible = "cgc,skybeam"; #address-cells = <1>; #size-cells = <1>; dcr-parent = <&SKYBEAM_PPC>; chosen { bootargs = "console=ttyS0 root=/dev/ram"; linux,stdout-path = "/plb/serial@02080000"; } ; aliases { serial0 = &STD_UART; } ; memory { device_type = "memory"; reg = < 0x0 0x01A00000 >; } ; cpus { #address-cells = <1>; #size-cells = <0>; SKYBEAM_PPC: cpu@0 { device_type = "cpu"; #address-cells = <1>; #size-cells = <1>; reg = <0>; clock-frequency = <25000000>; compatible = "PowerPC,440", "ibm,ppc440"; d-cache-line-size = <0x20>; d-cache-size = <0x8000>; dcr-access-method = "native"; dcr-controller ; i-cache-line-size = <0x20>; i-cache-size = <0x8000>; model = "PowerPC,440"; timebase-frequency = <25000000>; } ; } ; UIC0: interrupt-controller0 { compatible = "ibm,uic-440ep","ibm,uic"; interrupt-controller; cell-index = <0>; dcr-reg = <0x1c0 0x009>; #address-cells = <0>; #size-cells = <0>; #interrupt-cells = <2>; }; PLB: plb { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges ; STD_UART: serial@02080000 { device_type = "serial"; compatible = "ns16550"; reg = <0x02080000 0x00000008>; virtual-reg = <0x02080000>; clock-frequency = <125000000>; current-speed = <9600>; interrupt-parent = <&UIC0>; interrupts = <0x5 0x4>; } ; } ;} ;
boot log is as below:---------------------
zImage starting: loaded at 0x00400000 (sp: 0x004deeb0)Allocating 0x1dad84 bytes for kernel ...gunzipping (0x00000000 <- 0x0040c000:0x004dd3fc)...done 0x1c31cc bytes
Linux/PowerPC load: console=ttyS0 root=/dev/ramFinalizing device tree... flat tree at 0x4eb300Debug print:This worksDebug print:############!!!!###########Memory hole size: 0MB
Unable to handle kernel paging request for data at address 0x01a00000Faulting instruction address: 0xc0011434Oops: Kernel access of bad area, sig: 11 [#1]PREEMPT PowerPC 44x PlatformModules linked in:NIP: c0011434 LR: c010dcb0 CTR: 00000001REGS: c01bfe60 TRAP: 0300 Not tainted (2.6.30)MSR: 00021000 <ME,CE> CR: 22000024 XER: 20000000DEAR: 01a00000, ESR: 00000000TASK = c01a94b8[0] 'swapper' THREAD: c01be000GPR00: fffffff4 c01bff10 c01a94b8 01a00000 019fffff 0000000c c01958b0 00000000GPR08: 00000037 c0110000 00000042 00003fff 22000022 00000000 fffff104 00000000GPR16: 00000000 00000000 00000000 00000000 00000000 00000000 c010d750 c01958b0GPR24: 0000000c 00000000 c01a1dfc 01a00000 c01a1dfc 00003fff 0000000c 00000000NIP [c0011434] strlen+0x4/0x18LR [c010dcb0] match_token+0x1a0/0x228Call Trace:[c01bff50] [c01962f4] free_area_init_nodes+0x48/0x3a0[c01bff80] [c0191738] paging_init+0x80/0xa0[c01bffb0] [c01909b4] setup_arch+0x1c4/0x1dc[c01bffc0] [c018c648] start_kernel+0x54/0x288[c01bfff0] [c0000200] skpinv+0x190/0x1ccInstruction dump:4d820020 7ca903a6 38a3ffff 3884ffff 8c650001 2c830000 8c040001 7c6018514d860020 4102ffec 4e800020 3883ffff <8c040001> 2c000000 4082fff8 7c632050---[ end trace 31fd0ba7d8756001 ]---Kernel panic - not syncing: Attempted to kill the idle task!Call Trace:[c01bfd40] [c0005d5c] show_stack+0x4c/0x16c (unreliable)[c01bfd80] [c002f174] panic+0xa0/0x168[c01bfdd0] [c0032eb0] do_exit+0x61c/0x638[c01bfe10] [c000b60c] kernel_bad_stack+0x0/0x4c[c01bfe40] [c000f328] bad_page_fault+0x90/0xd8[c01bfe50] [c000e19c] handle_page_fault+0x7c/0x80[c01bff10] [00000000] (null)[c01bff50] [c01962f4] free_area_init_nodes+0x48/0x3a0[c01bff80] [c0191738] paging_init+0x80/0xa0[c01bffb0] [c01909b4] setup_arch+0x1c4/0x1dc[c01bffc0] [c018c648] start_kernel+0x54/0x288[c01bfff0] [c0000200] skpinv+0x190/0x1ccRebooting in 180 seconds..
Can anyone tell what would be the problem..?
thanks,Sumesh.
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^ permalink raw reply
* Re: Question about powerpc branch instructions
From: Benjamin Herrenschmidt @ 2009-08-07 8:52 UTC (permalink / raw)
To: HongWoo Lee; +Cc: linuxppc-dev
In-Reply-To: <4A7BEA04.7030006@gmail.com>
On Fri, 2009-08-07 at 17:47 +0900, HongWoo Lee wrote:
> #1: Is there any special reason to concatenate 0b00 ? Why 0b00 ??
Because instructions have to be aligned on 4 bytes boundaries ?
> #2: Is b similar to the jmp in x86 ? and bl is similar to the call in x86 ?
I'm not totally familiar with x86 but I "sounds" like it, though of
course they can be (ab)used in some more subtle ways.
Cheers,
Ben.
> Thanks in advance.
>
> HongWoo.
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