* Re: [PATCH 3/5] powerpc/5200: dts: remove unused properties
From: Grant Likely @ 2011-01-04 1:29 UTC (permalink / raw)
To: John Bonesio
Cc: jdl, glikely, devicetree-discuss, linux-kernel, linuxppc-dev,
david
In-Reply-To: <20101117232838.25947.81482.stgit@riker>
On Wed, Nov 17, 2010 at 03:28:39PM -0800, John Bonesio wrote:
> This patch remove unused properties in dts files in preparation of refactoring
> the dts files for MPC5200b based boards.
>
> Signed-off-by: John Bonesio <bones@secretlab.ca>
Applied, thanks.
g.
> ---
>
> arch/powerpc/boot/dts/cm5200.dts | 2 --
> arch/powerpc/boot/dts/lite5200b.dts | 3 ---
> arch/powerpc/boot/dts/media5200.dts | 2 --
> arch/powerpc/boot/dts/motionpro.dts | 2 --
> arch/powerpc/boot/dts/pcm030.dts | 2 --
> arch/powerpc/boot/dts/pcm032.dts | 2 --
> 6 files changed, 0 insertions(+), 13 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
> index 9369dcd..d549897 100644
> --- a/arch/powerpc/boot/dts/cm5200.dts
> +++ b/arch/powerpc/boot/dts/cm5200.dts
> @@ -230,8 +230,6 @@
> reg = <0 0 0x2000000>;
> bank-width = <2>;
> device-width = <2>;
> - #size-cells = <1>;
> - #address-cells = <1>;
> };
> };
> };
> diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
> index a74b790..c0a4e45 100644
> --- a/arch/powerpc/boot/dts/lite5200b.dts
> +++ b/arch/powerpc/boot/dts/lite5200b.dts
> @@ -174,7 +174,6 @@
>
> psc@2000 { // PSC1
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - cell-index = <0>;
> reg = <0x2000 0x100>;
> interrupts = <2 1 0>;
> };
> @@ -198,7 +197,6 @@
> // PSC4 in uart mode example
> //serial@2600 { // PSC4
> // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - // cell-index = <3>;
> // reg = <0x2600 0x100>;
> // interrupts = <2 11 0>;
> //};
> @@ -206,7 +204,6 @@
> // PSC5 in uart mode example
> //serial@2800 { // PSC5
> // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - // cell-index = <4>;
> // reg = <0x2800 0x100>;
> // interrupts = <2 12 0>;
> //};
> diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
> index a70ef68..e027f45 100644
> --- a/arch/powerpc/boot/dts/media5200.dts
> +++ b/arch/powerpc/boot/dts/media5200.dts
> @@ -185,8 +185,6 @@
> // PSC6 in uart mode
> console: psc@2c00 { // PSC6
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - cell-index = <5>;
> - port-number = <0>; // Logical port assignment
> reg = <0x2c00 0x100>;
> interrupts = <2 4 0>;
> };
> diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
> index f6261ea..3ab4666 100644
> --- a/arch/powerpc/boot/dts/motionpro.dts
> +++ b/arch/powerpc/boot/dts/motionpro.dts
> @@ -277,8 +277,6 @@
> reg = <0 0 0x01000000>;
> bank-width = <2>;
> device-width = <2>;
> - #size-cells = <1>;
> - #address-cells = <1>;
> };
> };
> };
> diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
> index 3a4f554..f3e30bb 100644
> --- a/arch/powerpc/boot/dts/pcm030.dts
> +++ b/arch/powerpc/boot/dts/pcm030.dts
> @@ -196,7 +196,6 @@
>
> psc@2400 { /* PSC3 in UART mode */
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - cell-index = <2>;
> reg = <0x2400 0x100>;
> interrupts = <2 3 0>;
> };
> @@ -207,7 +206,6 @@
>
> psc@2c00 { /* PSC6 in UART mode */
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - cell-index = <5>;
> reg = <0x2c00 0x100>;
> interrupts = <2 4 0>;
> };
> diff --git a/arch/powerpc/boot/dts/pcm032.dts b/arch/powerpc/boot/dts/pcm032.dts
> index 17596c7..e0f2702 100644
> --- a/arch/powerpc/boot/dts/pcm032.dts
> +++ b/arch/powerpc/boot/dts/pcm032.dts
> @@ -196,7 +196,6 @@
>
> psc@2400 { /* PSC3 in UART mode */
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - cell-index = <2>;
> reg = <0x2400 0x100>;
> interrupts = <2 3 0>;
> };
> @@ -207,7 +206,6 @@
>
> psc@2c00 { /* PSC6 in UART mode */
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - cell-index = <5>;
> reg = <0x2c00 0x100>;
> interrupts = <2 4 0>;
> };
>
^ permalink raw reply
* Re: [PATCH 4/5] powerpc/5200: dts: Change combatible strings on localbus
From: Grant Likely @ 2011-01-04 1:29 UTC (permalink / raw)
To: John Bonesio
Cc: jdl, glikely, devicetree-discuss, linux-kernel, linuxppc-dev,
david
In-Reply-To: <20101117232847.25947.60171.stgit@riker>
On Wed, Nov 17, 2010 at 03:28:47PM -0800, John Bonesio wrote:
> This patch changes some incorrect compatible strings on the local plus bus node
> in dts files for MPC5200b based systems.
>
> Signed-off-by: John Bonesio <bones@secretlab.ca>
> ---
Applied, thanks.
g.
>
> arch/powerpc/boot/dts/cm5200.dts | 2 +-
> arch/powerpc/boot/dts/digsy_mtc.dts | 2 +-
> arch/powerpc/boot/dts/media5200.dts | 2 +-
> arch/powerpc/boot/dts/motionpro.dts | 2 +-
> 4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
> index d549897..22f7233 100644
> --- a/arch/powerpc/boot/dts/cm5200.dts
> +++ b/arch/powerpc/boot/dts/cm5200.dts
> @@ -219,7 +219,7 @@
> };
>
> localbus {
> - compatible = "fsl,mpc5200b-lpb","simple-bus";
> + compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
> #address-cells = <2>;
> #size-cells = <1>;
> ranges = <0 0 0xfc000000 0x2000000>;
> diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts
> index f0592de..3147b98 100644
> --- a/arch/powerpc/boot/dts/digsy_mtc.dts
> +++ b/arch/powerpc/boot/dts/digsy_mtc.dts
> @@ -218,7 +218,7 @@
> };
>
> localbus {
> - compatible = "fsl,mpc5200b-lpb","simple-bus";
> + compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
> #address-cells = <2>;
> #size-cells = <1>;
> ranges = <0 0 0xff000000 0x1000000>;
> diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
> index e027f45..861f09f 100644
> --- a/arch/powerpc/boot/dts/media5200.dts
> +++ b/arch/powerpc/boot/dts/media5200.dts
> @@ -270,7 +270,7 @@
> };
>
> localbus {
> - compatible = "fsl,mpc5200b-lpb","simple-bus";
> + compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
> #address-cells = <2>;
> #size-cells = <1>;
>
> diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
> index 3ab4666..97cb085 100644
> --- a/arch/powerpc/boot/dts/motionpro.dts
> +++ b/arch/powerpc/boot/dts/motionpro.dts
> @@ -236,7 +236,7 @@
> };
>
> localbus {
> - compatible = "fsl,mpc5200b-lpb","simple-bus";
> + compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
> #address-cells = <2>;
> #size-cells = <1>;
> ranges = <0 0 0xff000000 0x01000000
>
^ permalink raw reply
* Re: [PATCH 5/5] powerpc/5200: dts: refactor dts files
From: Grant Likely @ 2011-01-04 1:31 UTC (permalink / raw)
To: John Bonesio
Cc: jdl, glikely, devicetree-discuss, linux-kernel, linuxppc-dev,
david
In-Reply-To: <20101117232856.25947.26060.stgit@riker>
On Wed, Nov 17, 2010 at 03:28:56PM -0800, John Bonesio wrote:
> This patch creates mpc5200b.dtsi containing the information for the MPC5200b
> SoC then modifies all of the dts files for MPC5200b based systems to use
> mpc5200b.dtsi.
>
> Signed-off-by: John Bonesio <bones@secretlab.ca>
Applied, thanks. I may pull it out again before I ask Linus to pull
because this patch depends on a patch that I posted today to skip
registration of disabled devices, but for the time being it is in
next-devicetree.
g.
> ---
>
> arch/powerpc/boot/dts/cm5200.dts | 196 +++----------------------
> arch/powerpc/boot/dts/digsy_mtc.dts | 173 +++-------------------
> arch/powerpc/boot/dts/lite5200b.dts | 229 ++---------------------------
> arch/powerpc/boot/dts/media5200.dts | 212 +++------------------------
> arch/powerpc/boot/dts/motionpro.dts | 190 +++---------------------
> arch/powerpc/boot/dts/mpc5200b.dtsi | 276 +++++++++++++++++++++++++++++++++++
> arch/powerpc/boot/dts/mucmc52.dts | 176 ++++++----------------
> arch/powerpc/boot/dts/pcm030.dts | 193 ++----------------------
> arch/powerpc/boot/dts/pcm032.dts | 197 +------------------------
> arch/powerpc/boot/dts/uc101.dts | 162 ++++-----------------
> 10 files changed, 486 insertions(+), 1518 deletions(-)
> create mode 100644 arch/powerpc/boot/dts/mpc5200b.dtsi
>
> diff --git a/arch/powerpc/boot/dts/cm5200.dts b/arch/powerpc/boot/dts/cm5200.dts
> index 22f7233..c6d5d46 100644
> --- a/arch/powerpc/boot/dts/cm5200.dts
> +++ b/arch/powerpc/boot/dts/cm5200.dts
> @@ -10,226 +10,78 @@
> * option) any later version.
> */
>
> -/dts-v1/;
> +/include/ "mpc5200b.dtsi"
>
> / {
> model = "schindler,cm5200";
> compatible = "schindler,cm5200";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - interrupt-parent = <&mpc5200_pic>;
> -
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - PowerPC,5200@0 {
> - device_type = "cpu";
> - reg = <0>;
> - d-cache-line-size = <32>;
> - i-cache-line-size = <32>;
> - d-cache-size = <0x4000>; // L1, 16K
> - i-cache-size = <0x4000>; // L1, 16K
> - timebase-frequency = <0>; // from bootloader
> - bus-frequency = <0>; // from bootloader
> - clock-frequency = <0>; // from bootloader
> - };
> - };
> -
> - memory {
> - device_type = "memory";
> - reg = <0x00000000 0x04000000>; // 64MB
> - };
>
> soc5200@f0000000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,mpc5200b-immr";
> - ranges = <0 0xf0000000 0x0000c000>;
> - reg = <0xf0000000 0x00000100>;
> - bus-frequency = <0>; // from bootloader
> - system-frequency = <0>; // from bootloader
> -
> - cdm@200 {
> - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
> - reg = <0x200 0x38>;
> - };
> -
> - mpc5200_pic: interrupt-controller@500 {
> - // 5200 interrupts are encoded into two levels;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
> - reg = <0x500 0x80>;
> - };
> -
> timer@600 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x600 0x10>;
> - interrupts = <1 9 0>;
> fsl,has-wdt;
> };
>
> - timer@610 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x610 0x10>;
> - interrupts = <1 10 0>;
> - };
> -
> - timer@620 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x620 0x10>;
> - interrupts = <1 11 0>;
> - };
> -
> - timer@630 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x630 0x10>;
> - interrupts = <1 12 0>;
> - };
> -
> - timer@640 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x640 0x10>;
> - interrupts = <1 13 0>;
> - };
> -
> - timer@650 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x650 0x10>;
> - interrupts = <1 14 0>;
> - };
> -
> - timer@660 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x660 0x10>;
> - interrupts = <1 15 0>;
> - };
> -
> - timer@670 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x670 0x10>;
> - interrupts = <1 16 0>;
> - };
> -
> - rtc@800 { // Real time clock
> - compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
> - reg = <0x800 0x100>;
> - interrupts = <1 5 0 1 6 0>;
> - };
> -
> - gpio_simple: gpio@b00 {
> - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
> - reg = <0xb00 0x40>;
> - interrupts = <1 7 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> -
> - gpio_wkup: gpio@c00 {
> - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
> - reg = <0xc00 0x40>;
> - interrupts = <1 8 0 0 3 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> -
> - spi@f00 {
> - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
> - reg = <0xf00 0x20>;
> - interrupts = <2 13 0 2 14 0>;
> - };
> -
> - usb@1000 {
> - compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
> - reg = <0x1000 0xff>;
> - interrupts = <2 6 0>;
> - };
> -
> - dma-controller@1200 {
> - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
> - reg = <0x1200 0x80>;
> - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
> - 3 4 0 3 5 0 3 6 0 3 7 0
> - 3 8 0 3 9 0 3 10 0 3 11 0
> - 3 12 0 3 13 0 3 14 0 3 15 0>;
> + can@900 {
> + status = "disabled";
> };
>
> - xlb@1f00 {
> - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
> - reg = <0x1f00 0x100>;
> + can@980 {
> + status = "disabled";
> };
>
> psc@2000 { // PSC1
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2000 0x100>;
> - interrupts = <2 1 0>;
> };
>
> psc@2200 { // PSC2
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2200 0x100>;
> - interrupts = <2 2 0>;
> };
>
> psc@2400 { // PSC3
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2400 0x100>;
> - interrupts = <2 3 0>;
> };
>
> - psc@2c00 { // PSC6
> - compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2c00 0x100>;
> - interrupts = <2 4 0>;
> + psc@2600 { // PSC4
> + status = "disabled";
> };
>
> - ethernet@3000 {
> - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
> - reg = <0x3000 0x400>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupts = <2 5 0>;
> - phy-handle = <&phy0>;
> + psc@2800 { // PSC5
> + status = "disabled";
> };
>
> - mdio@3000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
> - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
> - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
> + psc@2c00 { // PSC6
> + compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> + };
>
> + mdio@3000 {
> phy0: ethernet-phy@0 {
> reg = <0>;
> };
> };
>
> - i2c@3d40 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> - reg = <0x3d40 0x40>;
> - interrupts = <2 16 0>;
> + ata@3a00 {
> + status = "disabled";
> };
>
> - sram@8000 {
> - compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
> - reg = <0x8000 0x4000>;
> + i2c@3d00 {
> + status = "disabled";
> };
> +
> };
>
> - localbus {
> - compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
> - #address-cells = <2>;
> - #size-cells = <1>;
> - ranges = <0 0 0xfc000000 0x2000000>;
> + pci@f0000d00 {
> + status = "disabled";
> + };
>
> + localbus {
> // 16-bit flash device at LocalPlus Bus CS0
> flash@0,0 {
> compatible = "cfi-flash";
> reg = <0 0 0x2000000>;
> bank-width = <2>;
> device-width = <2>;
> + #size-cells = <1>;
> + #address-cells = <1>;
> };
> };
> };
> diff --git a/arch/powerpc/boot/dts/digsy_mtc.dts b/arch/powerpc/boot/dts/digsy_mtc.dts
> index 3147b98..a12b587 100644
> --- a/arch/powerpc/boot/dts/digsy_mtc.dts
> +++ b/arch/powerpc/boot/dts/digsy_mtc.dts
> @@ -11,195 +11,64 @@
> * option) any later version.
> */
>
> -/dts-v1/;
> +/include/ "mpc5200b.dtsi"
>
> / {
> model = "intercontrol,digsy-mtc";
> compatible = "intercontrol,digsy-mtc";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - interrupt-parent = <&mpc5200_pic>;
> -
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - PowerPC,5200@0 {
> - device_type = "cpu";
> - reg = <0>;
> - d-cache-line-size = <32>;
> - i-cache-line-size = <32>;
> - d-cache-size = <0x4000>; // L1, 16K
> - i-cache-size = <0x4000>; // L1, 16K
> - timebase-frequency = <0>; // from bootloader
> - bus-frequency = <0>; // from bootloader
> - clock-frequency = <0>; // from bootloader
> - };
> - };
>
> memory {
> - device_type = "memory";
> reg = <0x00000000 0x02000000>; // 32MB
> };
>
> soc5200@f0000000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,mpc5200b-immr";
> - ranges = <0 0xf0000000 0x0000c000>;
> - reg = <0xf0000000 0x00000100>;
> - bus-frequency = <0>; // from bootloader
> - system-frequency = <0>; // from bootloader
> -
> - cdm@200 {
> - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
> - reg = <0x200 0x38>;
> - };
> -
> - mpc5200_pic: interrupt-controller@500 {
> - // 5200 interrupts are encoded into two levels;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
> - reg = <0x500 0x80>;
> - };
> -
> timer@600 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x600 0x10>;
> - interrupts = <1 9 0>;
> fsl,has-wdt;
> };
>
> - timer@610 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x610 0x10>;
> - interrupts = <1 10 0>;
> - };
> -
> - timer@620 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x620 0x10>;
> - interrupts = <1 11 0>;
> - };
> -
> - timer@630 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x630 0x10>;
> - interrupts = <1 12 0>;
> - };
> -
> - timer@640 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x640 0x10>;
> - interrupts = <1 13 0>;
> - };
> -
> - timer@650 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x650 0x10>;
> - interrupts = <1 14 0>;
> + rtc@800 {
> + status = "disabled";
> };
>
> - timer@660 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x660 0x10>;
> - interrupts = <1 15 0>;
> + can@900 {
> + status = "disabled";
> };
>
> - timer@670 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x670 0x10>;
> - interrupts = <1 16 0>;
> + can@980 {
> + status = "disabled";
> };
>
> - gpio_simple: gpio@b00 {
> - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
> - reg = <0xb00 0x40>;
> - interrupts = <1 7 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> + psc@2000 { // PSC1
> + status = "disabled";
> };
>
> - gpio_wkup: gpio@c00 {
> - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
> - reg = <0xc00 0x40>;
> - interrupts = <1 8 0 0 3 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> + psc@2200 { // PSC2
> + status = "disabled";
> };
>
> - spi@f00 {
> - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
> - reg = <0xf00 0x20>;
> - interrupts = <2 13 0 2 14 0>;
> - };
> -
> - usb@1000 {
> - compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
> - reg = <0x1000 0xff>;
> - interrupts = <2 6 0>;
> - };
> -
> - dma-controller@1200 {
> - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
> - reg = <0x1200 0x80>;
> - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
> - 3 4 0 3 5 0 3 6 0 3 7 0
> - 3 8 0 3 9 0 3 10 0 3 11 0
> - 3 12 0 3 13 0 3 14 0 3 15 0>;
> - };
> -
> - xlb@1f00 {
> - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
> - reg = <0x1f00 0x100>;
> + psc@2400 { // PSC3
> + status = "disabled";
> };
>
> psc@2600 { // PSC4
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2600 0x100>;
> - interrupts = <2 11 0>;
> };
>
> psc@2800 { // PSC5
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2800 0x100>;
> - interrupts = <2 12 0>;
> };
>
> - ethernet@3000 {
> - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
> - reg = <0x3000 0x400>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupts = <2 5 0>;
> - phy-handle = <&phy0>;
> + psc@2c00 { // PSC6
> + status = "disabled";
> };
>
> mdio@3000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
> - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
> - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
> -
> phy0: ethernet-phy@0 {
> reg = <0>;
> };
> };
>
> - ata@3a00 {
> - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
> - reg = <0x3a00 0x100>;
> - interrupts = <2 7 0>;
> - };
> -
> i2c@3d00 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> - reg = <0x3d00 0x40>;
> - interrupts = <2 15 0>;
> -
> rtc@50 {
> compatible = "at,24c08";
> reg = <0x50>;
> @@ -211,16 +80,16 @@
> };
> };
>
> - sram@8000 {
> - compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
> - reg = <0x8000 0x4000>;
> + i2c@3d40 {
> + status = "disabled";
> };
> };
>
> + pci@f0000d00 {
> + status = "disabled";
> + };
> +
> localbus {
> - compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
> - #address-cells = <2>;
> - #size-cells = <1>;
> ranges = <0 0 0xff000000 0x1000000>;
>
> // 16-bit flash device at LocalPlus Bus CS0
> diff --git a/arch/powerpc/boot/dts/lite5200b.dts b/arch/powerpc/boot/dts/lite5200b.dts
> index c0a4e45..8d15dfd 100644
> --- a/arch/powerpc/boot/dts/lite5200b.dts
> +++ b/arch/powerpc/boot/dts/lite5200b.dts
> @@ -10,253 +10,71 @@
> * option) any later version.
> */
>
> -/dts-v1/;
> +/include/ "mpc5200b.dtsi"
>
> / {
> model = "fsl,lite5200b";
> compatible = "fsl,lite5200b";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - interrupt-parent = <&mpc5200_pic>;
> -
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - PowerPC,5200@0 {
> - device_type = "cpu";
> - reg = <0>;
> - d-cache-line-size = <32>;
> - i-cache-line-size = <32>;
> - d-cache-size = <0x4000>; // L1, 16K
> - i-cache-size = <0x4000>; // L1, 16K
> - timebase-frequency = <0>; // from bootloader
> - bus-frequency = <0>; // from bootloader
> - clock-frequency = <0>; // from bootloader
> - };
> - };
>
> memory {
> - device_type = "memory";
> reg = <0x00000000 0x10000000>; // 256MB
> };
>
> soc5200@f0000000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,mpc5200b-immr";
> - ranges = <0 0xf0000000 0x0000c000>;
> - reg = <0xf0000000 0x00000100>;
> - bus-frequency = <0>; // from bootloader
> - system-frequency = <0>; // from bootloader
> -
> - cdm@200 {
> - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
> - reg = <0x200 0x38>;
> - };
> -
> - mpc5200_pic: interrupt-controller@500 {
> - // 5200 interrupts are encoded into two levels;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
> - reg = <0x500 0x80>;
> - };
> -
> timer@600 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x600 0x10>;
> - interrupts = <1 9 0>;
> fsl,has-wdt;
> };
>
> - timer@610 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x610 0x10>;
> - interrupts = <1 10 0>;
> - };
> -
> - timer@620 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x620 0x10>;
> - interrupts = <1 11 0>;
> - };
> -
> - timer@630 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x630 0x10>;
> - interrupts = <1 12 0>;
> - };
> -
> - timer@640 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x640 0x10>;
> - interrupts = <1 13 0>;
> - };
> -
> - timer@650 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x650 0x10>;
> - interrupts = <1 14 0>;
> - };
> -
> - timer@660 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x660 0x10>;
> - interrupts = <1 15 0>;
> - };
> -
> - timer@670 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x670 0x10>;
> - interrupts = <1 16 0>;
> - };
> -
> - rtc@800 { // Real time clock
> - compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
> - reg = <0x800 0x100>;
> - interrupts = <1 5 0 1 6 0>;
> - };
> -
> - can@900 {
> - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
> - interrupts = <2 17 0>;
> - reg = <0x900 0x80>;
> - };
> -
> - can@980 {
> - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
> - interrupts = <2 18 0>;
> - reg = <0x980 0x80>;
> - };
> -
> - gpio_simple: gpio@b00 {
> - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
> - reg = <0xb00 0x40>;
> - interrupts = <1 7 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> -
> - gpio_wkup: gpio@c00 {
> - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
> - reg = <0xc00 0x40>;
> - interrupts = <1 8 0 0 3 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> + psc@2000 { // PSC1
> + compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> + cell-index = <0>;
> };
>
> - spi@f00 {
> - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
> - reg = <0xf00 0x20>;
> - interrupts = <2 13 0 2 14 0>;
> + psc@2200 { // PSC2
> + status = "disabled";
> };
>
> - usb@1000 {
> - compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
> - reg = <0x1000 0xff>;
> - interrupts = <2 6 0>;
> + psc@2400 { // PSC3
> + status = "disabled";
> };
>
> - dma-controller@1200 {
> - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
> - reg = <0x1200 0x80>;
> - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
> - 3 4 0 3 5 0 3 6 0 3 7 0
> - 3 8 0 3 9 0 3 10 0 3 11 0
> - 3 12 0 3 13 0 3 14 0 3 15 0>;
> + psc@2600 { // PSC4
> + status = "disabled";
> };
>
> - xlb@1f00 {
> - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
> - reg = <0x1f00 0x100>;
> + psc@2800 { // PSC5
> + status = "disabled";
> };
>
> - psc@2000 { // PSC1
> - compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2000 0x100>;
> - interrupts = <2 1 0>;
> + psc@2c00 { // PSC6
> + status = "disabled";
> };
>
> // PSC2 in ac97 mode example
> //ac97@2200 { // PSC2
> // compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
> // cell-index = <1>;
> - // reg = <0x2200 0x100>;
> - // interrupts = <2 2 0>;
> //};
>
> // PSC3 in CODEC mode example
> //i2s@2400 { // PSC3
> // compatible = "fsl,mpc5200b-psc-i2s"; //not 5200 compatible
> // cell-index = <2>;
> - // reg = <0x2400 0x100>;
> - // interrupts = <2 3 0>;
> - //};
> -
> - // PSC4 in uart mode example
> - //serial@2600 { // PSC4
> - // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - // reg = <0x2600 0x100>;
> - // interrupts = <2 11 0>;
> - //};
> -
> - // PSC5 in uart mode example
> - //serial@2800 { // PSC5
> - // compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - // reg = <0x2800 0x100>;
> - // interrupts = <2 12 0>;
> //};
>
> // PSC6 in spi mode example
> //spi@2c00 { // PSC6
> // compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
> // cell-index = <5>;
> - // reg = <0x2c00 0x100>;
> - // interrupts = <2 4 0>;
> //};
>
> - ethernet@3000 {
> - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
> - reg = <0x3000 0x400>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupts = <2 5 0>;
> - phy-handle = <&phy0>;
> - };
> -
> mdio@3000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
> - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
> - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
> -
> phy0: ethernet-phy@0 {
> reg = <0>;
> };
> };
>
> - ata@3a00 {
> - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
> - reg = <0x3a00 0x100>;
> - interrupts = <2 7 0>;
> - };
> -
> - i2c@3d00 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> - reg = <0x3d00 0x40>;
> - interrupts = <2 15 0>;
> - };
> -
> i2c@3d40 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> - reg = <0x3d40 0x40>;
> - interrupts = <2 16 0>;
> -
> eeprom@50 {
> compatible = "atmel,24c02";
> reg = <0x50>;
> @@ -270,12 +88,6 @@
> };
>
> pci@f0000d00 {
> - #interrupt-cells = <1>;
> - #size-cells = <2>;
> - #address-cells = <3>;
> - device_type = "pci";
> - compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
> - reg = <0xf0000d00 0x100>;
> interrupt-map-mask = <0xf800 0 0 7>;
> interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
> 0xc000 0 0 2 &mpc5200_pic 1 1 3
> @@ -295,19 +107,14 @@
> };
>
> localbus {
> - compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
> -
> - #address-cells = <2>;
> - #size-cells = <1>;
> -
> ranges = <0 0 0xfe000000 0x02000000>;
>
> flash@0,0 {
> compatible = "cfi-flash";
> - reg = <0 0 0x02000000>;
> - bank-width = <1>;
> - #size-cells = <1>;
> - #address-cells = <1>;
> + reg = <0 0 0x02000000>;
> + bank-width = <1>;
> + #size-cells = <1>;
> + #address-cells = <1>;
>
> partition@0 {
> label = "kernel";
> diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
> index 861f09f..84558f8 100644
> --- a/arch/powerpc/boot/dts/media5200.dts
> +++ b/arch/powerpc/boot/dts/media5200.dts
> @@ -11,14 +11,11 @@
> * option) any later version.
> */
>
> -/dts-v1/;
> +/include/ "mpc5200b.dtsi"
>
> / {
> model = "fsl,media5200";
> compatible = "fsl,media5200";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - interrupt-parent = <&mpc5200_pic>;
>
> aliases {
> console = &console;
> @@ -30,16 +27,7 @@
> };
>
> cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> PowerPC,5200@0 {
> - device_type = "cpu";
> - reg = <0>;
> - d-cache-line-size = <32>;
> - i-cache-line-size = <32>;
> - d-cache-size = <0x4000>; // L1, 16K
> - i-cache-size = <0x4000>; // L1, 16K
> timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
> bus-frequency = <132000000>; // 132 MHz
> clock-frequency = <396000000>; // 396 MHz
> @@ -47,203 +35,53 @@
> };
>
> memory {
> - device_type = "memory";
> reg = <0x00000000 0x08000000>; // 128MB RAM
> };
>
> - soc@f0000000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,mpc5200b-immr";
> - ranges = <0 0xf0000000 0x0000c000>;
> - reg = <0xf0000000 0x00000100>;
> + soc5200@f0000000 {
> bus-frequency = <132000000>;// 132 MHz
> - system-frequency = <0>; // from bootloader
> -
> - cdm@200 {
> - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
> - reg = <0x200 0x38>;
> - };
> -
> - mpc5200_pic: interrupt-controller@500 {
> - // 5200 interrupts are encoded into two levels;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
> - reg = <0x500 0x80>;
> - };
>
> timer@600 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x600 0x10>;
> - interrupts = <1 9 0>;
> fsl,has-wdt;
> };
>
> - timer@610 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x610 0x10>;
> - interrupts = <1 10 0>;
> - };
> -
> - timer@620 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x620 0x10>;
> - interrupts = <1 11 0>;
> - };
> -
> - timer@630 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x630 0x10>;
> - interrupts = <1 12 0>;
> - };
> -
> - timer@640 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x640 0x10>;
> - interrupts = <1 13 0>;
> + psc@2000 { // PSC1
> + status = "disabled";
> };
>
> - timer@650 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x650 0x10>;
> - interrupts = <1 14 0>;
> + psc@2200 { // PSC2
> + status = "disabled";
> };
>
> - timer@660 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x660 0x10>;
> - interrupts = <1 15 0>;
> + psc@2400 { // PSC3
> + status = "disabled";
> };
>
> - timer@670 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x670 0x10>;
> - interrupts = <1 16 0>;
> + psc@2600 { // PSC4
> + status = "disabled";
> };
>
> - rtc@800 { // Real time clock
> - compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
> - reg = <0x800 0x100>;
> - interrupts = <1 5 0 1 6 0>;
> - };
> -
> - can@900 {
> - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
> - interrupts = <2 17 0>;
> - reg = <0x900 0x80>;
> - };
> -
> - can@980 {
> - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
> - interrupts = <2 18 0>;
> - reg = <0x980 0x80>;
> - };
> -
> - gpio_simple: gpio@b00 {
> - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
> - reg = <0xb00 0x40>;
> - interrupts = <1 7 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> -
> - gpio_wkup: gpio@c00 {
> - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
> - reg = <0xc00 0x40>;
> - interrupts = <1 8 0 0 3 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> -
> - spi@f00 {
> - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
> - reg = <0xf00 0x20>;
> - interrupts = <2 13 0 2 14 0>;
> - };
> -
> - usb@1000 {
> - compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
> - reg = <0x1000 0x100>;
> - interrupts = <2 6 0>;
> - };
> -
> - dma-controller@1200 {
> - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
> - reg = <0x1200 0x80>;
> - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
> - 3 4 0 3 5 0 3 6 0 3 7 0
> - 3 8 0 3 9 0 3 10 0 3 11 0
> - 3 12 0 3 13 0 3 14 0 3 15 0>;
> - };
> -
> - xlb@1f00 {
> - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
> - reg = <0x1f00 0x100>;
> + psc@2800 { // PSC5
> + status = "disabled";
> };
>
> // PSC6 in uart mode
> console: psc@2c00 { // PSC6
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2c00 0x100>;
> - interrupts = <2 4 0>;
> - };
> -
> - eth0: ethernet@3000 {
> - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
> - reg = <0x3000 0x400>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupts = <2 5 0>;
> - phy-handle = <&phy0>;
> };
>
> mdio@3000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
> - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
> - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
> -
> phy0: ethernet-phy@0 {
> reg = <0>;
> };
> };
>
> - ata@3a00 {
> - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
> - reg = <0x3a00 0x100>;
> - interrupts = <2 7 0>;
> - };
> -
> - i2c@3d00 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> - reg = <0x3d00 0x40>;
> - interrupts = <2 15 0>;
> - };
> -
> - i2c@3d40 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> - reg = <0x3d40 0x40>;
> - interrupts = <2 16 0>;
> - };
> -
> - sram@8000 {
> - compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
> - reg = <0x8000 0x4000>;
> + usb@1000 {
> + reg = <0x1000 0x100>;
> };
> };
>
> pci@f0000d00 {
> - #interrupt-cells = <1>;
> - #size-cells = <2>;
> - #address-cells = <3>;
> - device_type = "pci";
> - compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
> - reg = <0xf0000d00 0x100>;
> interrupt-map-mask = <0xf800 0 0 7>;
> interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
> 0xc000 0 0 2 &media5200_fpga 0 3
> @@ -260,37 +98,29 @@
>
> 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
> >;
> - clock-frequency = <0>; // From boot loader
> - interrupts = <2 8 0 2 9 0 2 10 0>;
> - interrupt-parent = <&mpc5200_pic>;
> - bus-range = <0 0>;
> ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
> 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
> 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
> + interrupt-parent = <&mpc5200_pic>;
> };
>
> localbus {
> - compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
> - #address-cells = <2>;
> - #size-cells = <1>;
> -
> ranges = < 0 0 0xfc000000 0x02000000
> 1 0 0xfe000000 0x02000000
> 2 0 0xf0010000 0x00010000
> 3 0 0xf0020000 0x00010000 >;
> -
> flash@0,0 {
> compatible = "amd,am29lv28ml", "cfi-flash";
> - reg = <0 0x0 0x2000000>; // 32 MB
> - bank-width = <4>; // Width in bytes of the flash bank
> - device-width = <2>; // Two devices on each bank
> + reg = <0 0x0 0x2000000>; // 32 MB
> + bank-width = <4>; // Width in bytes of the flash bank
> + device-width = <2>; // Two devices on each bank
> };
>
> flash@1,0 {
> compatible = "amd,am29lv28ml", "cfi-flash";
> - reg = <1 0 0x2000000>; // 32 MB
> - bank-width = <4>; // Width in bytes of the flash bank
> - device-width = <2>; // Two devices on each bank
> + reg = <1 0 0x2000000>; // 32 MB
> + bank-width = <4>; // Width in bytes of the flash bank
> + device-width = <2>; // Two devices on each bank
> };
>
> media5200_fpga: fpga@2,0 {
> diff --git a/arch/powerpc/boot/dts/motionpro.dts b/arch/powerpc/boot/dts/motionpro.dts
> index 97cb085..2276ccd 100644
> --- a/arch/powerpc/boot/dts/motionpro.dts
> +++ b/arch/powerpc/boot/dts/motionpro.dts
> @@ -10,219 +10,69 @@
> * option) any later version.
> */
>
> -/dts-v1/;
> +/include/ "mpc5200b.dtsi"
>
> / {
> model = "promess,motionpro";
> compatible = "promess,motionpro";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - interrupt-parent = <&mpc5200_pic>;
> -
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - PowerPC,5200@0 {
> - device_type = "cpu";
> - reg = <0>;
> - d-cache-line-size = <32>;
> - i-cache-line-size = <32>;
> - d-cache-size = <0x4000>; // L1, 16K
> - i-cache-size = <0x4000>; // L1, 16K
> - timebase-frequency = <0>; // from bootloader
> - bus-frequency = <0>; // from bootloader
> - clock-frequency = <0>; // from bootloader
> - };
> - };
> -
> - memory {
> - device_type = "memory";
> - reg = <0x00000000 0x04000000>; // 64MB
> - };
>
> soc5200@f0000000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,mpc5200b-immr";
> - ranges = <0 0xf0000000 0x0000c000>;
> - reg = <0xf0000000 0x00000100>;
> - bus-frequency = <0>; // from bootloader
> - system-frequency = <0>; // from bootloader
> -
> - cdm@200 {
> - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
> - reg = <0x200 0x38>;
> - };
> -
> - mpc5200_pic: interrupt-controller@500 {
> - // 5200 interrupts are encoded into two levels;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
> - reg = <0x500 0x80>;
> - };
> -
> timer@600 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x600 0x10>;
> - interrupts = <1 9 0>;
> fsl,has-wdt;
> };
>
> - timer@610 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x610 0x10>;
> - interrupts = <1 10 0>;
> - };
> -
> - timer@620 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x620 0x10>;
> - interrupts = <1 11 0>;
> - };
> -
> - timer@630 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x630 0x10>;
> - interrupts = <1 12 0>;
> - };
> -
> - timer@640 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x640 0x10>;
> - interrupts = <1 13 0>;
> - };
> -
> - timer@650 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x650 0x10>;
> - interrupts = <1 14 0>;
> - };
> -
> timer@660 { // Motion-PRO status LED
> compatible = "promess,motionpro-led";
> label = "motionpro-statusled";
> - reg = <0x660 0x10>;
> - interrupts = <1 15 0>;
> blink-delay = <100>; // 100 msec
> };
>
> timer@670 { // Motion-PRO ready LED
> compatible = "promess,motionpro-led";
> label = "motionpro-readyled";
> - reg = <0x670 0x10>;
> - interrupts = <1 16 0>;
> };
>
> - rtc@800 { // Real time clock
> - compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
> - reg = <0x800 0x100>;
> - interrupts = <1 5 0 1 6 0>;
> - };
> -
> - can@980 {
> - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
> - interrupts = <2 18 0>;
> - reg = <0x980 0x80>;
> - };
> -
> - gpio_simple: gpio@b00 {
> - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
> - reg = <0xb00 0x40>;
> - interrupts = <1 7 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> -
> - gpio_wkup: gpio@c00 {
> - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
> - reg = <0xc00 0x40>;
> - interrupts = <1 8 0 0 3 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> -
> - spi@f00 {
> - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
> - reg = <0xf00 0x20>;
> - interrupts = <2 13 0 2 14 0>;
> - };
> -
> - usb@1000 {
> - compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
> - reg = <0x1000 0xff>;
> - interrupts = <2 6 0>;
> - };
> -
> - dma-controller@1200 {
> - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
> - reg = <0x1200 0x80>;
> - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
> - 3 4 0 3 5 0 3 6 0 3 7 0
> - 3 8 0 3 9 0 3 10 0 3 11 0
> - 3 12 0 3 13 0 3 14 0 3 15 0>;
> - };
> -
> - xlb@1f00 {
> - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
> - reg = <0x1f00 0x100>;
> + can@900 {
> + status = "disabled";
> };
>
> psc@2000 { // PSC1
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2000 0x100>;
> - interrupts = <2 1 0>;
> };
>
> // PSC2 in spi master mode
> psc@2200 { // PSC2
> compatible = "fsl,mpc5200b-psc-spi","fsl,mpc5200-psc-spi";
> cell-index = <1>;
> - reg = <0x2200 0x100>;
> - interrupts = <2 2 0>;
> };
>
> - // PSC5 in uart mode
> + psc@2400 { // PSC3
> + status = "disabled";
> + };
> +
> + psc@2600 { // PSC4
> + status = "disabled";
> + };
> +
> psc@2800 { // PSC5
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2800 0x100>;
> - interrupts = <2 12 0>;
> };
>
> - ethernet@3000 {
> - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
> - reg = <0x3000 0x400>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupts = <2 5 0>;
> - phy-handle = <&phy0>;
> + psc@2c00 { // PSC6
> + status = "disabled";
> };
>
> mdio@3000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
> - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
> - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
> -
> phy0: ethernet-phy@2 {
> reg = <2>;
> };
> };
>
> - ata@3a00 {
> - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
> - reg = <0x3a00 0x100>;
> - interrupts = <2 7 0>;
> + i2c@3d00 {
> + status = "disabled";
> };
>
> i2c@3d40 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> - reg = <0x3d40 0x40>;
> - interrupts = <2 16 0>;
> -
> rtc@68 {
> compatible = "dallas,ds1339";
> reg = <0x68>;
> @@ -235,10 +85,11 @@
> };
> };
>
> + pci@f0000d00 {
> + status = "disabled";
> + };
> +
> localbus {
> - compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
> - #address-cells = <2>;
> - #size-cells = <1>;
> ranges = <0 0 0xff000000 0x01000000
> 1 0 0x50000000 0x00010000
> 2 0 0x50010000 0x00010000
> @@ -277,6 +128,9 @@
> reg = <0 0 0x01000000>;
> bank-width = <2>;
> device-width = <2>;
> + #size-cells = <1>;
> + #address-cells = <1>;
> };
> +
> };
> };
> diff --git a/arch/powerpc/boot/dts/mpc5200b.dtsi b/arch/powerpc/boot/dts/mpc5200b.dtsi
> new file mode 100644
> index 0000000..62cb4c9
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/mpc5200b.dtsi
> @@ -0,0 +1,276 @@
> +/*
> + * base MPC5200b Device Tree Source
> + *
> + * Copyright (C) 2010 SecretLab
> + * Grant Likely <grant@secretlab.ca>
> + * John Bonesio <bones@secretlab.ca>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +/dts-v1/;
> +
> +/ {
> + model = "fsl,mpc5200b";
> + compatible = "fsl,mpc5200b";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&mpc5200_pic>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + powerpc: PowerPC,5200@0 {
> + device_type = "cpu";
> + reg = <0>;
> + d-cache-line-size = <32>;
> + i-cache-line-size = <32>;
> + d-cache-size = <0x4000>; // L1, 16K
> + i-cache-size = <0x4000>; // L1, 16K
> + timebase-frequency = <0>; // from bootloader
> + bus-frequency = <0>; // from bootloader
> + clock-frequency = <0>; // from bootloader
> + };
> + };
> +
> + memory: memory {
> + device_type = "memory";
> + reg = <0x00000000 0x04000000>; // 64MB
> + };
> +
> + soc: soc5200@f0000000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "fsl,mpc5200b-immr";
> + ranges = <0 0xf0000000 0x0000c000>;
> + reg = <0xf0000000 0x00000100>;
> + bus-frequency = <0>; // from bootloader
> + system-frequency = <0>; // from bootloader
> +
> + cdm@200 {
> + compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
> + reg = <0x200 0x38>;
> + };
> +
> + mpc5200_pic: interrupt-controller@500 {
> + // 5200 interrupts are encoded into two levels;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
> + reg = <0x500 0x80>;
> + };
> +
> + timer@600 { // General Purpose Timer
> + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> + reg = <0x600 0x10>;
> + interrupts = <1 9 0>;
> + };
> +
> + timer@610 { // General Purpose Timer
> + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> + reg = <0x610 0x10>;
> + interrupts = <1 10 0>;
> + };
> +
> + timer@620 { // General Purpose Timer
> + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> + reg = <0x620 0x10>;
> + interrupts = <1 11 0>;
> + };
> +
> + timer@630 { // General Purpose Timer
> + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> + reg = <0x630 0x10>;
> + interrupts = <1 12 0>;
> + };
> +
> + timer@640 { // General Purpose Timer
> + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> + reg = <0x640 0x10>;
> + interrupts = <1 13 0>;
> + };
> +
> + timer@650 { // General Purpose Timer
> + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> + reg = <0x650 0x10>;
> + interrupts = <1 14 0>;
> + };
> +
> + timer@660 { // General Purpose Timer
> + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> + reg = <0x660 0x10>;
> + interrupts = <1 15 0>;
> + };
> +
> + timer@670 { // General Purpose Timer
> + compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> + reg = <0x670 0x10>;
> + interrupts = <1 16 0>;
> + };
> +
> + rtc@800 { // Real time clock
> + compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
> + reg = <0x800 0x100>;
> + interrupts = <1 5 0 1 6 0>;
> + };
> +
> + can@900 {
> + compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
> + interrupts = <2 17 0>;
> + reg = <0x900 0x80>;
> + };
> +
> + can@980 {
> + compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
> + interrupts = <2 18 0>;
> + reg = <0x980 0x80>;
> + };
> +
> + gpio_simple: gpio@b00 {
> + compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
> + reg = <0xb00 0x40>;
> + interrupts = <1 7 0>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + gpio_wkup: gpio@c00 {
> + compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
> + reg = <0xc00 0x40>;
> + interrupts = <1 8 0 0 3 0>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + spi@f00 {
> + compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
> + reg = <0xf00 0x20>;
> + interrupts = <2 13 0 2 14 0>;
> + };
> +
> + usb: usb@1000 {
> + compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
> + reg = <0x1000 0xff>;
> + interrupts = <2 6 0>;
> + };
> +
> + dma-controller@1200 {
> + compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
> + reg = <0x1200 0x80>;
> + interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
> + 3 4 0 3 5 0 3 6 0 3 7 0
> + 3 8 0 3 9 0 3 10 0 3 11 0
> + 3 12 0 3 13 0 3 14 0 3 15 0>;
> + };
> +
> + xlb@1f00 {
> + compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
> + reg = <0x1f00 0x100>;
> + };
> +
> + psc1: psc@2000 { // PSC1
> + compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
> + reg = <0x2000 0x100>;
> + interrupts = <2 1 0>;
> + };
> +
> + psc2: psc@2200 { // PSC2
> + compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
> + reg = <0x2200 0x100>;
> + interrupts = <2 2 0>;
> + };
> +
> + psc3: psc@2400 { // PSC3
> + compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
> + reg = <0x2400 0x100>;
> + interrupts = <2 3 0>;
> + };
> +
> + psc4: psc@2600 { // PSC4
> + compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
> + reg = <0x2600 0x100>;
> + interrupts = <2 11 0>;
> + };
> +
> + psc5: psc@2800 { // PSC5
> + compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
> + reg = <0x2800 0x100>;
> + interrupts = <2 12 0>;
> + };
> +
> + psc6: psc@2c00 { // PSC6
> + compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc";
> + reg = <0x2c00 0x100>;
> + interrupts = <2 4 0>;
> + };
> +
> + eth0: ethernet@3000 {
> + compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
> + reg = <0x3000 0x400>;
> + local-mac-address = [ 00 00 00 00 00 00 ];
> + interrupts = <2 5 0>;
> + phy-handle = <&phy0>;
> + };
> +
> + mdio@3000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
> + reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
> + interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
> + };
> +
> + ata@3a00 {
> + compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
> + reg = <0x3a00 0x100>;
> + interrupts = <2 7 0>;
> + };
> +
> + i2c@3d00 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> + reg = <0x3d00 0x40>;
> + interrupts = <2 15 0>;
> + };
> +
> + i2c@3d40 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> + reg = <0x3d40 0x40>;
> + interrupts = <2 16 0>;
> + };
> +
> + sram@8000 {
> + compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
> + reg = <0x8000 0x4000>;
> + };
> + };
> +
> + pci: pci@f0000d00 {
> + #interrupt-cells = <1>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> + device_type = "pci";
> + compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
> + reg = <0xf0000d00 0x100>;
> + // interrupt-map-mask = need to add
> + // interrupt-map = need to add
> + clock-frequency = <0>; // From boot loader
> + interrupts = <2 8 0 2 9 0 2 10 0>;
> + bus-range = <0 0>;
> + // ranges = need to add
> + };
> +
> + localbus: localbus {
> + compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0 0xfc000000 0x2000000>;
> + };
> +};
> diff --git a/arch/powerpc/boot/dts/mucmc52.dts b/arch/powerpc/boot/dts/mucmc52.dts
> index 8dc212d..b369db5 100644
> --- a/arch/powerpc/boot/dts/mucmc52.dts
> +++ b/arch/powerpc/boot/dts/mucmc52.dts
> @@ -11,172 +11,105 @@
> * option) any later version.
> */
>
> -/dts-v1/;
> +/include/ "mpc5200b.dtsi"
>
> / {
> model = "manroland,mucmc52";
> compatible = "manroland,mucmc52";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - interrupt-parent = <&mpc5200_pic>;
> -
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - PowerPC,5200@0 {
> - device_type = "cpu";
> - reg = <0>;
> - d-cache-line-size = <32>;
> - i-cache-line-size = <32>;
> - d-cache-size = <0x4000>; // L1, 16K
> - i-cache-size = <0x4000>; // L1, 16K
> - timebase-frequency = <0>; // from bootloader
> - bus-frequency = <0>; // from bootloader
> - clock-frequency = <0>; // from bootloader
> - };
> - };
> -
> - memory {
> - device_type = "memory";
> - reg = <0x00000000 0x04000000>; // 64MB
> - };
>
> soc5200@f0000000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,mpc5200b-immr";
> - ranges = <0 0xf0000000 0x0000c000>;
> - reg = <0xf0000000 0x00000100>;
> - bus-frequency = <0>; // from bootloader
> - system-frequency = <0>; // from bootloader
> -
> - cdm@200 {
> - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
> - reg = <0x200 0x38>;
> - };
> -
> - mpc5200_pic: interrupt-controller@500 {
> - // 5200 interrupts are encoded into two levels;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
> - reg = <0x500 0x80>;
> - };
> -
> gpt0: timer@600 { // GPT 0 in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x600 0x10>;
> - interrupts = <1 9 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt1: timer@610 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x610 0x10>;
> - interrupts = <1 10 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt2: timer@620 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x620 0x10>;
> - interrupts = <1 11 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt3: timer@630 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x630 0x10>;
> - interrupts = <1 12 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> - gpio_simple: gpio@b00 {
> - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
> - reg = <0xb00 0x40>;
> - interrupts = <1 7 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> + timer@640 {
> + status = "disabled";
> };
>
> - gpio_wkup: gpio@c00 {
> - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
> - reg = <0xc00 0x40>;
> - interrupts = <1 8 0 0 3 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> + timer@650 {
> + status = "disabled";
> };
>
> - dma-controller@1200 {
> - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
> - reg = <0x1200 0x80>;
> - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
> - 3 4 0 3 5 0 3 6 0 3 7 0
> - 3 8 0 3 9 0 3 10 0 3 11 0
> - 3 12 0 3 13 0 3 14 0 3 15 0>;
> + timer@660 {
> + status = "disabled";
> };
>
> - xlb@1f00 {
> - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
> - reg = <0x1f00 0x100>;
> + timer@670 {
> + status = "disabled";
> };
>
> - psc@2000 { /* PSC1 in UART mode */
> - compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2000 0x100>;
> - interrupts = <2 1 0>;
> + rtc@800 {
> + status = "disabled";
> + };
> +
> + can@900 {
> + status = "disabled";
> + };
> +
> + can@980 {
> + status = "disabled";
> + };
> +
> + spi@f00 {
> + status = "disabled";
> + };
> +
> + usb@1000 {
> + status = "disabled";
> };
>
> - psc@2200 { /* PSC2 in UART mode */
> + psc@2000 { // PSC1
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2200 0x100>;
> - interrupts = <2 2 0>;
> };
>
> - psc@2c00 { /* PSC6 in UART mode */
> + psc@2200 { // PSC2
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2c00 0x100>;
> - interrupts = <2 4 0>;
> };
>
> - ethernet@3000 {
> - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
> - reg = <0x3000 0x400>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupts = <2 5 0>;
> - phy-handle = <&phy0>;
> + psc@2400 { // PSC3
> + status = "disabled";
> };
>
> - mdio@3000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
> - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
> - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
> + psc@2600 { // PSC4
> + status = "disabled";
> + };
> +
> + psc@2800 { // PSC5
> + status = "disabled";
> + };
>
> + psc@2c00 { // PSC6
> + compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> + };
> +
> + mdio@3000 {
> phy0: ethernet-phy@0 {
> compatible = "intel,lxt971";
> reg = <0>;
> };
> };
>
> - ata@3a00 {
> - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
> - reg = <0x3a00 0x100>;
> - interrupts = <2 7 0>;
> + i2c@3d00 {
> + status = "disabled";
> };
>
> i2c@3d40 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> - reg = <0x3d40 0x40>;
> - interrupts = <2 16 0>;
> hwmon@2c {
> compatible = "ad,adm9240";
> reg = <0x2c>;
> @@ -186,20 +119,9 @@
> reg = <0x51>;
> };
> };
> -
> - sram@8000 {
> - compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
> - reg = <0x8000 0x4000>;
> - };
> };
>
> pci@f0000d00 {
> - #interrupt-cells = <1>;
> - #size-cells = <2>;
> - #address-cells = <3>;
> - device_type = "pci";
> - compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
> - reg = <0xf0000d00 0x100>;
> interrupt-map-mask = <0xf800 0 0 7>;
> interrupt-map = <
> /* IDSEL 0x10 */
> @@ -208,20 +130,12 @@
> 0x8000 0 0 3 &mpc5200_pic 0 2 3
> 0x8000 0 0 4 &mpc5200_pic 0 1 3
> >;
> - clock-frequency = <0>; // From boot loader
> - interrupts = <2 8 0 2 9 0 2 10 0>;
> - bus-range = <0 0>;
> ranges = <0x42000000 0 0x60000000 0x60000000 0 0x10000000
> 0x02000000 0 0x90000000 0x90000000 0 0x10000000
> 0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
> };
>
> localbus {
> - compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
> -
> - #address-cells = <2>;
> - #size-cells = <1>;
> -
> ranges = <0 0 0xff800000 0x00800000
> 1 0 0x80000000 0x00800000
> 3 0 0x80000000 0x00800000>;
> diff --git a/arch/powerpc/boot/dts/pcm030.dts b/arch/powerpc/boot/dts/pcm030.dts
> index f3e30bb..b2ee689 100644
> --- a/arch/powerpc/boot/dts/pcm030.dts
> +++ b/arch/powerpc/boot/dts/pcm030.dts
> @@ -12,244 +12,88 @@
> * option) any later version.
> */
>
> -/dts-v1/;
> +/include/ "mpc5200b.dtsi"
>
> / {
> model = "phytec,pcm030";
> compatible = "phytec,pcm030";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - interrupt-parent = <&mpc5200_pic>;
> -
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - PowerPC,5200@0 {
> - device_type = "cpu";
> - reg = <0>;
> - d-cache-line-size = <32>;
> - i-cache-line-size = <32>;
> - d-cache-size = <0x4000>; // L1, 16K
> - i-cache-size = <0x4000>; // L1, 16K
> - timebase-frequency = <0>; // from bootloader
> - bus-frequency = <0>; // from bootloader
> - clock-frequency = <0>; // from bootloader
> - };
> - };
> -
> - memory {
> - device_type = "memory";
> - reg = <0x00000000 0x04000000>; // 64MB
> - };
>
> soc5200@f0000000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,mpc5200b-immr";
> - ranges = <0 0xf0000000 0x0000c000>;
> - bus-frequency = <0>; // from bootloader
> - system-frequency = <0>; // from bootloader
> -
> - cdm@200 {
> - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
> - reg = <0x200 0x38>;
> - };
> -
> - mpc5200_pic: interrupt-controller@500 {
> - // 5200 interrupts are encoded into two levels;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
> - reg = <0x500 0x80>;
> - };
> -
> - timer@600 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x600 0x10>;
> - interrupts = <1 9 0>;
> + timer@600 { // General Purpose Timer
> fsl,has-wdt;
> };
>
> - timer@610 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x610 0x10>;
> - interrupts = <1 10 0>;
> - };
> -
> gpt2: timer@620 { // General Purpose Timer in GPIO mode
> compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
> - reg = <0x620 0x10>;
> - interrupts = <1 11 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt3: timer@630 { // General Purpose Timer in GPIO mode
> compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
> - reg = <0x630 0x10>;
> - interrupts = <1 12 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt4: timer@640 { // General Purpose Timer in GPIO mode
> compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
> - reg = <0x640 0x10>;
> - interrupts = <1 13 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt5: timer@650 { // General Purpose Timer in GPIO mode
> compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
> - reg = <0x650 0x10>;
> - interrupts = <1 14 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt6: timer@660 { // General Purpose Timer in GPIO mode
> compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
> - reg = <0x660 0x10>;
> - interrupts = <1 15 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt7: timer@670 { // General Purpose Timer in GPIO mode
> compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
> - reg = <0x670 0x10>;
> - interrupts = <1 16 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> -
> - rtc@800 { // Real time clock
> - compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
> - reg = <0x800 0x100>;
> - interrupts = <1 5 0 1 6 0>;
> - };
> -
> - can@900 {
> - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
> - interrupts = <2 17 0>;
> - reg = <0x900 0x80>;
> - };
> -
> - can@980 {
> - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
> - interrupts = <2 18 0>;
> - reg = <0x980 0x80>;
> - };
> -
> - gpio_simple: gpio@b00 {
> - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
> - reg = <0xb00 0x40>;
> - interrupts = <1 7 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> -
> - gpio_wkup: gpio@c00 {
> - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
> - reg = <0xc00 0x40>;
> - interrupts = <1 8 0 0 3 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> - spi@f00 {
> - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
> - reg = <0xf00 0x20>;
> - interrupts = <2 13 0 2 14 0>;
> - };
> -
> - usb@1000 {
> - compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
> - reg = <0x1000 0xff>;
> - interrupts = <2 6 0>;
> - };
> -
> - dma-controller@1200 {
> - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
> - reg = <0x1200 0x80>;
> - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
> - 3 4 0 3 5 0 3 6 0 3 7 0
> - 3 8 0 3 9 0 3 10 0 3 11 0
> - 3 12 0 3 13 0 3 14 0 3 15 0>;
> - };
> -
> - xlb@1f00 {
> - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
> - reg = <0x1f00 0x100>;
> - };
> -
> psc@2000 { /* PSC1 in ac97 mode */
> compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
> cell-index = <0>;
> - reg = <0x2000 0x100>;
> - interrupts = <2 1 0>;
> };
>
> /* PSC2 port is used by CAN1/2 */
> + psc@2200 {
> + status = "disabled";
> + };
>
> psc@2400 { /* PSC3 in UART mode */
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2400 0x100>;
> - interrupts = <2 3 0>;
> };
>
> /* PSC4 is ??? */
> -
> + psc@2600 {
> + status = "disabled";
> + };
> +
> /* PSC5 is ??? */
> + psc@2800 {
> + status = "disabled";
> + };
>
> psc@2c00 { /* PSC6 in UART mode */
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2c00 0x100>;
> - interrupts = <2 4 0>;
> - };
> -
> - ethernet@3000 {
> - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
> - reg = <0x3000 0x400>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupts = <2 5 0>;
> - phy-handle = <&phy0>;
> };
>
> mdio@3000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
> - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
> - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
> -
> phy0: ethernet-phy@0 {
> reg = <0>;
> };
> };
>
> - ata@3a00 {
> - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
> - reg = <0x3a00 0x100>;
> - interrupts = <2 7 0>;
> - };
> -
> - i2c@3d00 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> - reg = <0x3d00 0x40>;
> - interrupts = <2 15 0>;
> - };
> -
> i2c@3d40 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> - reg = <0x3d40 0x40>;
> - interrupts = <2 16 0>;
> rtc@51 {
> compatible = "nxp,pcf8563";
> reg = <0x51>;
> @@ -267,12 +111,6 @@
> };
>
> pci@f0000d00 {
> - #interrupt-cells = <1>;
> - #size-cells = <2>;
> - #address-cells = <3>;
> - device_type = "pci";
> - compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
> - reg = <0xf0000d00 0x100>;
> interrupt-map-mask = <0xf800 0 0 7>;
> interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
> 0xc000 0 0 2 &mpc5200_pic 1 1 3
> @@ -283,11 +121,12 @@
> 0xc800 0 0 2 &mpc5200_pic 1 2 3
> 0xc800 0 0 3 &mpc5200_pic 1 3 3
> 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
> - clock-frequency = <0>; // From boot loader
> - interrupts = <2 8 0 2 9 0 2 10 0>;
> - bus-range = <0 0>;
> ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
> 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
> 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
> };
> +
> + localbus {
> + status = "disabled";
> + };
> };
> diff --git a/arch/powerpc/boot/dts/pcm032.dts b/arch/powerpc/boot/dts/pcm032.dts
> index e0f2702..184e194 100644
> --- a/arch/powerpc/boot/dts/pcm032.dts
> +++ b/arch/powerpc/boot/dts/pcm032.dts
> @@ -12,99 +12,37 @@
> * option) any later version.
> */
>
> -/dts-v1/;
> +/include/ "mpc5200b.dtsi"
>
> / {
> model = "phytec,pcm032";
> compatible = "phytec,pcm032";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - interrupt-parent = <&mpc5200_pic>;
> -
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - PowerPC,5200@0 {
> - device_type = "cpu";
> - reg = <0>;
> - d-cache-line-size = <32>;
> - i-cache-line-size = <32>;
> - d-cache-size = <0x4000>; // L1, 16K
> - i-cache-size = <0x4000>; // L1, 16K
> - timebase-frequency = <0>; // from bootloader
> - bus-frequency = <0>; // from bootloader
> - clock-frequency = <0>; // from bootloader
> - };
> - };
>
> memory {
> - device_type = "memory";
> reg = <0x00000000 0x08000000>; // 128MB
> };
>
> soc5200@f0000000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,mpc5200b-immr";
> - ranges = <0 0xf0000000 0x0000c000>;
> - bus-frequency = <0>; // from bootloader
> - system-frequency = <0>; // from bootloader
> -
> - cdm@200 {
> - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
> - reg = <0x200 0x38>;
> - };
> -
> - mpc5200_pic: interrupt-controller@500 {
> - // 5200 interrupts are encoded into two levels;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
> - reg = <0x500 0x80>;
> - };
> -
> - timer@600 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x600 0x10>;
> - interrupts = <1 9 0>;
> + timer@600 { // General Purpose Timer
> fsl,has-wdt;
> };
>
> - timer@610 { // General Purpose Timer
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x610 0x10>;
> - interrupts = <1 10 0>;
> - };
> -
> gpt2: timer@620 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x620 0x10>;
> - interrupts = <1 11 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt3: timer@630 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x630 0x10>;
> - interrupts = <1 12 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt4: timer@640 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x640 0x10>;
> - interrupts = <1 13 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt5: timer@650 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x650 0x10>;
> - interrupts = <1 14 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
> @@ -118,138 +56,45 @@
> };
>
> gpt7: timer@670 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x670 0x10>;
> - interrupts = <1 16 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> -
> - rtc@800 { // Real time clock
> - compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
> - reg = <0x800 0x100>;
> - interrupts = <1 5 0 1 6 0>;
> - };
> -
> - can@900 {
> - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
> - interrupts = <2 17 0>;
> - reg = <0x900 0x80>;
> - };
> -
> - can@980 {
> - compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
> - interrupts = <2 18 0>;
> - reg = <0x980 0x80>;
> - };
> -
> - gpio_simple: gpio@b00 {
> - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
> - reg = <0xb00 0x40>;
> - interrupts = <1 7 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> - };
> -
> - gpio_wkup: gpio@c00 {
> - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
> - reg = <0xc00 0x40>;
> - interrupts = <1 8 0 0 3 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> - spi@f00 {
> - compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
> - reg = <0xf00 0x20>;
> - interrupts = <2 13 0 2 14 0>;
> - };
> -
> - usb@1000 {
> - compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
> - reg = <0x1000 0xff>;
> - interrupts = <2 6 0>;
> - };
> -
> - dma-controller@1200 {
> - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
> - reg = <0x1200 0x80>;
> - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
> - 3 4 0 3 5 0 3 6 0 3 7 0
> - 3 8 0 3 9 0 3 10 0 3 11 0
> - 3 12 0 3 13 0 3 14 0 3 15 0>;
> - };
> -
> - xlb@1f00 {
> - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
> - reg = <0x1f00 0x100>;
> - };
> -
> psc@2000 { /* PSC1 is ac97 */
> compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
> cell-index = <0>;
> - reg = <0x2000 0x100>;
> - interrupts = <2 1 0>;
> };
>
> /* PSC2 port is used by CAN1/2 */
> + psc@2200 {
> + status = "disabled";
> + };
>
> psc@2400 { /* PSC3 in UART mode */
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2400 0x100>;
> - interrupts = <2 3 0>;
> };
>
> /* PSC4 is ??? */
> + psc@2600 {
> + status = "disabled";
> + };
>
> /* PSC5 is ??? */
> + psc@2800 {
> + status = "disabled";
> + };
>
> psc@2c00 { /* PSC6 in UART mode */
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2c00 0x100>;
> - interrupts = <2 4 0>;
> - };
> -
> - ethernet@3000 {
> - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
> - reg = <0x3000 0x400>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupts = <2 5 0>;
> - phy-handle = <&phy0>;
> };
>
> mdio@3000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
> - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
> - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
> -
> phy0: ethernet-phy@0 {
> reg = <0>;
> };
> };
>
> - ata@3a00 {
> - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
> - reg = <0x3a00 0x100>;
> - interrupts = <2 7 0>;
> - };
> -
> - i2c@3d00 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> - reg = <0x3d00 0x40>;
> - interrupts = <2 15 0>;
> - };
> -
> i2c@3d40 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> - reg = <0x3d40 0x40>;
> - interrupts = <2 16 0>;
> rtc@51 {
> compatible = "nxp,pcf8563";
> reg = <0x51>;
> @@ -259,20 +104,9 @@
> reg = <0x52>;
> };
> };
> -
> - sram@8000 {
> - compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
> - reg = <0x8000 0x4000>;
> - };
> };
>
> pci@f0000d00 {
> - #interrupt-cells = <1>;
> - #size-cells = <2>;
> - #address-cells = <3>;
> - device_type = "pci";
> - compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
> - reg = <0xf0000d00 0x100>;
> interrupt-map-mask = <0xf800 0 0 7>;
> interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
> 0xc000 0 0 2 &mpc5200_pic 1 1 3
> @@ -283,20 +117,12 @@
> 0xc800 0 0 2 &mpc5200_pic 1 2 3
> 0xc800 0 0 3 &mpc5200_pic 1 3 3
> 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
> - clock-frequency = <0>; // From boot loader
> - interrupts = <2 8 0 2 9 0 2 10 0>;
> - bus-range = <0 0>;
> ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
> 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
> 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
> };
>
> localbus {
> - compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
> -
> - #address-cells = <2>;
> - #size-cells = <1>;
> -
> ranges = <0 0 0xfe000000 0x02000000
> 1 0 0xfc000000 0x02000000
> 2 0 0xfbe00000 0x00200000
> @@ -385,4 +211,3 @@
> */
> };
> };
> -
> diff --git a/arch/powerpc/boot/dts/uc101.dts b/arch/powerpc/boot/dts/uc101.dts
> index e00441a..49be562 100644
> --- a/arch/powerpc/boot/dts/uc101.dts
> +++ b/arch/powerpc/boot/dts/uc101.dts
> @@ -11,79 +11,24 @@
> * option) any later version.
> */
>
> -/dts-v1/;
> +/include/ "mpc5200b.dtsi"
>
> / {
> model = "manroland,uc101";
> compatible = "manroland,uc101";
> - #address-cells = <1>;
> - #size-cells = <1>;
> - interrupt-parent = <&mpc5200_pic>;
> -
> - cpus {
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - PowerPC,5200@0 {
> - device_type = "cpu";
> - reg = <0>;
> - d-cache-line-size = <32>;
> - i-cache-line-size = <32>;
> - d-cache-size = <0x4000>; // L1, 16K
> - i-cache-size = <0x4000>; // L1, 16K
> - timebase-frequency = <0>; // from bootloader
> - bus-frequency = <0>; // from bootloader
> - clock-frequency = <0>; // from bootloader
> - };
> - };
> -
> - memory {
> - device_type = "memory";
> - reg = <0x00000000 0x04000000>; // 64MB
> - };
>
> soc5200@f0000000 {
> - #address-cells = <1>;
> - #size-cells = <1>;
> - compatible = "fsl,mpc5200b-immr";
> - ranges = <0 0xf0000000 0x0000c000>;
> - reg = <0xf0000000 0x00000100>;
> - bus-frequency = <0>; // from bootloader
> - system-frequency = <0>; // from bootloader
> -
> - cdm@200 {
> - compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
> - reg = <0x200 0x38>;
> - };
> -
> - mpc5200_pic: interrupt-controller@500 {
> - // 5200 interrupts are encoded into two levels;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
> - reg = <0x500 0x80>;
> - };
> -
> gpt0: timer@600 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x600 0x10>;
> - interrupts = <1 9 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt1: timer@610 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x610 0x10>;
> - interrupts = <1 10 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt2: timer@620 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x620 0x10>;
> - interrupts = <1 11 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
> @@ -97,118 +42,81 @@
> };
>
> gpt4: timer@640 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x640 0x10>;
> - interrupts = <1 13 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt5: timer@650 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x650 0x10>;
> - interrupts = <1 14 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt6: timer@660 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x660 0x10>;
> - interrupts = <1 15 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> gpt7: timer@670 { // General Purpose Timer in GPIO mode
> - compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
> - reg = <0x670 0x10>;
> - interrupts = <1 16 0>;
> gpio-controller;
> #gpio-cells = <2>;
> };
>
> - gpio_simple: gpio@b00 {
> - compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
> - reg = <0xb00 0x40>;
> - interrupts = <1 7 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> + rtc@800 {
> + status = "disabled";
> };
>
> - gpio_wkup: gpio@c00 {
> - compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
> - reg = <0xc00 0x40>;
> - interrupts = <1 8 0 0 3 0>;
> - gpio-controller;
> - #gpio-cells = <2>;
> + can@900 {
> + status = "disabled";
> };
>
> - dma-controller@1200 {
> - compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
> - reg = <0x1200 0x80>;
> - interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
> - 3 4 0 3 5 0 3 6 0 3 7 0
> - 3 8 0 3 9 0 3 10 0 3 11 0
> - 3 12 0 3 13 0 3 14 0 3 15 0>;
> + can@980 {
> + status = "disabled";
> };
>
> - xlb@1f00 {
> - compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
> - reg = <0x1f00 0x100>;
> + spi@f00 {
> + status = "disabled";
> };
>
> - psc@2000 { /* PSC1 in UART mode */
> - compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2000 0x100>;
> - interrupts = <2 1 0>;
> + usb@1000 {
> + status = "disabled";
> };
>
> - psc@2200 { /* PSC2 in UART mode */
> + psc@2000 { // PSC1
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2200 0x100>;
> - interrupts = <2 2 0>;
> };
>
> - psc@2c00 { /* PSC6 in UART mode */
> + psc@2200 { // PSC2
> compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> - reg = <0x2c00 0x100>;
> - interrupts = <2 4 0>;
> };
>
> - ethernet@3000 {
> - compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
> - reg = <0x3000 0x400>;
> - local-mac-address = [ 00 00 00 00 00 00 ];
> - interrupts = <2 5 0>;
> - phy-handle = <&phy0>;
> + psc@2400 { // PSC3
> + status = "disabled";
> };
>
> - mdio@3000 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
> - reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
> - interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
> + psc@2600 { // PSC4
> + status = "disabled";
> + };
> +
> + psc@2800 { // PSC5
> + status = "disabled";
> + };
>
> + psc@2c00 { // PSC6
> + compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
> + };
> +
> + mdio@3000 {
> phy0: ethernet-phy@0 {
> compatible = "intel,lxt971";
> reg = <0>;
> };
> };
>
> - ata@3a00 {
> - compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
> - reg = <0x3a00 0x100>;
> - interrupts = <2 7 0>;
> + i2c@3d00 {
> + status = "disabled";
> };
>
> i2c@3d40 {
> - #address-cells = <1>;
> - #size-cells = <0>;
> - compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
> - reg = <0x3d40 0x40>;
> - interrupts = <2 16 0>;
> fsl,preserve-clocking;
> clock-frequency = <400000>;
>
> @@ -221,19 +129,13 @@
> reg = <0x51>;
> };
> };
> + };
>
> - sram@8000 {
> - compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
> - reg = <0x8000 0x4000>;
> - };
> + pci@f0000d00 {
> + status = "disabled";
> };
>
> localbus {
> - compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus";
> -
> - #address-cells = <2>;
> - #size-cells = <1>;
> -
> ranges = <0 0 0xff800000 0x00800000
> 1 0 0x80000000 0x00800000
> 3 0 0x80000000 0x00800000>;
>
^ permalink raw reply
* [PATCH] RapidIO: Fix hang on RapidIO doorbell queue full condition
From: Thomas Taranowski @ 2011-01-04 7:29 UTC (permalink / raw)
To: linux-kernel, linuxppc-dev
In fsl_rio_dbell_handler, the code currently simply acknowledges the QFI queue
full interrupt, but does nothing to resolve the queue full condition. Instead,
it jumps to the end of the isr. When a queue full condition occurs, the isr is
then re-entered immediately and continually, forever.
The fix is to just fall through and read out current doorbell entries.
Tested against 2.6.26-rc8 on a p2020
Signed-off-by: Thomas Taranowski <tom@baringforge.com>
---
arch/powerpc/sysdev/fsl_rio.c | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 9725369..9f99bef 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -973,7 +973,6 @@ fsl_rio_dbell_handler(int irq, void *dev_instance)
if (dsr & DOORBELL_DSR_QFI) {
pr_info("RIO: doorbell queue full\n");
out_be32(&priv->msg_regs->dsr, DOORBELL_DSR_QFI);
- goto out;
}
/* XXX Need to check/dispatch until queue empty */
--
1.7.0.4
Thomas Taranowski
Certified netburner consultant
baringforge.com
^ permalink raw reply related
* AMCC 460EX GPIO
From: musaab ali @ 2011-01-04 8:00 UTC (permalink / raw)
To: linuxppc-dev
[-- Attachment #1: Type: text/plain, Size: 445 bytes --]
Hi there,
I'm using the Canyonlands evaluation board for the ppc 460ex processor. I want to access the GPIO pins, set its direction and set/get their values.
Is there is any common driver to do so? I went throught the Documentation/gpio.txt and the arch/powerpc/sysdev/ppc4xx_gpio.c but I don't know
how to test the later driver either from kernel space or from user space. Any ideas or sample codes?
Thanks in advance.
Musaab.
[-- Attachment #2: Type: text/html, Size: 653 bytes --]
^ permalink raw reply
* Re: [PATCH] powerpc/dts: fix syntax bugs in bluestone.dts
From: Josh Boyer @ 2011-01-04 13:59 UTC (permalink / raw)
To: Grant Likely; +Cc: tmarri, linuxppc-dev
In-Reply-To: <20110103210715.10427.56175.stgit@localhost6.localdomain6>
On Mon, Jan 03, 2011 at 02:07:40PM -0700, Grant Likely wrote:
>Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
>---
>
>I'm picking this one up immediately into my next-devicetree branch
Hm. So these are of course correct, and with that:
Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
but I do wonder how you noticed them? DTC didn't throw an error when I
built this originally. Either way, more diligence on my part would be
appropriate, but knowing how you came across these might teach me
something.
Nit: C++ comments still make me get queasy. Maybe just remove the
properties that point to lables that don't exist?
josh
^ permalink raw reply
* Re: [PATCH] powerpc/405: Fix missing #{address,size}-cells in i2c node
From: Josh Boyer @ 2011-01-04 14:01 UTC (permalink / raw)
To: Grant Likely; +Cc: linuxppc-dev, solomon
In-Reply-To: <20110103220520.9355.2745.stgit@localhost6.localdomain6>
On Mon, Jan 03, 2011 at 03:06:03PM -0700, Grant Likely wrote:
>Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
>---
>
>I'm putting this patch into my next-devicetree branch.
Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
^ permalink raw reply
* Re: [PATCH] powerpc/dts: fix syntax bugs in bluestone.dts
From: Grant Likely @ 2011-01-04 14:30 UTC (permalink / raw)
To: Josh Boyer; +Cc: tmarri, linuxppc-dev
In-Reply-To: <20110104135930.GA2364@zod.rchland.ibm.com>
On Tue, Jan 04, 2011 at 08:59:31AM -0500, Josh Boyer wrote:
> On Mon, Jan 03, 2011 at 02:07:40PM -0700, Grant Likely wrote:
> >Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> >---
> >
> >I'm picking this one up immediately into my next-devicetree branch
>
> Hm. So these are of course correct, and with that:
>
> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
>
> but I do wonder how you noticed them? DTC didn't throw an error when I
> built this originally. Either way, more diligence on my part would be
> appropriate, but knowing how you came across these might teach me
> something.
I updated the copy of dtc in the kernel and rebuilt all the .dts files.
g.
^ permalink raw reply
* Re: [PATCH] powerpc/dts: fix syntax bugs in bluestone.dts
From: Josh Boyer @ 2011-01-04 14:31 UTC (permalink / raw)
To: Grant Likely; +Cc: tmarri, linuxppc-dev
In-Reply-To: <20110104143030.GA11738@angua.secretlab.ca>
On Tue, Jan 04, 2011 at 07:30:30AM -0700, Grant Likely wrote:
>On Tue, Jan 04, 2011 at 08:59:31AM -0500, Josh Boyer wrote:
>> On Mon, Jan 03, 2011 at 02:07:40PM -0700, Grant Likely wrote:
>> >Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
>> >---
>> >
>> >I'm picking this one up immediately into my next-devicetree branch
>>
>> Hm. So these are of course correct, and with that:
>>
>> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
>>
>> but I do wonder how you noticed them? DTC didn't throw an error when I
>> built this originally. Either way, more diligence on my part would be
>> appropriate, but knowing how you came across these might teach me
>> something.
>
>I updated the copy of dtc in the kernel and rebuilt all the .dts files.
Are you going to push that DTC update into the kernel as well?
josh
^ permalink raw reply
* Re: [PATCH] powerpc/dts: fix syntax bugs in bluestone.dts
From: Grant Likely @ 2011-01-04 18:38 UTC (permalink / raw)
To: Josh Boyer; +Cc: tmarri, linuxppc-dev
In-Reply-To: <20110104143132.GC2364@zod.rchland.ibm.com>
On Tue, Jan 04, 2011 at 09:31:32AM -0500, Josh Boyer wrote:
> On Tue, Jan 04, 2011 at 07:30:30AM -0700, Grant Likely wrote:
> >On Tue, Jan 04, 2011 at 08:59:31AM -0500, Josh Boyer wrote:
> >> On Mon, Jan 03, 2011 at 02:07:40PM -0700, Grant Likely wrote:
> >> >Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
> >> >---
> >> >
> >> >I'm picking this one up immediately into my next-devicetree branch
> >>
> >> Hm. So these are of course correct, and with that:
> >>
> >> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
> >>
> >> but I do wonder how you noticed them? DTC didn't throw an error when I
> >> built this originally. Either way, more diligence on my part would be
> >> appropriate, but knowing how you came across these might teach me
> >> something.
> >
> >I updated the copy of dtc in the kernel and rebuilt all the .dts files.
>
> Are you going to push that DTC update into the kernel as well?
Yes, that's what I mean by updating dtc. It is in my next-devicetree branch.
g.
^ permalink raw reply
* Question about combining a PCI driver with an OF driver
From: Bruce_Leonard @ 2011-01-04 18:58 UTC (permalink / raw)
To: linuxppc-dev
Hi all,
I'm working on a project with an MPC8347 and three ethernet ports. Because
of end of life issues we've had to replace the part we're using for the
third ethernet port and we decided rather than rely on a vendor who would
pull a part out from under us every two to three years we would do our own
MAC in an FPGA. In order to reduce driver work it was decided that we
would use the same hardware interface as the TSEC in the 8347 so we could
reuse the gianfar driver. And for speed sake it would go on the PCI bus.
(So much for letting HW make decisions regarding SW :) )
So now I'm stuck with hacking the gianfar driver to work on PCI. However,
I think it would be a lot more elegant if I could wrap the gianfar driver
with a PCI interface. After all the idea is sound, with a HW interface
that looks like the TSEC I should be able to reuse the gianfar driver. But
the gianfar driver is an open firmware driver registered with a call to
of_register_platform_driver() and depending on the order in which the
busses are walked the PCI bus may not be enumerated and available when the
onboard TSECS are detected and the gianfar driver claims them.
So the question is, how can I wrap an OF driver with a PCI driver so that
I can just do a thin layer of probing the PCI bus, registering with the
PCI sub-system, and then calling the OF probe in the gianfar driver?
Thanks for any insight.
Bruce
^ permalink raw reply
* Re: Question about combining a PCI driver with an OF driver
From: Scott Wood @ 2011-01-04 19:23 UTC (permalink / raw)
To: Bruce_Leonard; +Cc: linuxppc-dev
In-Reply-To: <OF413F3FA8.B1C9F99A-ON8825780E.006706F6-8825780E.00683E0B@selinc.com>
On Tue, 4 Jan 2011 10:58:35 -0800
<Bruce_Leonard@selinc.com> wrote:
> Hi all,
>
> I'm working on a project with an MPC8347 and three ethernet ports. Because
> of end of life issues we've had to replace the part we're using for the
> third ethernet port and we decided rather than rely on a vendor who would
> pull a part out from under us every two to three years we would do our own
> MAC in an FPGA. In order to reduce driver work it was decided that we
> would use the same hardware interface as the TSEC in the 8347 so we could
> reuse the gianfar driver.
Making a faithful clone of any reasonably complex device strikes me as
more work than writing a new ethernet driver.
The last thing you want to end up doing is...
> And for speed sake it would go on the PCI bus.
> (So much for letting HW make decisions regarding SW :) )
...hacking up the existing driver to deal with the quirks of the clone,
and having to maintain those hacks. :-)
> So now I'm stuck with hacking the gianfar driver to work on PCI. However,
> I think it would be a lot more elegant if I could wrap the gianfar driver
> with a PCI interface. After all the idea is sound, with a HW interface
> that looks like the TSEC I should be able to reuse the gianfar driver. But
> the gianfar driver is an open firmware driver registered with a call to
> of_register_platform_driver() and depending on the order in which the
> busses are walked the PCI bus may not be enumerated and available when the
> onboard TSECS are detected and the gianfar driver claims them.
It shouldn't matter -- the way buses work in Linux, you should be able
to add a platform device at any time, and the driver will receive a
probe() callback. The driver never actively searches for devices to
claim.
-Scott
^ permalink raw reply
* Re: [RFC] MPIC Bindings and Bindings for AMP Systems
From: Blanchard, Hollis @ 2011-01-04 20:14 UTC (permalink / raw)
To: Grant Likely; +Cc: Inge, Meador, devicetree-discuss, linuxppc-dev
In-Reply-To: <4D13C402.2090209@mentor.com>
On 12/23/2010 01:49 PM, Meador Inge wrote:
>
> We can't just remove the IRQ of the _other_ OS from the 'interrupts'=20
> property in the message node because we need to know the IRQ in order=20
> to talk to the other OS. So, we use protected sources to tell the OS=20
> that an IRQ is not available for its own use, while at the same time=20
> keeping=20
> complete information on all the IRQ mappings for the message =
registers.
There's a simpler and more fundamental problem: the Linux MPIC driver=20
initializes the "VECPRI" register for all interrupt sources (which is=20
how you associate a source with a vector). We need the Linux driver not=20
to do this.
(The "no-reset" property solves a related problem: it tells the driver=20
not to use the hardware's special "reset all registers" bit.)
Hollis Blanchard
Mentor Graphics, Embedded Systems Division
^ permalink raw reply
* Re: Question about combining a PCI driver with an OF driver
From: Bruce_Leonard @ 2011-01-04 21:00 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <20110104132317.006ead39@udp111988uds.am.freescale.net>
Scott,
Thanks for the feedback.
>
> Making a faithful clone of any reasonably complex device strikes me as
> more work than writing a new ethernet driver.
>
> The last thing you want to end up doing is...
>
> > And for speed sake it would go on the PCI bus.
> > (So much for letting HW make decisions regarding SW :) )
>
> ...hacking up the existing driver to deal with the quirks of the clone,
> and having to maintain those hacks. :-)
>
True, but we really didn't want to recreate all the infrastructure that
the gianfar driver has in it we wanted to just use it. Maybe what I
should do is just take the guts of the gianfar driver and make a pure PCI
driver out of it.
>
> It shouldn't matter -- the way buses work in Linux, you should be able
> to add a platform device at any time, and the driver will receive a
> probe() callback. The driver never actively searches for devices to
> claim.
>
Okay, I get that and it makes sense with what I know so far about how the
kernel device model works (which I'm still learning). So how would I
manually add a device? Say I create the PCI wrapper driver that claims
the clone-TSEC, is there a "register device" type call similar to
pci_register_driver() that I could put in the wrapper code that causes the
gfar_probe() to be called?
Bruce
^ permalink raw reply
* Re: Question about combining a PCI driver with an OF driver
From: Benjamin Herrenschmidt @ 2011-01-04 21:05 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, Bruce_Leonard
In-Reply-To: <20110104132317.006ead39@udp111988uds.am.freescale.net>
On Tue, 2011-01-04 at 13:23 -0600, Scott Wood wrote:
> On Tue, 4 Jan 2011 10:58:35 -0800
> <Bruce_Leonard@selinc.com> wrote:
>
> > Hi all,
> >
> > I'm working on a project with an MPC8347 and three ethernet ports. Because
> > of end of life issues we've had to replace the part we're using for the
> > third ethernet port and we decided rather than rely on a vendor who would
> > pull a part out from under us every two to three years we would do our own
> > MAC in an FPGA. In order to reduce driver work it was decided that we
> > would use the same hardware interface as the TSEC in the 8347 so we could
> > reuse the gianfar driver.
>
> Making a faithful clone of any reasonably complex device strikes me as
> more work than writing a new ethernet driver.
>
> The last thing you want to end up doing is...
>
> > And for speed sake it would go on the PCI bus.
> > (So much for letting HW make decisions regarding SW :) )
>
> ...hacking up the existing driver to deal with the quirks of the clone,
> and having to maintain those hacks. :-)
I definitely agree. You're up for more work and problems than just doing
a new design or getting an existing one off opencores or even buying an
IP block with its own driver.
> > So now I'm stuck with hacking the gianfar driver to work on PCI. However,
> > I think it would be a lot more elegant if I could wrap the gianfar driver
> > with a PCI interface. After all the idea is sound, with a HW interface
> > that looks like the TSEC I should be able to reuse the gianfar driver. But
> > the gianfar driver is an open firmware driver registered with a call to
> > of_register_platform_driver() and depending on the order in which the
> > busses are walked the PCI bus may not be enumerated and available when the
> > onboard TSECS are detected and the gianfar driver claims them.
>
> It shouldn't matter -- the way buses work in Linux, you should be able
> to add a platform device at any time, and the driver will receive a
> probe() callback. The driver never actively searches for devices to
> claim.
Cheers,
Ben.
> -Scott
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
^ permalink raw reply
* Re: [PATCH] KVM: PPC: Fix SPRG get/set for Book3S and BookE
From: Alexander Graf @ 2011-01-04 21:09 UTC (permalink / raw)
To: Peter Tyser; +Cc: linuxppc-dev, kvm, kvm-ppc
In-Reply-To: <1293652285-13313-1-git-send-email-ptyser@xes-inc.com>
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 29.12.2010, at 20:51, Peter Tyser wrote:
> Previously SPRGs 4-7 were improperly read and written in
> kvm_arch_vcpu_ioctl_get_regs() and kvm_arch_vcpu_ioctl_set_regs();
>=20
> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Thanks a lot for the catch. At least for Book3S we don't support SPRGs > =
3 anyways, so it's not really too bad of a glitch. It's irritating =
nevertheless :).
Marcelo/Avi, please include this patch in the kvm tree.
Signed-off-by: Alexander Graf <agraf@suse.de>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG/MacGPG2 v2.0.16 (Darwin)
iEYEARECAAYFAk0jjJIACgkQq7Wi27wfN1PIMwCfffOOFsI5K6LXi5AYBUcwK07Q
dGoAn21M9Brz8vxpXxHFNs1QhGOuPGlo
=3D/b/r
-----END PGP SIGNATURE-----
^ permalink raw reply
* Re: Question about combining a PCI driver with an OF driver
From: Scott Wood @ 2011-01-04 21:20 UTC (permalink / raw)
To: Bruce_Leonard; +Cc: linuxppc-dev
In-Reply-To: <OF2F9BC586.7E8383F3-ON8825780E.0072ACEA-8825780E.00735E90@selinc.com>
On Tue, 4 Jan 2011 13:00:07 -0800
<Bruce_Leonard@selinc.com> wrote:
> Okay, I get that and it makes sense with what I know so far about how the
> kernel device model works (which I'm still learning). So how would I
> manually add a device? Say I create the PCI wrapper driver that claims
> the clone-TSEC, is there a "register device" type call similar to
> pci_register_driver() that I could put in the wrapper code that causes the
> gfar_probe() to be called?
Create an OF node (probably under the root node) programatically with
all the information the gianfar driver will want, based on what you
detect on PCI, and call of_platform_device_create().
-Scott
^ permalink raw reply
* Re: Question about combining a PCI driver with an OF driver
From: Sean MacLennan @ 2011-01-04 21:26 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <OF2F9BC586.7E8383F3-ON8825780E.0072ACEA-8825780E.00735E90@selinc.com>
On Tue, 4 Jan 2011 13:00:07 -0800
Bruce_Leonard@selinc.com wrote:
> True, but we really didn't want to recreate all the infrastructure
> that the gianfar driver has in it we wanted to just use it. Maybe
> what I should do is just take the guts of the gianfar driver and make
> a pure PCI driver out of it.
This is what I would do. Odds are the final FPGA driver will have a lot
of "optimizations" and "we don't need this" changes to the point where
you won't be able to read the original code for ifdefs ;)
Cheers,
Sean
^ permalink raw reply
* Re: problem backporting talitos for MPC8272
From: Alexandru Ionut Grama @ 2011-01-04 21:42 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <20110103160706.4329947c@udp111988uds.am.freescale.net>
[-- Attachment #1: Type: text/plain, Size: 3921 bytes --]
You're right Scott, there's no section in arch/powerpc/boot/Makefile
involving dts file for mpc8272ads.
Well some time ago I've already write an email explaining that I've try to
port a custom board patch from 2.6.21 to 2.6.35. I can't make the changes
properly in 2.6.35, so that's why I've decided to backport cryptoAPI and
talitos to 2.6.21.
Because it's custom, the CPM_MAP_ADDR it's change from 0xF0000000 to
0xFF000000. ¿Changing this in mpc8272ads.dts
soc8272@f0000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <00000000 f0000000 00053000>;
reg = <f0000000 10000>;
cpm@f0000000 {
linux,phandle = <f0000000>;
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "cpm";
model = "CPM2";
ranges = <00000000 00000000 20000>;
reg = <0 20000>;
command-proc = <119c0>;
brg-frequency = <17D7840>;
cpm_clk = <BEBC200>;
to this
soc8272@ff000000 {
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "soc";
ranges = <00000000 ff000000 00053000>;
reg = <ff000000 10000>;
cpm@ff000000 {
linux,phandle = <ff000000>;
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <2>;
device_type = "cpm";
model = "CPM2";
ranges = <00000000 00000000 20000>;
reg = <0 20000>;
command-proc = <119c0>;
brg-frequency = <17D7840>;
cpm_clk = <BEBC200>;
should solve this issue?
Also there is change in arch/powerpc/platforms/82xx/mpc82xx_ads.c
+ static void __init m82xx_map_io(void) /* gonza */
+ {
+ io_block_mapping(CPM_MAP_ADDR, CPM_MAP_ADDR, ((uint)(4 * 64 * 1024)),
_PAGE_IO);
+ }
+
+
define_machine(mpc82xx_ads)
{
.name = "MPC82xx ADS",
***************
*** 642,645 ****
--- 648,652 ----
.get_irq = cpm2_get_irq,
.calibrate_decr = m82xx_calibrate_decr,
.restart = m82xx_restart,.halt = m82xx_halt,
+ .setup_io_mappings = m82xx_map_io, /* gonza */
};
Redefining the address of CPM in the dts file, the kernel "io_block_map"
properly that address without no more code?
Thank you very much.
Alexandru.
2011/1/3 Scott Wood <scottwood@freescale.com>
> On Wed, 29 Dec 2010 02:10:55 +0100
> Alexandru Ionut Grama <gramaalexandruionut@gmail.com> wrote:
>
> > My final question it's about of-tree. I have the mpc8272ads.dts file with
> a
> > tree that involves talitos, but I've changed the properties acording the
> new
> > version of it on 2.6.35. ¿This file (mpc8272ads.dts) when it's used?I
> think
> > I don't use this file for nothing (it doesn't appears on make V=1)
> because I
> > don't have a normal bootloader and I have to load the kernel like a
> > flat-binary gz, so there's no more step after building System.map.
>
> IIRC, in 2.6.21, it wasn't used on 82xx (I think there was only
> arch/ppc support for 82xx, or at best 82xx arch/powerpc support was
> just getting started). 2.6.21 is very old, and doing new development on
> it is not recommended.
>
> Why not work with the current kernel?
>
> -Scott
>
>
--
*---------------------------------------------------------------
Alexandru Ionut Grama
**email: gramaalexandruionut@gmail.com**
*
[-- Attachment #2: Type: text/html, Size: 5031 bytes --]
^ permalink raw reply
* Re: problem backporting talitos for MPC8272
From: Scott Wood @ 2011-01-04 22:00 UTC (permalink / raw)
To: Alexandru Ionut Grama; +Cc: linuxppc-dev
In-Reply-To: <AANLkTi=s5id7QJ4nmfdSsuY3Y==b_5xyqHM3Y+K2HUXr@mail.gmail.com>
On Tue, 4 Jan 2011 22:42:49 +0100
Alexandru Ionut Grama <gramaalexandruionut@gmail.com> wrote:
> You're right Scott, there's no section in arch/powerpc/boot/Makefile
> involving dts file for mpc8272ads.
>
> Well some time ago I've already write an email explaining that I've try to
> port a custom board patch from 2.6.21 to 2.6.35. I can't make the changes
> properly in 2.6.35, so that's why I've decided to backport cryptoAPI and
> talitos to 2.6.21.
Well, you may now find that it's not any easier going the other
direction. If you have to put significant effort into either a forward
port of the board code, or a backport of crypto and/or 82xx
arch/powerpc support, it's more useful long-term to get yourself
unstuck from the old kernel -- and people will be more interested in
offering support.
> Redefining the address of CPM in the dts file, the kernel "io_block_map"
> properly that address without no more code?
You can try it, but you're on your own. That was a very early attempt
at support for 82xx in arch/powerpc. I do not recommend using it at
all, much less sinking extensive backporting work into it. Things
change for a reason.
-Scott
^ permalink raw reply
* Re: Question about combining a PCI driver with an OF driver
From: Bruce_Leonard @ 2011-01-04 22:03 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev
In-Reply-To: <20110104152018.080ff075@udp111988uds.am.freescale.net>
>
> > Okay, I get that and it makes sense with what I know so far about how
the
> > kernel device model works (which I'm still learning). So how would I
> > manually add a device? Say I create the PCI wrapper driver that
claims
> > the clone-TSEC, is there a "register device" type call similar to
> > pci_register_driver() that I could put in the wrapper code that causes
the
> > gfar_probe() to be called?
>
> Create an OF node (probably under the root node) programatically with
> all the information the gianfar driver will want, based on what you
> detect on PCI, and call of_platform_device_create().
>
Ah, the light bulb clicks on! Thanks for the info. I appreciate it.
Bruce
^ permalink raw reply
* Re: [RFC] MPIC Bindings and Bindings for AMP Systems
From: Meador Inge @ 2011-01-04 23:52 UTC (permalink / raw)
To: Scott Wood; +Cc: linuxppc-dev, devicetree-discuss, Blanchard, Hollis
In-Reply-To: <20110103142200.738c0b17@udp111988uds.am.freescale.net>
Thanks for the feedback Scott.
On 01/03/2011 02:22 PM, Scott Wood wrote:
> On Wed, 22 Dec 2010 23:58:09 -0600
> These nodes cannot go under the mpic node, because interrupt
> controllers need #address-cells =<0>.
Good point. Do they actually need it or is that just the way it
currently is? [1] mandates it, I didn't see anything in [2] and I can't
access [3].
However, AFAIK '#address-cells' is taken directly from the parent node
and is not inherited from ancestors higher in the tree. So another
option would be to do something like:
mpic: pic@40000 {
...
message-registers@0 {
#address-cells = <1>;
#size-cells = <1>;
msgr@1400 {
compatible = "fsl,mpic-v3.0-msgr";
reg = <0x1400 0x200>;
interrupts = <0xb0 0x2 0xb1 0x2 0xb2 0x2 0xb3 0x2>;
};
msgr@2400 {
compatible = "fsl,mpic-v3.0-msgr";
reg = <0x2400 0x200>;
interrupts = <0xb4 0x2 0xb5 0x2 0xb6 0x2 0xb7 0x2>;
};
};
};
I like the nesting as it models the physical relationship closer and
creates a clean namespace.
> It would be nice if the binding provided some way of partitioning
> up individual message interrupts within a block.
>
> Interrupt generation could be exported as a "service", similar to
> (inbound) interrupts and gpios.
>
> Perhaps a something like this, with "doorbell" being a new standard
> hw-independent service with its own binding:
I need to think about this proposal more, but our original intent was to
just have a simple description of the message registers in the device
tree and the policy for how those message registers are used is in
software (not necessarily an exact API use case, but you get the point):
/* Core 0 */
mpic_msgr_reserve(0);
mpic_msgr_reserve(1);
/* Send message to Core 1 */
mpic_msgr_write(3, 13);
/* Read a value */
u32 value;
mpic_msgr_read(0, &value);
/* Free the register */
mpic_msgr_release(0);
...
/* Core 1 */
mpic_msgr_reserve(3);
mpic_msgr_reserve(4);
/* Send message to Core 0 */
mpic_msgr_write(0, 1);
Note that a "reservation" is still isolated to a particular core, e.g.
'mpic_msgr_reserve(0)' on core 0 will not cause 'mpic_msgr_reserve(0)'
to fail on another core. Where as two invocations of
'mpic_msgr_reserve(0)' on the same core without an interleaved
'mpic_msgr_release(0)' would, of course, fail.
> msg1: mpic-msg@1400 {
> compatible = "fsl,mpic-v3.0-msg";
> reg =<0x1400 0x200>;
> interrupts<176 2 178 2>;
>
> // We have message registers 0 and 2 for sending,
> // and 1 and 3 for receiving.
> // If absent, we own all message registers in this block.
> fsl,mpic-msg-send-mask =<0x5>;
> fsl,mpic-msg-receive-mask =<0xa>;
>
> doorbell-controller;
>
> // split into #doorbell-send-cells and #doorbell-receive-cells?
> #doorbell-cells =<1>;
> };
>
> some-amp-protocol-thingy {
> send-doorbells =<&msg1 0>; // generate messages on MSGR0
> receive-doorbells =<&msg1 0>; // receive messages on MSGR1
> };
>
> some-other-amp-protocol-thingy {
> send-doorbells =<&msg1 1>; // generate messages on MSGR2
> receive-doorbells =<&msg1 1>; // receive messages on MSGR3
> };
>
> Doorbell capabilities such as passing a 32-bit message can be negotiated
> between the drivers for the doorbell controller and the doorbell client.
--
Meador Inge | meador_inge AT mentor.com
Mentor Embedded | http://www.mentor.com/embedded-software
[1] Power.org™ Standard for Embedded Power Architecture™ Platform
Requirements (ePAPR) Version 1.0
[2] PowerPC Microprocessor Common Hardware Reference Platform (CHRP)
Binding, Version 1.8, 1998. Published by the Open Firmware Working Group.
[3] The Open Programmable Interrupt Controller (PIC) Register Interface
Specification Revision 1.2
^ permalink raw reply
* Re: [RFC] MPIC Bindings and Bindings for AMP Systems
From: Scott Wood @ 2011-01-05 0:13 UTC (permalink / raw)
To: Meador Inge; +Cc: Blanchard, Hollis, devicetree-discuss, linuxppc-dev
In-Reply-To: <4D23B2C6.8050607@mentor.com>
On Tue, 4 Jan 2011 17:52:38 -0600
Meador Inge <meador_inge@mentor.com> wrote:
> Thanks for the feedback Scott.
>
> On 01/03/2011 02:22 PM, Scott Wood wrote:
> > On Wed, 22 Dec 2010 23:58:09 -0600
> > These nodes cannot go under the mpic node, because interrupt
> > controllers need #address-cells =<0>.
>
> Good point. Do they actually need it or is that just the way it
> currently is? [1] mandates it, I didn't see anything in [2] and I can't
> access [3].
It's because of the way interrupt maps work -- a full interrupt
specifier includes the node's reg address as well as the values in the
interrupts property. This is useful for things like PCI controllers,
but normal interrupt controllers won't have any use for it.
In theory, I suppose you could have a non-zero #address-cells in an
interrupt controller, but then you'd have to pad the parent interrupt
specifiers in any interrupt map entries that point at the MPIC node with
that many don't-care cells.
Better to just avoid the issue.
> However, AFAIK '#address-cells' is taken directly from the parent node
> and is not inherited from ancestors higher in the tree. So another
> option would be to do something like:
>
> mpic: pic@40000 {
> ...
> message-registers@0 {
> #address-cells = <1>;
> #size-cells = <1>;
>
> msgr@1400 {
> compatible = "fsl,mpic-v3.0-msgr";
> reg = <0x1400 0x200>;
> interrupts = <0xb0 0x2 0xb1 0x2 0xb2 0x2 0xb3 0x2>;
> };
>
> msgr@2400 {
> compatible = "fsl,mpic-v3.0-msgr";
> reg = <0x2400 0x200>;
> interrupts = <0xb4 0x2 0xb5 0x2 0xb6 0x2 0xb7 0x2>;
> };
> };
> };
Won't work, the reg addresses need to be translatable through ranges all
the way up to the root.
> I like the nesting as it models the physical relationship closer and
> creates a clean namespace.
Sure, if it weren't for the #address-cells issue I'd agree.
> > It would be nice if the binding provided some way of partitioning
> > up individual message interrupts within a block.
> >
> > Interrupt generation could be exported as a "service", similar to
> > (inbound) interrupts and gpios.
> >
> > Perhaps a something like this, with "doorbell" being a new standard
> > hw-independent service with its own binding:
>
> I need to think about this proposal more, but our original intent was to
> just have a simple description of the message registers in the device
> tree and the policy for how those message registers are used is in
> software (not necessarily an exact API use case, but you get the point):
That may be fine for your use case (just as some people may be happy
to hardcode device knowledge into their kernel), but in the general case
inter-partition protocols are effectively a non-probeable part of the
"hardware" the partition runs on. It's good to have a standard way of
labelling what goes where. The details of the protocol would still be
in software, referenced by the compatible string on the protocol node.
> /* Core 0 */
> mpic_msgr_reserve(0);
> mpic_msgr_reserve(1);
>
> /* Send message to Core 1 */
> mpic_msgr_write(3, 13);
>
> /* Read a value */
> u32 value;
> mpic_msgr_read(0, &value);
>
> /* Free the register */
> mpic_msgr_release(0);
> ...
>
> /* Core 1 */
> mpic_msgr_reserve(3);
> mpic_msgr_reserve(4);
>
> /* Send message to Core 0 */
> mpic_msgr_write(0, 1);
You're hardcoding into software that core 0 gets msg0 and msg1, and
core 1 gets msg3 and msg4, etc. Not much different than hardcoding that
core 0 gets enet0 and core 1 gets enet1 and enet2.
> Note that a "reservation" is still isolated to a particular core, e.g.
> 'mpic_msgr_reserve(0)' on core 0 will not cause 'mpic_msgr_reserve(0)'
> to fail on another core. Where as two invocations of
> 'mpic_msgr_reserve(0)' on the same core without an interleaved
> 'mpic_msgr_release(0)' would, of course, fail.
So basically, you're assigning the resource to both partitions, and
relying on dynamic cooperation. That's fine, in that case both
partitions would see the resource in their device tree, hopefully along
with something to indicate what the situation is. But dedicated
ownership is common enough, and similar enough to the question of
whether the hardware exists at all, that it's nice to be able to express
it in the device tree. It also makes it easier to deal with situations
where you later want to plug in different hardware (or possibly a
virtualized interface) underneath the protocol.
I'm not sure how much practical benefit there is to dynamically
allocating message registers across partitions, though -- you'd have
to have some way of communicating to the other end the result of the
allocation, so it knows which one to send a message on. And if you
only have 2 cores, and unhypervised AMP, you'll be able to dedicate 4
message registers to each partition...
-Scott
^ permalink raw reply
* Re: powerpc: Per process DSCR
From: Alexey Kardashevskiy @ 2011-01-05 7:01 UTC (permalink / raw)
To: linuxppc-dev
joining the thread...
--
Alexey Kardashevskiy
IBM OzLabs, LTC Team
e-mail/sametime: aik@au1.ibm.com
notes: Alexey Kardashevskiy/Australia/IBM
^ permalink raw reply
* Re: powerpc: Per process DSCR
From: Alexey Kardashevskiy @ 2011-01-05 7:21 UTC (permalink / raw)
To: linuxppc-dev
joining the thread...
--
Alexey Kardashevskiy
IBM OzLabs, LTC Team
e-mail/sametime: aik@au1.ibm.com
notes: Alexey Kardashevskiy/Australia/IBM
^ permalink raw reply
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