* Re: [PATCH v3 00/25] irq_domain generalization and refinement
From: Rob Herring @ 2012-02-06 0:51 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Stephen Rothwell, devicetree-discuss, linux-kernel, Rob Herring,
Milton Miller, Thomas Gleixner, linuxppc-dev, linux-arm-kernel
In-Reply-To: <20120204221748.GN14129@n2100.arm.linux.org.uk>
Russell,
On 02/04/2012 04:17 PM, Russell King - ARM Linux wrote:
> On Fri, Jan 27, 2012 at 02:35:54PM -0700, Grant Likely wrote:
>> Hey everyone,
>>
>> This patch series is ready for much wider consumption now. I'd like
>> to get it into linux-next ASAP because there will be ARM board support
>> depending on it. I'll wait a few days before I ask Stephen to pull
>> this in.
>
> Grant,
>
> Can you answer me this: does this irqdomain support require DT?
>
No. It's the other way around, DT requires irqdomain. The GIC and VIC
code for example can be built with or w/o DT enabled, but both select
IRQ_DOMAIN.
FYI, I just submitted a patch that selects IRQ_DOMAIN for all of ARM:
http://www.gossamer-threads.com/lists/linux/kernel/1487231?page=last
Either we do that or we select IRQ_DOMAIN one irq_chip at a time. With
the "new" irq_domain code, we could probably do better to shrink the
code needed in the non-DT case.
> The question comes up because OMAP has converted some of their support
> to require irq domain support for their PMICs, and it seems irq domain
> support requires DT. This seems to have made the whole of OMAP
> essentially become a DT-only platform.
I think we should select DT or not at the sub-arch level. Trying to
support both builds is a needless headache.
>
> Removing the dependency on IRQ_DOMAIN brings up these build errors
> in the twl-core code (that being the PMIC for OMAP CPUs):
>
> drivers/mfd/twl-core.c: In function 'twl_probe':
> drivers/mfd/twl-core.c:1229: error: invalid use of undefined type 'struct irq_domain'
> drivers/mfd/twl-core.c:1230: error: invalid use of undefined type 'struct irq_domain'
> drivers/mfd/twl-core.c:1235: error: implicit declaration of function 'irq_domain_add'
>
> That's a bit of a problem, because afaik there aren't the DT descriptions
> for the boards I have yet, so it's causing me to see regressions when
> building and booting kernels with CONFIG_OF=n.
>
> The more core-code we end up with which requires DT, the worse this
> problem is going to become - and obviously saying "everyone must now
> convert to DT" is, even today, a mammoth task.
>
> Now, here's the thing: I believe that IRQ domains - at least as far as
> the hwirq stuff - should be available irrespective of whether we have
> the rest of the IRQ domain support code in place, so that IRQ support
> code doesn't have to keep playing games to decode from the global
> space to the per-controller number space.
>
> I believe that would certainly help the current OMAP problems, where
> the current lack of CONFIG_IRQ_DOMAIN basically makes the kernel oops
> on boot.
>
> How we fix this regression for 3.4 I've no idea at present, I'm trying
> to work out what the real dependencies are for OMAP on this stuff.
>
> Finally, do we need asm/irq.h in our asm/prom.h ? That's causing
> fragility between DT and non-DT builds, because people are finding
> that their DT builds work without their mach/irqs.h includes but
> fail when built with non-DT. The only thing which DT might need -
> at the most - is NR_IRQS, but I'd hope with things like irq domains
> it doesn't actually require it.
Doesn't look like it is needed.
Rob
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
^ permalink raw reply
* [PATCH 1/2] powerpc/44x: Add new compatible value for EMAC node of APM821XX dts file.
From: Duc Dang @ 2012-02-06 4:08 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: Duc Dang, linuxppc-dev, linux-kernel
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 1298 bytes --]
This compatible value will be used to distinguish some special
features of APM821XX EMAC: no half duplex mode support, configuring
jumbo frame.
Signed-off-by: Duc Dang <dhdang@apm.com>
---
arch/powerpc/boot/dts/bluestone.dts | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/bluestone.dts b/arch/powerpc/boot/dts/bluestone.dts
index 2a56a0d..74876f7 100644
--- a/arch/powerpc/boot/dts/bluestone.dts
+++ b/arch/powerpc/boot/dts/bluestone.dts
@@ -222,7 +222,7 @@
EMAC0: ethernet@ef600c00 {
device_type = "network";
- compatible = "ibm,emac4sync";
+ compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
interrupt-parent = <&EMAC0>;
interrupts = <0x0 0x1>;
#interrupt-cells = <1>;
--
1.7.5.4
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is for the sole use of the intended recipient(s) and contains information
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* [PATCH 2/2] powerpc/44x: Add more changes for APM821XX EMAC driver
From: Duc Dang @ 2012-02-06 4:10 UTC (permalink / raw)
To: Benjamin Herrenschmidt, Paul Mackerras
Cc: Duc Dang, linuxppc-dev, linux-kernel
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain, Size: 5611 bytes --]
This patch includes:
Configure EMAC PHY clock source (clock from PHY or internal clock).
Do not advertise PHY half duplex capability as APM821XX EMAC does not
support half duplex mode.
Add changes to support configuring jumbo frame for APM821XX EMAC.
Signed-off-by: Duc Dang <dhdang@apm.com>
---
drivers/net/ethernet/ibm/emac/core.c | 26 +++++++++++++++++++++++++-
drivers/net/ethernet/ibm/emac/core.h | 13 +++++++++++--
drivers/net/ethernet/ibm/emac/emac.h | 5 ++++-
3 files changed, 40 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/ibm/emac/core.c b/drivers/net/ethernet/ibm/emac/core.c
index ed79b2d..de620f1 100644
--- a/drivers/net/ethernet/ibm/emac/core.c
+++ b/drivers/net/ethernet/ibm/emac/core.c
@@ -434,6 +434,11 @@ static inline u32 emac_iff2rmr(struct net_device *ndev)
else if (!netdev_mc_empty(ndev))
r |= EMAC_RMR_MAE;
+ if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE)) {
+ r &= ~EMAC4_RMR_MJS_MASK;
+ r |= EMAC4_RMR_MJS(ndev->mtu);
+ }
+
return r;
}
@@ -965,6 +970,7 @@ static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
int rx_sync_size = emac_rx_sync_size(new_mtu);
int rx_skb_size = emac_rx_skb_size(new_mtu);
int i, ret = 0;
+ int mr1_jumbo_bit_change = 0;
mutex_lock(&dev->link_lock);
emac_netif_stop(dev);
@@ -1013,7 +1019,14 @@ static int emac_resize_rx_ring(struct emac_instance *dev, int new_mtu)
}
skip:
/* Check if we need to change "Jumbo" bit in MR1 */
- if ((new_mtu > ETH_DATA_LEN) ^ (dev->ndev->mtu > ETH_DATA_LEN)) {
+ if (emac_has_feature(dev, EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE))
+ mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ||
+ (dev->ndev->mtu > ETH_DATA_LEN);
+ else
+ mr1_jumbo_bit_change = (new_mtu > ETH_DATA_LEN) ^
+ (dev->ndev->mtu > ETH_DATA_LEN);
+
+ if (mr1_jumbo_bit_change) {
/* This is to prevent starting RX channel in emac_rx_enable() */
set_bit(MAL_COMMAC_RX_STOPPED, &dev->commac.flags);
@@ -2471,6 +2484,7 @@ static int __devinit emac_init_phy(struct emac_instance *dev)
/* Disable any PHY features not supported by the platform */
dev->phy.def->features &= ~dev->phy_feat_exc;
+ dev->phy.features &= ~dev->phy_feat_exc;
/* Setup initial link parameters */
if (dev->phy.features & SUPPORTED_Autoneg) {
@@ -2568,6 +2582,10 @@ static int __devinit emac_init_config(struct emac_instance *dev)
if (of_device_is_compatible(np, "ibm,emac-405ex") ||
of_device_is_compatible(np, "ibm,emac-405exr"))
dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX;
+ if (of_device_is_compatible(np, "ibm,emac-apm821xx"))
+ dev->features |= (EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE
+ | EMAC_FTR_APM821XX_NO_HALF_DUPLEX
+ | EMAC_FTR_460EX_PHY_CLK_FIX);
} else if (of_device_is_compatible(np, "ibm,emac4")) {
dev->features |= EMAC_FTR_EMAC4;
if (of_device_is_compatible(np, "ibm,emac-440gx"))
@@ -2818,6 +2836,12 @@ static int __devinit emac_probe(struct platform_device *ofdev)
dev->stop_timeout = STOP_TIMEOUT_100;
INIT_DELAYED_WORK(&dev->link_work, emac_link_timer);
+ /* Some SoCs like APM821xx does not support Half Duplex mode. */
+ if (emac_has_feature(dev, EMAC_FTR_APM821XX_NO_HALF_DUPLEX))
+ dev->phy_feat_exc = (SUPPORTED_1000baseT_Half
+ | SUPPORTED_100baseT_Half
+ | SUPPORTED_10baseT_Half);
+
/* Find PHY if any */
err = emac_init_phy(dev);
if (err != 0)
diff --git a/drivers/net/ethernet/ibm/emac/core.h b/drivers/net/ethernet/ibm/emac/core.h
index fa3ec57..9dea85a 100644
--- a/drivers/net/ethernet/ibm/emac/core.h
+++ b/drivers/net/ethernet/ibm/emac/core.h
@@ -325,7 +325,14 @@ struct emac_instance {
* Set if we need phy clock workaround for 460ex or 460gt
*/
#define EMAC_FTR_460EX_PHY_CLK_FIX 0x00000400
-
+/*
+ * APM821xx requires Jumbo frame size set explicitly
+ */
+#define EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE 0x00000800
+/*
+ * APM821xx does not support Half Duplex mode
+ */
+#define EMAC_FTR_APM821XX_NO_HALF_DUPLEX 0x00001000
/* Right now, we don't quite handle the always/possible masks on the
* most optimal way as we don't have a way to say something like
@@ -353,7 +360,9 @@ enum {
EMAC_FTR_NO_FLOW_CONTROL_40x |
#endif
EMAC_FTR_460EX_PHY_CLK_FIX |
- EMAC_FTR_440EP_PHY_CLK_FIX,
+ EMAC_FTR_440EP_PHY_CLK_FIX |
+ EMAC_APM821XX_REQ_JUMBO_FRAME_SIZE |
+ EMAC_FTR_APM821XX_NO_HALF_DUPLEX,
};
static inline int emac_has_feature(struct emac_instance *dev,
diff --git a/drivers/net/ethernet/ibm/emac/emac.h b/drivers/net/ethernet/ibm/emac/emac.h
index 1568278..36bcd69 100644
--- a/drivers/net/ethernet/ibm/emac/emac.h
+++ b/drivers/net/ethernet/ibm/emac/emac.h
@@ -212,7 +212,10 @@ struct emac_regs {
#define EMAC4_RMR_RFAF_64_1024 0x00000006
#define EMAC4_RMR_RFAF_128_2048 0x00000007
#define EMAC4_RMR_BASE EMAC4_RMR_RFAF_128_2048
-
+#if defined(CONFIG_APM821xx)
+#define EMAC4_RMR_MJS_MASK 0x0001fff8
+#define EMAC4_RMR_MJS(s) (((s) << 3) & EMAC4_RMR_MJS_MASK)
+#endif
/* EMACx_ISR & EMACx_ISER */
#define EMAC4_ISR_TXPE 0x20000000
#define EMAC4_ISR_RXPE 0x10000000
--
1.7.5.4
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is for the sole use of the intended recipient(s) and contains information
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^ permalink raw reply related
* Re: [PATCH v3 21/25] irqdomain/powerpc: Replace custom xlate functions with library functions
From: Michael Neuling @ 2012-02-06 5:22 UTC (permalink / raw)
To: Grant Likely
Cc: Stephen Rothwell, devicetree-discuss, linux-kernel, Rob Herring,
Milton Miller, Thomas Gleixner, linuxppc-dev, linux-arm-kernel
In-Reply-To: <1327700179-17454-22-git-send-email-grant.likely@secretlab.ca>
> static const struct irq_domain_ops pmac_pic_host_ops = {
> .match = pmac_pic_host_match,
> .map = pmac_pic_host_map,
> - .xlate = pmac_pic_host_xlate,
> + .xlate = irq_domain_xlate_onecell;
> };
>
This causes a compile fail (in next-20120206):
arch/powerpc/platforms/powermac/pic.c:294: error: expected '}' before ';' token
Trivial fix below:
irqdomain/powerpc: Fix compile error in powermac/pic.c
Error introduced in:
commit 72d6b477675374eafd206720d6c9146520df18ce
Author: Grant Likely <grant.likely@secretlab.ca>
irqdomain/powerpc: Replace custom xlate functions with library functions
Signed-off-by: Michael Neuling <mikey@neuling.org>
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 3af29d1..92afc38 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -291,7 +291,7 @@ static int pmac_pic_host_map(struct irq_domain *h, unsigned int virq,
static const struct irq_domain_ops pmac_pic_host_ops = {
.match = pmac_pic_host_match,
.map = pmac_pic_host_map,
- .xlate = irq_domain_xlate_onecell;
+ .xlate = irq_domain_xlate_onecell,
};
static void __init pmac_pic_probe_oldstyle(void)
^ permalink raw reply related
* Re: [PATCH v3 00/25] irq_domain generalization and refinement
From: Grant Likely @ 2012-02-06 5:56 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Stephen Rothwell, devicetree-discuss, linux-kernel, Rob Herring,
Milton Miller, Thomas Gleixner, linuxppc-dev, linux-arm-kernel
In-Reply-To: <20120204221748.GN14129@n2100.arm.linux.org.uk>
On Sat, Feb 04, 2012 at 10:17:48PM +0000, Russell King - ARM Linux wrote:
> On Fri, Jan 27, 2012 at 02:35:54PM -0700, Grant Likely wrote:
> > Hey everyone,
> >
> > This patch series is ready for much wider consumption now. I'd like
> > to get it into linux-next ASAP because there will be ARM board support
> > depending on it. I'll wait a few days before I ask Stephen to pull
> > this in.
>
> Grant,
>
> Can you answer me this: does this irqdomain support require DT?
No, it should not. Any situation where it does is a bug.
> Now, here's the thing: I believe that IRQ domains - at least as far as
> the hwirq stuff - should be available irrespective of whether we have
> the rest of the IRQ domain support code in place, so that IRQ support
> code doesn't have to keep playing games to decode from the global
> space to the per-controller number space.
Correct. That's the intent. My new series flushes out irq_domain quite a
bit better and gets all architectures doing the same thing if they use
irq_domains. I've done some testing on both CONFIG_OF and !CONFIG_OF builds,
but I'm going to do some more to make sure I've not missed anything.
> I believe that would certainly help the current OMAP problems, where
> the current lack of CONFIG_IRQ_DOMAIN basically makes the kernel oops
> on boot.
>
> How we fix this regression for 3.4 I've no idea at present, I'm trying
> to work out what the real dependencies are for OMAP on this stuff.
>
> Finally, do we need asm/irq.h in our asm/prom.h ? That's causing
> fragility between DT and non-DT builds, because people are finding
> that their DT builds work without their mach/irqs.h includes but
> fail when built with non-DT. The only thing which DT might need -
> at the most - is NR_IRQS, but I'd hope with things like irq domains
> it doesn't actually require it.
I don't think so. There may be a file or two that break because they're
not including everything they need, but I don't think anything in the
header requires it.
The irq_domain code is well isolated. The header file doesn't need to
be including it.
g.
^ permalink raw reply
* Re: [PATCH v3 21/25] irqdomain/powerpc: Replace custom xlate functions with library functions
From: Grant Likely @ 2012-02-06 6:00 UTC (permalink / raw)
To: Michael Neuling
Cc: Stephen Rothwell, devicetree-discuss, linux-kernel, Rob Herring,
Milton Miller, Thomas Gleixner, linuxppc-dev, linux-arm-kernel
In-Reply-To: <24476.1328505761@neuling.org>
On Mon, Feb 06, 2012 at 04:22:41PM +1100, Michael Neuling wrote:
> > static const struct irq_domain_ops pmac_pic_host_ops = {
> > .match = pmac_pic_host_match,
> > .map = pmac_pic_host_map,
> > - .xlate = pmac_pic_host_xlate,
> > + .xlate = irq_domain_xlate_onecell;
> > };
> >
>
> This causes a compile fail (in next-20120206):
> arch/powerpc/platforms/powermac/pic.c:294: error: expected '}' before ';' token
> Trivial fix below:
fixed, thanks.
g.
>
>
>
> irqdomain/powerpc: Fix compile error in powermac/pic.c
>
> Error introduced in:
> commit 72d6b477675374eafd206720d6c9146520df18ce
> Author: Grant Likely <grant.likely@secretlab.ca>
> irqdomain/powerpc: Replace custom xlate functions with library functions
>
> Signed-off-by: Michael Neuling <mikey@neuling.org>
>
> diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
> index 3af29d1..92afc38 100644
> --- a/arch/powerpc/platforms/powermac/pic.c
> +++ b/arch/powerpc/platforms/powermac/pic.c
> @@ -291,7 +291,7 @@ static int pmac_pic_host_map(struct irq_domain *h, unsigned int virq,
> static const struct irq_domain_ops pmac_pic_host_ops = {
> .match = pmac_pic_host_match,
> .map = pmac_pic_host_map,
> - .xlate = irq_domain_xlate_onecell;
> + .xlate = irq_domain_xlate_onecell,
> };
>
> static void __init pmac_pic_probe_oldstyle(void)
^ permalink raw reply
* Erase flash boot from default env
From: smitha.vanga @ 2012-02-06 14:25 UTC (permalink / raw)
To: wd; +Cc: scottwood, linuxppc-dev
In-Reply-To: <20120110215509.2D08D1167AA4@gemini.denx.de>
Hi ,
When I run flinfo in bootloader I get some locatios indicated with RO meani=
ng read only.
Can I erase these locations. Actually I tried to erase and could not erase e=
ven when I set protect off for this address
Range in the environment parameters.
I want to get the bootloader to boot with the default enironment parameters.=
Insetad of the saved environment params. How to go about this.
Regards,
Smitha
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^ permalink raw reply
* [PATCH] powerpc/fsl: add PAMUBYPENR register definition to fsl_guts.h
From: Timur Tabi @ 2012-02-06 19:17 UTC (permalink / raw)
To: galak, linuxppc-dev
Add a defintion of register PAMUBYPENR (offset 0x604) to the global
utilities structure.
PAMUBYPENR is the PAMU bypass enable register. It contains control
bits for enabling bypass mode on each PAMU.
Signed-off-by: Timur Tabi <timur@freescale.com>
---
arch/powerpc/include/asm/fsl_guts.h | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
index bebd124..a9a85ef 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -85,7 +85,9 @@ struct ccsr_guts_86xx {
u8 res0c4[0x224 - 0xc4];
__be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
__be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
- u8 res22c[0x800 - 0x22c];
+ u8 res22c[0x604 - 0x22c];
+ __be32 pamubypenr; /* 0x.0604 - PAMU bypass enable register */
+ u8 res608[0x800 - 0x608];
__be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
u8 res804[0x900 - 0x804];
__be32 ircr; /* 0x.0900 - Infrared Control Register */
--
1.7.3.4
^ permalink raw reply related
* [PATCH 0/2] powerpc: Add support for GE IMP3A
From: Martyn Welch @ 2012-02-07 11:28 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Martyn Welch, Wim Van Sebroeck, linux-kernel
These patches add support for the GE IMP3A. This board (based on a Freescale
P2020) uses some support for FPGA logic common with the PPC9A and other 86xx
based boards, so this support has been moved out of the 86xx directory. A
config option (GE_FPGA) has been added to reduce churn on dependant drivers
(such as the watchdog timer) when further boards are added.
^ permalink raw reply
* [PATCH 1/2] powerpc: Move GE GPIO and PIC drivers
From: Martyn Welch @ 2012-02-07 11:28 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Martyn Welch, Wim Van Sebroeck, linux-kernel
In-Reply-To: <1328614121-17803-1-git-send-email-martyn.welch@ge.com>
Move the GE GPIO and PIC drivers to allow these to be used by non-86xx
boards.
Signed-off-by: Martyn Welch <martyn.welch@ge.com>
---
arch/powerpc/platforms/86xx/Kconfig | 3 +
arch/powerpc/platforms/86xx/Makefile | 7 +-
arch/powerpc/platforms/86xx/gef_gpio.c | 171 --------------------
arch/powerpc/platforms/86xx/gef_pic.c | 252 ------------------------------
arch/powerpc/platforms/86xx/gef_pic.h | 11 --
arch/powerpc/platforms/86xx/gef_ppc9a.c | 3 +-
arch/powerpc/platforms/86xx/gef_sbc310.c | 3 +-
arch/powerpc/platforms/86xx/gef_sbc610.c | 3 +-
arch/powerpc/platforms/Kconfig | 7 +
arch/powerpc/platforms/Makefile | 3 +
arch/powerpc/platforms/ge_gpio.c | 171 ++++++++++++++++++++
arch/powerpc/platforms/ge_pic.c | 252 ++++++++++++++++++++++++++++++
arch/powerpc/platforms/ge_pic.h | 11 ++
drivers/watchdog/Kconfig | 2 +-
14 files changed, 457 insertions(+), 442 deletions(-)
delete mode 100644 arch/powerpc/platforms/86xx/gef_gpio.c
delete mode 100644 arch/powerpc/platforms/86xx/gef_pic.c
delete mode 100644 arch/powerpc/platforms/86xx/gef_pic.h
create mode 100644 arch/powerpc/platforms/ge_gpio.c
create mode 100644 arch/powerpc/platforms/ge_pic.c
create mode 100644 arch/powerpc/platforms/ge_pic.h
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 8d6599d..2015022 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -39,6 +39,7 @@ config GEF_PPC9A
select MMIO_NVRAM
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
+ select GE_FPGA
help
This option enables support for the GE PPC9A.
@@ -48,6 +49,7 @@ config GEF_SBC310
select MMIO_NVRAM
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
+ select GE_FPGA
help
This option enables support for the GE SBC310.
@@ -58,6 +60,7 @@ config GEF_SBC610
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
select HAS_RAPIDIO
+ select GE_FPGA
help
This option enables support for the GE SBC610.
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index 4b0d7b1..ede815d 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -7,7 +7,6 @@ obj-$(CONFIG_SMP) += mpc86xx_smp.o
obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
obj-$(CONFIG_SBC8641D) += sbc8641d.o
obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
-gef-gpio-$(CONFIG_GPIOLIB) += gef_gpio.o
-obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o gef_pic.o $(gef-gpio-y)
-obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o gef_pic.o $(gef-gpio-y)
-obj-$(CONFIG_GEF_PPC9A) += gef_ppc9a.o gef_pic.o $(gef-gpio-y)
+obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o
+obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o
+obj-$(CONFIG_GEF_PPC9A) += gef_ppc9a.o
diff --git a/arch/powerpc/platforms/86xx/gef_gpio.c b/arch/powerpc/platforms/86xx/gef_gpio.c
deleted file mode 100644
index 2a70336..0000000
--- a/arch/powerpc/platforms/86xx/gef_gpio.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Driver for GE FPGA based GPIO
- *
- * Author: Martyn Welch <martyn.welch@ge.com>
- *
- * 2008 (c) GE Intelligent Platforms Embedded Systems, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/* TODO
- *
- * Configuration of output modes (totem-pole/open-drain)
- * Interrupt configuration - interrupts are always generated the FPGA relies on
- * the I/O interrupt controllers mask to stop them propergating
- */
-
-#include <linux/kernel.h>
-#include <linux/compiler.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/of_platform.h>
-#include <linux/of_gpio.h>
-#include <linux/gpio.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-
-#define GEF_GPIO_DIRECT 0x00
-#define GEF_GPIO_IN 0x04
-#define GEF_GPIO_OUT 0x08
-#define GEF_GPIO_TRIG 0x0C
-#define GEF_GPIO_POLAR_A 0x10
-#define GEF_GPIO_POLAR_B 0x14
-#define GEF_GPIO_INT_STAT 0x18
-#define GEF_GPIO_OVERRUN 0x1C
-#define GEF_GPIO_MODE 0x20
-
-static void _gef_gpio_set(void __iomem *reg, unsigned int offset, int value)
-{
- unsigned int data;
-
- data = ioread32be(reg);
- /* value: 0=low; 1=high */
- if (value & 0x1)
- data = data | (0x1 << offset);
- else
- data = data & ~(0x1 << offset);
-
- iowrite32be(data, reg);
-}
-
-
-static int gef_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
-{
- unsigned int data;
- struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
-
- data = ioread32be(mmchip->regs + GEF_GPIO_DIRECT);
- data = data | (0x1 << offset);
- iowrite32be(data, mmchip->regs + GEF_GPIO_DIRECT);
-
- return 0;
-}
-
-static int gef_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
-{
- unsigned int data;
- struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
-
- /* Set direction before switching to input */
- _gef_gpio_set(mmchip->regs + GEF_GPIO_OUT, offset, value);
-
- data = ioread32be(mmchip->regs + GEF_GPIO_DIRECT);
- data = data & ~(0x1 << offset);
- iowrite32be(data, mmchip->regs + GEF_GPIO_DIRECT);
-
- return 0;
-}
-
-static int gef_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
- unsigned int data;
- int state = 0;
- struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
-
- data = ioread32be(mmchip->regs + GEF_GPIO_IN);
- state = (int)((data >> offset) & 0x1);
-
- return state;
-}
-
-static void gef_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
- struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
-
- _gef_gpio_set(mmchip->regs + GEF_GPIO_OUT, offset, value);
-}
-
-static int __init gef_gpio_init(void)
-{
- struct device_node *np;
- int retval;
- struct of_mm_gpio_chip *gef_gpio_chip;
-
- for_each_compatible_node(np, NULL, "gef,sbc610-gpio") {
-
- pr_debug("%s: Initialising GEF GPIO\n", np->full_name);
-
- /* Allocate chip structure */
- gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
- if (!gef_gpio_chip) {
- pr_err("%s: Unable to allocate structure\n",
- np->full_name);
- continue;
- }
-
- /* Setup pointers to chip functions */
- gef_gpio_chip->gc.of_gpio_n_cells = 2;
- gef_gpio_chip->gc.ngpio = 19;
- gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
- gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
- gef_gpio_chip->gc.get = gef_gpio_get;
- gef_gpio_chip->gc.set = gef_gpio_set;
-
- /* This function adds a memory mapped GPIO chip */
- retval = of_mm_gpiochip_add(np, gef_gpio_chip);
- if (retval) {
- kfree(gef_gpio_chip);
- pr_err("%s: Unable to add GPIO\n", np->full_name);
- }
- }
-
- for_each_compatible_node(np, NULL, "gef,sbc310-gpio") {
-
- pr_debug("%s: Initialising GEF GPIO\n", np->full_name);
-
- /* Allocate chip structure */
- gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
- if (!gef_gpio_chip) {
- pr_err("%s: Unable to allocate structure\n",
- np->full_name);
- continue;
- }
-
- /* Setup pointers to chip functions */
- gef_gpio_chip->gc.of_gpio_n_cells = 2;
- gef_gpio_chip->gc.ngpio = 6;
- gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
- gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
- gef_gpio_chip->gc.get = gef_gpio_get;
- gef_gpio_chip->gc.set = gef_gpio_set;
-
- /* This function adds a memory mapped GPIO chip */
- retval = of_mm_gpiochip_add(np, gef_gpio_chip);
- if (retval) {
- kfree(gef_gpio_chip);
- pr_err("%s: Unable to add GPIO\n", np->full_name);
- }
- }
-
- return 0;
-};
-arch_initcall(gef_gpio_init);
-
-MODULE_DESCRIPTION("GE I/O FPGA GPIO driver");
-MODULE_AUTHOR("Martyn Welch <martyn.welch@ge.com");
-MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/platforms/86xx/gef_pic.c
deleted file mode 100644
index 94594e5..0000000
--- a/arch/powerpc/platforms/86xx/gef_pic.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * Interrupt handling for GE FPGA based PIC
- *
- * Author: Martyn Welch <martyn.welch@ge.com>
- *
- * 2008 (c) GE Intelligent Platforms Embedded Systems, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <asm/prom.h>
-#include <asm/irq.h>
-
-#include "gef_pic.h"
-
-#define DEBUG
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(fmt...) do { printk(KERN_DEBUG "gef_pic: " fmt); } while (0)
-#else
-#define DBG(fmt...) do { } while (0)
-#endif
-
-#define GEF_PIC_NUM_IRQS 32
-
-/* Interrupt Controller Interface Registers */
-#define GEF_PIC_INTR_STATUS 0x0000
-
-#define GEF_PIC_INTR_MASK(cpu) (0x0010 + (0x4 * cpu))
-#define GEF_PIC_CPU0_INTR_MASK GEF_PIC_INTR_MASK(0)
-#define GEF_PIC_CPU1_INTR_MASK GEF_PIC_INTR_MASK(1)
-
-#define GEF_PIC_MCP_MASK(cpu) (0x0018 + (0x4 * cpu))
-#define GEF_PIC_CPU0_MCP_MASK GEF_PIC_MCP_MASK(0)
-#define GEF_PIC_CPU1_MCP_MASK GEF_PIC_MCP_MASK(1)
-
-
-static DEFINE_RAW_SPINLOCK(gef_pic_lock);
-
-static void __iomem *gef_pic_irq_reg_base;
-static struct irq_host *gef_pic_irq_host;
-static int gef_pic_cascade_irq;
-
-/*
- * Interrupt Controller Handling
- *
- * The interrupt controller handles interrupts for most on board interrupts,
- * apart from PCI interrupts. For example on SBC610:
- *
- * 17:31 RO Reserved
- * 16 RO PCI Express Doorbell 3 Status
- * 15 RO PCI Express Doorbell 2 Status
- * 14 RO PCI Express Doorbell 1 Status
- * 13 RO PCI Express Doorbell 0 Status
- * 12 RO Real Time Clock Interrupt Status
- * 11 RO Temperature Interrupt Status
- * 10 RO Temperature Critical Interrupt Status
- * 9 RO Ethernet PHY1 Interrupt Status
- * 8 RO Ethernet PHY3 Interrupt Status
- * 7 RO PEX8548 Interrupt Status
- * 6 RO Reserved
- * 5 RO Watchdog 0 Interrupt Status
- * 4 RO Watchdog 1 Interrupt Status
- * 3 RO AXIS Message FIFO A Interrupt Status
- * 2 RO AXIS Message FIFO B Interrupt Status
- * 1 RO AXIS Message FIFO C Interrupt Status
- * 0 RO AXIS Message FIFO D Interrupt Status
- *
- * Interrupts can be forwarded to one of two output lines. Nothing
- * clever is done, so if the masks are incorrectly set, a single input
- * interrupt could generate interrupts on both output lines!
- *
- * The dual lines are there to allow the chained interrupts to be easily
- * passed into two different cores. We currently do not use this functionality
- * in this driver.
- *
- * Controller can also be configured to generate Machine checks (MCP), again on
- * two lines, to be attached to two different cores. It is suggested that these
- * should be masked out.
- */
-
-void gef_pic_cascade(unsigned int irq, struct irq_desc *desc)
-{
- struct irq_chip *chip = irq_desc_get_chip(desc);
- unsigned int cascade_irq;
-
- /*
- * See if we actually have an interrupt, call generic handling code if
- * we do.
- */
- cascade_irq = gef_pic_get_irq();
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-
- chip->irq_eoi(&desc->irq_data);
-}
-
-static void gef_pic_mask(struct irq_data *d)
-{
- unsigned long flags;
- unsigned int hwirq = irqd_to_hwirq(d);
- u32 mask;
-
- raw_spin_lock_irqsave(&gef_pic_lock, flags);
- mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
- mask &= ~(1 << hwirq);
- out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
- raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
-}
-
-static void gef_pic_mask_ack(struct irq_data *d)
-{
- /* Don't think we actually have to do anything to ack an interrupt,
- * we just need to clear down the devices interrupt and it will go away
- */
- gef_pic_mask(d);
-}
-
-static void gef_pic_unmask(struct irq_data *d)
-{
- unsigned long flags;
- unsigned int hwirq = irqd_to_hwirq(d);
- u32 mask;
-
- raw_spin_lock_irqsave(&gef_pic_lock, flags);
- mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
- mask |= (1 << hwirq);
- out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
- raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
-}
-
-static struct irq_chip gef_pic_chip = {
- .name = "gefp",
- .irq_mask = gef_pic_mask,
- .irq_mask_ack = gef_pic_mask_ack,
- .irq_unmask = gef_pic_unmask,
-};
-
-
-/* When an interrupt is being configured, this call allows some flexibilty
- * in deciding which irq_chip structure is used
- */
-static int gef_pic_host_map(struct irq_host *h, unsigned int virq,
- irq_hw_number_t hwirq)
-{
- /* All interrupts are LEVEL sensitive */
- irq_set_status_flags(virq, IRQ_LEVEL);
- irq_set_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
-
- return 0;
-}
-
-static int gef_pic_host_xlate(struct irq_host *h, struct device_node *ct,
- const u32 *intspec, unsigned int intsize,
- irq_hw_number_t *out_hwirq, unsigned int *out_flags)
-{
-
- *out_hwirq = intspec[0];
- if (intsize > 1)
- *out_flags = intspec[1];
- else
- *out_flags = IRQ_TYPE_LEVEL_HIGH;
-
- return 0;
-}
-
-static struct irq_host_ops gef_pic_host_ops = {
- .map = gef_pic_host_map,
- .xlate = gef_pic_host_xlate,
-};
-
-
-/*
- * Initialisation of PIC, this should be called in BSP
- */
-void __init gef_pic_init(struct device_node *np)
-{
- unsigned long flags;
-
- /* Map the devices registers into memory */
- gef_pic_irq_reg_base = of_iomap(np, 0);
-
- raw_spin_lock_irqsave(&gef_pic_lock, flags);
-
- /* Initialise everything as masked. */
- out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_INTR_MASK, 0);
- out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_INTR_MASK, 0);
-
- out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_MCP_MASK, 0);
- out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_MCP_MASK, 0);
-
- raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
-
- /* Map controller */
- gef_pic_cascade_irq = irq_of_parse_and_map(np, 0);
- if (gef_pic_cascade_irq == NO_IRQ) {
- printk(KERN_ERR "SBC610: failed to map cascade interrupt");
- return;
- }
-
- /* Setup an irq_host structure */
- gef_pic_irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
- GEF_PIC_NUM_IRQS,
- &gef_pic_host_ops, NO_IRQ);
- if (gef_pic_irq_host == NULL)
- return;
-
- /* Chain with parent controller */
- irq_set_chained_handler(gef_pic_cascade_irq, gef_pic_cascade);
-}
-
-/*
- * This is called when we receive an interrupt with apparently comes from this
- * chip - check, returning the highest interrupt generated or return NO_IRQ
- */
-unsigned int gef_pic_get_irq(void)
-{
- u32 cause, mask, active;
- unsigned int virq = NO_IRQ;
- int hwirq;
-
- cause = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_STATUS);
-
- mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
-
- active = cause & mask;
-
- if (active) {
- for (hwirq = GEF_PIC_NUM_IRQS - 1; hwirq > -1; hwirq--) {
- if (active & (0x1 << hwirq))
- break;
- }
- virq = irq_linear_revmap(gef_pic_irq_host,
- (irq_hw_number_t)hwirq);
- }
-
- return virq;
-}
-
diff --git a/arch/powerpc/platforms/86xx/gef_pic.h b/arch/powerpc/platforms/86xx/gef_pic.h
deleted file mode 100644
index 6149916..0000000
--- a/arch/powerpc/platforms/86xx/gef_pic.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __GEF_PIC_H__
-#define __GEF_PIC_H__
-
-#include <linux/init.h>
-
-void gef_pic_cascade(unsigned int, struct irq_desc *);
-unsigned int gef_pic_get_irq(void);
-void gef_pic_init(struct device_node *);
-
-#endif /* __GEF_PIC_H__ */
-
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 60ce07e..132917d 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -38,8 +38,9 @@
#include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h>
+#include <platforms/ge_pic.h>
+
#include "mpc86xx.h"
-#include "gef_pic.h"
#undef DEBUG
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c b/arch/powerpc/platforms/86xx/gef_sbc310.c
index 3ecee25..3d7894d 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc310.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -38,8 +38,9 @@
#include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h>
+#include <platforms/ge_pic.h>
+
#include "mpc86xx.h"
-#include "gef_pic.h"
#undef DEBUG
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index 5090d60..4f6b6a4 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -38,8 +38,9 @@
#include <sysdev/fsl_pci.h>
#include <sysdev/fsl_soc.h>
+#include <platforms/ge_pic.h>
+
#include "mpc86xx.h"
-#include "gef_pic.h"
#undef DEBUG
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 0cfb46d..2578e82 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -363,4 +363,11 @@ config XILINX_PCI
bool "Xilinx PCI host bridge support"
depends on PCI && XILINX_VIRTEX
+config GE_FPGA
+ bool
+ default n
+ help
+ Support for common GPIO and interrupt routing functionality provided
+ on some GE Single Board Computers.
+
endmenu
diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile
index 2635a22..38742cf 100644
--- a/arch/powerpc/platforms/Makefile
+++ b/arch/powerpc/platforms/Makefile
@@ -3,6 +3,9 @@ subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
obj-$(CONFIG_FSL_ULI1575) += fsl_uli1575.o
+gef-gpio-$(CONFIG_GPIOLIB) += ge_gpio.o
+obj-$(CONFIG_GE_FPGA) += ge_pic.o $(gef-gpio-y)
+
obj-$(CONFIG_PPC_PMAC) += powermac/
obj-$(CONFIG_PPC_CHRP) += chrp/
obj-$(CONFIG_40x) += 40x/
diff --git a/arch/powerpc/platforms/ge_gpio.c b/arch/powerpc/platforms/ge_gpio.c
new file mode 100644
index 0000000..2a70336
--- /dev/null
+++ b/arch/powerpc/platforms/ge_gpio.c
@@ -0,0 +1,171 @@
+/*
+ * Driver for GE FPGA based GPIO
+ *
+ * Author: Martyn Welch <martyn.welch@ge.com>
+ *
+ * 2008 (c) GE Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/* TODO
+ *
+ * Configuration of output modes (totem-pole/open-drain)
+ * Interrupt configuration - interrupts are always generated the FPGA relies on
+ * the I/O interrupt controllers mask to stop them propergating
+ */
+
+#include <linux/kernel.h>
+#include <linux/compiler.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+
+#define GEF_GPIO_DIRECT 0x00
+#define GEF_GPIO_IN 0x04
+#define GEF_GPIO_OUT 0x08
+#define GEF_GPIO_TRIG 0x0C
+#define GEF_GPIO_POLAR_A 0x10
+#define GEF_GPIO_POLAR_B 0x14
+#define GEF_GPIO_INT_STAT 0x18
+#define GEF_GPIO_OVERRUN 0x1C
+#define GEF_GPIO_MODE 0x20
+
+static void _gef_gpio_set(void __iomem *reg, unsigned int offset, int value)
+{
+ unsigned int data;
+
+ data = ioread32be(reg);
+ /* value: 0=low; 1=high */
+ if (value & 0x1)
+ data = data | (0x1 << offset);
+ else
+ data = data & ~(0x1 << offset);
+
+ iowrite32be(data, reg);
+}
+
+
+static int gef_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
+{
+ unsigned int data;
+ struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
+
+ data = ioread32be(mmchip->regs + GEF_GPIO_DIRECT);
+ data = data | (0x1 << offset);
+ iowrite32be(data, mmchip->regs + GEF_GPIO_DIRECT);
+
+ return 0;
+}
+
+static int gef_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
+{
+ unsigned int data;
+ struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
+
+ /* Set direction before switching to input */
+ _gef_gpio_set(mmchip->regs + GEF_GPIO_OUT, offset, value);
+
+ data = ioread32be(mmchip->regs + GEF_GPIO_DIRECT);
+ data = data & ~(0x1 << offset);
+ iowrite32be(data, mmchip->regs + GEF_GPIO_DIRECT);
+
+ return 0;
+}
+
+static int gef_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ unsigned int data;
+ int state = 0;
+ struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
+
+ data = ioread32be(mmchip->regs + GEF_GPIO_IN);
+ state = (int)((data >> offset) & 0x1);
+
+ return state;
+}
+
+static void gef_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
+
+ _gef_gpio_set(mmchip->regs + GEF_GPIO_OUT, offset, value);
+}
+
+static int __init gef_gpio_init(void)
+{
+ struct device_node *np;
+ int retval;
+ struct of_mm_gpio_chip *gef_gpio_chip;
+
+ for_each_compatible_node(np, NULL, "gef,sbc610-gpio") {
+
+ pr_debug("%s: Initialising GEF GPIO\n", np->full_name);
+
+ /* Allocate chip structure */
+ gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
+ if (!gef_gpio_chip) {
+ pr_err("%s: Unable to allocate structure\n",
+ np->full_name);
+ continue;
+ }
+
+ /* Setup pointers to chip functions */
+ gef_gpio_chip->gc.of_gpio_n_cells = 2;
+ gef_gpio_chip->gc.ngpio = 19;
+ gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
+ gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
+ gef_gpio_chip->gc.get = gef_gpio_get;
+ gef_gpio_chip->gc.set = gef_gpio_set;
+
+ /* This function adds a memory mapped GPIO chip */
+ retval = of_mm_gpiochip_add(np, gef_gpio_chip);
+ if (retval) {
+ kfree(gef_gpio_chip);
+ pr_err("%s: Unable to add GPIO\n", np->full_name);
+ }
+ }
+
+ for_each_compatible_node(np, NULL, "gef,sbc310-gpio") {
+
+ pr_debug("%s: Initialising GEF GPIO\n", np->full_name);
+
+ /* Allocate chip structure */
+ gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
+ if (!gef_gpio_chip) {
+ pr_err("%s: Unable to allocate structure\n",
+ np->full_name);
+ continue;
+ }
+
+ /* Setup pointers to chip functions */
+ gef_gpio_chip->gc.of_gpio_n_cells = 2;
+ gef_gpio_chip->gc.ngpio = 6;
+ gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
+ gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
+ gef_gpio_chip->gc.get = gef_gpio_get;
+ gef_gpio_chip->gc.set = gef_gpio_set;
+
+ /* This function adds a memory mapped GPIO chip */
+ retval = of_mm_gpiochip_add(np, gef_gpio_chip);
+ if (retval) {
+ kfree(gef_gpio_chip);
+ pr_err("%s: Unable to add GPIO\n", np->full_name);
+ }
+ }
+
+ return 0;
+};
+arch_initcall(gef_gpio_init);
+
+MODULE_DESCRIPTION("GE I/O FPGA GPIO driver");
+MODULE_AUTHOR("Martyn Welch <martyn.welch@ge.com");
+MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/platforms/ge_pic.c b/arch/powerpc/platforms/ge_pic.c
new file mode 100644
index 0000000..a1ccef2
--- /dev/null
+++ b/arch/powerpc/platforms/ge_pic.c
@@ -0,0 +1,252 @@
+/*
+ * Interrupt handling for GE FPGA based PIC
+ *
+ * Author: Martyn Welch <martyn.welch@ge.com>
+ *
+ * 2008 (c) GE Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/irq.h>
+
+#include <platforms/ge_pic.h>
+
+#define DEBUG
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt...) do { printk(KERN_DEBUG "gef_pic: " fmt); } while (0)
+#else
+#define DBG(fmt...) do { } while (0)
+#endif
+
+#define GEF_PIC_NUM_IRQS 32
+
+/* Interrupt Controller Interface Registers */
+#define GEF_PIC_INTR_STATUS 0x0000
+
+#define GEF_PIC_INTR_MASK(cpu) (0x0010 + (0x4 * cpu))
+#define GEF_PIC_CPU0_INTR_MASK GEF_PIC_INTR_MASK(0)
+#define GEF_PIC_CPU1_INTR_MASK GEF_PIC_INTR_MASK(1)
+
+#define GEF_PIC_MCP_MASK(cpu) (0x0018 + (0x4 * cpu))
+#define GEF_PIC_CPU0_MCP_MASK GEF_PIC_MCP_MASK(0)
+#define GEF_PIC_CPU1_MCP_MASK GEF_PIC_MCP_MASK(1)
+
+
+static DEFINE_RAW_SPINLOCK(gef_pic_lock);
+
+static void __iomem *gef_pic_irq_reg_base;
+static struct irq_host *gef_pic_irq_host;
+static int gef_pic_cascade_irq;
+
+/*
+ * Interrupt Controller Handling
+ *
+ * The interrupt controller handles interrupts for most on board interrupts,
+ * apart from PCI interrupts. For example on SBC610:
+ *
+ * 17:31 RO Reserved
+ * 16 RO PCI Express Doorbell 3 Status
+ * 15 RO PCI Express Doorbell 2 Status
+ * 14 RO PCI Express Doorbell 1 Status
+ * 13 RO PCI Express Doorbell 0 Status
+ * 12 RO Real Time Clock Interrupt Status
+ * 11 RO Temperature Interrupt Status
+ * 10 RO Temperature Critical Interrupt Status
+ * 9 RO Ethernet PHY1 Interrupt Status
+ * 8 RO Ethernet PHY3 Interrupt Status
+ * 7 RO PEX8548 Interrupt Status
+ * 6 RO Reserved
+ * 5 RO Watchdog 0 Interrupt Status
+ * 4 RO Watchdog 1 Interrupt Status
+ * 3 RO AXIS Message FIFO A Interrupt Status
+ * 2 RO AXIS Message FIFO B Interrupt Status
+ * 1 RO AXIS Message FIFO C Interrupt Status
+ * 0 RO AXIS Message FIFO D Interrupt Status
+ *
+ * Interrupts can be forwarded to one of two output lines. Nothing
+ * clever is done, so if the masks are incorrectly set, a single input
+ * interrupt could generate interrupts on both output lines!
+ *
+ * The dual lines are there to allow the chained interrupts to be easily
+ * passed into two different cores. We currently do not use this functionality
+ * in this driver.
+ *
+ * Controller can also be configured to generate Machine checks (MCP), again on
+ * two lines, to be attached to two different cores. It is suggested that these
+ * should be masked out.
+ */
+
+void gef_pic_cascade(unsigned int irq, struct irq_desc *desc)
+{
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned int cascade_irq;
+
+ /*
+ * See if we actually have an interrupt, call generic handling code if
+ * we do.
+ */
+ cascade_irq = gef_pic_get_irq();
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+
+ chip->irq_eoi(&desc->irq_data);
+}
+
+static void gef_pic_mask(struct irq_data *d)
+{
+ unsigned long flags;
+ unsigned int hwirq = irqd_to_hwirq(d);
+ u32 mask;
+
+ raw_spin_lock_irqsave(&gef_pic_lock, flags);
+ mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
+ mask &= ~(1 << hwirq);
+ out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
+ raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
+}
+
+static void gef_pic_mask_ack(struct irq_data *d)
+{
+ /* Don't think we actually have to do anything to ack an interrupt,
+ * we just need to clear down the devices interrupt and it will go away
+ */
+ gef_pic_mask(d);
+}
+
+static void gef_pic_unmask(struct irq_data *d)
+{
+ unsigned long flags;
+ unsigned int hwirq = irqd_to_hwirq(d);
+ u32 mask;
+
+ raw_spin_lock_irqsave(&gef_pic_lock, flags);
+ mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
+ mask |= (1 << hwirq);
+ out_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0), mask);
+ raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
+}
+
+static struct irq_chip gef_pic_chip = {
+ .name = "gefp",
+ .irq_mask = gef_pic_mask,
+ .irq_mask_ack = gef_pic_mask_ack,
+ .irq_unmask = gef_pic_unmask,
+};
+
+
+/* When an interrupt is being configured, this call allows some flexibilty
+ * in deciding which irq_chip structure is used
+ */
+static int gef_pic_host_map(struct irq_host *h, unsigned int virq,
+ irq_hw_number_t hwirq)
+{
+ /* All interrupts are LEVEL sensitive */
+ irq_set_status_flags(virq, IRQ_LEVEL);
+ irq_set_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
+
+ return 0;
+}
+
+static int gef_pic_host_xlate(struct irq_host *h, struct device_node *ct,
+ const u32 *intspec, unsigned int intsize,
+ irq_hw_number_t *out_hwirq, unsigned int *out_flags)
+{
+
+ *out_hwirq = intspec[0];
+ if (intsize > 1)
+ *out_flags = intspec[1];
+ else
+ *out_flags = IRQ_TYPE_LEVEL_HIGH;
+
+ return 0;
+}
+
+static struct irq_host_ops gef_pic_host_ops = {
+ .map = gef_pic_host_map,
+ .xlate = gef_pic_host_xlate,
+};
+
+
+/*
+ * Initialisation of PIC, this should be called in BSP
+ */
+void __init gef_pic_init(struct device_node *np)
+{
+ unsigned long flags;
+
+ /* Map the devices registers into memory */
+ gef_pic_irq_reg_base = of_iomap(np, 0);
+
+ raw_spin_lock_irqsave(&gef_pic_lock, flags);
+
+ /* Initialise everything as masked. */
+ out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_INTR_MASK, 0);
+ out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_INTR_MASK, 0);
+
+ out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU0_MCP_MASK, 0);
+ out_be32(gef_pic_irq_reg_base + GEF_PIC_CPU1_MCP_MASK, 0);
+
+ raw_spin_unlock_irqrestore(&gef_pic_lock, flags);
+
+ /* Map controller */
+ gef_pic_cascade_irq = irq_of_parse_and_map(np, 0);
+ if (gef_pic_cascade_irq == NO_IRQ) {
+ printk(KERN_ERR "SBC610: failed to map cascade interrupt");
+ return;
+ }
+
+ /* Setup an irq_host structure */
+ gef_pic_irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
+ GEF_PIC_NUM_IRQS,
+ &gef_pic_host_ops, NO_IRQ);
+ if (gef_pic_irq_host == NULL)
+ return;
+
+ /* Chain with parent controller */
+ irq_set_chained_handler(gef_pic_cascade_irq, gef_pic_cascade);
+}
+
+/*
+ * This is called when we receive an interrupt with apparently comes from this
+ * chip - check, returning the highest interrupt generated or return NO_IRQ
+ */
+unsigned int gef_pic_get_irq(void)
+{
+ u32 cause, mask, active;
+ unsigned int virq = NO_IRQ;
+ int hwirq;
+
+ cause = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_STATUS);
+
+ mask = in_be32(gef_pic_irq_reg_base + GEF_PIC_INTR_MASK(0));
+
+ active = cause & mask;
+
+ if (active) {
+ for (hwirq = GEF_PIC_NUM_IRQS - 1; hwirq > -1; hwirq--) {
+ if (active & (0x1 << hwirq))
+ break;
+ }
+ virq = irq_linear_revmap(gef_pic_irq_host,
+ (irq_hw_number_t)hwirq);
+ }
+
+ return virq;
+}
+
diff --git a/arch/powerpc/platforms/ge_pic.h b/arch/powerpc/platforms/ge_pic.h
new file mode 100644
index 0000000..6149916
--- /dev/null
+++ b/arch/powerpc/platforms/ge_pic.h
@@ -0,0 +1,11 @@
+#ifndef __GEF_PIC_H__
+#define __GEF_PIC_H__
+
+#include <linux/init.h>
+
+void gef_pic_cascade(unsigned int, struct irq_desc *);
+unsigned int gef_pic_get_irq(void);
+void gef_pic_init(struct device_node *);
+
+#endif /* __GEF_PIC_H__ */
+
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 877b107..2955c3f 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -1039,7 +1039,7 @@ config LANTIQ_WDT
config GEF_WDT
tristate "GE Watchdog Timer"
- depends on GEF_SBC610 || GEF_SBC310 || GEF_PPC9A
+ depends on GE_FPGA
---help---
Watchdog timer found in a number of GE single board computers.
--
1.7.0.4
^ permalink raw reply related
* [PATCH 2/2] powerpc: Board support for GE IMP3A
From: Martyn Welch @ 2012-02-07 11:28 UTC (permalink / raw)
To: linuxppc-dev; +Cc: Martyn Welch, Wim Van Sebroeck, linux-kernel
In-Reply-To: <1328614121-17803-1-git-send-email-martyn.welch@ge.com>
Initial board support for the GE IMP3A, a 3U compactPCI card with a p2020
processor.
Signed-off-by: Martyn Welch <martyn.welch@ge.com>
---
arch/powerpc/boot/dts/ge_imp3a.dts | 254 ++++++++++++++++++++++++++++++
arch/powerpc/configs/ge_imp3a_defconfig | 256 ++++++++++++++++++++++++++++++
arch/powerpc/platforms/85xx/Kconfig | 12 ++
arch/powerpc/platforms/85xx/Makefile | 1 +
arch/powerpc/platforms/85xx/ge_imp3a.c | 258 +++++++++++++++++++++++++++++++
arch/powerpc/platforms/ge_gpio.c | 28 ++++
6 files changed, 809 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts/ge_imp3a.dts
create mode 100644 arch/powerpc/configs/ge_imp3a_defconfig
create mode 100644 arch/powerpc/platforms/85xx/ge_imp3a.c
diff --git a/arch/powerpc/boot/dts/ge_imp3a.dts b/arch/powerpc/boot/dts/ge_imp3a.dts
new file mode 100644
index 0000000..f30fadb
--- /dev/null
+++ b/arch/powerpc/boot/dts/ge_imp3a.dts
@@ -0,0 +1,254 @@
+/*
+ * GE IMP3A Device Tree Source
+ *
+ * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Based on: P2020 DS Device Tree Source
+ * Copyright 2009 Freescale Semiconductor Inc.
+ */
+
+/include/ "fsl/p2020si-pre.dtsi"
+
+/ {
+ model = "GE_IMP3A";
+ compatible = "ge,imp3a";
+
+ memory {
+ device_type = "memory";
+ };
+
+ lbc: localbus@fef05000 {
+ reg = <0 0xfef05000 0 0x1000>;
+
+ ranges = <0x0 0x0 0x0 0xff000000 0x01000000
+ 0x1 0x0 0x0 0xe0000000 0x08000000
+ 0x2 0x0 0x0 0xe8000000 0x08000000
+ 0x3 0x0 0x0 0xfc100000 0x00020000
+ 0x4 0x0 0x0 0xfc000000 0x00008000
+ 0x5 0x0 0x0 0xfc008000 0x00008000
+ 0x6 0x0 0x0 0xfee00000 0x00040000
+ 0x7 0x0 0x0 0xfee80000 0x00040000>;
+
+ /* nor@0,0 is a mirror of part of the memory in nor@1,0
+ nor@0,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
+ reg = <0x0 0x0 0x1000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition@0 {
+ label = "firmware";
+ reg = <0x0 0x1000000>;
+ read-only;
+ };
+ };
+ */
+
+ nor@1,0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ge,imp3a-paged-flash", "cfi-flash";
+ reg = <0x1 0x0 0x8000000>;
+ bank-width = <2>;
+ device-width = <1>;
+
+ partition@0 {
+ label = "user";
+ reg = <0x0 0x7800000>;
+ };
+
+ partition@7800000 {
+ label = "firmware";
+ reg = <0x7800000 0x800000>;
+ read-only;
+ };
+ };
+
+ nvram@3,0 {
+ device_type = "nvram";
+ compatible = "simtek,stk14ca8";
+ reg = <0x3 0x0 0x20000>;
+ };
+
+ fpga@4,0 {
+ compatible = "ge,imp3a-fpga-regs";
+ reg = <0x4 0x0 0x20>;
+ };
+
+ gef_pic: pic@4,20 {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "ge,imp3a-fpga-pic", "gef,fpga-pic-1.00";
+ reg = <0x4 0x20 0x20>;
+ interrupts = <6 7 0 0>;
+ };
+
+ gef_gpio: gpio@4,400 {
+ #gpio-cells = <2>;
+ compatible = "ge,imp3a-gpio";
+ reg = <0x4 0x400 0x24>;
+ gpio-controller;
+ };
+
+ wdt@4,800 {
+ compatible = "ge,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
+ "gef,fpga-wdt";
+ reg = <0x4 0x800 0x8>;
+ interrupts = <10 4>;
+ interrupt-parent = <&gef_pic>;
+ };
+
+ /* Second watchdog available, driver currently supports one.
+ wdt@4,808 {
+ compatible = "gef,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
+ "gef,fpga-wdt";
+ reg = <0x4 0x808 0x8>;
+ interrupts = <9 4>;
+ interrupt-parent = <&gef_pic>;
+ };
+ */
+
+ nand@6,0 {
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x6 0x0 0x40000>;
+ };
+
+ nand@7,0 {
+ compatible = "fsl,elbc-fcm-nand";
+ reg = <0x7 0x0 0x40000>;
+ };
+ };
+
+ soc: soc@fef00000 {
+ ranges = <0x0 0 0xfef00000 0x100000>;
+
+ i2c@3000 {
+ hwmon@48 {
+ compatible = "national,lm92";
+ reg = <0x48>;
+ };
+
+ hwmon@4c {
+ compatible = "adi,adt7461";
+ reg = <0x4c>;
+ };
+
+ rtc@51 {
+ compatible = "epson,rx8581";
+ reg = <0x51>;
+ };
+
+ eti@6b {
+ compatible = "dallas,ds1682";
+ reg = <0x6b>;
+ };
+ };
+
+ usb@22000 {
+ phy_type = "ulpi";
+ dr_mode = "host";
+ };
+
+ mdio@24520 {
+ phy0: ethernet-phy@0 {
+ interrupt-parent = <&gef_pic>;
+ interrupts = <0xc 0x4>;
+ reg = <0x1>;
+ };
+ phy1: ethernet-phy@1 {
+ interrupt-parent = <&gef_pic>;
+ interrupts = <0xb 0x4>;
+ reg = <0x2>;
+ };
+ tbi0: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@25520 {
+ tbi1: tbi-phy@11 {
+ reg = <0x11>;
+ device_type = "tbi-phy";
+ };
+ };
+
+ mdio@26520 {
+ status = "disabled";
+ };
+
+ enet0: ethernet@24000 {
+ tbi-handle = <&tbi0>;
+ phy-handle = <&phy0>;
+ phy-connection-type = "gmii";
+ };
+
+ enet1: ethernet@25000 {
+ tbi-handle = <&tbi1>;
+ phy-handle = <&phy1>;
+ phy-connection-type = "gmii";
+ };
+
+ enet2: ethernet@26000 {
+ status = "disabled";
+ };
+ };
+
+ pci0: pcie@fef08000 {
+ ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xfe020000 0x0 0x10000>;
+ reg = <0 0xfef08000 0 0x1000>;
+
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xc0000000
+ 0x2000000 0x0 0xc0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+ };
+
+ pci1: pcie@fef09000 {
+ reg = <0 0xfef09000 0 0x1000>;
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xfe010000 0x0 0x10000>;
+
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+
+ };
+
+ pci2: pcie@fef0a000 {
+ reg = <0 0xfef0a000 0 0x1000>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xfe000000 0x0 0x10000>;
+
+ pcie@0 {
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x10000>;
+ };
+ };
+};
+
+/include/ "fsl/p2020si-post.dtsi"
diff --git a/arch/powerpc/configs/ge_imp3a_defconfig b/arch/powerpc/configs/ge_imp3a_defconfig
new file mode 100644
index 0000000..ca4c5cb
--- /dev/null
+++ b/arch/powerpc/configs/ge_imp3a_defconfig
@@ -0,0 +1,256 @@
+CONFIG_PPC_85xx=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_PERF_EVENTS=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_GE_IMP3A=y
+CONFIG_QUICC_ENGINE=y
+CONFIG_QE_GPIO=y
+CONFIG_CPM2=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+CONFIG_PREEMPT=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_MISC=m
+CONFIG_MATH_EMULATION=y
+CONFIG_IRQ_ALL_CPUS=y
+CONFIG_FORCE_MAX_ZONEORDER=17
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_MSI=y
+CONFIG_PCCARD=y
+# CONFIG_PCMCIA_LOAD_CIS is not set
+CONFIG_YENTA=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=m
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=m
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_TUNNEL=m
+CONFIG_NET_PKTGEN=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSL_ELBC=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=131072
+CONFIG_MISC_DEVICES=y
+CONFIG_DS1682=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_SIL24=y
+# CONFIG_ATA_SFF is not set
+CONFIG_NETDEVICES=y
+CONFIG_BONDING=m
+CONFIG_DUMMY=m
+CONFIG_NETCONSOLE=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_TUN=m
+# CONFIG_NET_VENDOR_3COM is not set
+CONFIG_FS_ENET=y
+CONFIG_UCC_GETH=y
+CONFIG_GIANFAR=y
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_SLIP=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLIP_SMART=y
+CONFIG_SLIP_MODE_SLIP6=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_QE=m
+CONFIG_NVRAM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_CPM=m
+CONFIG_I2C_MPC=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_SENSORS_LM90=y
+CONFIG_SENSORS_LM92=y
+CONFIG_WATCHDOG=y
+CONFIG_GEF_WDT=y
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+CONFIG_HID_DRAGONRISE=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_TWINHAN=y
+CONFIG_HID_ORTEK=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_HID_GREENASIA=y
+CONFIG_HID_SMARTJOYPLUS=y
+CONFIG_HID_TOPSEED=y
+CONFIG_HID_THRUSTMASTER=y
+CONFIG_HID_ZEROPLUS=y
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
+CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
+CONFIG_USB_STORAGE=y
+CONFIG_EDAC=y
+CONFIG_EDAC_MM_EDAC=y
+CONFIG_EDAC_MPC85XX=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_INTF_PROC is not set
+CONFIG_RTC_DRV_RX8581=y
+CONFIG_DMADEVICES=y
+CONFIG_FSL_DMA=y
+# CONFIG_NET_DMA is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=850
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_NTFS_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V4=y
+CONFIG_CIFS=m
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_LIBCRC32C=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_TALITOS=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index d7946be..96ae241 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -171,6 +171,18 @@ config SBC8560
help
This option enables support for the Wind River SBC8560 board
+config GE_IMP3A
+ bool "GE Intelligent Platforms IMP3A"
+ select DEFAULT_UIMAGE
+ select SWIOTLB
+ select MMIO_NVRAM
+ select GENERIC_GPIO
+ select ARCH_REQUIRE_GPIOLIB
+ select GE_FPGA
+ help
+ This option enables support for the GE Intelligent Platforms IMP3A
+ board.
+
config P2041_RDB
bool "Freescale P2041 RDB"
select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 9cb2d43..2125d4c 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -27,3 +27,4 @@ obj-$(CONFIG_SBC8548) += sbc8548.o
obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
obj-$(CONFIG_KSI8560) += ksi8560.o
obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
+obj-$(CONFIG_GE_IMP3A) += ge_imp3a.o
diff --git a/arch/powerpc/platforms/85xx/ge_imp3a.c b/arch/powerpc/platforms/85xx/ge_imp3a.c
new file mode 100644
index 0000000..cae3e15
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/ge_imp3a.c
@@ -0,0 +1,258 @@
+/*
+ * GE IMP3A Board Setup
+ *
+ * Author Martyn Welch <martyn.welch@ge.com>
+ *
+ * Copyright 2010 GE Intelligent Platforms Embedded Systems, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * Based on: mpc85xx_ds.c (MPC85xx DS Board Setup)
+ * Copyright 2007 Freescale Semiconductor Inc.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/seq_file.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+#include <linux/memblock.h>
+
+#include <asm/system.h>
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+#include <asm/swiotlb.h>
+#include <asm/nvram.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+
+#include "mpc85xx.h"
+#include <platforms/ge_pic.h>
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
+#else
+#define DBG(fmt, args...)
+#endif
+
+void __iomem *imp3a_regs;
+
+void __init ge_imp3a_pic_init(void)
+{
+ struct mpic *mpic;
+ struct device_node *np;
+ struct device_node *cascade_node = NULL;
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
+ mpic = mpic_alloc(NULL, 0,
+ MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+ MPIC_SINGLE_DEST_CPU,
+ 0, 256, " OpenPIC ");
+ } else {
+ mpic = mpic_alloc(NULL, 0,
+ MPIC_WANTS_RESET |
+ MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
+ MPIC_SINGLE_DEST_CPU,
+ 0, 256, " OpenPIC ");
+ }
+
+ BUG_ON(mpic == NULL);
+ mpic_init(mpic);
+ /*
+ * There is a simple interrupt handler in the main FPGA, this needs
+ * to be cascaded into the MPIC
+ */
+ for_each_node_by_type(np, "interrupt-controller")
+ if (of_device_is_compatible(np, "gef,fpga-pic-1.00")) {
+ cascade_node = np;
+ break;
+ }
+
+ if (cascade_node == NULL) {
+ printk(KERN_WARNING "IMP3A: No FPGA PIC\n");
+ return;
+ }
+
+ gef_pic_init(cascade_node);
+ of_node_put(cascade_node);
+}
+
+#ifdef CONFIG_PCI
+static int primary_phb_addr;
+#endif /* CONFIG_PCI */
+
+/*
+ * Setup the architecture
+ */
+#ifdef CONFIG_SMP
+extern void __init mpc85xx_smp_init(void);
+#endif
+static void __init ge_imp3a_setup_arch(void)
+{
+ struct device_node *regs;
+#ifdef CONFIG_PCI
+ struct device_node *np;
+ struct pci_controller *hose;
+#endif
+ dma_addr_t max = 0xffffffff;
+
+ if (ppc_md.progress)
+ ppc_md.progress("ge_imp3a_setup_arch()", 0);
+
+#ifdef CONFIG_PCI
+ for_each_node_by_type(np, "pci") {
+ if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
+ of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
+ of_device_is_compatible(np, "fsl,p2020-pcie")) {
+ struct resource rsrc;
+ of_address_to_resource(np, 0, &rsrc);
+ if ((rsrc.start & 0xfffff) == primary_phb_addr)
+ fsl_add_bridge(np, 1);
+ else
+ fsl_add_bridge(np, 0);
+
+ hose = pci_find_hose_for_OF_device(np);
+ max = min(max, hose->dma_window_base_cur +
+ hose->dma_window_size);
+ }
+ }
+#endif
+
+#ifdef CONFIG_SMP
+ mpc85xx_smp_init();
+#endif
+
+#ifdef CONFIG_SWIOTLB
+ if (memblock_end_of_DRAM() > max) {
+ ppc_swiotlb_enable = 1;
+ set_pci_dma_ops(&swiotlb_dma_ops);
+ ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+ }
+#endif
+
+ /* Remap basic board registers */
+ regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs");
+ if (regs) {
+ imp3a_regs = of_iomap(regs, 0);
+ if (imp3a_regs == NULL)
+ printk(KERN_WARNING "Unable to map board registers\n");
+ of_node_put(regs);
+ }
+
+#if defined(CONFIG_MMIO_NVRAM)
+ mmio_nvram_init();
+#endif
+
+ printk("GE Intelligent Platforms IMP3A 3U cPCI SBC\n");
+}
+
+/* Return the PCB revision */
+static unsigned int ge_imp3a_get_pcb_rev(void)
+{
+ unsigned int reg;
+
+ reg = ioread16(imp3a_regs);
+ return (reg >> 8) & 0xff;
+}
+
+/* Return the board (software) revision */
+static unsigned int ge_imp3a_get_board_rev(void)
+{
+ unsigned int reg;
+
+ reg = ioread16(imp3a_regs + 0x2);
+ return reg & 0xff;
+}
+
+/* Return the FPGA revision */
+static unsigned int ge_imp3a_get_fpga_rev(void)
+{
+ unsigned int reg;
+
+ reg = ioread16(imp3a_regs + 0x2);
+ return (reg >> 8) & 0xff;
+}
+
+/* Return compactPCI Geographical Address */
+static unsigned int ge_imp3a_get_cpci_geo_addr(void)
+{
+ unsigned int reg;
+
+ reg = ioread16(imp3a_regs + 0x6);
+ return ((reg & 0x0f00) >> 8);
+}
+
+/* Return compactPCI System Controller Status */
+static unsigned int ge_imp3a_get_cpci_is_syscon(void)
+{
+ unsigned int reg;
+
+ reg = ioread16(imp3a_regs + 0x6);
+ return reg & (1 << 12);
+}
+
+static void ge_imp3a_show_cpuinfo(struct seq_file *m)
+{
+ seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
+
+ seq_printf(m, "Revision\t: %u%c\n", ge_imp3a_get_pcb_rev(),
+ ('A' + ge_imp3a_get_board_rev() - 1));
+
+ seq_printf(m, "FPGA Revision\t: %u\n", ge_imp3a_get_fpga_rev());
+
+ seq_printf(m, "cPCI geo. addr\t: %u\n", ge_imp3a_get_cpci_geo_addr());
+
+ seq_printf(m, "cPCI syscon\t: %s\n",
+ ge_imp3a_get_cpci_is_syscon() ? "yes" : "no");
+}
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init ge_imp3a_probe(void)
+{
+ unsigned long root = of_get_flat_dt_root();
+
+ if (of_flat_dt_is_compatible(root, "ge,IMP3A")) {
+#ifdef CONFIG_PCI
+ primary_phb_addr = 0x9000;
+#endif
+ return 1;
+ }
+
+ return 0;
+}
+
+machine_device_initcall(ge_imp3a, mpc85xx_common_publish_devices);
+
+machine_arch_initcall(ge_imp3a, swiotlb_setup_bus_notifier);
+
+define_machine(ge_imp3a) {
+ .name = "GE_IMP3A",
+ .probe = ge_imp3a_probe,
+ .setup_arch = ge_imp3a_setup_arch,
+ .init_IRQ = ge_imp3a_pic_init,
+ .show_cpuinfo = ge_imp3a_show_cpuinfo,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+#endif
+ .get_irq = mpic_get_irq,
+ .restart = fsl_rstcr_restart,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/ge_gpio.c b/arch/powerpc/platforms/ge_gpio.c
index 2a70336..a017def 100644
--- a/arch/powerpc/platforms/ge_gpio.c
+++ b/arch/powerpc/platforms/ge_gpio.c
@@ -162,6 +162,34 @@ static int __init gef_gpio_init(void)
}
}
+ for_each_compatible_node(np, NULL, "ge,imp3a-gpio") {
+
+ pr_debug("%s: Initialising GE GPIO\n", np->full_name);
+
+ /* Allocate chip structure */
+ gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
+ if (!gef_gpio_chip) {
+ pr_err("%s: Unable to allocate structure\n",
+ np->full_name);
+ continue;
+ }
+
+ /* Setup pointers to chip functions */
+ gef_gpio_chip->gc.of_gpio_n_cells = 2;
+ gef_gpio_chip->gc.ngpio = 16;
+ gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
+ gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
+ gef_gpio_chip->gc.get = gef_gpio_get;
+ gef_gpio_chip->gc.set = gef_gpio_set;
+
+ /* This function adds a memory mapped GPIO chip */
+ retval = of_mm_gpiochip_add(np, gef_gpio_chip);
+ if (retval) {
+ kfree(gef_gpio_chip);
+ pr_err("%s: Unable to add GPIO\n", np->full_name);
+ }
+ }
+
return 0;
};
arch_initcall(gef_gpio_init);
--
1.7.0.4
^ permalink raw reply related
* Re: [PATCH v3 00/25] irq_domain generalization and refinement
From: Mark Brown @ 2012-02-07 15:26 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Stephen Rothwell, Tony Lindgren, devicetree-discuss, linux-kernel,
Rob Herring, Milton Miller, Thomas Gleixner, linuxppc-dev,
linux-arm-kernel
In-Reply-To: <20120205161348.GZ889@n2100.arm.linux.org.uk>
On Sun, Feb 05, 2012 at 04:13:48PM +0000, Russell King - ARM Linux wrote:
> It's not quite correct, because OMAP4 has issues in this area as well
> (which does select IRQ_DOMAIN but can be without OF.) The result is
> an oops from irq_domain_add() because domain->ops is NULL.
> The right solution is three fold:
> 1. Wrap the bits of code in CONFIG_IRQ_DOMAIN
> 2. Get rid of the #ifdef CONFIG_OF there, so the 'ops' member can be
> initialized.
> 3. Fix the OMAP vp code not to oops when voltdm->pmic is NULL
> which I have in my combined patch for fixing OMAP so far.
It'd also help if we supported null ops, I sent patches for that a few
times over the 3.3 cycle since I was running into it on my systems but
apparently to /dev/null and further changes in this area have made the
patches not apply any more.
^ permalink raw reply
* Re: [PATCH] powerpc/fsl: add PAMUBYPENR register definition to fsl_guts.h
From: Kumar Gala @ 2012-02-07 18:21 UTC (permalink / raw)
To: Timur Tabi; +Cc: linuxppc-dev
In-Reply-To: <1328555872-9616-1-git-send-email-timur@freescale.com>
On Mon, 6 Feb 2012, Timur Tabi wrote:
> Add a defintion of register PAMUBYPENR (offset 0x604) to the global
> utilities structure.
>
> PAMUBYPENR is the PAMU bypass enable register. It contains control
> bits for enabling bypass mode on each PAMU.
>
> Signed-off-by: Timur Tabi <timur@freescale.com>
> ---
> arch/powerpc/include/asm/fsl_guts.h | 4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
>
What code will use this? Once such code exists, have this patch in that
patch series.
- k
^ permalink raw reply
* Re: [PATCH v3 24/25] irq_domain: remove "hint" when allocating irq numbers
From: Nicolas Ferre @ 2012-02-07 18:07 UTC (permalink / raw)
To: Grant Likely
Cc: Stephen Rothwell, devicetree-discuss, linux-kernel, Rob Herring,
Milton Miller, Thomas Gleixner, linuxppc-dev, linux-arm-kernel
In-Reply-To: <1327700179-17454-25-git-send-email-grant.likely@secretlab.ca>
On 01/27/2012 10:36 PM, Grant Likely :
> The 'hint' used to try and line up irq numbers with hw irq numbers is
> rather a hack and not very useful. Now that /proc/interrupts also outputs
> the hwirq number, it is even less useful to keep around the 'hint' heuristic.
>
> This patch removes it.
Grant,
While trying your patch series in conjunction with Rob one, I do not
find this patch in your irqdomain/next branch (and a couple of others).
Can you tell me if this v3 series is available as a git tree?
Thanks, best regards,
--
Nicolas Ferre
^ permalink raw reply
* Re: [PATCH] powerpc/fsl: add PAMUBYPENR register definition to fsl_guts.h
From: Timur Tabi @ 2012-02-07 19:25 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
In-Reply-To: <Pine.LNX.4.64.1202071221150.22169@gate.crashing.org>
Kumar Gala wrote:
> What code will use this? Once such code exists, have this patch in that
> patch series.
Isn't this patch harmless? I'm not adding any code, and there already are
plenty of fields defined in that struct that aren't used anywhere.
The register is for the PAMU driver, which is nowhere near ready for
upstream anyway. I was hoping to get the this patch in the pipeline ahead
of schedule.
So if you don't mind, I'd like you to consider this patch as-is.
--
Timur Tabi
Linux kernel developer at Freescale
^ permalink raw reply
* Re: MPC5200B FEC TX packets getting stuck
From: Joey Nelson @ 2012-02-08 2:47 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <CAL_WD7hkuhi4D2CPuoLyG2-7w8JmSQDnxiYbqKxzGNep5ONsrg@mail.gmail.com>
I've revisited my testing, and found I was wrong about the packets
getting stuck in the FEC queue. The packets are getting stuck in the
bestcomm.
I generate a timestamp for each skb's ip_hdr->id at the beginning of
mpc52xx_fec_start_xmit, and for each skb retrieved from the bestcomm.
Typically the packets make it through bestcomm in under 200us. But
sometimes a single packet will sit in bestcomm until the next packet
added. In the case of a delayed ACK this can be around 400ms.
When I look at the state of the registers when this condition is
detected (before adding the next bd):
tx_dmatsk->flags = 1
tcr[1] = 0x20c1
Both of these values seem to indicate the the TX task is disabled.
I'm pretty sure that nothing in the kernel is disabling the task, so
it must be an automatic behavior. I notice that
bcom_submit_next_buffer() checks the task->flags and if the LSB is set
it enables the task. So I'm guessing that is what gets things moving
again when the freeze happens.
My best guess is this is a race condition between the driver and the
dma controller. Is there any risk to just calling bcom_enable(tsk).
Maybe after a short sleep.
Joey Nelson
^ permalink raw reply
* Question about fsl_pq_mdio_probe and dts file for p1010rdb...
From: Bob Cochran @ 2012-02-08 2:13 UTC (permalink / raw)
To: linuxppc-dev
In-Reply-To: <1328555872-9616-1-git-send-email-timur@freescale.com>
Hello,
Using the mainline kernel & p1010rdb.dts, fsl_pq_mdio_probe returns busy
on my P1010RDB when first probing the MDIO during kernel boot. On the
console, the error is reported as:
"fsl-pq_mdio: probe of ffe24000.mdio failed with error -16"
I have determined that the failure occurs in the
for_each_child_of_node() loop shown below, which is part of the
fsl_pq_mdio_probe routine. It turns out that tbi->type is always <NULL>
although tbi->name will be "tbi-phy" when scanning the last child node (
I have also attached the relevant portion of the p1010rdb.dtsi file
below). Since tbi-type is never "tbi-phy", the "if (tbi)" statement is
always false, and err is subsequently set to EBUSY below.
Can someone please tell me whether this is an issue with the dts file,
the of library, or the probe function? Any direction on the right way
to patch this would be appreciated.
// from fsl_pq_mdio.c:
for_each_child_of_node(np, tbi) {
if (!strncmp(tbi->type, "tbi-phy", 8))
break;
}
if (tbi) {
const u32 *prop = of_get_property(tbi, "reg", NULL);
if (prop)
tbiaddr = *prop;
}
if (tbiaddr == -1) {
err = -EBUSY;
goto err_free_irqs;
} else {
out_be32(tbipa, tbiaddr);
}
// from p1010rdb.dtsi:
mdio@24000 {
phy0: ethernet-phy@0 {
interrupts = <3 1 0 0>;
reg = <0x1>;
};
phy1: ethernet-phy@1 {
interrupts = <2 1 0 0>;
reg = <0x0>;
};
phy2: ethernet-phy@2 {
interrupts = <2 1 0 0>;
reg = <0x2>;
};
tbi-phy@3 {
device-type = "tbi-phy";
reg = <0x3>;
};
};
^ permalink raw reply
* Re: [PATCH 00/14] Backport 8xx TLB to 2.4
From: Joakim Tjernlund @ 2012-02-08 8:44 UTC (permalink / raw)
To: Willy Tarreau; +Cc: Scott Wood, linuxppc-dev, Dan Malek
In-Reply-To: <20111211173346.GC9019@1wt.eu>
Willy Tarreau <w@1wt.eu> wrote on 2011/12/11 18:33:46:
>
> Hi Joakim,
>
> On Sun, Dec 11, 2011 at 06:19:54PM +0100, Joakim Tjernlund wrote:
> > > To: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
> > > From: Willy Tarreau <w@1wt.eu>
> > >
> > > Hi Joakim, On Mon, Oct 10, 2011 at 01:30:06PM +0200, Joakim Tjernlund wrote: > This is a
> > > backport from 2.6 which I did to overcome 8xx CPU > bugs. 8xx does not update the DAR register
> > > when taking a TLB > error caused by dcbX and icbi insns which makes it very > tricky to use these
> > > insns. Also the dcbst wrongly sets the > the store bit when faulting into DTLB error. > A few
> > > more bugs very found during development. > > I know 2.4 is in strict maintenance mode and 8xx is
> > > obsolete > but as it is still in use I wanted 8xx to age with grace. Thank you. I must admit I
> > > was hoping those patches would come in for a last release before the end of the year :-) Unless
> > > there is any objection from anyone, I'll merge them when kernel.org is back online. Cheers,
> > > Willy
> >
> > Did this go anywhere?
>
> Not yet, I just need to find some time to release another 2.4 with these
> patches.
Ping? There should be a tree somewhere by now :)
Jocke
^ permalink raw reply
* [PATCH 1/2] powerpc/85xx: Change style of partition nodes in dts for MPC8572DS
From: Jia Hongtao @ 2012-02-08 9:27 UTC (permalink / raw)
To: linuxppc-dev; +Cc: b38951
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/boot/dts/mpc8572ds.dtsi | 44 ++++++++++++++++++++--------------
1 files changed, 26 insertions(+), 18 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dtsi b/arch/powerpc/boot/dts/mpc8572ds.dtsi
index c3d4fac..e10fa61 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8572ds.dtsi
@@ -41,37 +41,41 @@
bank-width = <2>;
device-width = <1>;
- ramdisk@0 {
+ partition@0 {
reg = <0x0 0x03000000>;
- read-only;
+ label = "ramdisk-nor";
};
- diagnostic@3000000 {
+ partition@3000000 {
reg = <0x03000000 0x00e00000>;
+ label = "diagnostic-nor";
read-only;
};
- dink@3e00000 {
+ partition@3e00000 {
reg = <0x03e00000 0x00200000>;
+ label = "dink-nor";
read-only;
};
- kernel@4000000 {
+ partition@4000000 {
reg = <0x04000000 0x00400000>;
- read-only;
+ label = "kernel-nor";
};
- jffs2@4400000 {
+ partition@4400000 {
reg = <0x04400000 0x03b00000>;
+ label = "fs-nor";
};
- dtb@7f00000 {
+ partition@7f00000 {
reg = <0x07f00000 0x00080000>;
- read-only;
+ label = "dtb-nor";
};
- u-boot@7f80000 {
+ partition@7f80000 {
reg = <0x07f80000 0x00080000>;
+ label = "u-boot-nor";
read-only;
};
};
@@ -83,31 +87,35 @@
"fsl,elbc-fcm-nand";
reg = <0x2 0x0 0x40000>;
- u-boot@0 {
+ partition@0 {
reg = <0x0 0x02000000>;
+ label = "u-boot-nand";
read-only;
};
- jffs2@2000000 {
+ partition@2000000 {
reg = <0x02000000 0x10000000>;
+ label = "fs-nand";
};
- ramdisk@12000000 {
+ partition@12000000 {
reg = <0x12000000 0x08000000>;
- read-only;
+ label = "ramdisk-nand";
};
- kernel@1a000000 {
+ partition@1a000000 {
reg = <0x1a000000 0x04000000>;
+ label = "kernel-nand";
};
- dtb@1e000000 {
+ partition@1e000000 {
reg = <0x1e000000 0x01000000>;
- read-only;
+ label = "dtb-nand";
};
- empty@1f000000 {
+ partition@1f000000 {
reg = <0x1f000000 0x21000000>;
+ label = "empty-nand";
};
};
--
1.7.5.1
^ permalink raw reply related
* [PATCH 2/2] powerpc/85xx: update SEC node in dts for MPC8572DS
From: Jia Hongtao @ 2012-02-08 9:27 UTC (permalink / raw)
To: linuxppc-dev; +Cc: b38951
In-Reply-To: <1328693276-12057-1-git-send-email-B38951@freescale.com>
Add sec3.1 support
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Zhao Chenhui <b35336@freescale.com>
Signed-off-by: Jia Hongtao <B38951@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
---
arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
index d44e25a..cdda34f 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8572si-post.dtsi
@@ -184,7 +184,7 @@
/include/ "pq3-etsec1-1.dtsi"
/include/ "pq3-etsec1-2.dtsi"
/include/ "pq3-etsec1-3.dtsi"
-/include/ "pq3-sec3.0-0.dtsi"
+/include/ "pq3-sec3.1-0.dtsi"
/include/ "pq3-mpic.dtsi"
/include/ "pq3-mpic-timer-B.dtsi"
--
1.7.5.1
^ permalink raw reply related
* [PATCH 2/2 v2] powerpc: Abstract common define of signal multiplex control for qe
From: Zhicheng Fan @ 2012-02-08 9:52 UTC (permalink / raw)
To: galak, linuxppc-dev; +Cc: Zhicheng Fan
From: Zhicheng Fan <b32736@freeescale.com>
The mpc85xx_rdb and mpc85xx_mds have commom define of signal multiplex for qe ,so
they need to go in common header, the patch abstract them to fsl_guts.h
Signed-off-by: Zhicheng Fan <b32736@freeescale.com>
---
arch/powerpc/include/asm/fsl_guts.h | 19 +++++++++++++++++++
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 7 ++-----
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
index bebd124..efacfe3 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -114,6 +114,25 @@ struct ccsr_guts_86xx {
__be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
} __attribute__ ((packed));
+#ifdef CONFIG_PPC_85xx
+
+/* Alternate function signal multiplex control */
+#define MPC85xx_PMUXCR_OFFSET 0x60
+#define MPC85xx_PMUXCR_QE0 0x00008000
+#define MPC85xx_PMUXCR_QE2 0x00002000
+#define MPC85xx_PMUXCR_QE3 0x00001000
+#define MPC85xx_PMUXCR_QE4 0x00000800
+#define MPC85xx_PMUXCR_QE5 0x00000400
+#define MPC85xx_PMUXCR_QE6 0x00000200
+#define MPC85xx_PMUXCR_QE7 0x00000100
+#define MPC85xx_PMUXCR_QE8 0x00000080
+#define MPC85xx_PMUXCR_QE9 0x00000040
+#define MPC85xx_PMUXCR_QE10 0x00000020
+#define MPC85xx_PMUXCR_QE11 0x00000010
+#define MPC85xx_PMUXCR_QE12 0x00000008
+
+#endif
+
#ifdef CONFIG_PPC_86xx
#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 1d15a0c..1bd339a 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -51,6 +51,7 @@
#include <asm/qe_ic.h>
#include <asm/mpic.h>
#include <asm/swiotlb.h>
+#include <asm/fsl_guts.h>
#include "smp.h"
#include "mpc85xx.h"
@@ -268,11 +269,7 @@ static void __init mpc85xx_mds_qe_init(void)
mpc85xx_mds_reset_ucc_phys();
if (machine_is(p1021_mds)) {
-#define MPC85xx_PMUXCR_OFFSET 0x60
-#define MPC85xx_PMUXCR_QE0 0x00008000
-#define MPC85xx_PMUXCR_QE3 0x00001000
-#define MPC85xx_PMUXCR_QE9 0x00000040
-#define MPC85xx_PMUXCR_QE12 0x00000008
+
static __be32 __iomem *pmuxcr;
np = of_find_node_by_name(NULL, "global-utilities");
--
1.7.0.4
^ permalink raw reply related
* [PATCH 1/2 v2] P1025RDB: Add Quicc Engine support
From: Zhicheng Fan @ 2012-02-08 9:52 UTC (permalink / raw)
To: galak, linuxppc-dev; +Cc: Zhicheng Fan
In-Reply-To: <1328694779-24024-1-git-send-email-B32736@freescale.com>
From: Zhicheng Fan <b32736@freeescale.com>
Signed-off-by: Zhicheng Fan <b32736@freeescale.com>
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 80 ++++++++++++++++++++++++++++-
1 files changed, 79 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 1950076..4c27b3b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -26,6 +26,9 @@
#include <asm/prom.h>
#include <asm/udbg.h>
#include <asm/mpic.h>
+#include <asm/qe.h>
+#include <asm/qe_ic.h>
+#include <asm/fsl_guts.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
@@ -47,6 +50,10 @@ void __init mpc85xx_rdb_pic_init(void)
struct mpic *mpic;
unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_QUICC_ENGINE
+ struct device_node *np;
+#endif
+
if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) {
mpic = mpic_alloc(NULL, 0,
MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
@@ -62,6 +69,18 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+ if (np) {
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
+ qe_ic_cascade_high_mpic);
+ of_node_put(np);
+
+ } else
+ pr_err("Could not find qe-ic node\n");
+#endif
+
}
/*
@@ -69,7 +88,7 @@ void __init mpc85xx_rdb_pic_init(void)
*/
static void __init mpc85xx_rdb_setup_arch(void)
{
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
struct device_node *np;
#endif
@@ -85,6 +104,65 @@ static void __init mpc85xx_rdb_setup_arch(void)
#endif
mpc85xx_smp_init();
+
+#ifdef CONFIG_QUICC_ENGINE
+ np = of_find_compatible_node(NULL, NULL, "fsl,qe");
+ if (!np) {
+ pr_err("Could not find Quicc Engine node\n");
+ goto qe_fail;
+ }
+
+ qe_reset();
+ of_node_put(np);
+
+ np = of_find_node_by_name(NULL, "par_io");
+ if (np) {
+ struct device_node *ucc;
+
+ par_io_init(np);
+ of_node_put(np);
+
+ for_each_node_by_name(ucc, "ucc")
+ par_io_of_config(ucc);
+
+ }
+ if (machine_is(p1025_rdb)) {
+
+ __be32 __iomem *pmuxcr;
+
+ np = of_find_node_by_name(NULL, "global-utilities");
+
+ if (np) {
+ pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET;
+
+ if (!pmuxcr)
+ pr_err(KERN_EMERG "Error: Alternate function"
+ " signal multiplex control register not"
+ " mapped!\n");
+ else {
+#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
+ /* P1025 has pins muxed for QE and other functions. To
+ * enable QE UEC mode, we need to set bit QE0 for UCC1
+ * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
+ * and QE12 for QE MII management singals in PMUXCR
+ * register.
+ */
+ setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 |
+ MPC85xx_PMUXCR_QE3 |
+ MPC85xx_PMUXCR_QE9 |
+ MPC85xx_PMUXCR_QE12);
+#endif
+ }
+
+ iounmap(pmuxcr);
+ of_node_put(np);
+ }
+
+ }
+
+qe_fail:
+#endif /* CONFIG_QUICC_ENGINE */
+
printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
}
--
1.7.0.4
^ permalink raw reply related
* Re: [PATCH 00/14] Backport 8xx TLB to 2.4
From: Willy Tarreau @ 2012-02-08 9:44 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev, Dan Malek
In-Reply-To: <OF173F1835.8171C985-ONC125799E.002FE8C7-C125799E.0030008A@transmode.se>
Hi Joakim,
On Wed, Feb 08, 2012 at 09:44:18AM +0100, Joakim Tjernlund wrote:
> Willy Tarreau <w@1wt.eu> wrote on 2011/12/11 18:33:46:
> >
> > Hi Joakim,
> >
> > On Sun, Dec 11, 2011 at 06:19:54PM +0100, Joakim Tjernlund wrote:
> > > > To: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
> > > > From: Willy Tarreau <w@1wt.eu>
> > > >
> > > > Hi Joakim, On Mon, Oct 10, 2011 at 01:30:06PM +0200, Joakim Tjernlund wrote: > This is a
> > > > backport from 2.6 which I did to overcome 8xx CPU > bugs. 8xx does not update the DAR register
> > > > when taking a TLB > error caused by dcbX and icbi insns which makes it very > tricky to use these
> > > > insns. Also the dcbst wrongly sets the > the store bit when faulting into DTLB error. > A few
> > > > more bugs very found during development. > > I know 2.4 is in strict maintenance mode and 8xx is
> > > > obsolete > but as it is still in use I wanted 8xx to age with grace. Thank you. I must admit I
> > > > was hoping those patches would come in for a last release before the end of the year :-) Unless
> > > > there is any objection from anyone, I'll merge them when kernel.org is back online. Cheers,
> > > > Willy
> > >
> > > Did this go anywhere?
> >
> > Not yet, I just need to find some time to release another 2.4 with these
> > patches.
>
> Ping? There should be a tree somewhere by now :)
I'm planning on doing 2.4.37.12 once I'm finished with 2.6.27.60. However I'll
have to find another place to host it, as the 2.4 tree was never completely
recovered from master.kernel.org after the break-in, and admins there have
many more important things to do than to spend their time restoring the 2.4
files. Probably that I'll put that into my account.
BTW, since you're asking, you seem to still be using 2.4. Do you think it's
worth pursuing maintenance over 2.4.37.12 and if so for how long ? I'm asking
because until the break-in, I felt like almost nobody was using it anymore,
but since the break-in, I received a number of mails asking where to download
it. So now I assume that there are still users, but they're too much silent.
Regards,
Willy
^ permalink raw reply
* Re: [PATCH 00/14] Backport 8xx TLB to 2.4
From: Joakim Tjernlund @ 2012-02-08 11:39 UTC (permalink / raw)
To: Willy Tarreau; +Cc: Scott Wood, linuxppc-dev, Dan Malek
In-Reply-To: <20120208094426.GC1379@1wt.eu>
Willy Tarreau <w@1wt.eu> wrote on 2012/02/08 10:44:26:
>
> Hi Joakim,
>
> On Wed, Feb 08, 2012 at 09:44:18AM +0100, Joakim Tjernlund wrote:
> > Willy Tarreau <w@1wt.eu> wrote on 2011/12/11 18:33:46:
> > >
> > > Hi Joakim,
> > >
> > > On Sun, Dec 11, 2011 at 06:19:54PM +0100, Joakim Tjernlund wrote:
> > > > > To: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
> > > > > From: Willy Tarreau <w@1wt.eu>
> > > > >
> > > > > Hi Joakim, On Mon, Oct 10, 2011 at 01:30:06PM +0200, Joakim Tjernlund wrote: > This is a
> > > > > backport from 2.6 which I did to overcome 8xx CPU > bugs. 8xx does not update the DAR register
> > > > > when taking a TLB > error caused by dcbX and icbi insns which makes it very > tricky to use these
> > > > > insns. Also the dcbst wrongly sets the > the store bit when faulting into DTLB error. > A few
> > > > > more bugs very found during development. > > I know 2.4 is in strict maintenance mode and 8xx is
> > > > > obsolete > but as it is still in use I wanted 8xx to age with grace. Thank you. I must admit I
> > > > > was hoping those patches would come in for a last release before the end of the year :-) Unless
> > > > > there is any objection from anyone, I'll merge them when kernel.org is back online. Cheers,
> > > > > Willy
> > > >
> > > > Did this go anywhere?
> > >
> > > Not yet, I just need to find some time to release another 2.4 with these
> > > patches.
> >
> > Ping? There should be a tree somewhere by now :)
>
> I'm planning on doing 2.4.37.12 once I'm finished with 2.6.27.60. However I'll
> have to find another place to host it, as the 2.4 tree was never completely
> recovered from master.kernel.org after the break-in, and admins there have
> many more important things to do than to spend their time restoring the 2.4
> files. Probably that I'll put that into my account.
I see.
>
> BTW, since you're asking, you seem to still be using 2.4. Do you think it's
> worth pursuing maintenance over 2.4.37.12 and if so for how long ? I'm asking
> because until the break-in, I felt like almost nobody was using it anymore,
> but since the break-in, I received a number of mails asking where to download
> it. So now I assume that there are still users, but they're too much silent.
yes, they are silent I guess. I figure, after 2.4.37.12, a public git tree
on kernel org which still receives fixes would be enough.
Jocke
^ permalink raw reply
* Re: [PATCH 00/14] Backport 8xx TLB to 2.4
From: Willy Tarreau @ 2012-02-08 12:26 UTC (permalink / raw)
To: Joakim Tjernlund; +Cc: Scott Wood, linuxppc-dev, Dan Malek
In-Reply-To: <OFE7D02EF5.C8AA7552-ONC125799E.0037BB62-C125799E.0040126D@transmode.se>
On Wed, Feb 08, 2012 at 12:39:50PM +0100, Joakim Tjernlund wrote:
> > BTW, since you're asking, you seem to still be using 2.4. Do you think it's
> > worth pursuing maintenance over 2.4.37.12 and if so for how long ? I'm asking
> > because until the break-in, I felt like almost nobody was using it anymore,
> > but since the break-in, I received a number of mails asking where to download
> > it. So now I assume that there are still users, but they're too much silent.
>
> yes, they are silent I guess. I figure, after 2.4.37.12, a public git tree
> on kernel org which still receives fixes would be enough.
That's probably a good idea indeed. It avoids the need for a release for a
single patch and still allows people to pick patches when they intend to
build something.
Regards,
Willy
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