* Re: [PATCH v6 0/5] PCI: Unify ECAM constants in native PCI Express drivers
From: Bjorn Helgaas @ 2020-12-09 14:57 UTC (permalink / raw)
To: Michael Walle
Cc: kw, heiko, shawn.lin, Alexandru Marginean, paulus,
thomas.petazzoni, jonnyc, toan, will, robh, lorenzo.pieralisi,
michal.simek, linux-rockchip, bcm-kernel-feedback-list,
linux-arm-kernel, linux-pci, rjui, f.fainelli, linux-rpi-kernel,
Jonathan.Cameron, bhelgaas, jonathan.derrick, sbranden, wangzhou1,
rrichter, Vladimir Oltean, linuxppc-dev, nsaenzjulienne
In-Reply-To: <595028ce6b04ea589f802ff61d8710f0@walle.cc>
On Wed, Dec 09, 2020 at 02:08:00PM +0100, Michael Walle wrote:
> [+ Vladimir and Alex]
>
> Am 2020-12-09 13:36, schrieb Bjorn Helgaas:
> > On Tue, Dec 08, 2020 at 04:41:50PM +0100, Michael Walle wrote:
> > > >On Sun, 29 Nov 2020 23:07:38 +0000, Krzysztof Wilczyński wrote:
> > > >> Unify ECAM-related constants into a single set of standard constants
> > > >> defining memory address shift values for the byte-level address that can
> > > >> be used when accessing the PCI Express Configuration Space, and then
> > > >> move native PCI Express controller drivers to use newly introduced
> > > >> definitions retiring any driver-specific ones.
> > > >>
> > > >> The ECAM ("Enhanced Configuration Access Mechanism") is defined by the
> > > >> PCI Express specification (see PCI Express Base Specification, Revision
> > > >> 5.0, Version 1.0, Section 7.2.2, p. 676), thus most hardware should
> > > >> implement it the same way.
> > > >>
> > > >> [...]
> > > >
> > > >Applied to pci/ecam, thanks!
> > > >
> > > >[1/5] PCI: Unify ECAM constants in native PCI Express drivers
> > > > https://git.kernel.org/lpieralisi/pci/c/f3c07cf692
> >
> > > Patch 1/5 breaks LS1028A boards:
> > >
> > > [..]
> > > [ 1.144426] pci-host-generic 1f0000000.pcie: host bridge
> > > /soc/pcie@1f0000000 ranges:
> > > [ 1.152276] pci-host-generic 1f0000000.pcie: MEM
> > > 0x01f8000000..0x01f815ffff -> 0x0000000000
> > > [ 1.161161] pci-host-generic 1f0000000.pcie: MEM
> > > 0x01f8160000..0x01f81cffff -> 0x0000000000
> > > [ 1.170043] pci-host-generic 1f0000000.pcie: MEM
> > > 0x01f81d0000..0x01f81effff -> 0x0000000000
> > > [ 1.178924] pci-host-generic 1f0000000.pcie: MEM
> > > 0x01f81f0000..0x01f820ffff -> 0x0000000000
> > > [ 1.187805] pci-host-generic 1f0000000.pcie: MEM
> > > 0x01f8210000..0x01f822ffff -> 0x0000000000
> > > [ 1.196686] pci-host-generic 1f0000000.pcie: MEM
> > > 0x01f8230000..0x01f824ffff -> 0x0000000000
> > > [ 1.205562] pci-host-generic 1f0000000.pcie: MEM
> > > 0x01fc000000..0x01fc3fffff -> 0x0000000000
> >
> > Can you attach your DT?
> That would be the following:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts
>
> You'll find the PCI devices/bridge in:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
>
> > The fact that all these windows map to PCI
> > bus address 0 looks broken. Prior to patch 1/5, do the devices below
> > this bridge actually work?
>
> Yes, these should be the onboard network controller and ethernet
> switch.
Interesting. I can't see how they could work with those address
mappings, but that's another question we can look at later.
> > Looks like you're using the pci-host-generic driver; which of the
> > .compatible strings (pci-host-cam-generic, pci-host-ecam-generic,
> > marvell,armada8k-pcie-ecam, etc) are you using? (I think that's in
> > the DT as well.)
>
> compatible = "pci-host-ecam-generic";
> -michael
Can you try the following just to get started?
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 46935695cfb9..569a45727bc7 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -79,6 +79,7 @@ int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
{
void __iomem *addr;
+ pci_info(bus, "%s(%#x %#05x %d)\n", __func__, devfn, where, size);
addr = bus->ops->map_bus(bus, devfn, where);
if (!addr) {
*val = ~0;
@@ -101,6 +102,7 @@ int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
{
void __iomem *addr;
+ pci_info(bus, "%s(%#x %#05x %d)\n", __func__, devfn, where, size);
addr = bus->ops->map_bus(bus, devfn, where);
if (!addr)
return PCIBIOS_DEVICE_NOT_FOUND;
diff --git a/drivers/pci/ecam.c b/drivers/pci/ecam.c
index 59f91d434859..78f776e590be 100644
--- a/drivers/pci/ecam.c
+++ b/drivers/pci/ecam.c
@@ -33,6 +33,8 @@ struct pci_config_window *pci_ecam_create(struct device *dev,
struct resource *conflict;
int i, err;
+ dev_info(dev, "%s cfg %pR bus %pR\n", __func__, cfgres, busr);
+
if (busr->start > busr->end)
return ERR_PTR(-EINVAL);
@@ -85,6 +87,9 @@ struct pci_config_window *pci_ecam_create(struct device *dev,
goto err_exit_iomap;
}
+ dev_info(dev, "%s per_bus_mapping %d win %px\n", __func__,
+ per_bus_mapping, cfg->win);
+
if (ops->init) {
err = ops->init(cfg);
if (err)
@@ -140,6 +145,8 @@ void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn,
if (busn < cfg->busr.start || busn > cfg->busr.end)
return NULL;
+ pci_info(bus, "%s(%#x %#05x): %pR\n", __func__, devfn, where,
+ &cfg->busr);
busn -= cfg->busr.start;
if (per_bus_mapping) {
base = cfg->winp[busn];
@@ -147,6 +154,8 @@ void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn,
} else
base = cfg->win;
+ pci_info(bus, "%s base %px bus_shift %d\n", __func__, base,
+ cfg->ops->bus_shift);
if (cfg->ops->bus_shift) {
bus_offset = (busn & PCIE_ECAM_BUS_MASK) << bus_shift;
devfn_offset = (devfn & PCIE_ECAM_DEVFN_MASK) << devfn_shift;
^ permalink raw reply related
* Re: [PATCH 10/13] powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_MASK_FW
From: Greg Kurz @ 2020-12-09 15:21 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: linuxppc-dev
In-Reply-To: <20201208151124.1329942-11-clg@kaod.org>
On Tue, 8 Dec 2020 16:11:21 +0100
Cédric Le Goater <clg@kaod.org> wrote:
> This flag was used to support the PHB4 LSIs on P9 DD1 and we have
> stopped supporting this CPU when DD2 came out. See skiboot commit:
>
> https://github.com/open-power/skiboot/commit/0b0d15e3c170
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
In case a v2 is required, same suggestion to comment out the removed
items entirely, plus fix an indent nit....
> arch/powerpc/include/asm/opal-api.h | 2 +-
> arch/powerpc/include/asm/xive.h | 2 +-
> arch/powerpc/kvm/book3s_xive.c | 54 +++++------------------------
> arch/powerpc/sysdev/xive/common.c | 39 +--------------------
> arch/powerpc/sysdev/xive/native.c | 2 --
> 5 files changed, 11 insertions(+), 88 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
> index 48ee604ca39a..0455b679c050 100644
> --- a/arch/powerpc/include/asm/opal-api.h
> +++ b/arch/powerpc/include/asm/opal-api.h
> @@ -1092,7 +1092,7 @@ enum {
> OPAL_XIVE_IRQ_STORE_EOI = 0x00000002,
> OPAL_XIVE_IRQ_LSI = 0x00000004,
> OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008, /* P9 DD1.0 workaround */
> - OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010,
> + OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010, /* P9 DD1.0 workaround */
> OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020,
> };
>
> diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
> index ff805885a028..d62368d0ba91 100644
> --- a/arch/powerpc/include/asm/xive.h
> +++ b/arch/powerpc/include/asm/xive.h
> @@ -61,7 +61,7 @@ struct xive_irq_data {
> #define XIVE_IRQ_FLAG_STORE_EOI 0x01
> #define XIVE_IRQ_FLAG_LSI 0x02
> #define XIVE_IRQ_FLAG_SHIFT_BUG 0x04 /* P9 DD1.0 workaround */
> -#define XIVE_IRQ_FLAG_MASK_FW 0x08
> +#define XIVE_IRQ_FLAG_MASK_FW 0x08 /* P9 DD1.0 workaround */
> #define XIVE_IRQ_FLAG_EOI_FW 0x10
> #define XIVE_IRQ_FLAG_H_INT_ESB 0x20
>
> diff --git a/arch/powerpc/kvm/book3s_xive.c b/arch/powerpc/kvm/book3s_xive.c
> index fae1c2e8da29..59a986ae640b 100644
> --- a/arch/powerpc/kvm/book3s_xive.c
> +++ b/arch/powerpc/kvm/book3s_xive.c
> @@ -419,37 +419,16 @@ static u8 xive_lock_and_mask(struct kvmppc_xive *xive,
> /* Get the right irq */
> kvmppc_xive_select_irq(state, &hw_num, &xd);
>
> - /*
> - * If the interrupt is marked as needing masking via
> - * firmware, we do it here. Firmware masking however
> - * is "lossy", it won't return the old p and q bits
> - * and won't set the interrupt to a state where it will
> - * record queued ones. If this is an issue we should do
> - * lazy masking instead.
> - *
> - * For now, we work around this in unmask by forcing
> - * an interrupt whenever we unmask a non-LSI via FW
> - * (if ever).
> - */
> - if (xd->flags & OPAL_XIVE_IRQ_MASK_VIA_FW) {
> - xive_native_configure_irq(hw_num,
> - kvmppc_xive_vp(xive, state->act_server),
> - MASKED, state->number);
> - /* set old_p so we can track if an H_EOI was done */
> - state->old_p = true;
> - state->old_q = false;
> - } else {
> - /* Set PQ to 10, return old P and old Q and remember them */
> - val = xive_vm_esb_load(xd, XIVE_ESB_SET_PQ_10);
> - state->old_p = !!(val & 2);
> - state->old_q = !!(val & 1);
> + /* Set PQ to 10, return old P and old Q and remember them */
> + val = xive_vm_esb_load(xd, XIVE_ESB_SET_PQ_10);
> + state->old_p = !!(val & 2);
> + state->old_q = !!(val & 1);
>
> - /*
> - * Synchronize hardware to sensure the queues are updated
> - * when masking
> + /*
> + * Synchronize hardware to sensure the queues are updated
> + * when masking
> */
... here ^^
> - xive_native_sync_source(hw_num);
> - }
> + xive_native_sync_source(hw_num);
>
> return old_prio;
> }
> @@ -483,23 +462,6 @@ static void xive_finish_unmask(struct kvmppc_xive *xive,
> /* Get the right irq */
> kvmppc_xive_select_irq(state, &hw_num, &xd);
>
> - /*
> - * See comment in xive_lock_and_mask() concerning masking
> - * via firmware.
> - */
> - if (xd->flags & OPAL_XIVE_IRQ_MASK_VIA_FW) {
> - xive_native_configure_irq(hw_num,
> - kvmppc_xive_vp(xive, state->act_server),
> - state->act_priority, state->number);
> - /* If an EOI is needed, do it here */
> - if (!state->old_p)
> - xive_vm_source_eoi(hw_num, xd);
> - /* If this is not an LSI, force a trigger */
> - if (!(xd->flags & OPAL_XIVE_IRQ_LSI))
> - xive_irq_trigger(xd);
> - goto bail;
> - }
> -
> /* Old Q set, set PQ to 11 */
> if (state->old_q)
> xive_vm_esb_load(xd, XIVE_ESB_SET_PQ_11);
> diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
> index a9259470bf9f..a71412fefb65 100644
> --- a/arch/powerpc/sysdev/xive/common.c
> +++ b/arch/powerpc/sysdev/xive/common.c
> @@ -424,9 +424,7 @@ static void xive_irq_eoi(struct irq_data *d)
> }
>
> /*
> - * Helper used to mask and unmask an interrupt source. This
> - * is only called for normal interrupts that do not require
> - * masking/unmasking via firmware.
> + * Helper used to mask and unmask an interrupt source.
> */
> static void xive_do_source_set_mask(struct xive_irq_data *xd,
> bool mask)
> @@ -673,20 +671,6 @@ static void xive_irq_unmask(struct irq_data *d)
>
> pr_devel("xive_irq_unmask: irq %d data @%p\n", d->irq, xd);
>
> - /*
> - * This is a workaround for PCI LSI problems on P9, for
> - * these, we call FW to set the mask. The problems might
> - * be fixed by P9 DD2.0, if that is the case, firmware
> - * will no longer set that flag.
> - */
> - if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) {
> - unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
> - xive_ops->configure_irq(hw_irq,
> - get_hard_smp_processor_id(xd->target),
> - xive_irq_priority, d->irq);
> - return;
> - }
> -
> xive_do_source_set_mask(xd, false);
> }
>
> @@ -696,20 +680,6 @@ static void xive_irq_mask(struct irq_data *d)
>
> pr_devel("xive_irq_mask: irq %d data @%p\n", d->irq, xd);
>
> - /*
> - * This is a workaround for PCI LSI problems on P9, for
> - * these, we call OPAL to set the mask. The problems might
> - * be fixed by P9 DD2.0, if that is the case, firmware
> - * will no longer set that flag.
> - */
> - if (xd->flags & XIVE_IRQ_FLAG_MASK_FW) {
> - unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
> - xive_ops->configure_irq(hw_irq,
> - get_hard_smp_processor_id(xd->target),
> - 0xff, d->irq);
> - return;
> - }
> -
> xive_do_source_set_mask(xd, true);
> }
>
> @@ -852,13 +822,6 @@ static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
> int rc;
> u8 pq;
>
> - /*
> - * We only support this on interrupts that do not require
> - * firmware calls for masking and unmasking
> - */
> - if (xd->flags & XIVE_IRQ_FLAG_MASK_FW)
> - return -EIO;
> -
> /*
> * This is called by KVM with state non-NULL for enabling
> * pass-through or NULL for disabling it
> diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
> index 0310783241b5..deb97ad25d62 100644
> --- a/arch/powerpc/sysdev/xive/native.c
> +++ b/arch/powerpc/sysdev/xive/native.c
> @@ -64,8 +64,6 @@ int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
> data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
> if (opal_flags & OPAL_XIVE_IRQ_LSI)
> data->flags |= XIVE_IRQ_FLAG_LSI;
> - if (opal_flags & OPAL_XIVE_IRQ_MASK_VIA_FW)
> - data->flags |= XIVE_IRQ_FLAG_MASK_FW;
> if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
> data->flags |= XIVE_IRQ_FLAG_EOI_FW;
> data->eoi_page = be64_to_cpu(eoi_page);
^ permalink raw reply
* Re: [PATCH 11/13] powerpc/xive: Remove P9 DD1 flag XIVE_IRQ_FLAG_EOI_FW
From: Greg Kurz @ 2020-12-09 15:24 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: linuxppc-dev
In-Reply-To: <20201208151124.1329942-12-clg@kaod.org>
On Tue, 8 Dec 2020 16:11:22 +0100
Cédric Le Goater <clg@kaod.org> wrote:
> This flag was used to support the P9 DD1 and we have stopped
> supporting this CPU when DD2 came out. See skiboot commit:
>
> https://github.com/open-power/skiboot/commit/0b0d15e3c170
>
> Also, remove eoi handler which is now unused.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
Same suggestion as with previous patch.
> arch/powerpc/include/asm/opal-api.h | 2 +-
> arch/powerpc/include/asm/xive.h | 2 +-
> arch/powerpc/sysdev/xive/xive-internal.h | 1 -
> arch/powerpc/kvm/book3s_xive_template.c | 2 --
> arch/powerpc/sysdev/xive/common.c | 13 +------------
> arch/powerpc/sysdev/xive/native.c | 12 ------------
> arch/powerpc/sysdev/xive/spapr.c | 6 ------
> 7 files changed, 3 insertions(+), 35 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
> index 0455b679c050..0b63ba7d5917 100644
> --- a/arch/powerpc/include/asm/opal-api.h
> +++ b/arch/powerpc/include/asm/opal-api.h
> @@ -1093,7 +1093,7 @@ enum {
> OPAL_XIVE_IRQ_LSI = 0x00000004,
> OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008, /* P9 DD1.0 workaround */
> OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010, /* P9 DD1.0 workaround */
> - OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020,
> + OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020, /* P9 DD1.0 workaround */
> };
>
> /* Flags for OPAL_XIVE_GET/SET_QUEUE_INFO */
> diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h
> index d62368d0ba91..f6150d7a757a 100644
> --- a/arch/powerpc/include/asm/xive.h
> +++ b/arch/powerpc/include/asm/xive.h
> @@ -62,7 +62,7 @@ struct xive_irq_data {
> #define XIVE_IRQ_FLAG_LSI 0x02
> #define XIVE_IRQ_FLAG_SHIFT_BUG 0x04 /* P9 DD1.0 workaround */
> #define XIVE_IRQ_FLAG_MASK_FW 0x08 /* P9 DD1.0 workaround */
> -#define XIVE_IRQ_FLAG_EOI_FW 0x10
> +#define XIVE_IRQ_FLAG_EOI_FW 0x10 /* P9 DD1.0 workaround */
> #define XIVE_IRQ_FLAG_H_INT_ESB 0x20
>
> /* Special flag set by KVM for excalation interrupts */
> diff --git a/arch/powerpc/sysdev/xive/xive-internal.h b/arch/powerpc/sysdev/xive/xive-internal.h
> index 066d6fe3dc1d..3b7dd2cba9db 100644
> --- a/arch/powerpc/sysdev/xive/xive-internal.h
> +++ b/arch/powerpc/sysdev/xive/xive-internal.h
> @@ -52,7 +52,6 @@ struct xive_ops {
> void (*shutdown)(void);
>
> void (*update_pending)(struct xive_cpu *xc);
> - void (*eoi)(u32 hw_irq);
> void (*sync_source)(u32 hw_irq);
> u64 (*esb_rw)(u32 hw_irq, u32 offset, u64 data, bool write);
> #ifdef CONFIG_SMP
> diff --git a/arch/powerpc/kvm/book3s_xive_template.c b/arch/powerpc/kvm/book3s_xive_template.c
> index ece36e024a8f..b0015e05d99a 100644
> --- a/arch/powerpc/kvm/book3s_xive_template.c
> +++ b/arch/powerpc/kvm/book3s_xive_template.c
> @@ -74,8 +74,6 @@ static void GLUE(X_PFX,source_eoi)(u32 hw_irq, struct xive_irq_data *xd)
> /* If the XIVE supports the new "store EOI facility, use it */
> if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
> __x_writeq(0, __x_eoi_page(xd) + XIVE_ESB_STORE_EOI);
> - else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW)
> - opal_int_eoi(hw_irq);
> else if (xd->flags & XIVE_IRQ_FLAG_LSI) {
> /*
> * For LSIs the HW EOI cycle is used rather than PQ bits,
> diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
> index a71412fefb65..fe6229dd3241 100644
> --- a/arch/powerpc/sysdev/xive/common.c
> +++ b/arch/powerpc/sysdev/xive/common.c
> @@ -354,18 +354,7 @@ static void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd)
> /* If the XIVE supports the new "store EOI facility, use it */
> if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
> xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);
> - else if (hw_irq && xd->flags & XIVE_IRQ_FLAG_EOI_FW) {
> - /*
> - * The FW told us to call it. This happens for some
> - * interrupt sources that need additional HW whacking
> - * beyond the ESB manipulation. For example LPC interrupts
> - * on P9 DD1.0 needed a latch to be clared in the LPC bridge
> - * itself. The Firmware will take care of it.
> - */
> - if (WARN_ON_ONCE(!xive_ops->eoi))
> - return;
> - xive_ops->eoi(hw_irq);
> - } else {
> + else {
> u8 eoi_val;
>
> /*
> diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
> index deb97ad25d62..4902d05ebbd1 100644
> --- a/arch/powerpc/sysdev/xive/native.c
> +++ b/arch/powerpc/sysdev/xive/native.c
> @@ -64,8 +64,6 @@ int xive_native_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
> data->flags |= XIVE_IRQ_FLAG_STORE_EOI;
> if (opal_flags & OPAL_XIVE_IRQ_LSI)
> data->flags |= XIVE_IRQ_FLAG_LSI;
> - if (opal_flags & OPAL_XIVE_IRQ_EOI_VIA_FW)
> - data->flags |= XIVE_IRQ_FLAG_EOI_FW;
> data->eoi_page = be64_to_cpu(eoi_page);
> data->trig_page = be64_to_cpu(trig_page);
> data->esb_shift = be32_to_cpu(esb_shift);
> @@ -380,15 +378,6 @@ static void xive_native_update_pending(struct xive_cpu *xc)
> }
> }
>
> -static void xive_native_eoi(u32 hw_irq)
> -{
> - /*
> - * Not normally used except if specific interrupts need
> - * a workaround on EOI.
> - */
> - opal_int_eoi(hw_irq);
> -}
> -
> static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
> {
> s64 rc;
> @@ -471,7 +460,6 @@ static const struct xive_ops xive_native_ops = {
> .match = xive_native_match,
> .shutdown = xive_native_shutdown,
> .update_pending = xive_native_update_pending,
> - .eoi = xive_native_eoi,
> .setup_cpu = xive_native_setup_cpu,
> .teardown_cpu = xive_native_teardown_cpu,
> .sync_source = xive_native_sync_source,
> diff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c
> index 6610e5149d5a..01ccc0786ada 100644
> --- a/arch/powerpc/sysdev/xive/spapr.c
> +++ b/arch/powerpc/sysdev/xive/spapr.c
> @@ -628,11 +628,6 @@ static void xive_spapr_update_pending(struct xive_cpu *xc)
> }
> }
>
> -static void xive_spapr_eoi(u32 hw_irq)
> -{
> - /* Not used */;
> -}
> -
> static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
> {
> /* Only some debug on the TIMA settings */
> @@ -677,7 +672,6 @@ static const struct xive_ops xive_spapr_ops = {
> .match = xive_spapr_match,
> .shutdown = xive_spapr_shutdown,
> .update_pending = xive_spapr_update_pending,
> - .eoi = xive_spapr_eoi,
> .setup_cpu = xive_spapr_setup_cpu,
> .teardown_cpu = xive_spapr_teardown_cpu,
> .sync_source = xive_spapr_sync_source,
^ permalink raw reply
* Re: [PATCH 13/13] powerpc/xive: Improve error reporting of OPAL calls
From: Greg Kurz @ 2020-12-09 15:30 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: linuxppc-dev
In-Reply-To: <20201208151124.1329942-14-clg@kaod.org>
On Tue, 8 Dec 2020 16:11:24 +0100
Cédric Le Goater <clg@kaod.org> wrote:
> Introduce a vp_err() macro to standardize error reporting.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Reviewed-by: Greg Kurz <groug@kaod.org>
> arch/powerpc/sysdev/xive/native.c | 28 ++++++++++++++++------------
> 1 file changed, 16 insertions(+), 12 deletions(-)
>
> diff --git a/arch/powerpc/sysdev/xive/native.c b/arch/powerpc/sysdev/xive/native.c
> index 4902d05ebbd1..42297a131a6e 100644
> --- a/arch/powerpc/sysdev/xive/native.c
> +++ b/arch/powerpc/sysdev/xive/native.c
> @@ -122,6 +122,8 @@ static int xive_native_get_irq_config(u32 hw_irq, u32 *target, u8 *prio,
> return rc == 0 ? 0 : -ENXIO;
> }
>
> +#define vp_err(vp, fmt, ...) pr_err("VP[0x%x]: " fmt, vp, ##__VA_ARGS__)
> +
> /* This can be called multiple time to change a queue configuration */
> int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
> __be32 *qpage, u32 order, bool can_escalate)
> @@ -149,7 +151,7 @@ int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
> &esc_irq_be,
> NULL);
> if (rc) {
> - pr_err("Error %lld getting queue info prio %d\n", rc, prio);
> + vp_err(vp_id, "Failed to get queue %d info : %lld\n", prio, rc);
> rc = -EIO;
> goto fail;
> }
> @@ -172,7 +174,7 @@ int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
> msleep(OPAL_BUSY_DELAY_MS);
> }
> if (rc) {
> - pr_err("Error %lld setting queue for prio %d\n", rc, prio);
> + vp_err(vp_id, "Failed to set queue %d info: %lld\n", prio, rc);
> rc = -EIO;
> } else {
> /*
> @@ -199,7 +201,7 @@ static void __xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
> msleep(OPAL_BUSY_DELAY_MS);
> }
> if (rc)
> - pr_err("Error %lld disabling queue for prio %d\n", rc, prio);
> + vp_err(vp_id, "Failed to disable queue %d : %lld\n", prio, rc);
> }
>
> void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio)
> @@ -698,6 +700,8 @@ int xive_native_enable_vp(u32 vp_id, bool single_escalation)
> break;
> msleep(OPAL_BUSY_DELAY_MS);
> }
> + if (rc)
> + vp_err(vp_id, "Failed to enable VP : %lld\n", rc);
> return rc ? -EIO : 0;
> }
> EXPORT_SYMBOL_GPL(xive_native_enable_vp);
> @@ -712,6 +716,8 @@ int xive_native_disable_vp(u32 vp_id)
> break;
> msleep(OPAL_BUSY_DELAY_MS);
> }
> + if (rc)
> + vp_err(vp_id, "Failed to disable VP : %lld\n", rc);
> return rc ? -EIO : 0;
> }
> EXPORT_SYMBOL_GPL(xive_native_disable_vp);
> @@ -723,8 +729,10 @@ int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id)
> s64 rc;
>
> rc = opal_xive_get_vp_info(vp_id, NULL, &vp_cam_be, NULL, &vp_chip_id_be);
> - if (rc)
> + if (rc) {
> + vp_err(vp_id, "Failed to get VP info : %lld\n", rc);
> return -EIO;
> + }
> *out_cam_id = be64_to_cpu(vp_cam_be) & 0xffffffffu;
> *out_chip_id = be32_to_cpu(vp_chip_id_be);
>
> @@ -755,8 +763,7 @@ int xive_native_get_queue_info(u32 vp_id, u32 prio,
> rc = opal_xive_get_queue_info(vp_id, prio, &qpage, &qsize,
> &qeoi_page, &escalate_irq, &qflags);
> if (rc) {
> - pr_err("OPAL failed to get queue info for VCPU %d/%d : %lld\n",
> - vp_id, prio, rc);
> + vp_err(vp_id, "failed to get queue %d info : %lld\n", prio, rc);
> return -EIO;
> }
>
> @@ -784,8 +791,7 @@ int xive_native_get_queue_state(u32 vp_id, u32 prio, u32 *qtoggle, u32 *qindex)
> rc = opal_xive_get_queue_state(vp_id, prio, &opal_qtoggle,
> &opal_qindex);
> if (rc) {
> - pr_err("OPAL failed to get queue state for VCPU %d/%d : %lld\n",
> - vp_id, prio, rc);
> + vp_err(vp_id, "failed to get queue %d state : %lld\n", prio, rc);
> return -EIO;
> }
>
> @@ -804,8 +810,7 @@ int xive_native_set_queue_state(u32 vp_id, u32 prio, u32 qtoggle, u32 qindex)
>
> rc = opal_xive_set_queue_state(vp_id, prio, qtoggle, qindex);
> if (rc) {
> - pr_err("OPAL failed to set queue state for VCPU %d/%d : %lld\n",
> - vp_id, prio, rc);
> + vp_err(vp_id, "failed to set queue %d state : %lld\n", prio, rc);
> return -EIO;
> }
>
> @@ -827,8 +832,7 @@ int xive_native_get_vp_state(u32 vp_id, u64 *out_state)
>
> rc = opal_xive_get_vp_state(vp_id, &state);
> if (rc) {
> - pr_err("OPAL failed to get vp state for VCPU %d : %lld\n",
> - vp_id, rc);
> + vp_err(vp_id, "failed to get vp state : %lld\n", rc);
> return -EIO;
> }
>
^ permalink raw reply
* Re: [PATCH v6 0/5] PCI: Unify ECAM constants in native PCI Express drivers
From: Michael Walle @ 2020-12-09 15:40 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: kw, heiko, shawn.lin, Alexandru Marginean, paulus,
thomas.petazzoni, jonnyc, toan, will, robh, lorenzo.pieralisi,
michal.simek, linux-rockchip, bcm-kernel-feedback-list,
linux-arm-kernel, linux-pci, rjui, f.fainelli, linux-rpi-kernel,
Jonathan.Cameron, bhelgaas, jonathan.derrick, sbranden, wangzhou1,
rrichter, Vladimir Oltean, linuxppc-dev, nsaenzjulienne
In-Reply-To: <20201209145707.GA2521966@bjorn-Precision-5520>
Am 2020-12-09 15:57, schrieb Bjorn Helgaas:
[..]
> Can you try the following just to get started?
>
> diff --git a/drivers/pci/access.c b/drivers/pci/access.c
> index 46935695cfb9..569a45727bc7 100644
> --- a/drivers/pci/access.c
> +++ b/drivers/pci/access.c
> @@ -79,6 +79,7 @@ int pci_generic_config_read(struct pci_bus *bus,
> unsigned int devfn,
> {
> void __iomem *addr;
>
> + pci_info(bus, "%s(%#x %#05x %d)\n", __func__, devfn, where, size);
> addr = bus->ops->map_bus(bus, devfn, where);
> if (!addr) {
> *val = ~0;
> @@ -101,6 +102,7 @@ int pci_generic_config_write(struct pci_bus *bus,
> unsigned int devfn,
> {
> void __iomem *addr;
>
> + pci_info(bus, "%s(%#x %#05x %d)\n", __func__, devfn, where, size);
> addr = bus->ops->map_bus(bus, devfn, where);
> if (!addr)
> return PCIBIOS_DEVICE_NOT_FOUND;
> diff --git a/drivers/pci/ecam.c b/drivers/pci/ecam.c
> index 59f91d434859..78f776e590be 100644
> --- a/drivers/pci/ecam.c
> +++ b/drivers/pci/ecam.c
> @@ -33,6 +33,8 @@ struct pci_config_window *pci_ecam_create(struct
> device *dev,
> struct resource *conflict;
> int i, err;
>
> + dev_info(dev, "%s cfg %pR bus %pR\n", __func__, cfgres, busr);
> +
> if (busr->start > busr->end)
> return ERR_PTR(-EINVAL);
>
> @@ -85,6 +87,9 @@ struct pci_config_window *pci_ecam_create(struct
> device *dev,
> goto err_exit_iomap;
> }
>
> + dev_info(dev, "%s per_bus_mapping %d win %px\n", __func__,
> + per_bus_mapping, cfg->win);
> +
> if (ops->init) {
> err = ops->init(cfg);
> if (err)
> @@ -140,6 +145,8 @@ void __iomem *pci_ecam_map_bus(struct pci_bus
> *bus, unsigned int devfn,
> if (busn < cfg->busr.start || busn > cfg->busr.end)
> return NULL;
>
> + pci_info(bus, "%s(%#x %#05x): %pR\n", __func__, devfn, where,
> + &cfg->busr);
> busn -= cfg->busr.start;
> if (per_bus_mapping) {
> base = cfg->winp[busn];
> @@ -147,6 +154,8 @@ void __iomem *pci_ecam_map_bus(struct pci_bus
> *bus, unsigned int devfn,
> } else
> base = cfg->win;
>
> + pci_info(bus, "%s base %px bus_shift %d\n", __func__, base,
> + cfg->ops->bus_shift);
> if (cfg->ops->bus_shift) {
> bus_offset = (busn & PCIE_ECAM_BUS_MASK) << bus_shift;
> devfn_offset = (devfn & PCIE_ECAM_DEVFN_MASK) << devfn_shift;
Hopefully my mail client won't mess up the output that much.
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd083]
[ 0.000000] Linux version 5.10.0-rc7-next-20201208-dirty
(mwalle@mwalle01) (aarch64-linux-gnu-gcc (Debian 8.3.0-2) 8.3.0, GNU ld
(GNU Binutils for Debian) 2.31.1) #207 SMP PREEMPT Wed Dec 9 16:35:46
CET 2020
[ 0.000000] Machine model: Kontron SMARC-sAL28 (Single PHY) on SMARC
Eval 2.0 carrier
[ 0.000000] efi: UEFI not found.
[ 0.000000] cma: Reserved 32 MiB at 0x00000000fcc00000
[ 0.000000] earlycon: ns16550a0 at MMIO 0x00000000021c0500 (options
'115200n8')
[ 0.000000] printk: bootconsole [ns16550a0] enabled
[ 0.000000] NUMA: No NUMA configuration found
[ 0.000000] NUMA: Faking a node at [mem
0x0000000080000000-0x00000020ffffffff]
[ 0.000000] NUMA: NODE_DATA [mem 0x20ff7dcc00-0x20ff7defff]
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000080000000-0x00000000ffffffff]
[ 0.000000] DMA32 empty
[ 0.000000] Normal [mem 0x0000000100000000-0x00000020ffffffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000080000000-0x00000000ffffffff]
[ 0.000000] node 0: [mem 0x0000002080000000-0x00000020ffffffff]
[ 0.000000] Initmem setup node 0 [mem
0x0000000080000000-0x00000020ffffffff]
[ 0.000000] On node 0 totalpages: 1048576
[ 0.000000] DMA zone: 8192 pages used for memmap
[ 0.000000] DMA zone: 0 pages reserved
[ 0.000000] DMA zone: 524288 pages, LIFO batch:63
[ 0.000000] Normal zone: 8192 pages used for memmap
[ 0.000000] Normal zone: 524288 pages, LIFO batch:63
[ 0.000000] percpu: Embedded 32 pages/cpu s90264 r8192 d32616 u131072
[ 0.000000] pcpu-alloc: s90264 r8192 d32616 u131072 alloc=32*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1
[ 0.000000] Detected PIPT I-cache on CPU0
[ 0.000000] CPU features: detected: GIC system register CPU interface
[ 0.000000] CPU features: detected: Spectre-v3a
[ 0.000000] CPU features: detected: Spectre-v2
[ 0.000000] CPU features: detected: Spectre-v4
[ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or
1530923
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages:
1032192
[ 0.000000] Policy zone: Normal
[ 0.000000] Kernel command line: debug earlycon console=ttyS0,115200
[ 0.000000] Dentry cache hash table entries: 524288 (order: 10,
4194304 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152
bytes, linear)
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] software IO TLB: mapped [mem
0x00000000f8c00000-0x00000000fcc00000] (64MB)
[ 0.000000] Memory: 3978952K/4194304K available (15680K kernel code,
3706K rwdata, 8048K rodata, 8256K init, 510K bss, 182584K reserved,
32768K cma-reserved)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2,
Nodes=1
[ 0.000000] ftrace: allocating 55767 entries in 218 pages
[ 0.000000] ftrace: allocated 218 pages with 5 groups
[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
[ 0.000000] rcu: RCU event tracing is enabled.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to
nr_cpu_ids=2.
[ 0.000000] Trampoline variant of Tasks RCU enabled.
[ 0.000000] Rude variant of Tasks RCU enabled.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay
is 25 jiffies.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16,
nr_cpu_ids=2
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[ 0.000000] GICv3: 256 SPIs implemented
[ 0.000000] GICv3: 0 Extended SPIs implemented
[ 0.000000] GICv3: Distributor has no Range Selector support
[ 0.000000] GICv3: 16 PPIs implemented
[ 0.000000] GICv3: CPU0: found redistributor 0 region
0:0x0000000006040000
[ 0.000000] ITS [mem 0x06020000-0x0603ffff]
[ 0.000000] ITS@0x0000000006020000: allocated 65536 Devices
@2080200000 (flat, esz 8, psz 64K, shr 0)
[ 0.000000] ITS: using cache flushing for cmd queue
[ 0.000000] GICv3: using LPI property table @0x00000020801c0000
[ 0.000000] GIC: using cache flushing for LPI property table
[ 0.000000] GICv3: CPU0: using allocated LPI pending table
@0x00000020801d0000
[ 0.000000] random: get_random_bytes called from
start_kernel+0x3bc/0x578 with crng_init=0
[ 0.000000] arch_timer: cp15 timer(s) running at 25.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff
max_cycles: 0x5c40939b5, max_idle_ns: 440795202646 ns
[ 0.000002] sched_clock: 56 bits at 25MHz, resolution 40ns, wraps
every 4398046511100ns
[ 0.008419] Console: colour dummy device 80x25
[ 0.012951] Calibrating delay loop (skipped), value calculated using
timer frequency.. 50.00 BogoMIPS (lpj=100000)
[ 0.023407] pid_max: default: 32768 minimum: 301
[ 0.028106] LSM: Security Framework initializing
[ 0.032816] Mount-cache hash table entries: 8192 (order: 4, 65536
bytes, linear)
[ 0.040307] Mountpoint-cache hash table entries: 8192 (order: 4,
65536 bytes, linear)
[ 0.049064] rcu: Hierarchical SRCU implementation.
[ 0.054069] Platform MSI: gic-its@6020000 domain created
[ 0.059517] PCI/MSI: /interrupt-controller@6000000/gic-its@6020000
domain created
[ 0.067116] fsl-mc MSI: gic-its@6020000 domain created
[ 0.072911] EFI services will not be available.
[ 0.077578] smp: Bringing up secondary CPUs ...
[ 0.082420] Detected PIPT I-cache on CPU1
[ 0.082441] GICv3: CPU1: found redistributor 1 region
0:0x0000000006060000
[ 0.082448] GICv3: CPU1: using allocated LPI pending table
@0x00000020801e0000
[ 0.082475] CPU1: Booted secondary processor 0x0000000001
[0x410fd083]
[ 0.082541] smp: Brought up 1 node, 2 CPUs
[ 0.111539] SMP: Total of 2 processors activated.
[ 0.116288] CPU features: detected: 32-bit EL0 Support
[ 0.121483] CPU features: detected: CRC32 instructions
[ 0.126673] CPU features: detected: 32-bit EL1 Support
[ 0.140754] CPU: All CPU(s) started at EL2
[ 0.144903] alternatives: patching kernel code
[ 0.150172] devtmpfs: initialized
[ 0.155754] KASLR disabled due to lack of seed
[ 0.160507] clocksource: jiffies: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.170354] futex hash table entries: 512 (order: 3, 32768 bytes,
linear)
[ 0.177810] pinctrl core: initialized pinctrl subsystem
[ 0.183687] DMI not present or invalid.
[ 0.187857] NET: Registered protocol family 16
[ 0.193117] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic
allocations
[ 0.200341] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for
atomic allocations
[ 0.208322] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for
atomic allocations
[ 0.216341] audit: initializing netlink subsys (disabled)
[ 0.221897] audit: type=2000 audit(0.172:1): state=initialized
audit_enabled=0 res=1
[ 0.222415] thermal_sys: Registered thermal governor 'step_wise'
[ 0.229723] thermal_sys: Registered thermal governor
'power_allocator'
[ 0.236033] cpuidle: using governor menu
[ 0.246693] hw-breakpoint: found 6 breakpoint and 4 watchpoint
registers.
[ 0.253571] ASID allocator initialised with 65536 entries
[ 0.259602] Serial: AMBA PL011 UART driver
[ 0.274466] Machine: Kontron SMARC-sAL28 (Single PHY) on SMARC Eval
2.0 carrier
[ 0.281853] SoC family: QorIQ LS1028A
[ 0.285542] SoC ID: svr:0x870b0110, Revision: 1.0
[ 0.297947] HugeTLB registered 1.00 GiB page size, pre-allocated 0
pages
[ 0.304722] HugeTLB registered 32.0 MiB page size, pre-allocated 0
pages
[ 0.311489] HugeTLB registered 2.00 MiB page size, pre-allocated 0
pages
[ 0.318254] HugeTLB registered 64.0 KiB page size, pre-allocated 0
pages
[ 0.325775] cryptd: max_cpu_qlen set to 1000
[ 0.331453] ACPI: Interpreter disabled.
[ 0.336254] iommu: Default domain type: Translated
[ 0.341365] vgaarb: loaded
[ 0.344250] SCSI subsystem initialized
[ 0.348129] libata version 3.00 loaded.
[ 0.352170] usbcore: registered new interface driver usbfs
[ 0.357733] usbcore: registered new interface driver hub
[ 0.363112] usbcore: registered new device driver usb
[ 0.368478] imx-i2c 2000000.i2c: can't get pinctrl, bus recovery not
supported
[ 0.376183] i2c i2c-0: IMX I2C adapter registered
[ 0.381068] imx-i2c 2030000.i2c: can't get pinctrl, bus recovery not
supported
[ 0.388483] i2c i2c-1: IMX I2C adapter registered
[ 0.393357] imx-i2c 2040000.i2c: can't get pinctrl, bus recovery not
supported
[ 0.400879] i2c i2c-2: IMX I2C adapter registered
[ 0.405900] pps_core: LinuxPPS API ver. 1 registered
[ 0.410913] pps_core: Software ver. 5.3.6 - Copyright 2005-2007
Rodolfo Giometti <giometti@linux.it>
[ 0.420156] PTP clock support registered
[ 0.424188] EDAC MC: Ver: 3.0.0
[ 0.428104] FPGA manager framework
[ 0.431612] Advanced Linux Sound Architecture Driver Initialized.
[ 0.438221] clocksource: Switched to clocksource arch_sys_counter
[ 0.908920] VFS: Disk quotas dquot_6.6.0
[ 0.912921] VFS: Dquot-cache hash table entries: 512 (order 0, 4096
bytes)
[ 0.919981] pnp: PnP ACPI: disabled
[ 0.927129] NET: Registered protocol family 2
[ 0.931782] tcp_listen_portaddr_hash hash table entries: 2048 (order:
3, 32768 bytes, linear)
[ 0.940413] TCP established hash table entries: 32768 (order: 6,
262144 bytes, linear)
[ 0.948491] TCP bind hash table entries: 32768 (order: 7, 524288
bytes, linear)
[ 0.956179] TCP: Hash tables configured (established 32768 bind
32768)
[ 0.962890] UDP hash table entries: 2048 (order: 4, 65536 bytes,
linear)
[ 0.969682] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes,
linear)
[ 0.977005] NET: Registered protocol family 1
[ 0.981700] RPC: Registered named UNIX socket transport module.
[ 0.987696] RPC: Registered udp transport module.
[ 0.992444] RPC: Registered tcp transport module.
[ 0.997191] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 1.003697] PCI: CLS 0 bytes, default 64
[ 1.008034] hw perfevents: enabled with armv8_cortex_a72 PMU driver,
7 counters available
[ 1.016471] kvm [1]: IPA Size Limit: 44 bits
[ 1.021451] kvm [1]: GICv3: no GICV resource entry
[ 1.026291] kvm [1]: disabling GICv2 emulation
[ 1.030786] kvm [1]: GIC system register CPU interface enabled
[ 1.036703] kvm [1]: vgic interrupt IRQ9
[ 1.040722] kvm [1]: Hyp mode initialized successfully
[ 1.046971] Initialise system trusted keyrings
[ 1.051545] workingset: timestamp_bits=42 max_order=20 bucket_order=0
[ 1.061455] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 1.067780] NFS: Registering the id_resolver key type
[ 1.072903] Key type id_resolver registered
[ 1.077125] Key type id_legacy registered
[ 1.081217] nfs4filelayout_init: NFSv4 File Layout Driver
Registering...
[ 1.088079] 9p: Installing v9fs 9p2000 file system support
[ 1.122728] Key type asymmetric registered
[ 1.126867] Asymmetric key parser 'x509' registered
[ 1.131809] Block layer SCSI generic (bsg) driver version 0.4 loaded
(major 245)
[ 1.139278] io scheduler mq-deadline registered
[ 1.143849] io scheduler kyber registered
[ 1.153103] pci-host-generic 1f0000000.pcie: host bridge
/soc/pcie@1f0000000 ranges:
[ 1.160949] pci-host-generic 1f0000000.pcie: MEM
0x01f8000000..0x01f815ffff -> 0x0000000000
[ 1.169837] pci-host-generic 1f0000000.pcie: MEM
0x01f8160000..0x01f81cffff -> 0x0000000000
[ 1.178723] pci-host-generic 1f0000000.pcie: MEM
0x01f81d0000..0x01f81effff -> 0x0000000000
[ 1.187605] pci-host-generic 1f0000000.pcie: MEM
0x01f81f0000..0x01f820ffff -> 0x0000000000
[ 1.196487] pci-host-generic 1f0000000.pcie: MEM
0x01f8210000..0x01f822ffff -> 0x0000000000
[ 1.205369] pci-host-generic 1f0000000.pcie: MEM
0x01f8230000..0x01f824ffff -> 0x0000000000
[ 1.214247] pci-host-generic 1f0000000.pcie: MEM
0x01fc000000..0x01fc3fffff -> 0x0000000000
[ 1.223141] pci-host-generic 1f0000000.pcie: pci_ecam_create cfg [mem
0x1f0000000-0x1f00fffff] bus [bus 00]
[ 1.232992] pci-host-generic 1f0000000.pcie: pci_ecam_create
per_bus_mapping 0 win ffff8000123b1000
[ 1.242128] pci-host-generic 1f0000000.pcie: ECAM at [mem
0x1f0000000-0x1f00fffff] for [bus 00]
[ 1.250984] pci-host-generic 1f0000000.pcie: PCI host bridge to bus
0000:00
[ 1.258015] pci_bus 0000:00: root bus resource [bus 00]
[ 1.263292] pci_bus 0000:00: root bus resource [mem
0x1f8000000-0x1f815ffff] (bus address [0x00000000-0x0015ffff])
[ 1.273751] pci_bus 0000:00: root bus resource [mem
0x1f8160000-0x1f81cffff pref] (bus address [0x00000000-0x0006ffff])
[ 1.284647] pci_bus 0000:00: root bus resource [mem
0x1f81d0000-0x1f81effff] (bus address [0x00000000-0x0001ffff])
[ 1.295104] pci_bus 0000:00: root bus resource [mem
0x1f81f0000-0x1f820ffff pref] (bus address [0x00000000-0x0001ffff])
[ 1.305995] pci_bus 0000:00: root bus resource [mem
0x1f8210000-0x1f822ffff] (bus address [0x00000000-0x0001ffff])
[ 1.316448] pci_bus 0000:00: root bus resource [mem
0x1f8230000-0x1f824ffff pref] (bus address [0x00000000-0x0001ffff])
[ 1.327340] pci_bus 0000:00: root bus resource [mem
0x1fc000000-0x1fc3fffff] (bus address [0x00000000-0x003fffff])
[ 1.337794] pci_bus 0000:00: pci_generic_config_read(0x0 0x000 4)
[ 1.343942] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x000): [bus 00]
[ 1.350177] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.357563] pci_bus 0000:00: pci_generic_config_read(0x0 0x00e 1)
[ 1.363711] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x00e): [bus 00]
[ 1.369946] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.377327] pci_bus 0000:00: pci_generic_config_read(0x0 0x006 2)
[ 1.383475] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x006): [bus 00]
[ 1.389709] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.397090] pci_bus 0000:00: pci_generic_config_read(0x0 0x034 1)
[ 1.403237] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x034): [bus 00]
[ 1.409471] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.416855] pci_bus 0000:00: pci_generic_config_read(0x0 0x040 2)
[ 1.423002] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x040): [bus 00]
[ 1.429237] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.436618] pci_bus 0000:00: pci_generic_config_read(0x0 0x042 2)
[ 1.442765] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x042): [bus 00]
[ 1.448999] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.456380] pci_bus 0000:00: pci_generic_config_read(0x0 0x044 2)
[ 1.462527] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x044): [bus 00]
[ 1.468762] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.476148] pci_bus 0000:00: pci_generic_config_read(0x0 0x008 4)
[ 1.482296] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x008): [bus 00]
[ 1.488530] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.495912] pci_bus 0000:00: pci_generic_config_read(0x0 0x100 4)
[ 1.502060] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x100): [bus 00]
[ 1.508294] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.515675] pci_bus 0000:00: pci_generic_config_read(0x0 0x000 4)
[ 1.521822] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x000): [bus 00]
[ 1.528056] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.535440] pci_bus 0000:00: pci_generic_config_read(0x0 0x100 4)
[ 1.541587] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x100): [bus 00]
[ 1.547821] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.555202] pci_bus 0000:00: pci_generic_config_read(0x0 0x100 4)
[ 1.561349] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x100): [bus 00]
[ 1.567583] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.574964] pci_bus 0000:00: pci_generic_config_read(0x0 0x130 4)
[ 1.581111] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x130): [bus 00]
[ 1.587346] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.594728] pci_bus 0000:00: pci_generic_config_read(0x0 0x140 4)
[ 1.600876] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x140): [bus 00]
[ 1.607110] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.614494] pci 0000:00:00.0: [1957:e100] type 00 class 0x020001
[ 1.620558] pci_bus 0000:00: pci_generic_config_read(0x0 0x004 2)
[ 1.626705] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 1.632940] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.640320] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 1.646555] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 1.652789] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.660171] pci_bus 0000:00: pci_generic_config_read(0x0 0x004 2)
[ 1.666319] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 1.672553] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.679933] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 1.686168] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 1.692402] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.699782] pci_bus 0000:00: pci_generic_config_read(0x0 0x03d 1)
[ 1.705929] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x03d): [bus 00]
[ 1.712163] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.719546] pci_bus 0000:00: pci_generic_config_read(0x0 0x004 2)
[ 1.725693] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 1.731928] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.739308] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 1.745543] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 1.751777] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.759156] pci_bus 0000:00: pci_generic_config_read(0x0 0x010 4)
[ 1.765303] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x010): [bus 00]
[ 1.771538] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.778920] pci_bus 0000:00: pci_generic_config_write(0x0 0x010 4)
[ 1.785155] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x010): [bus 00]
[ 1.791389] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.798770] pci_bus 0000:00: pci_generic_config_read(0x0 0x010 4)
[ 1.804917] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x010): [bus 00]
[ 1.811151] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.818531] pci_bus 0000:00: pci_generic_config_write(0x0 0x010 4)
[ 1.824766] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x010): [bus 00]
[ 1.831000] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.838382] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 1.844617] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 1.850852] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.858232] pci_bus 0000:00: pci_generic_config_read(0x0 0x004 2)
[ 1.864379] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 1.870613] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.877993] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 1.884228] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 1.890462] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.897843] pci_bus 0000:00: pci_generic_config_read(0x0 0x014 4)
[ 1.903990] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x014): [bus 00]
[ 1.910224] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.917628] pci_bus 0000:00: pci_generic_config_write(0x0 0x014 4)
[ 1.923864] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x014): [bus 00]
[ 1.930098] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.937479] pci_bus 0000:00: pci_generic_config_read(0x0 0x014 4)
[ 1.943626] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x014): [bus 00]
[ 1.949861] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.957241] pci_bus 0000:00: pci_generic_config_write(0x0 0x014 4)
[ 1.963476] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x014): [bus 00]
[ 1.969709] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.977092] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 1.983327] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 1.989562] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 1.996943] pci_bus 0000:00: pci_generic_config_read(0x0 0x004 2)
[ 2.003089] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.009324] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.016704] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 2.022938] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.029173] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.036555] pci_bus 0000:00: pci_generic_config_read(0x0 0x018 4)
[ 2.042702] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x018): [bus 00]
[ 2.048937] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.056317] pci_bus 0000:00: pci_generic_config_write(0x0 0x018 4)
[ 2.062552] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x018): [bus 00]
[ 2.068786] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.076166] pci_bus 0000:00: pci_generic_config_read(0x0 0x018 4)
[ 2.082313] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x018): [bus 00]
[ 2.088547] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.095930] pci_bus 0000:00: pci_generic_config_write(0x0 0x018 4)
[ 2.102165] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x018): [bus 00]
[ 2.108400] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.115780] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 2.122014] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.128248] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.135629] pci_bus 0000:00: pci_generic_config_read(0x0 0x004 2)
[ 2.141776] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.148010] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.155392] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 2.161626] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.167861] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.175241] pci_bus 0000:00: pci_generic_config_read(0x0 0x01c 4)
[ 2.181388] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x01c): [bus 00]
[ 2.187622] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.195002] pci_bus 0000:00: pci_generic_config_write(0x0 0x01c 4)
[ 2.201237] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x01c): [bus 00]
[ 2.207471] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.214854] pci_bus 0000:00: pci_generic_config_read(0x0 0x01c 4)
[ 2.221001] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x01c): [bus 00]
[ 2.227235] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.234615] pci_bus 0000:00: pci_generic_config_write(0x0 0x01c 4)
[ 2.240850] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x01c): [bus 00]
[ 2.247084] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.254464] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 2.260698] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.266932] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.274314] pci_bus 0000:00: pci_generic_config_read(0x0 0x004 2)
[ 2.280462] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.286696] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.294077] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 2.300312] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.306546] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.313925] pci_bus 0000:00: pci_generic_config_read(0x0 0x020 4)
[ 2.320072] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x020): [bus 00]
[ 2.326306] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.333686] pci_bus 0000:00: pci_generic_config_write(0x0 0x020 4)
[ 2.339921] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x020): [bus 00]
[ 2.346156] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.353538] pci_bus 0000:00: pci_generic_config_read(0x0 0x020 4)
[ 2.359685] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x020): [bus 00]
[ 2.365919] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.373300] pci_bus 0000:00: pci_generic_config_write(0x0 0x020 4)
[ 2.379534] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x020): [bus 00]
[ 2.385768] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.393148] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 2.399382] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.405617] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.413000] pci_bus 0000:00: pci_generic_config_read(0x0 0x004 2)
[ 2.419148] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.425382] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.432762] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 2.438997] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.445231] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.452611] pci_bus 0000:00: pci_generic_config_read(0x0 0x024 4)
[ 2.458758] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x024): [bus 00]
[ 2.464993] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.472374] pci_bus 0000:00: pci_generic_config_write(0x0 0x024 4)
[ 2.478609] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x024): [bus 00]
[ 2.484843] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.492223] pci_bus 0000:00: pci_generic_config_read(0x0 0x024 4)
[ 2.498370] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x024): [bus 00]
[ 2.504604] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.511985] pci_bus 0000:00: pci_generic_config_write(0x0 0x024 4)
[ 2.518219] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x024): [bus 00]
[ 2.524454] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.531836] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 2.538071] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.544305] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.551686] pci_bus 0000:00: pci_generic_config_read(0x0 0x004 2)
[ 2.557833] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.564067] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.571447] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 2.577681] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.583916] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.591298] pci_bus 0000:00: pci_generic_config_read(0x0 0x030 4)
[ 2.597445] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x030): [bus 00]
[ 2.603680] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.611060] pci_bus 0000:00: pci_generic_config_write(0x0 0x030 4)
[ 2.617295] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x030): [bus 00]
[ 2.623530] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.630910] pci_bus 0000:00: pci_generic_config_read(0x0 0x030 4)
[ 2.637057] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x030): [bus 00]
[ 2.643291] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.650673] pci_bus 0000:00: pci_generic_config_write(0x0 0x030 4)
[ 2.656908] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x030): [bus 00]
[ 2.663143] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.670523] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 2.676757] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 2.682992] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.690372] pci_bus 0000:00: pci_generic_config_read(0x0 0x02c 2)
[ 2.696519] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x02c): [bus 00]
[ 2.702754] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.710133] pci_bus 0000:00: pci_generic_config_read(0x0 0x02e 2)
[ 2.716281] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x02e): [bus 00]
[ 2.722515] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.729899] pci_bus 0000:00: pci_generic_config_read(0x0 0x048 2)
[ 2.736046] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x048): [bus 00]
[ 2.742280] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.749661] pci_bus 0000:00: pci_generic_config_write(0x0 0x048 2)
[ 2.755895] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x048): [bus 00]
[ 2.762130] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.769510] pci_bus 0000:00: pci_generic_config_read(0x0 0x044 4)
[ 2.775657] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x044): [bus 00]
[ 2.781891] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.789274] pci_bus 0000:00: pci_generic_config_read(0x0 0x048 2)
[ 2.795421] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x048): [bus 00]
[ 2.801655] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.809036] pci_bus 0000:00: pci_generic_config_read(0x0 0x100 4)
[ 2.815183] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x100): [bus 00]
[ 2.821418] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.828798] pci_bus 0000:00: pci_generic_config_read(0x0 0x130 4)
[ 2.834945] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x130): [bus 00]
[ 2.841180] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.848562] pci_bus 0000:00: pci_generic_config_read(0x0 0x140 4)
[ 2.854709] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x140): [bus 00]
[ 2.860943] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.868324] pci_bus 0000:00: pci_generic_config_read(0x0 0x064 4)
[ 2.874471] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x064): [bus 00]
[ 2.880705] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.888085] pci_bus 0000:00: pci_generic_config_read(0x0 0x064 4)
[ 2.894233] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x064): [bus 00]
[ 2.900467] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.907864] pci_bus 0000:00: pci_generic_config_read(0x0 0x006 2)
[ 2.914012] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x006): [bus 00]
[ 2.920246] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.927628] pci_bus 0000:00: pci_generic_config_read(0x0 0x034 1)
[ 2.933776] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x034): [bus 00]
[ 2.940010] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.947390] pci_bus 0000:00: pci_generic_config_read(0x0 0x040 2)
[ 2.953537] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x040): [bus 00]
[ 2.959771] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.967154] pci_bus 0000:00: pci_generic_config_read(0x0 0x080 2)
[ 2.973301] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x080): [bus 00]
[ 2.979535] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 2.986916] pci_bus 0000:00: pci_generic_config_read(0x0 0x090 2)
[ 2.993063] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x090): [bus 00]
[ 2.999297] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.006677] pci_bus 0000:00: pci_generic_config_read(0x0 0x09c 2)
[ 3.012824] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x09c): [bus 00]
[ 3.019058] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.026441] pci_bus 0000:00: pci_generic_config_read(0x0 0x09e 1)
[ 3.032587] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x09e): [bus 00]
[ 3.038822] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.046202] pci_bus 0000:00: pci_generic_config_read(0x0 0x0a0 4)
[ 3.052349] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0a0): [bus 00]
[ 3.058584] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.065964] pci_bus 0000:00: pci_generic_config_read(0x0 0x0a4 4)
[ 3.072111] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0a4): [bus 00]
[ 3.078345] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.085725] pci_bus 0000:00: pci_generic_config_read(0x0 0x0a8 4)
[ 3.091872] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0a8): [bus 00]
[ 3.098106] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.105488] pci_bus 0000:00: pci_generic_config_read(0x0 0x0ac 4)
[ 3.111635] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0ac): [bus 00]
[ 3.117869] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.125251] pci 0000:00:00.0: BAR 0: [mem 0x1f8000000-0x1f803ffff
64bit] (from Enhanced Allocation, properties 0x0)
[ 3.135790] pci_bus 0000:00: pci_generic_config_read(0x0 0x0b0 4)
[ 3.141937] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0b0): [bus 00]
[ 3.148172] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.155552] pci_bus 0000:00: pci_generic_config_read(0x0 0x0b4 4)
[ 3.161698] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0b4): [bus 00]
[ 3.167933] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.175315] pci_bus 0000:00: pci_generic_config_read(0x0 0x0b8 4)
[ 3.181462] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0b8): [bus 00]
[ 3.187696] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.195076] pci_bus 0000:00: pci_generic_config_read(0x0 0x0bc 4)
[ 3.201223] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0bc): [bus 00]
[ 3.207457] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.214838] pci 0000:00:00.0: BAR 2: [mem 0x1f8160000-0x1f816ffff
64bit pref] (from Enhanced Allocation, properties 0x1)
[ 3.225816] pci_bus 0000:00: pci_generic_config_read(0x0 0x0c0 4)
[ 3.231963] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0c0): [bus 00]
[ 3.238197] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.245580] pci_bus 0000:00: pci_generic_config_read(0x0 0x0c4 4)
[ 3.251727] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0c4): [bus 00]
[ 3.257961] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.265342] pci_bus 0000:00: pci_generic_config_read(0x0 0x0c8 4)
[ 3.271489] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0c8): [bus 00]
[ 3.277723] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.285103] pci_bus 0000:00: pci_generic_config_read(0x0 0x0cc 4)
[ 3.291250] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0cc): [bus 00]
[ 3.297485] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.304868] pci 0000:00:00.0: VF BAR 0: [mem 0x1f81d0000-0x1f81dffff
64bit] (from Enhanced Allocation, properties 0x4)
[ 3.315671] pci_bus 0000:00: pci_generic_config_read(0x0 0x0d0 4)
[ 3.321818] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0d0): [bus 00]
[ 3.328053] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.335433] pci_bus 0000:00: pci_generic_config_read(0x0 0x0d4 4)
[ 3.341579] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0d4): [bus 00]
[ 3.347813] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.355193] pci_bus 0000:00: pci_generic_config_read(0x0 0x0d8 4)
[ 3.361340] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0d8): [bus 00]
[ 3.367575] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.374957] pci_bus 0000:00: pci_generic_config_read(0x0 0x0dc 4)
[ 3.381103] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x0dc): [bus 00]
[ 3.387337] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.394719] pci 0000:00:00.0: VF BAR 2: [mem 0x1f81f0000-0x1f81fffff
64bit pref] (from Enhanced Allocation, properties 0x3)
[ 3.405959] pci_bus 0000:00: pci_generic_config_read(0x0 0x006 2)
[ 3.412106] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x006): [bus 00]
[ 3.418340] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.425722] pci_bus 0000:00: pci_generic_config_read(0x0 0x034 1)
[ 3.431868] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x034): [bus 00]
[ 3.438103] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.445485] pci_bus 0000:00: pci_generic_config_read(0x0 0x040 2)
[ 3.451632] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x040): [bus 00]
[ 3.457866] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.465247] pci_bus 0000:00: pci_generic_config_read(0x0 0x080 2)
[ 3.471394] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x080): [bus 00]
[ 3.477628] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.485008] pci_bus 0000:00: pci_generic_config_read(0x0 0x090 2)
[ 3.491155] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x090): [bus 00]
[ 3.497389] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.504771] pci_bus 0000:00: pci_generic_config_read(0x0 0x09c 2)
[ 3.510918] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x09c): [bus 00]
[ 3.517153] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.524533] pci_bus 0000:00: pci_generic_config_read(0x0 0x006 2)
[ 3.530680] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x006): [bus 00]
[ 3.536914] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.544294] pci_bus 0000:00: pci_generic_config_read(0x0 0x034 1)
[ 3.550441] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x034): [bus 00]
[ 3.556675] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.564058] pci_bus 0000:00: pci_generic_config_read(0x0 0x040 2)
[ 3.570205] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x040): [bus 00]
[ 3.576440] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.583820] pci_bus 0000:00: pci_generic_config_read(0x0 0x080 2)
[ 3.589967] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x080): [bus 00]
[ 3.596202] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.603581] pci_bus 0000:00: pci_generic_config_read(0x0 0x082 2)
[ 3.609729] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x082): [bus 00]
[ 3.615964] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.623346] pci_bus 0000:00: pci_generic_config_read(0x0 0x006 2)
[ 3.629493] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x006): [bus 00]
[ 3.635728] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.643108] pci_bus 0000:00: pci_generic_config_read(0x0 0x034 1)
[ 3.649255] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x034): [bus 00]
[ 3.655489] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.662869] pci_bus 0000:00: pci_generic_config_read(0x0 0x040 2)
[ 3.669016] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x040): [bus 00]
[ 3.675250] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.682634] pci_bus 0000:00: pci_generic_config_read(0x0 0x006 2)
[ 3.688780] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x006): [bus 00]
[ 3.695015] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.702395] pci_bus 0000:00: pci_generic_config_read(0x0 0x034 1)
[ 3.708542] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x034): [bus 00]
[ 3.714777] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.722157] pci_bus 0000:00: pci_generic_config_read(0x0 0x040 2)
[ 3.728304] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x040): [bus 00]
[ 3.734538] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.741918] pci_bus 0000:00: pci_generic_config_read(0x0 0x080 2)
[ 3.748065] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x080): [bus 00]
[ 3.754300] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.761682] pci_bus 0000:00: pci_generic_config_read(0x0 0x090 2)
[ 3.767829] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x090): [bus 00]
[ 3.774063] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.781443] pci_bus 0000:00: pci_generic_config_read(0x0 0x09c 2)
[ 3.787590] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x09c): [bus 00]
[ 3.793825] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.801205] pci_bus 0000:00: pci_generic_config_read(0x0 0x100 4)
[ 3.807352] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x100): [bus 00]
[ 3.813586] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.820968] pci_bus 0000:00: pci_generic_config_read(0x0 0x130 4)
[ 3.827115] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x130): [bus 00]
[ 3.833350] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.840730] pci_bus 0000:00: pci_generic_config_read(0x0 0x140 4)
[ 3.846877] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x140): [bus 00]
[ 3.853111] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.860491] pci_bus 0000:00: pci_generic_config_read(0x0 0x100 4)
[ 3.866637] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x100): [bus 00]
[ 3.872872] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.880254] pci_bus 0000:00: pci_generic_config_read(0x0 0x130 4)
[ 3.886401] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x130): [bus 00]
[ 3.892636] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.900016] pci_bus 0000:00: pci_generic_config_read(0x0 0x140 4)
[ 3.906163] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x140): [bus 00]
[ 3.912397] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.919778] pci_bus 0000:00: pci_generic_config_read(0x0 0x100 4)
[ 3.925925] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x100): [bus 00]
[ 3.932159] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.939543] pci_bus 0000:00: pci_generic_config_read(0x0 0x130 4)
[ 3.945690] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x130): [bus 00]
[ 3.951924] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.959305] pci_bus 0000:00: pci_generic_config_read(0x0 0x140 4)
[ 3.965452] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x140): [bus 00]
[ 3.971686] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.979066] pci_bus 0000:00: pci_generic_config_read(0x0 0x100 4)
[ 3.985213] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x100): [bus 00]
[ 3.991447] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 3.998829] pci_bus 0000:00: pci_generic_config_read(0x0 0x130 4)
[ 4.004976] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x130): [bus 00]
[ 4.011211] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.018591] pci_bus 0000:00: pci_generic_config_read(0x0 0x140 4)
[ 4.024738] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x140): [bus 00]
[ 4.030973] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.038353] pci_bus 0000:00: pci_generic_config_read(0x0 0x100 4)
[ 4.044500] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x100): [bus 00]
[ 4.050734] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.058114] pci_bus 0000:00: pci_generic_config_read(0x0 0x130 4)
[ 4.064261] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x130): [bus 00]
[ 4.070495] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.077877] pci_bus 0000:00: pci_generic_config_read(0x0 0x140 4)
[ 4.084024] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x140): [bus 00]
[ 4.090259] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.097642] pci_bus 0000:00: pci_generic_config_read(0x0 0x006 2)
[ 4.103789] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x006): [bus 00]
[ 4.110023] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.117403] pci_bus 0000:00: pci_generic_config_read(0x0 0x034 1)
[ 4.123550] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x034): [bus 00]
[ 4.129784] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.137166] pci_bus 0000:00: pci_generic_config_read(0x0 0x040 2)
[ 4.143314] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x040): [bus 00]
[ 4.149548] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.156929] pci_bus 0000:00: pci_generic_config_read(0x0 0x080 2)
[ 4.163076] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x080): [bus 00]
[ 4.169310] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.176690] pci_bus 0000:00: pci_generic_config_read(0x0 0x090 2)
[ 4.182837] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x090): [bus 00]
[ 4.189071] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.196453] pci_bus 0000:00: pci_generic_config_read(0x0 0x092 2)
[ 4.202600] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x092): [bus 00]
[ 4.208835] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.216216] pci 0000:00:00.0: PME# supported from D0 D3hot
[ 4.221754] pci_bus 0000:00: pci_generic_config_read(0x0 0x094 2)
[ 4.227901] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x094): [bus 00]
[ 4.234135] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.241516] pci_bus 0000:00: pci_generic_config_write(0x0 0x094 2)
[ 4.247750] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x094): [bus 00]
[ 4.253985] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.261368] pci_bus 0000:00: pci_generic_config_read(0x0 0x006 2)
[ 4.267515] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x006): [bus 00]
[ 4.273749] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.281130] pci_bus 0000:00: pci_generic_config_read(0x0 0x006 2)
[ 4.287277] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x006): [bus 00]
[ 4.293511] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.300891] pci_bus 0000:00: pci_generic_config_read(0x0 0x034 1)
[ 4.307038] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x034): [bus 00]
[ 4.313273] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.320655] pci_bus 0000:00: pci_generic_config_read(0x0 0x040 2)
[ 4.326802] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x040): [bus 00]
[ 4.333036] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.340417] pci_bus 0000:00: pci_generic_config_read(0x0 0x080 2)
[ 4.346563] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x080): [bus 00]
[ 4.352798] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.360178] pci_bus 0000:00: pci_generic_config_read(0x0 0x090 2)
[ 4.366325] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x090): [bus 00]
[ 4.372559] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.379941] pci_bus 0000:00: pci_generic_config_read(0x0 0x09c 2)
[ 4.386088] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x09c): [bus 00]
[ 4.392322] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.399703] pci_bus 0000:00: pci_generic_config_read(0x0 0x100 4)
[ 4.405850] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x100): [bus 00]
[ 4.412085] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.419465] pci_bus 0000:00: pci_generic_config_read(0x0 0x130 4)
[ 4.425612] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x130): [bus 00]
[ 4.431846] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.439228] pci_bus 0000:00: pci_generic_config_read(0x0 0x140 4)
[ 4.445376] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x140): [bus 00]
[ 4.451610] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.458992] pci_bus 0000:00: pci_generic_config_read(0x0 0x148 2)
[ 4.465139] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x148): [bus 00]
[ 4.471373] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.478754] pci_bus 0000:00: pci_generic_config_write(0x0 0x148 2)
[ 4.484988] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x148): [bus 00]
[ 4.491222] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.498604] pci_bus 0000:00: pci_generic_config_read(0x0 0x14e 2)
[ 4.504752] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x14e): [bus 00]
[ 4.510986] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.518367] pci_bus 0000:00: pci_generic_config_read(0x0 0x15c 4)
[ 4.524514] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x15c): [bus 00]
[ 4.530748] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.538128] pci_bus 0000:00: pci_generic_config_write(0x0 0x160 4)
[ 4.544362] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x160): [bus 00]
[ 4.550597] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.557979] pci 0000:00:00.0: VF(n) BAR0 space: [mem
0x1f81d0000-0x1f81effff 64bit] (contains BAR0 for 2 VFs)
[ 4.567995] pci 0000:00:00.0: VF(n) BAR2 space: [mem
0x1f81f0000-0x1f820ffff 64bit pref] (contains BAR2 for 2 VFs)
[ 4.578446] pci_bus 0000:00: pci_generic_config_read(0x0 0x004 2)
[ 4.584593] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 4.590828] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.598208] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 4.604443] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 4.610677] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.618057] pci_bus 0000:00: pci_generic_config_read(0x0 0x174 4)
[ 4.624204] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x174): [bus 00]
[ 4.630438] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.637821] pci_bus 0000:00: pci_generic_config_write(0x0 0x174 4)
[ 4.644055] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x174): [bus 00]
[ 4.650290] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.657670] pci_bus 0000:00: pci_generic_config_read(0x0 0x174 4)
[ 4.663817] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x174): [bus 00]
[ 4.670052] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.677431] pci_bus 0000:00: pci_generic_config_write(0x0 0x174 4)
[ 4.683666] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x174): [bus 00]
[ 4.689901] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.697283] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 4.703518] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 4.709752] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.717133] pci_bus 0000:00: pci_generic_config_read(0x0 0x004 2)
[ 4.723279] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 4.729513] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.736893] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 4.743128] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 4.749363] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.756745] pci_bus 0000:00: pci_generic_config_read(0x0 0x178 4)
[ 4.762892] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x178): [bus 00]
[ 4.769127] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.776507] pci_bus 0000:00: pci_generic_config_write(0x0 0x178 4)
[ 4.782741] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x178): [bus 00]
[ 4.788976] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.796356] pci_bus 0000:00: pci_generic_config_read(0x0 0x178 4)
[ 4.802503] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x178): [bus 00]
[ 4.808738] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.816120] pci_bus 0000:00: pci_generic_config_write(0x0 0x178 4)
[ 4.822355] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x178): [bus 00]
[ 4.828589] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.835969] pci_bus 0000:00: pci_generic_config_write(0x0 0x004 2)
[ 4.842204] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x004): [bus 00]
[ 4.848438] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.855818] pci_bus 0000:00: pci_generic_config_read(0x0 0x15a 2)
[ 4.861965] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x15a): [bus 00]
[ 4.868199] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.875582] pci_bus 0000:00: pci_generic_config_read(0x0 0x144 4)
[ 4.881729] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x144): [bus 00]
[ 4.887963] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.895344] pci_bus 0000:00: pci_generic_config_read(0x0 0x152 1)
[ 4.901491] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x152): [bus 00]
[ 4.907725] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.915105] pci_bus 0000:00: pci_generic_config_write(0x0 0x150 2)
[ 4.921340] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x150): [bus 00]
[ 4.927574] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.934956] pci_bus 0000:00: pci_generic_config_read(0x0 0x154 2)
[ 4.941104] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x154): [bus 00]
[ 4.947338] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.954718] pci_bus 0000:00: pci_generic_config_read(0x0 0x156 2)
[ 4.960865] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x156): [bus 00]
[ 4.967099] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.974480] pci_bus 0000:00: pci_generic_config_write(0x0 0x150 2)
[ 4.980714] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x150): [bus 00]
[ 4.986948] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 4.994331] pci_bus 0000:00: pci_generic_config_read(0x0 0x154 2)
[ 5.000478] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x154): [bus 00]
[ 5.006712] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.014093] pci_bus 0000:00: pci_generic_config_read(0x0 0x156 2)
[ 5.020239] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x156): [bus 00]
[ 5.026474] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.033854] pci_bus 0000:00: pci_generic_config_write(0x0 0x150 2)
[ 5.040089] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x150): [bus 00]
[ 5.046323] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.053703] pci_bus 0000:00: pci_generic_config_read(0x0 0x154 2)
[ 5.059850] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x154): [bus 00]
[ 5.066084] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.073467] pci_bus 0000:00: pci_generic_config_read(0x0 0x156 2)
[ 5.079614] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x156): [bus 00]
[ 5.085848] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.093229] pci_bus 0000:00: pci_generic_config_read(0x0 0x100 4)
[ 5.099376] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x100): [bus 00]
[ 5.105610] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.112990] pci_bus 0000:00: pci_generic_config_read(0x0 0x130 4)
[ 5.119137] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x130): [bus 00]
[ 5.125372] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.132754] pci_bus 0000:00: pci_generic_config_read(0x0 0x140 4)
[ 5.138901] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x140): [bus 00]
[ 5.145135] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.152515] pci_bus 0000:00: pci_generic_config_read(0x0 0x100 4)
[ 5.158662] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x100): [bus 00]
[ 5.164897] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.172277] pci_bus 0000:00: pci_generic_config_read(0x0 0x130 4)
[ 5.178423] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x130): [bus 00]
[ 5.184658] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.192039] pci_bus 0000:00: pci_generic_config_read(0x0 0x140 4)
[ 5.198186] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x140): [bus 00]
[ 5.204420] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.211801] pci_bus 0000:00: pci_generic_config_read(0x0 0x100 4)
[ 5.217948] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x100): [bus 00]
[ 5.224182] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.231562] pci_bus 0000:00: pci_generic_config_read(0x0 0x130 4)
[ 5.237709] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x130): [bus 00]
[ 5.243943] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.251327] pci_bus 0000:00: pci_generic_config_read(0x0 0x044 4)
[ 5.257474] pci_bus 0000:00: pci_ecam_map_bus(0x0 0x044): [bus 00]
[ 5.263708] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.271245] pci_bus 0000:00: pci_generic_config_read(0x1 0x000 4)
[ 5.277392] pci_bus 0000:00: pci_ecam_map_bus(0x1 0x000): [bus 00]
[ 5.283627] pci_bus 0000:00: pci_ecam_map_bus base ffff8000123b1000
bus_shift 0
[ 5.291007] Unable to handle kernel paging request at virtual address
ffff8000123b2000
[ 5.298996] Mem abort info:
[ 5.301807] ESR = 0x96000007
[ 5.304883] EC = 0x25: DABT (current EL), IL = 32 bits
[ 5.310240] SET = 0, FnV = 0
[ 5.313315] EA = 0, S1PTW = 0
[ 5.316477] Data abort info:
[ 5.319376] ISV = 0, ISS = 0x00000007
[ 5.323240] CM = 0, WnR = 0
[ 5.326228] swapper pgtable: 4k pages, 48-bit VAs,
pgdp=0000000083741000
[ 5.332989] [ffff8000123b2000] pgd=00000020fffff003,
p4d=00000020fffff003, pud=00000020ffffe003, pmd=00000020ffff8003,
pte=0000000000000000
[ 5.345641] Internal error: Oops: 96000007 [#1] PREEMPT SMP
[ 5.351262] Modules linked in:
[ 5.354342] CPU: 1 PID: 1 Comm: swapper/0 Not tainted
5.10.0-rc7-next-20201208-dirty #207
[ 5.362595] Hardware name: Kontron SMARC-sAL28 (Single PHY) on SMARC
Eval 2.0 carrier (DT)
[ 5.370937] pstate: 20000085 (nzCv daIf -PAN -UAO -TCO BTYPE=--)
[ 5.377005] pc : pci_generic_config_read+0xdc/0x110
[ 5.381925] lr : pci_generic_config_read+0x70/0x110
[ 5.386842] sp : ffff80001239b8f0
[ 5.390181] x29: ffff80001239b8f0 x28: 0000000000000000
[ 5.395541] x27: ffff8000117504e4 x26: 0000000000000000
[ 5.400902] x25: 0000000000000001 x24: ffff80001239ba44
[ 5.406262] x23: 0000000000000000 x22: 0000000000000001
[ 5.411622] x21: ffff002001490000 x20: 0000000000000004
[ 5.416982] x19: ffff80001239b984 x18: 0000000000000010
[ 5.422342] x17: 0000000000007fff x16: 00000000ffffffff
[ 5.427702] x15: ffffffffffffffff x14: ffff800011f69948
[ 5.433062] x13: ffff80009239b4f7 x12: ffff800012004188
[ 5.438421] x11: 0000000000000003 x10: ffff800011fec148
[ 5.443781] x9 : ffff800010101b10 x8 : 0000000000017fe8
[ 5.449141] x7 : c0000000ffffefff x6 : 0000000000000001
[ 5.454501] x5 : 0000000000000000 x4 : ffff8000123b2000
[ 5.459860] x3 : 00000000fffffff8 x2 : 0000000001000000
[ 5.465220] x1 : 0000000000000000 x0 : ffff8000123b2000
[ 5.470580] Call trace:
[ 5.473043] pci_generic_config_read+0xdc/0x110
[ 5.477614] pci_bus_read_config_dword+0x8c/0xe0
[ 5.482271] pci_bus_generic_read_dev_vendor_id+0x3c/0x1b8
[ 5.487804] pci_bus_read_dev_vendor_id+0x54/0x78
[ 5.492548] pci_scan_single_device+0x8c/0xe8
[ 5.496941] pci_scan_slot+0x74/0x128
[ 5.500632] pci_scan_child_bus_extend+0x5c/0x2a0
[ 5.505376] pci_scan_root_bus_bridge+0xdc/0xf8
[ 5.509944] pci_host_probe+0x20/0xb8
[ 5.513635] pci_host_common_probe+0x144/0x1a8
[ 5.518116] platform_drv_probe+0x5c/0xb0
[ 5.522158] really_probe+0xec/0x3c0
[ 5.525761] driver_probe_device+0x60/0xc0
[ 5.529891] device_driver_attach+0x7c/0x88
[ 5.534108] __driver_attach+0x60/0xe8
[ 5.537886] bus_for_each_dev+0x7c/0xd0
[ 5.541752] driver_attach+0x2c/0x38
[ 5.545355] bus_add_driver+0x194/0x1f8
[ 5.549221] driver_register+0x6c/0x128
[ 5.553087] __platform_driver_register+0x50/0x60
[ 5.557831] gen_pci_driver_init+0x24/0x30
[ 5.561962] do_one_initcall+0x54/0x2d0
[ 5.565830] kernel_init_freeable+0x1ec/0x258
[ 5.570223] kernel_init+0x1c/0x120
[ 5.573738] ret_from_fork+0x10/0x30
[ 5.577342] Code: b5000000 52800000 b9000261 14000008 (b9400001)
[ 5.583496] ---[ end trace c0958e83ad22f359 ]---
[ 5.588152] note: swapper/0[1] exited with preempt_count 1
[ 5.593687] Kernel panic - not syncing: Attempted to kill init!
exitcode=0x0000000b
[ 5.601414] SMP: stopping secondary CPUs
[ 5.605371] Kernel Offset: disabled
[ 5.608885] CPU features: 0x00240022,61006008
[ 5.613276] Memory Limit: none
[ 5.616355] ---[ end Kernel panic - not syncing: Attempted to kill
init! exitcode=0x0000000b ]---
-michael
^ permalink raw reply
* Re: [PATCH 07/13] powerpc/xive: Add a debug_show handler to the XIVE irq_domain
From: Greg Kurz @ 2020-12-09 15:50 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: linuxppc-dev
In-Reply-To: <20201208151124.1329942-8-clg@kaod.org>
On Tue, 8 Dec 2020 16:11:18 +0100
Cédric Le Goater <clg@kaod.org> wrote:
> Full state of the Linux interrupt descriptors can be dumped under
> debugfs when compiled with CONFIG_GENERIC_IRQ_DEBUGFS. Add support for
> the XIVE interrupt controller.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> arch/powerpc/sysdev/xive/common.c | 58 +++++++++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
> index 721617f0f854..411cba12d73b 100644
> --- a/arch/powerpc/sysdev/xive/common.c
> +++ b/arch/powerpc/sysdev/xive/common.c
> @@ -1303,11 +1303,69 @@ static int xive_irq_domain_match(struct irq_domain *h, struct device_node *node,
> return xive_ops->match(node);
> }
>
> +#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
> +static const char * const esb_names[] = { "RESET", "OFF", "PENDING", "QUEUED" };
> +
> +static const struct {
> + u64 mask;
> + char *name;
> +} xive_irq_flags[] = {
> + { XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },
> + { XIVE_IRQ_FLAG_LSI, "LSI" },
> + { XIVE_IRQ_FLAG_SHIFT_BUG, "SHIFT_BUG" },
> + { XIVE_IRQ_FLAG_MASK_FW, "MASK_FW" },
> + { XIVE_IRQ_FLAG_EOI_FW, "EOI_FW" },
If seems that you don't even need these ^^ if you move this patch after
patch 11 actually.
> + { XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },
> + { XIVE_IRQ_FLAG_NO_EOI, "NO_EOI" },
> +};
> +
> +static void xive_irq_domain_debug_show(struct seq_file *m, struct irq_domain *d,
> + struct irq_data *irqd, int ind)
> +{
> + struct xive_irq_data *xd;
> + u64 val;
> + int i;
> +
> + /* No IRQ domain level information. To be done */
> + if (!irqd)
> + return;
> +
> + if (!is_xive_irq(irq_data_get_irq_chip(irqd)))
Wouldn't it be a bug to get anything else but the XIVE irqchip here ?
WARN_ON_ONCE() ?
> + return;
> +
> + seq_printf(m, "%*sXIVE:\n", ind, "");
> + ind++;
> +
> + xd = irq_data_get_irq_handler_data(irqd);
> + if (!xd) {
> + seq_printf(m, "%*snot assigned\n", ind, "");
> + return;
> + }
> +
> + val = xive_esb_read(xd, XIVE_ESB_GET);
> + seq_printf(m, "%*sESB: %s\n", ind, "", esb_names[val & 0x3]);
> + seq_printf(m, "%*sPstate: %s %s\n", ind, "", xd->stale_p ? "stale" : "",
> + xd->saved_p ? "saved" : "");
> + seq_printf(m, "%*sTarget: %d\n", ind, "", xd->target);
> + seq_printf(m, "%*sChip: %d\n", ind, "", xd->src_chip);
> + seq_printf(m, "%*sTrigger: 0x%016llx\n", ind, "", xd->trig_page);
> + seq_printf(m, "%*sEOI: 0x%016llx\n", ind, "", xd->eoi_page);
> + seq_printf(m, "%*sFlags: 0x%llx\n", ind, "", xd->flags);
> + for (i = 0; i < ARRAY_SIZE(xive_irq_flags); i++) {
> + if (xd->flags & xive_irq_flags[i].mask)
> + seq_printf(m, "%*s%s\n", ind + 12, "", xive_irq_flags[i].name);
> + }
> +}
> +#endif
> +
> static const struct irq_domain_ops xive_irq_domain_ops = {
> .match = xive_irq_domain_match,
> .map = xive_irq_domain_map,
> .unmap = xive_irq_domain_unmap,
> .xlate = xive_irq_domain_xlate,
> +#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
> + .debug_show = xive_irq_domain_debug_show,
> +#endif
> };
>
> static void __init xive_init_host(struct device_node *np)
^ permalink raw reply
* Re: [PATCH 12/13] powerpc/xive: Simplify xive_do_source_eoi()
From: Greg Kurz @ 2020-12-09 15:28 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: linuxppc-dev
In-Reply-To: <20201208151124.1329942-13-clg@kaod.org>
On Tue, 8 Dec 2020 16:11:23 +0100
Cédric Le Goater <clg@kaod.org> wrote:
> Previous patches removed the need of the first argument which was a
> hack for Firwmware EOI. Remove it and flatten the routine which has
> became simpler.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
Much nicer indeed.
Reviewed-by: Greg Kurz <groug@kaod.org>
> arch/powerpc/sysdev/xive/common.c | 72 ++++++++++++++-----------------
> 1 file changed, 33 insertions(+), 39 deletions(-)
>
> diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
> index fe6229dd3241..fb438203d5ee 100644
> --- a/arch/powerpc/sysdev/xive/common.c
> +++ b/arch/powerpc/sysdev/xive/common.c
> @@ -348,39 +348,40 @@ static void xive_do_queue_eoi(struct xive_cpu *xc)
> * EOI an interrupt at the source. There are several methods
> * to do this depending on the HW version and source type
> */
> -static void xive_do_source_eoi(u32 hw_irq, struct xive_irq_data *xd)
> +static void xive_do_source_eoi(struct xive_irq_data *xd)
> {
> + u8 eoi_val;
> +
> xd->stale_p = false;
> +
> /* If the XIVE supports the new "store EOI facility, use it */
> - if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI)
> + if (xd->flags & XIVE_IRQ_FLAG_STORE_EOI) {
> xive_esb_write(xd, XIVE_ESB_STORE_EOI, 0);
> - else {
> - u8 eoi_val;
> + return;
> + }
>
> - /*
> - * Otherwise for EOI, we use the special MMIO that does
> - * a clear of both P and Q and returns the old Q,
> - * except for LSIs where we use the "EOI cycle" special
> - * load.
> - *
> - * This allows us to then do a re-trigger if Q was set
> - * rather than synthesizing an interrupt in software
> - *
> - * For LSIs the HW EOI cycle is used rather than PQ bits,
> - * as they are automatically re-triggred in HW when still
> - * pending.
> - */
> - if (xd->flags & XIVE_IRQ_FLAG_LSI)
> - xive_esb_read(xd, XIVE_ESB_LOAD_EOI);
> - else {
> - eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
> - DBG_VERBOSE("eoi_val=%x\n", eoi_val);
> -
> - /* Re-trigger if needed */
> - if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio)
> - out_be64(xd->trig_mmio, 0);
> - }
> + /*
> + * For LSIs, we use the "EOI cycle" special load rather than
> + * PQ bits, as they are automatically re-triggered in HW when
> + * still pending.
> + */
> + if (xd->flags & XIVE_IRQ_FLAG_LSI) {
> + xive_esb_read(xd, XIVE_ESB_LOAD_EOI);
> + return;
> }
> +
> + /*
> + * Otherwise, we use the special MMIO that does a clear of
> + * both P and Q and returns the old Q. This allows us to then
> + * do a re-trigger if Q was set rather than synthesizing an
> + * interrupt in software
> + */
> + eoi_val = xive_esb_read(xd, XIVE_ESB_SET_PQ_00);
> + DBG_VERBOSE("eoi_val=%x\n", eoi_val);
> +
> + /* Re-trigger if needed */
> + if ((eoi_val & XIVE_ESB_VAL_Q) && xd->trig_mmio)
> + out_be64(xd->trig_mmio, 0);
> }
>
> /* irq_chip eoi callback, called with irq descriptor lock held */
> @@ -398,7 +399,7 @@ static void xive_irq_eoi(struct irq_data *d)
> */
> if (!irqd_irq_disabled(d) && !irqd_is_forwarded_to_vcpu(d) &&
> !(xd->flags & XIVE_IRQ_FLAG_NO_EOI))
> - xive_do_source_eoi(irqd_to_hwirq(d), xd);
> + xive_do_source_eoi(xd);
> else
> xd->stale_p = true;
>
> @@ -788,14 +789,7 @@ static int xive_irq_retrigger(struct irq_data *d)
> * 11, then perform an EOI.
> */
> xive_esb_read(xd, XIVE_ESB_SET_PQ_11);
> -
> - /*
> - * Note: We pass "0" to the hw_irq argument in order to
> - * avoid calling into the backend EOI code which we don't
> - * want to do in the case of a re-trigger. Backends typically
> - * only do EOI for LSIs anyway.
> - */
> - xive_do_source_eoi(0, xd);
> + xive_do_source_eoi(xd);
>
> return 1;
> }
> @@ -910,7 +904,7 @@ static int xive_irq_set_vcpu_affinity(struct irq_data *d, void *state)
> * while masked, the generic code will re-mask it anyway.
> */
> if (!xd->saved_p)
> - xive_do_source_eoi(hw_irq, xd);
> + xive_do_source_eoi(xd);
>
> }
> return 0;
> @@ -1054,7 +1048,7 @@ static void xive_ipi_eoi(struct irq_data *d)
> DBG_VERBOSE("IPI eoi: irq=%d [0x%lx] (HW IRQ 0x%x) pending=%02x\n",
> d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio);
>
> - xive_do_source_eoi(xc->hw_ipi, &xc->ipi_data);
> + xive_do_source_eoi(&xc->ipi_data);
> xive_do_queue_eoi(xc);
> }
>
> @@ -1443,7 +1437,7 @@ static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc)
> * still asserted. Otherwise do an MSI retrigger.
> */
> if (xd->flags & XIVE_IRQ_FLAG_LSI)
> - xive_do_source_eoi(irqd_to_hwirq(d), xd);
> + xive_do_source_eoi(xd);
> else
> xive_irq_retrigger(d);
>
^ permalink raw reply
* Re: [PATCH 07/13] powerpc/xive: Add a debug_show handler to the XIVE irq_domain
From: Cédric Le Goater @ 2020-12-09 16:04 UTC (permalink / raw)
To: Greg Kurz; +Cc: linuxppc-dev
In-Reply-To: <20201209165035.65c8a731@bahia.lan>
On 12/9/20 4:50 PM, Greg Kurz wrote:
> On Tue, 8 Dec 2020 16:11:18 +0100
> Cédric Le Goater <clg@kaod.org> wrote:
>
>> Full state of the Linux interrupt descriptors can be dumped under
>> debugfs when compiled with CONFIG_GENERIC_IRQ_DEBUGFS. Add support for
>> the XIVE interrupt controller.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> arch/powerpc/sysdev/xive/common.c | 58 +++++++++++++++++++++++++++++++
>> 1 file changed, 58 insertions(+)
>>
>> diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
>> index 721617f0f854..411cba12d73b 100644
>> --- a/arch/powerpc/sysdev/xive/common.c
>> +++ b/arch/powerpc/sysdev/xive/common.c
>> @@ -1303,11 +1303,69 @@ static int xive_irq_domain_match(struct irq_domain *h, struct device_node *node,
>> return xive_ops->match(node);
>> }
>>
>> +#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
>> +static const char * const esb_names[] = { "RESET", "OFF", "PENDING", "QUEUED" };
>> +
>> +static const struct {
>> + u64 mask;
>> + char *name;
>> +} xive_irq_flags[] = {
>> + { XIVE_IRQ_FLAG_STORE_EOI, "STORE_EOI" },
>> + { XIVE_IRQ_FLAG_LSI, "LSI" },
>
>> + { XIVE_IRQ_FLAG_SHIFT_BUG, "SHIFT_BUG" },
>> + { XIVE_IRQ_FLAG_MASK_FW, "MASK_FW" },
>> + { XIVE_IRQ_FLAG_EOI_FW, "EOI_FW" },
>
> If seems that you don't even need these ^^ if you move this patch after
> patch 11 actually.>
>
>> + { XIVE_IRQ_FLAG_H_INT_ESB, "H_INT_ESB" },
>> + { XIVE_IRQ_FLAG_NO_EOI, "NO_EOI" },
>> +};
>> +
>> +static void xive_irq_domain_debug_show(struct seq_file *m, struct irq_domain *d,
>> + struct irq_data *irqd, int ind)
>> +{
>> + struct xive_irq_data *xd;
>> + u64 val;
>> + int i;
>> +
>> + /* No IRQ domain level information. To be done */
>> + if (!irqd)
>> + return;
>> +
>> + if (!is_xive_irq(irq_data_get_irq_chip(irqd)))
>
> Wouldn't it be a bug to get anything else but the XIVE irqchip here ?
no.
> WARN_ON_ONCE() ?
XIVE IPIs are in the same domain but have a different chip.
C.
>> + return;
>> +
>> + seq_printf(m, "%*sXIVE:\n", ind, "");
>> + ind++;
>> +
>> + xd = irq_data_get_irq_handler_data(irqd);
>> + if (!xd) {
>> + seq_printf(m, "%*snot assigned\n", ind, "");
>> + return;
>> + }
>> +
>> + val = xive_esb_read(xd, XIVE_ESB_GET);
>> + seq_printf(m, "%*sESB: %s\n", ind, "", esb_names[val & 0x3]);
>> + seq_printf(m, "%*sPstate: %s %s\n", ind, "", xd->stale_p ? "stale" : "",
>> + xd->saved_p ? "saved" : "");
>> + seq_printf(m, "%*sTarget: %d\n", ind, "", xd->target);
>> + seq_printf(m, "%*sChip: %d\n", ind, "", xd->src_chip);
>> + seq_printf(m, "%*sTrigger: 0x%016llx\n", ind, "", xd->trig_page);
>> + seq_printf(m, "%*sEOI: 0x%016llx\n", ind, "", xd->eoi_page);
>> + seq_printf(m, "%*sFlags: 0x%llx\n", ind, "", xd->flags);
>> + for (i = 0; i < ARRAY_SIZE(xive_irq_flags); i++) {
>> + if (xd->flags & xive_irq_flags[i].mask)
>> + seq_printf(m, "%*s%s\n", ind + 12, "", xive_irq_flags[i].name);
>> + }
>> +}
>> +#endif
>> +
>> static const struct irq_domain_ops xive_irq_domain_ops = {
>> .match = xive_irq_domain_match,
>> .map = xive_irq_domain_map,
>> .unmap = xive_irq_domain_unmap,
>> .xlate = xive_irq_domain_xlate,
>> +#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
>> + .debug_show = xive_irq_domain_debug_show,
>> +#endif
>> };
>>
>> static void __init xive_init_host(struct device_node *np)
>
^ permalink raw reply
* Re: [PATCH 04/13] powerpc/xive: Use cpu_to_node() instead of ibm, chip-id property
From: Cédric Le Goater @ 2020-12-09 15:50 UTC (permalink / raw)
To: Aneesh Kumar K.V, linuxppc-dev
In-Reply-To: <877dpregp5.fsf@linux.ibm.com>
On 12/9/20 5:39 AM, Aneesh Kumar K.V wrote:
> Cédric Le Goater <clg@kaod.org> writes:
>
>> The 'chip_id' field of the XIVE CPU structure is used to choose a
>> target for a source located on the same chip when possible. This field
>> is assigned on the PowerNV platform using the "ibm,chip-id" property
>> on pSeries under KVM when NUMA nodes are defined but it is undefined
>> under PowerVM. The XIVE source structure has a similar field
>> 'src_chip' which is only assigned on the PowerNV platform.
>>
>> cpu_to_node() returns a compatible value on all platforms, 0 being the
>> default node. It will also give us the opportunity to set the affinity
>> of a source on pSeries when we can localize them.
>
> But we should avoid assuming that linux numa node number is equivalent
> to chip id [1].
Yes. the common layers should not make the (wrong) assumption on what a
'node_id' represents and we should provide converting routines between
both spaces, HW and logical. like we already have for CPUs, IRQ and other
entities.
'chip_id' needs a rename in some places under xive. This is the first
patch in that direction.
cpu_to_node() gives the correct value on all platforms that need it today.
Meaning : I don't know how to define nodes on PowerVM but it's not used
in the XIVE layer under pseries.
> What do we expect this value represents on virtualized platforms like
> PowerVM and KVM?
on KVM, it's relatively simple to define a machine with numa nodes and
devices (PHBs) attached to a specific node. The topology is correctly
detected by Linux. If, under the hood, the HW topology matches the logical
topology exposed to the VM, we should be able to tune affinity correctly
directly from the VM and have good results.
But our drivers are not always doing the correct thing. IRQ and PCI MSIs
will require some massaging.
I can not tell for PowerVM. I am still learning in that space.
> Is this used for a hcall?
Source configuration hcalls do not have any and this is one of the missing
bits for interrupt affinity on pSeries. We have no direct ways to link a
source with a node and to choose a suitable target.
For PHB MSIs, we could deduce the node from the PHB. For other interrupts,
we need hcall support, probably an extension of H_INT_GET_SOURCE_INFO
with a new flag to return a node id.
The XIVE interrupt controller adds extra complexity at the HW level because
interrupt routing depends on a set of tables which are allocated by the
hypervisor. For best performance, these XIVE resources should be local to
the chip which means that allocation for virtual CPUs and and virtual
interrupts should be defined carefully. that's the hypervisor business
to have a good allocation strategy when defining virtual topologies.
> [1] https://lore.kernel.org/linuxppc-dev/20200817103238.158133-1-aneesh.kumar@linux.ibm.com
Isn't this trying to solve an issue when node 0 is missing ?
Because on a 4 nodes system (with a node 0), sparse numbering is not a
problem :
# numactl -H
available: 4 nodes (0,2,4,6)
node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107
node 0 size: 32269 MB
node 0 free: 29294 MB
node 2 cpus: 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195
node 2 size: 32447 MB
node 2 free: 31982 MB
node 4 cpus: 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267
node 4 size: 32489 MB
node 4 free: 31949 MB
node 6 cpus: 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351
node 6 size: 32427 MB
node 6 free: 32024 MB
node distances:
node 0 2 4 6
0: 10 40 40 40
2: 40 10 40 40
4: 40 40 10 40
6: 40 40 40 10
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>> arch/powerpc/sysdev/xive/common.c | 7 +------
>> 1 file changed, 1 insertion(+), 6 deletions(-)
>>
>> diff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c
>> index ee375daf8114..605238ca65e4 100644
>> --- a/arch/powerpc/sysdev/xive/common.c
>> +++ b/arch/powerpc/sysdev/xive/common.c
>> @@ -1342,16 +1342,11 @@ static int xive_prepare_cpu(unsigned int cpu)
>>
>> xc = per_cpu(xive_cpu, cpu);
>> if (!xc) {
>> - struct device_node *np;
>> -
>> xc = kzalloc_node(sizeof(struct xive_cpu),
>> GFP_KERNEL, cpu_to_node(cpu));
>> if (!xc)
>> return -ENOMEM;
>> - np = of_get_cpu_node(cpu, NULL);
>> - if (np)
>> - xc->chip_id = of_get_ibm_chip_id(np);
>> - of_node_put(np);
>> + xc->chip_id = cpu_to_node(cpu);
>> xc->hw_ipi = XIVE_BAD_IRQ;
>>
>> per_cpu(xive_cpu, cpu) = xc;
>> --
>> 2.26.2
^ permalink raw reply
* [PATCH v2 3/5] powerpc/smp: Rename init_thread_group_l1_cache_map() to make it generic
From: Gautham R. Shenoy @ 2020-12-09 17:08 UTC (permalink / raw)
To: Srikar Dronamraju, Anton Blanchard, Vaidyanathan Srinivasan,
Michael Ellerman, Michael Neuling, Nicholas Piggin, Nathan Lynch,
Peter Zijlstra, Valentin Schneider
Cc: Gautham R. Shenoy, linuxppc-dev, linux-kernel
In-Reply-To: <1607533700-5546-1-git-send-email-ego@linux.vnet.ibm.com>
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
init_thread_group_l1_cache_map() initializes the per-cpu cpumask
thread_group_l1_cache_map with the core-siblings which share L1 cache
with the CPU. Make this function generic to the cache-property (L1 or
L2) and update a suitable mask. This is a preparatory patch for the
next patch where we will introduce discovery of thread-groups that
share L2-cache.
No functional change.
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
---
arch/powerpc/kernel/smp.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index f3290d5..9078b5b5 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -866,15 +866,18 @@ static struct thread_groups *__init get_thread_groups(int cpu,
return tg;
}
-static int init_thread_group_l1_cache_map(int cpu)
+static int __init init_thread_group_cache_map(int cpu, int cache_property)
{
int first_thread = cpu_first_thread_sibling(cpu);
int i, cpu_group_start = -1, err = 0;
struct thread_groups *tg = NULL;
+ cpumask_var_t *mask;
- tg = get_thread_groups(cpu, THREAD_GROUP_SHARE_L1,
- &err);
+ if (cache_property != THREAD_GROUP_SHARE_L1)
+ return -EINVAL;
+
+ tg = get_thread_groups(cpu, cache_property, &err);
if (!tg)
return err;
@@ -885,8 +888,8 @@ static int init_thread_group_l1_cache_map(int cpu)
return -ENODATA;
}
- zalloc_cpumask_var_node(&per_cpu(thread_group_l1_cache_map, cpu),
- GFP_KERNEL, cpu_to_node(cpu));
+ mask = &per_cpu(thread_group_l1_cache_map, cpu);
+ zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cpu));
for (i = first_thread; i < first_thread + threads_per_core; i++) {
int i_group_start = get_cpu_thread_group_start(i, tg);
@@ -897,7 +900,7 @@ static int init_thread_group_l1_cache_map(int cpu)
}
if (i_group_start == cpu_group_start)
- cpumask_set_cpu(i, per_cpu(thread_group_l1_cache_map, cpu));
+ cpumask_set_cpu(i, *mask);
}
return 0;
@@ -976,7 +979,7 @@ static int init_big_cores(void)
int cpu;
for_each_possible_cpu(cpu) {
- int err = init_thread_group_l1_cache_map(cpu);
+ int err = init_thread_group_cache_map(cpu, THREAD_GROUP_SHARE_L1);
if (err)
return err;
--
1.9.4
^ permalink raw reply related
* [PATCH v2 0/5] Extend Parsing "ibm, thread-groups" for Shared-L2 information
From: Gautham R. Shenoy @ 2020-12-09 17:08 UTC (permalink / raw)
To: Srikar Dronamraju, Anton Blanchard, Vaidyanathan Srinivasan,
Michael Ellerman, Michael Neuling, Nicholas Piggin, Nathan Lynch,
Peter Zijlstra, Valentin Schneider
Cc: Gautham R. Shenoy, linuxppc-dev, linux-kernel
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
Hi,
This is the v2 of the patchset to extend parsing of "ibm,thread-groups" property
to discover the Shared-L2 cache information.
The v1 can be found here :
https://lore.kernel.org/linuxppc-dev/1607057327-29822-1-git-send-email-ego@linux.vnet.ibm.com/T/#m0fabffa1ea1a2807b362f25c849bb19415216520
The key changes from v1 are as follows to incorporate the review
comments from Srikar and fix a build error on !PPC64 configs reported
by the kernel bot.
* Split Patch 1 into three patches
* First patch ensure that parse_thread_groups() is made generic to
support more than one property.
* Second patch renames cpu_l1_cache_map as
thread_group_l1_cache_map for consistency. No functional impact.
* The third patch makes init_thread_group_l1_cache_map()
generic. No functional impact.
* Patch 2 (Now patch 4): Incorporates the review comments from Srikar simplifying
the changes to update_mask_by_l2()
* Patch 3 (Now patch 5): Fix a build errors for 32-bit configs
reported by the kernel build bot.
Description of the Patchset
===========================
The "ibm,thread-groups" device-tree property is an array that is used
to indicate if groups of threads within a core share certain
properties. It provides details of which property is being shared by
which groups of threads. This array can encode information about
multiple properties being shared by different thread-groups within the
core.
Example: Suppose,
"ibm,thread-groups" = [1,2,4,8,10,12,14,9,11,13,15,2,2,4,8,10,12,14,9,11,13,15]
This can be decomposed up into two consecutive arrays:
a) [1,2,4,8,10,12,14,9,11,13,15]
b) [2,2,4,8,10,12,14,9,11,13,15]
where in,
a) provides information of Property "1" being shared by "2" groups,
each with "4" threads each. The "ibm,ppc-interrupt-server#s" of the
first group is {8,10,12,14} and the "ibm,ppc-interrupt-server#s" of
the second group is {9,11,13,15}. Property "1" is indicative of
the thread in the group sharing L1 cache, translation cache and
Instruction Data flow.
b) provides information of Property "2" being shared by "2" groups,
each group with "4" threads. The "ibm,ppc-interrupt-server#s" of
the first group is {8,10,12,14} and the
"ibm,ppc-interrupt-server#s" of the second group is
{9,11,13,15}. Property "2" indicates that the threads in each group
share the L2-cache.
The existing code assumes that the "ibm,thread-groups" encodes
information about only one property. Hence even on platforms which
encode information about multiple properties being shared by the
corresponding groups of threads, the current code will only pick the
first one. (In the above example, it will only consider
[1,2,4,8,10,12,14,9,11,13,15] but not [2,2,4,8,10,12,14,9,11,13,15]).
Furthermore, currently on platforms where groups of threads share L2
cache, we incorrectly create an extra CACHE level sched-domain that
maps to all the threads of the core.
For example, if "ibm,thread-groups" is
00000001 00000002 00000004 00000000
00000002 00000004 00000006 00000001
00000003 00000005 00000007 00000002
00000002 00000004 00000000 00000002
00000004 00000006 00000001 00000003
00000005 00000007
then, the sub-array
[00000002 00000002 00000004
00000000 00000002 00000004 00000006
00000001 00000003 00000005 00000007]
indicates that L2 (Property "2") is shared only between the threads of a single
group. There are "2" groups of threads where each group contains "4"
threads each. The groups being {0,2,4,6} and {1,3,5,7}.
However, the sched-domain hierarchy for CPUs 0,1 is
CPU0 attaching sched-domain(s):
domain-0: span=0,2,4,6 level=SMT
domain-1: span=0-7 level=CACHE
domain-2: span=0-15,24-39,48-55 level=MC
domain-3: span=0-55 level=DIE
CPU1 attaching sched-domain(s):
domain-0: span=1,3,5,7 level=SMT
domain-1: span=0-7 level=CACHE
domain-2: span=0-15,24-39,48-55 level=MC
domain-3: span=0-55 level=DIE
where the CACHE domain reports that L2 is shared across the entire
core which is incorrect on such platforms.
This patchset remedies these issues by extending the parsing support
for "ibm,thread-groups" to discover information about multiple
properties being shared by the corresponding groups of threads. In
particular we cano now detect if the groups of threads within a core
share the L2-cache. On such platforms, we populate the populating the
cpu_l2_cache_mask of every CPU to the core-siblings which share L2
with the CPU as specified in the by the "ibm,thread-groups" property
array.
With the patchset, the sched-domain hierarchy is correctly
reported. For eg for CPUs 0,1, with the patchset
CPU0 attaching sched-domain(s):
domain-0: span=0,2,4,6 level=SMT
domain-1: span=0-15,24-39,48-55 level=MC
domain-2: span=0-55 level=DIE
CPU1 attaching sched-domain(s):
domain-0: span=1,3,5,7 level=SMT
domain-1: span=0-15,24-39,48-55 level=MC
domain-2: span=0-55 level=DIE
The CACHE domain with span=0,2,4,6 for CPU 0 (span=1,3,5,7 for CPU 1
resp.) gets degenerated into the SMT domain. Furthermore, the
last-level-cache domain gets correctly set to the SMT sched-domain.
Testing
==========
With the producer-consumer
testcase(https://github.com/gautshen/misc/tree/master/producer_consumer)
where in the producer thread performs writes to 4096 random locations,
and the consumer thread subsequently reads from those 4096 random
location. We measure the time taken by the consumer to finish the 4096
reads (called an iteration of the consumer). Thus lower the value,
better is the result.
The best case occurs when the producer and consumer are affined to the
same L2 cache domain (Eg: CPU0, CPU2). On the platform with the
thread-groups sharing L2,
|-----------------------------------------------|
| Without Patch |
|-----------|-----------|-----------------------|
| Producer | Consumer | Avg time per Consumer |
| Affinity | Affinity | Iteration |
|-----------|-----------|-----------------------|
| CPU0 | CPU2 | 235us |
|-----------|-----------|-----------------------|
|Not affined|Not affined| 347us |
|-----------------------------------------------|
We see that out-of-box, the average time per consumer iteration is
higher since the tasks can be placed anywhere within the core without
them being in the L2 domain.
|-----------------------------------------------|
| With Patch |
|-----------|-----------|-----------------------|
| Producer | Consumer | Avg time per Consumer |
| Affinity | Affinity | Iteration |
|-----------|-----------|-----------------------|
| CPU0 | CPU2 | 235us |
|-----------|-----------|-----------------------|
|Not affined|Not affined| 236us |
|-----------------------------------------------|
With the patch, since the L2 domain is correctly identified, the
scheduler does the right thing by co-locating the producer and
consumer on the same L2 domain, thereby yielding the out-of-box
performance matching the best case.
Finally, this patchset reports the correct shared_cpu_map/list in the
sysfs for L2 cache on such platforms. With the patchset for CPUs0, 1,
for L2 cache we see the correct shared_cpu_map/list
/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_list:0,2,4,6
/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_map:000000,00000055
/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_list:1,3,5,7
/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_map:000000,000000aa
The patchset has been tested on older platforms which encode only the
L1 sharing information via "ibm,thread-groups" and there is no
regression found.
Gautham R. Shenoy (5):
powerpc/smp: Parse ibm,thread-groups with multiple properties
powerpc/smp: Rename cpu_l1_cache_map as thread_group_l1_cache_map
powerpc/smp: Rename init_thread_group_l1_cache_map() to make it
generic
powerpc/smp: Add support detecting thread-groups sharing L2 cache
powerpc/cacheinfo: Print correct cache-sibling map/list for L2 cache
arch/powerpc/include/asm/smp.h | 1 +
arch/powerpc/kernel/cacheinfo.c | 34 ++++--
arch/powerpc/kernel/smp.c | 241 ++++++++++++++++++++++++++++------------
3 files changed, 197 insertions(+), 79 deletions(-)
--
1.9.4
^ permalink raw reply
* [PATCH v2 5/5] powerpc/cacheinfo: Print correct cache-sibling map/list for L2 cache
From: Gautham R. Shenoy @ 2020-12-09 17:08 UTC (permalink / raw)
To: Srikar Dronamraju, Anton Blanchard, Vaidyanathan Srinivasan,
Michael Ellerman, Michael Neuling, Nicholas Piggin, Nathan Lynch,
Peter Zijlstra, Valentin Schneider
Cc: Gautham R. Shenoy, linuxppc-dev, linux-kernel
In-Reply-To: <1607533700-5546-1-git-send-email-ego@linux.vnet.ibm.com>
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
On POWER platforms where only some groups of threads within a core
share the L2-cache (indicated by the ibm,thread-groups device-tree
property), we currently print the incorrect shared_cpu_map/list for
L2-cache in the sysfs.
This patch reports the correct shared_cpu_map/list on such platforms.
Example:
On a platform with "ibm,thread-groups" set to
00000001 00000002 00000004 00000000
00000002 00000004 00000006 00000001
00000003 00000005 00000007 00000002
00000002 00000004 00000000 00000002
00000004 00000006 00000001 00000003
00000005 00000007
This indicates that threads {0,2,4,6} in the core share the L2-cache
and threads {1,3,5,7} in the core share the L2 cache.
However, without the patch, the shared_cpu_map/list for L2 for CPUs 0,
1 is reported in the sysfs as follows:
/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_list:0-7
/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_map:000000,000000ff
/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_list:0-7
/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_map:000000,000000ff
With the patch, the shared_cpu_map/list for L2 cache for CPUs 0, 1 is
correctly reported as follows:
/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_list:0,2,4,6
/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_map:000000,00000055
/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_list:1,3,5,7
/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_map:000000,000000aa
This patch adds #CONFIG_PPC64 checks for these cases to ensure that
32-bit configs build correctly.
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
---
arch/powerpc/kernel/cacheinfo.c | 34 ++++++++++++++++++++++++----------
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/kernel/cacheinfo.c b/arch/powerpc/kernel/cacheinfo.c
index 65ab9fc..cb87b68 100644
--- a/arch/powerpc/kernel/cacheinfo.c
+++ b/arch/powerpc/kernel/cacheinfo.c
@@ -641,6 +641,7 @@ static ssize_t level_show(struct kobject *k, struct kobj_attribute *attr, char *
static struct kobj_attribute cache_level_attr =
__ATTR(level, 0444, level_show, NULL);
+#ifdef CONFIG_PPC64
static unsigned int index_dir_to_cpu(struct cache_index_dir *index)
{
struct kobject *index_dir_kobj = &index->kobj;
@@ -650,16 +651,35 @@ static unsigned int index_dir_to_cpu(struct cache_index_dir *index)
return dev->id;
}
+#endif
/*
* On big-core systems, each core has two groups of CPUs each of which
* has its own L1-cache. The thread-siblings which share l1-cache with
* @cpu can be obtained via cpu_smallcore_mask().
+ *
+ * On some big-core systems, the L2 cache is shared only between some
+ * groups of siblings. This is already parsed and encoded in
+ * cpu_l2_cache_mask().
+ *
+ * TODO: cache_lookup_or_instantiate() needs to be made aware of the
+ * "ibm,thread-groups" property so that cache->shared_cpu_map
+ * reflects the correct siblings on platforms that have this
+ * device-tree property. This helper function is only a stop-gap
+ * solution so that we report the correct siblings to the
+ * userspace via sysfs.
*/
-static const struct cpumask *get_big_core_shared_cpu_map(int cpu, struct cache *cache)
+static const struct cpumask *get_shared_cpu_map(struct cache_index_dir *index, struct cache *cache)
{
- if (cache->level == 1)
- return cpu_smallcore_mask(cpu);
+#ifdef CONFIG_PPC64
+ if (has_big_cores) {
+ int cpu = index_dir_to_cpu(index);
+ if (cache->level == 1)
+ return cpu_smallcore_mask(cpu);
+ if (cache->level == 2 && thread_group_shares_l2)
+ return cpu_l2_cache_mask(cpu);
+ }
+#endif
return &cache->shared_cpu_map;
}
@@ -670,17 +690,11 @@ static const struct cpumask *get_big_core_shared_cpu_map(int cpu, struct cache *
struct cache_index_dir *index;
struct cache *cache;
const struct cpumask *mask;
- int cpu;
index = kobj_to_cache_index_dir(k);
cache = index->cache;
- if (has_big_cores) {
- cpu = index_dir_to_cpu(index);
- mask = get_big_core_shared_cpu_map(cpu, cache);
- } else {
- mask = &cache->shared_cpu_map;
- }
+ mask = get_shared_cpu_map(index, cache);
return cpumap_print_to_pagebuf(list, buf, mask);
}
--
1.9.4
^ permalink raw reply related
* [PATCH v2 4/5] powerpc/smp: Add support detecting thread-groups sharing L2 cache
From: Gautham R. Shenoy @ 2020-12-09 17:08 UTC (permalink / raw)
To: Srikar Dronamraju, Anton Blanchard, Vaidyanathan Srinivasan,
Michael Ellerman, Michael Neuling, Nicholas Piggin, Nathan Lynch,
Peter Zijlstra, Valentin Schneider
Cc: Gautham R. Shenoy, linuxppc-dev, linux-kernel
In-Reply-To: <1607533700-5546-1-git-send-email-ego@linux.vnet.ibm.com>
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
On POWER systems, groups of threads within a core sharing the L2-cache
can be indicated by the "ibm,thread-groups" property array with the
identifier "2".
This patch adds support for detecting this, and when present, populate
the populating the cpu_l2_cache_mask of every CPU to the core-siblings
which share L2 with the CPU as specified in the by the
"ibm,thread-groups" property array.
On a platform with the following "ibm,thread-group" configuration
00000001 00000002 00000004 00000000
00000002 00000004 00000006 00000001
00000003 00000005 00000007 00000002
00000002 00000004 00000000 00000002
00000004 00000006 00000001 00000003
00000005 00000007
Without this patch, the sched-domain hierarchy for CPUs 0,1 would be
CPU0 attaching sched-domain(s):
domain-0: span=0,2,4,6 level=SMT
domain-1: span=0-7 level=CACHE
domain-2: span=0-15,24-39,48-55 level=MC
domain-3: span=0-55 level=DIE
CPU1 attaching sched-domain(s):
domain-0: span=1,3,5,7 level=SMT
domain-1: span=0-7 level=CACHE
domain-2: span=0-15,24-39,48-55 level=MC
domain-3: span=0-55 level=DIE
The CACHE domain at 0-7 is incorrect since the ibm,thread-groups
sub-array
[00000002 00000002 00000004
00000000 00000002 00000004 00000006
00000001 00000003 00000005 00000007]
indicates that L2 (Property "2") is shared only between the threads of a single
group. There are "2" groups of threads where each group contains "4"
threads each. The groups being {0,2,4,6} and {1,3,5,7}.
With this patch, the sched-domain hierarchy for CPUs 0,1 would be
CPU0 attaching sched-domain(s):
domain-0: span=0,2,4,6 level=SMT
domain-1: span=0-15,24-39,48-55 level=MC
domain-2: span=0-55 level=DIE
CPU1 attaching sched-domain(s):
domain-0: span=1,3,5,7 level=SMT
domain-1: span=0-15,24-39,48-55 level=MC
domain-2: span=0-55 level=DIE
The CACHE domain with span=0,2,4,6 for CPU 0 (span=1,3,5,7 for CPU 1
resp.) gets degenerated into the SMT domain. Furthermore, the
last-level-cache domain gets correctly set to the SMT sched-domain.
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
---
arch/powerpc/include/asm/smp.h | 1 +
arch/powerpc/kernel/smp.c | 56 +++++++++++++++++++++++++++++++++++++++---
2 files changed, 53 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index b2035b2..8d3d081 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -134,6 +134,7 @@ static inline struct cpumask *cpu_smallcore_mask(int cpu)
extern int cpu_to_core_id(int cpu);
extern bool has_big_cores;
+extern bool thread_group_shares_l2;
#define cpu_smt_mask cpu_smt_mask
#ifdef CONFIG_SCHED_SMT
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 9078b5b5..a46cf3f 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -76,6 +76,7 @@
struct task_struct *secondary_current;
bool has_big_cores;
bool coregroup_enabled;
+bool thread_group_shares_l2;
DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
DEFINE_PER_CPU(cpumask_var_t, cpu_smallcore_map);
@@ -99,6 +100,7 @@ enum {
#define MAX_THREAD_LIST_SIZE 8
#define THREAD_GROUP_SHARE_L1 1
+#define THREAD_GROUP_SHARE_L2 2
struct thread_groups {
unsigned int property;
unsigned int nr_groups;
@@ -107,7 +109,7 @@ struct thread_groups {
};
/* Maximum number of properties that groups of threads within a core can share */
-#define MAX_THREAD_GROUP_PROPERTIES 1
+#define MAX_THREAD_GROUP_PROPERTIES 2
struct thread_groups_list {
unsigned int nr_properties;
@@ -121,6 +123,13 @@ struct thread_groups_list {
*/
DEFINE_PER_CPU(cpumask_var_t, thread_group_l1_cache_map);
+/*
+ * On some big-cores system, thread_group_l2_cache_map for each CPU
+ * corresponds to the set its siblings within the core that share the
+ * L2-cache.
+ */
+DEFINE_PER_CPU(cpumask_var_t, thread_group_l2_cache_map);
+
/* SMP operations for this machine */
struct smp_ops_t *smp_ops;
@@ -718,7 +727,9 @@ static void or_cpumasks_related(int i, int j, struct cpumask *(*srcmask)(int),
*
* ibm,thread-groups[i + 0] tells us the property based on which the
* threads are being grouped together. If this value is 1, it implies
- * that the threads in the same group share L1, translation cache.
+ * that the threads in the same group share L1, translation cache. If
+ * the value is 2, it implies that the threads in the same group share
+ * the same L2 cache.
*
* ibm,thread-groups[i+1] tells us how many such thread groups exist for the
* property ibm,thread-groups[i]
@@ -874,7 +885,8 @@ static int __init init_thread_group_cache_map(int cpu, int cache_property)
struct thread_groups *tg = NULL;
cpumask_var_t *mask;
- if (cache_property != THREAD_GROUP_SHARE_L1)
+ if (cache_property != THREAD_GROUP_SHARE_L1 &&
+ cache_property != THREAD_GROUP_SHARE_L2)
return -EINVAL;
tg = get_thread_groups(cpu, cache_property, &err);
@@ -888,7 +900,11 @@ static int __init init_thread_group_cache_map(int cpu, int cache_property)
return -ENODATA;
}
- mask = &per_cpu(thread_group_l1_cache_map, cpu);
+ if (cache_property == THREAD_GROUP_SHARE_L1)
+ mask = &per_cpu(thread_group_l1_cache_map, cpu);
+ else if (cache_property == THREAD_GROUP_SHARE_L2)
+ mask = &per_cpu(thread_group_l2_cache_map, cpu);
+
zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cpu));
for (i = first_thread; i < first_thread + threads_per_core; i++) {
@@ -990,6 +1006,16 @@ static int init_big_cores(void)
}
has_big_cores = true;
+
+ for_each_possible_cpu(cpu) {
+ int err = init_thread_group_cache_map(cpu, THREAD_GROUP_SHARE_L2);
+
+ if (err)
+ return err;
+ }
+
+ thread_group_shares_l2 = true;
+ pr_debug("L2 cache only shared by the threads in the small core\n");
return 0;
}
@@ -1304,6 +1330,28 @@ static bool update_mask_by_l2(int cpu, cpumask_var_t *mask)
if (has_big_cores)
submask_fn = cpu_smallcore_mask;
+ /*
+ * If the threads in a thread-group share L2 cache, then then
+ * the L2-mask can be obtained from thread_group_l2_cache_map.
+ */
+ if (thread_group_shares_l2) {
+ cpumask_set_cpu(cpu, cpu_l2_cache_mask(cpu));
+
+ for_each_cpu(i, per_cpu(thread_group_l2_cache_map, cpu)) {
+ if (cpu_online(i))
+ set_cpus_related(i, cpu, cpu_l2_cache_mask);
+ }
+
+ /* Verify that L1-cache siblings are a subset of L2 cache-siblings */
+ if (!cpumask_equal(submask_fn(cpu), cpu_l2_cache_mask(cpu)) &&
+ !cpumask_subset(submask_fn(cpu), cpu_l2_cache_mask(cpu))) {
+ pr_warn_once("CPU %d : Inconsistent L1 and L2 cache siblings\n",
+ cpu);
+ }
+
+ return true;
+ }
+
l2_cache = cpu_to_l2cache(cpu);
if (!l2_cache || !*mask) {
/* Assume only core siblings share cache with this CPU */
--
1.9.4
^ permalink raw reply related
* [PATCH v2 1/5] powerpc/smp: Parse ibm, thread-groups with multiple properties
From: Gautham R. Shenoy @ 2020-12-09 17:08 UTC (permalink / raw)
To: Srikar Dronamraju, Anton Blanchard, Vaidyanathan Srinivasan,
Michael Ellerman, Michael Neuling, Nicholas Piggin, Nathan Lynch,
Peter Zijlstra, Valentin Schneider
Cc: Gautham R. Shenoy, linuxppc-dev, linux-kernel
In-Reply-To: <1607533700-5546-1-git-send-email-ego@linux.vnet.ibm.com>
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
The "ibm,thread-groups" device-tree property is an array that is used
to indicate if groups of threads within a core share certain
properties. It provides details of which property is being shared by
which groups of threads. This array can encode information about
multiple properties being shared by different thread-groups within the
core.
Example: Suppose,
"ibm,thread-groups" = [1,2,4,8,10,12,14,9,11,13,15,2,2,4,8,10,12,14,9,11,13,15]
This can be decomposed up into two consecutive arrays:
a) [1,2,4,8,10,12,14,9,11,13,15]
b) [2,2,4,8,10,12,14,9,11,13,15]
where in,
a) provides information of Property "1" being shared by "2" groups,
each with "4" threads each. The "ibm,ppc-interrupt-server#s" of the
first group is {8,10,12,14} and the "ibm,ppc-interrupt-server#s" of
the second group is {9,11,13,15}. Property "1" is indicative of
the thread in the group sharing L1 cache, translation cache and
Instruction Data flow.
b) provides information of Property "2" being shared by "2" groups,
each group with "4" threads. The "ibm,ppc-interrupt-server#s" of
the first group is {8,10,12,14} and the
"ibm,ppc-interrupt-server#s" of the second group is
{9,11,13,15}. Property "2" indicates that the threads in each group
share the L2-cache.
The existing code assumes that the "ibm,thread-groups" encodes
information about only one property. Hence even on platforms which
encode information about multiple properties being shared by the
corresponding groups of threads, the current code will only pick the
first one. (In the above example, it will only consider
[1,2,4,8,10,12,14,9,11,13,15] but not [2,2,4,8,10,12,14,9,11,13,15]).
This patch extends the parsing support on platforms which encode
information about multiple properties being shared by the
corresponding groups of threads.
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
---
arch/powerpc/kernel/smp.c | 174 ++++++++++++++++++++++++++++++----------------
1 file changed, 113 insertions(+), 61 deletions(-)
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 8c2857c..88d88ad 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -106,6 +106,15 @@ struct thread_groups {
unsigned int thread_list[MAX_THREAD_LIST_SIZE];
};
+/* Maximum number of properties that groups of threads within a core can share */
+#define MAX_THREAD_GROUP_PROPERTIES 1
+
+struct thread_groups_list {
+ unsigned int nr_properties;
+ struct thread_groups property_tgs[MAX_THREAD_GROUP_PROPERTIES];
+};
+
+static struct thread_groups_list tgl[NR_CPUS] __initdata;
/*
* On big-cores system, cpu_l1_cache_map for each CPU corresponds to
* the set its siblings that share the L1-cache.
@@ -695,81 +704,98 @@ static void or_cpumasks_related(int i, int j, struct cpumask *(*srcmask)(int),
/*
* parse_thread_groups: Parses the "ibm,thread-groups" device tree
* property for the CPU device node @dn and stores
- * the parsed output in the thread_groups
- * structure @tg if the ibm,thread-groups[0]
- * matches @property.
+ * the parsed output in the thread_groups_list
+ * structure @tglp.
*
* @dn: The device node of the CPU device.
- * @tg: Pointer to a thread group structure into which the parsed
+ * @tglp: Pointer to a thread group list structure into which the parsed
* output of "ibm,thread-groups" is stored.
- * @property: The property of the thread-group that the caller is
- * interested in.
*
* ibm,thread-groups[0..N-1] array defines which group of threads in
* the CPU-device node can be grouped together based on the property.
*
- * ibm,thread-groups[0] tells us the property based on which the
+ * This array can represent thread groupings for multiple properties.
+ *
+ * ibm,thread-groups[i + 0] tells us the property based on which the
* threads are being grouped together. If this value is 1, it implies
* that the threads in the same group share L1, translation cache.
*
- * ibm,thread-groups[1] tells us how many such thread groups exist.
+ * ibm,thread-groups[i+1] tells us how many such thread groups exist for the
+ * property ibm,thread-groups[i]
*
- * ibm,thread-groups[2] tells us the number of threads in each such
+ * ibm,thread-groups[i+2] tells us the number of threads in each such
* group.
+ * Suppose k = (ibm,thread-groups[i+1] * ibm,thread-groups[i+2]), then,
*
- * ibm,thread-groups[3..N-1] is the list of threads identified by
+ * ibm,thread-groups[i+3..i+k+2] (is the list of threads identified by
* "ibm,ppc-interrupt-server#s" arranged as per their membership in
* the grouping.
*
- * Example: If ibm,thread-groups = [1,2,4,5,6,7,8,9,10,11,12] it
- * implies that there are 2 groups of 4 threads each, where each group
- * of threads share L1, translation cache.
+ * Example:
+ * If "ibm,thread-groups" = [1,2,4,8,10,12,14,9,11,13,15,2,2,4,8,10,12,14,9,11,13,15]
+ * This can be decomposed up into two consecutive arrays:
+ * a) [1,2,4,8,10,12,14,9,11,13,15]
+ * b) [2,2,4,8,10,12,14,9,11,13,15]
+ *
+ * where in,
+ *
+ * a) provides information of Property "1" being shared by "2" groups,
+ * each with "4" threads each. The "ibm,ppc-interrupt-server#s" of
+ * the first group is {8,10,12,14} and the
+ * "ibm,ppc-interrupt-server#s" of the second group is
+ * {9,11,13,15}. Property "1" is indicative of the thread in the
+ * group sharing L1 cache, translation cache and Instruction Data
+ * flow.
*
- * The "ibm,ppc-interrupt-server#s" of the first group is {5,6,7,8}
- * and the "ibm,ppc-interrupt-server#s" of the second group is {9, 10,
- * 11, 12} structure
+ * b) provides information of Property "2" being shared by "2" groups,
+ * each group with "4" threads. The "ibm,ppc-interrupt-server#s" of
+ * the first group is {8,10,12,14} and the
+ * "ibm,ppc-interrupt-server#s" of the second group is
+ * {9,11,13,15}. Property "2" indicates that the threads in each
+ * group share the L2-cache.
*
* Returns 0 on success, -EINVAL if the property does not exist,
* -ENODATA if property does not have a value, and -EOVERFLOW if the
* property data isn't large enough.
*/
static int parse_thread_groups(struct device_node *dn,
- struct thread_groups *tg,
- unsigned int property)
+ struct thread_groups_list *tglp)
{
- int i;
- u32 thread_group_array[3 + MAX_THREAD_LIST_SIZE];
- u32 *thread_list;
+ unsigned int property_idx = 0;
+ u32 *thread_group_array;
size_t total_threads;
- int ret;
+ int ret = 0, count;
+ u32 *thread_list;
+ int i = 0;
+ count = of_property_count_u32_elems(dn, "ibm,thread-groups");
+ thread_group_array = kcalloc(count, sizeof(u32), GFP_KERNEL);
ret = of_property_read_u32_array(dn, "ibm,thread-groups",
- thread_group_array, 3);
+ thread_group_array, count);
if (ret)
- return ret;
-
- tg->property = thread_group_array[0];
- tg->nr_groups = thread_group_array[1];
- tg->threads_per_group = thread_group_array[2];
- if (tg->property != property ||
- tg->nr_groups < 1 ||
- tg->threads_per_group < 1)
- return -ENODATA;
+ goto out_free;
- total_threads = tg->nr_groups * tg->threads_per_group;
+ while (i < count && property_idx < MAX_THREAD_GROUP_PROPERTIES) {
+ int j;
+ struct thread_groups *tg = &tglp->property_tgs[property_idx++];
- ret = of_property_read_u32_array(dn, "ibm,thread-groups",
- thread_group_array,
- 3 + total_threads);
- if (ret)
- return ret;
+ tg->property = thread_group_array[i];
+ tg->nr_groups = thread_group_array[i + 1];
+ tg->threads_per_group = thread_group_array[i + 2];
+ total_threads = tg->nr_groups * tg->threads_per_group;
- thread_list = &thread_group_array[3];
+ thread_list = &thread_group_array[i + 3];
- for (i = 0 ; i < total_threads; i++)
- tg->thread_list[i] = thread_list[i];
+ for (j = 0; j < total_threads; j++)
+ tg->thread_list[j] = thread_list[j];
+ i = i + 3 + total_threads;
+ }
- return 0;
+ tglp->nr_properties = property_idx;
+
+out_free:
+ kfree(thread_group_array);
+ return ret;
}
/*
@@ -805,50 +831,76 @@ static int get_cpu_thread_group_start(int cpu, struct thread_groups *tg)
return -1;
}
+static struct thread_groups *__init get_thread_groups(int cpu,
+ int group_property,
+ int *err)
+{
+ struct device_node *dn = of_get_cpu_node(cpu, NULL);
+ struct thread_groups_list *cpu_tgl = &tgl[cpu];
+ struct thread_groups *tg = NULL;
+ int i;
+ *err = 0;
+
+ if (!dn) {
+ *err = -ENODATA;
+ return NULL;
+ }
+
+ if (!cpu_tgl->nr_properties) {
+ *err = parse_thread_groups(dn, cpu_tgl);
+ if (*err)
+ goto out;
+ }
+
+ for (i = 0; i < cpu_tgl->nr_properties; i++) {
+ if (cpu_tgl->property_tgs[i].property == group_property) {
+ tg = &cpu_tgl->property_tgs[i];
+ break;
+ }
+ }
+
+ if (!tg)
+ *err = -EINVAL;
+out:
+ of_node_put(dn);
+ return tg;
+}
+
static int init_cpu_l1_cache_map(int cpu)
{
- struct device_node *dn = of_get_cpu_node(cpu, NULL);
- struct thread_groups tg = {.property = 0,
- .nr_groups = 0,
- .threads_per_group = 0};
int first_thread = cpu_first_thread_sibling(cpu);
int i, cpu_group_start = -1, err = 0;
+ struct thread_groups *tg = NULL;
- if (!dn)
- return -ENODATA;
-
- err = parse_thread_groups(dn, &tg, THREAD_GROUP_SHARE_L1);
- if (err)
- goto out;
+ tg = get_thread_groups(cpu, THREAD_GROUP_SHARE_L1,
+ &err);
+ if (!tg)
+ return err;
- cpu_group_start = get_cpu_thread_group_start(cpu, &tg);
+ cpu_group_start = get_cpu_thread_group_start(cpu, tg);
if (unlikely(cpu_group_start == -1)) {
WARN_ON_ONCE(1);
- err = -ENODATA;
- goto out;
+ return -ENODATA;
}
zalloc_cpumask_var_node(&per_cpu(cpu_l1_cache_map, cpu),
GFP_KERNEL, cpu_to_node(cpu));
for (i = first_thread; i < first_thread + threads_per_core; i++) {
- int i_group_start = get_cpu_thread_group_start(i, &tg);
+ int i_group_start = get_cpu_thread_group_start(i, tg);
if (unlikely(i_group_start == -1)) {
WARN_ON_ONCE(1);
- err = -ENODATA;
- goto out;
+ return -ENODATA;
}
if (i_group_start == cpu_group_start)
cpumask_set_cpu(i, per_cpu(cpu_l1_cache_map, cpu));
}
-out:
- of_node_put(dn);
- return err;
+ return 0;
}
static bool shared_caches;
--
1.9.4
^ permalink raw reply related
* [PATCH v2 2/5] powerpc/smp: Rename cpu_l1_cache_map as thread_group_l1_cache_map
From: Gautham R. Shenoy @ 2020-12-09 17:08 UTC (permalink / raw)
To: Srikar Dronamraju, Anton Blanchard, Vaidyanathan Srinivasan,
Michael Ellerman, Michael Neuling, Nicholas Piggin, Nathan Lynch,
Peter Zijlstra, Valentin Schneider
Cc: Gautham R. Shenoy, linuxppc-dev, linux-kernel
In-Reply-To: <1607533700-5546-1-git-send-email-ego@linux.vnet.ibm.com>
From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
On platforms which have the "ibm,thread-groups" property, the per-cpu
variable cpu_l1_cache_map keeps a track of which group of threads
within the same core share the L1 cache, Instruction and Data flow.
This patch renames the variable to "thread_group_l1_cache_map" to make
it consistent with a subsequent patch which will introduce
thread_group_l2_cache_map.
This patch introduces no functional change.
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
---
arch/powerpc/kernel/smp.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 88d88ad..f3290d5 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -116,10 +116,10 @@ struct thread_groups_list {
static struct thread_groups_list tgl[NR_CPUS] __initdata;
/*
- * On big-cores system, cpu_l1_cache_map for each CPU corresponds to
+ * On big-cores system, thread_group_l1_cache_map for each CPU corresponds to
* the set its siblings that share the L1-cache.
*/
-DEFINE_PER_CPU(cpumask_var_t, cpu_l1_cache_map);
+DEFINE_PER_CPU(cpumask_var_t, thread_group_l1_cache_map);
/* SMP operations for this machine */
struct smp_ops_t *smp_ops;
@@ -866,7 +866,7 @@ static struct thread_groups *__init get_thread_groups(int cpu,
return tg;
}
-static int init_cpu_l1_cache_map(int cpu)
+static int init_thread_group_l1_cache_map(int cpu)
{
int first_thread = cpu_first_thread_sibling(cpu);
@@ -885,7 +885,7 @@ static int init_cpu_l1_cache_map(int cpu)
return -ENODATA;
}
- zalloc_cpumask_var_node(&per_cpu(cpu_l1_cache_map, cpu),
+ zalloc_cpumask_var_node(&per_cpu(thread_group_l1_cache_map, cpu),
GFP_KERNEL, cpu_to_node(cpu));
for (i = first_thread; i < first_thread + threads_per_core; i++) {
@@ -897,7 +897,7 @@ static int init_cpu_l1_cache_map(int cpu)
}
if (i_group_start == cpu_group_start)
- cpumask_set_cpu(i, per_cpu(cpu_l1_cache_map, cpu));
+ cpumask_set_cpu(i, per_cpu(thread_group_l1_cache_map, cpu));
}
return 0;
@@ -976,7 +976,7 @@ static int init_big_cores(void)
int cpu;
for_each_possible_cpu(cpu) {
- int err = init_cpu_l1_cache_map(cpu);
+ int err = init_thread_group_l1_cache_map(cpu);
if (err)
return err;
@@ -1372,7 +1372,7 @@ static inline void add_cpu_to_smallcore_masks(int cpu)
cpumask_set_cpu(cpu, cpu_smallcore_mask(cpu));
- for_each_cpu(i, per_cpu(cpu_l1_cache_map, cpu)) {
+ for_each_cpu(i, per_cpu(thread_group_l1_cache_map, cpu)) {
if (cpu_online(i))
set_cpus_related(i, cpu, cpu_smallcore_mask);
}
--
1.9.4
^ permalink raw reply related
* Re: linux-next: build warning after merge of the akpm tree
From: Kees Cook @ 2020-12-09 18:56 UTC (permalink / raw)
To: Stephen Rothwell
Cc: Mathieu Malaterre, Linux Kernel Mailing List, Nicholas Piggin,
Linux Next Mailing List, Andrew Morton, PowerPC
In-Reply-To: <20201208230157.42c42789@canb.auug.org.au>
On Tue, Dec 08, 2020 at 11:01:57PM +1100, Stephen Rothwell wrote:
> Hi Stephen,
>
> On Fri, 4 Dec 2020 21:00:00 +1100 Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> >
> > Hi all,
> >
> > After merging the akpm tree, today's linux-next build (powerpc
> > allyesconfig) produced warnings like this:
> >
> > ld: warning: orphan section `.data..Lubsan_data177' from `arch/powerpc/oprofile/op_model_pa6t.o' being placed in section `.data..Lubsan_data177'
> >
> > (lots of these latter ones)
>
> 781584 of them today!
>
> > I don't know what produced these, but it is in the akpm-current or
> > akpm trees.
>
> Presumably the result of commit
>
> 186c3e18dba3 ("ubsan: enable for all*config builds")
>
> from the akpm-current tree.
>
> arch/powerpc/kernel/vmlinux.lds.S has:
>
> #ifdef CONFIG_PPC32
> .data : AT(ADDR(.data) - LOAD_OFFSET) {
> DATA_DATA
> #ifdef CONFIG_UBSAN
> *(.data..Lubsan_data*)
> *(.data..Lubsan_type*)
> #endif
> *(.data.rel*)
> *(SDATA_MAIN)
>
> added by commit
>
> beba24ac5913 ("powerpc/32: Add .data..Lubsan_data*/.data..Lubsan_type* sections explicitly")
>
> in 2018, but no equivalent for 64 bit.
>
> I will try the following patch tomorrow:
>
> From: Stephen Rothwell <sfr@canb.auug.org.au>
> Date: Tue, 8 Dec 2020 22:58:24 +1100
> Subject: [PATCH] powerpc: Add .data..Lubsan_data*/.data..Lubsan_type* sections explicitly
>
> Similarly to commit
>
> beba24ac5913 ("powerpc/32: Add .data..Lubsan_data*/.data..Lubsan_type* sections explicitly")
>
> since CONFIG_UBSAN bits can now be enabled for all*config.
>
> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
> ---
> arch/powerpc/kernel/vmlinux.lds.S | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
> index 3b4c26e94328..0318ba436f34 100644
> --- a/arch/powerpc/kernel/vmlinux.lds.S
> +++ b/arch/powerpc/kernel/vmlinux.lds.S
> @@ -296,6 +296,10 @@ SECTIONS
> #else
> .data : AT(ADDR(.data) - LOAD_OFFSET) {
> DATA_DATA
> +#ifdef CONFIG_UBSAN
> + *(.data..Lubsan_data*)
> + *(.data..Lubsan_type*)
> +#endif
> *(.data.rel*)
> *(.toc1)
> *(.branch_lt)
> --
> 2.29.2
>
> --
> Cheers,
> Stephen Rothwell
Reviewed-by: Kees Cook <keescook@chromium.org>
Thanks for figuring this one out. :) Andrew, can you add this to your
ubsan patch stack, or do you want me to resend it to you directly?
--
Kees Cook
^ permalink raw reply
* Re: [PATCH v6 0/5] PCI: Unify ECAM constants in native PCI Express drivers
From: Vladimir Oltean @ 2020-12-09 20:29 UTC (permalink / raw)
To: Michael Walle
Cc: kw, heiko, shawn.lin, Alexandru Marginean, paulus,
thomas.petazzoni, jonnyc, toan, will, robh, lorenzo.pieralisi,
michal.simek, linux-rockchip, bcm-kernel-feedback-list,
linux-arm-kernel, linux-pci, Bjorn Helgaas, rjui, f.fainelli,
linux-rpi-kernel, Jonathan.Cameron, bhelgaas, jonathan.derrick,
sbranden, wangzhou1, rrichter, linuxppc-dev, nsaenzjulienne
In-Reply-To: <c6d067abcdd5278f259bd7300730dc76@walle.cc>
On Wed, Dec 09, 2020 at 04:40:52PM +0100, Michael Walle wrote:
> Hopefully my mail client won't mess up the output that much.
I can reproduce on my LS1028A as well. The following fixes the bug for
me. I did not follow the discussion and see if it is helpful for others.
I don't understand how the bug came to be. There might be more to it
than what I'm seeing. If it's just what I'm seeing, then the patch was
pretty broken to begin with.
-----------------------------[cut here]-----------------------------
From b184da4088c9d39d25fee2486941cdf77688a409 Mon Sep 17 00:00:00 2001
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Wed, 9 Dec 2020 22:17:32 +0200
Subject: [PATCH] PCI: fix invalid window size for the ECAM config space
The blamed commit forgot that pci_ecam_create() calculates the size of
the window for the ECAM's config space based on the spacing between two
buses. The drivers whose .bus_shift from struct pci_ecam_ops was changed
to zero in this commit are now using this invalid value for bus_shift
in calculating the window size.
Before (broken):
pci_ecam_create: remapping config space from addr 0x1f0000000, bus_range 0x1, bsz 0x1
After (fixed/restored):
pci_ecam_create: remapping config space from addr 0x1f0000000, bus_range 0x1, bsz 0x100000
Fixes: f3c07cf6924e ("PCI: Unify ECAM constants in native PCI Express drivers")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/pci/ecam.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/ecam.c b/drivers/pci/ecam.c
index 59f91d434859..9fda0d49bc93 100644
--- a/drivers/pci/ecam.c
+++ b/drivers/pci/ecam.c
@@ -28,11 +28,19 @@ struct pci_config_window *pci_ecam_create(struct device *dev,
struct resource *cfgres, struct resource *busr,
const struct pci_ecam_ops *ops)
{
+ unsigned int bus_shift = ops->bus_shift;
struct pci_config_window *cfg;
unsigned int bus_range, bus_range_max, bsz;
struct resource *conflict;
int i, err;
+ /*
+ * struct pci_ecam_ops may omit specifying bus_shift
+ * if it is as per spec
+ */
+ if (!bus_shift)
+ bus_shift = PCIE_ECAM_BUS_SHIFT;
+
if (busr->start > busr->end)
return ERR_PTR(-EINVAL);
@@ -46,14 +54,14 @@ struct pci_config_window *pci_ecam_create(struct device *dev,
cfg->busr.end = busr->end;
cfg->busr.flags = IORESOURCE_BUS;
bus_range = resource_size(&cfg->busr);
- bus_range_max = resource_size(cfgres) >> ops->bus_shift;
+ bus_range_max = resource_size(cfgres) >> bus_shift;
if (bus_range > bus_range_max) {
bus_range = bus_range_max;
cfg->busr.end = busr->start + bus_range - 1;
dev_warn(dev, "ECAM area %pR can only accommodate %pR (reduced from %pR desired)\n",
cfgres, &cfg->busr, busr);
}
- bsz = 1 << ops->bus_shift;
+ bsz = 1 << bus_shift;
cfg->res.start = cfgres->start;
cfg->res.end = cfgres->end;
-----------------------------[cut here]-----------------------------
^ permalink raw reply related
* Re: [PATCH v6 0/5] PCI: Unify ECAM constants in native PCI Express drivers
From: Bjorn Helgaas @ 2020-12-09 20:59 UTC (permalink / raw)
To: Vladimir Oltean
Cc: kw, heiko, shawn.lin, Alexandru Marginean, paulus,
thomas.petazzoni, jonnyc, toan, will, robh, lorenzo.pieralisi,
michal.simek, linux-rockchip, bcm-kernel-feedback-list,
linux-arm-kernel, linux-pci, rjui, f.fainelli, linux-rpi-kernel,
Jonathan.Cameron, bhelgaas, jonathan.derrick, sbranden, wangzhou1,
Michael Walle, rrichter, linuxppc-dev, nsaenzjulienne
In-Reply-To: <20201209202904.2juzokqhleusgsts@skbuf>
On Wed, Dec 09, 2020 at 10:29:04PM +0200, Vladimir Oltean wrote:
> On Wed, Dec 09, 2020 at 04:40:52PM +0100, Michael Walle wrote:
> > Hopefully my mail client won't mess up the output that much.
>
> I can reproduce on my LS1028A as well. The following fixes the bug for
> me. I did not follow the discussion and see if it is helpful for others.
> I don't understand how the bug came to be. There might be more to it
> than what I'm seeing. If it's just what I'm seeing, then the patch was
> pretty broken to begin with.
>
> -----------------------------[cut here]-----------------------------
> From b184da4088c9d39d25fee2486941cdf77688a409 Mon Sep 17 00:00:00 2001
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
> Date: Wed, 9 Dec 2020 22:17:32 +0200
> Subject: [PATCH] PCI: fix invalid window size for the ECAM config space
>
> The blamed commit forgot that pci_ecam_create() calculates the size of
> the window for the ECAM's config space based on the spacing between two
> buses. The drivers whose .bus_shift from struct pci_ecam_ops was changed
> to zero in this commit are now using this invalid value for bus_shift
> in calculating the window size.
>
> Before (broken):
> pci_ecam_create: remapping config space from addr 0x1f0000000, bus_range 0x1, bsz 0x1
> After (fixed/restored):
> pci_ecam_create: remapping config space from addr 0x1f0000000, bus_range 0x1, bsz 0x100000
>
> Fixes: f3c07cf6924e ("PCI: Unify ECAM constants in native PCI Express drivers")
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> drivers/pci/ecam.c | 12 ++++++++++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/ecam.c b/drivers/pci/ecam.c
> index 59f91d434859..9fda0d49bc93 100644
> --- a/drivers/pci/ecam.c
> +++ b/drivers/pci/ecam.c
> @@ -28,11 +28,19 @@ struct pci_config_window *pci_ecam_create(struct device *dev,
> struct resource *cfgres, struct resource *busr,
> const struct pci_ecam_ops *ops)
> {
> + unsigned int bus_shift = ops->bus_shift;
> struct pci_config_window *cfg;
> unsigned int bus_range, bus_range_max, bsz;
> struct resource *conflict;
> int i, err;
>
> + /*
> + * struct pci_ecam_ops may omit specifying bus_shift
> + * if it is as per spec
> + */
> + if (!bus_shift)
> + bus_shift = PCIE_ECAM_BUS_SHIFT;
Yep, that's the theory. Thanks for testing it!
> if (busr->start > busr->end)
> return ERR_PTR(-EINVAL);
>
> @@ -46,14 +54,14 @@ struct pci_config_window *pci_ecam_create(struct device *dev,
> cfg->busr.end = busr->end;
> cfg->busr.flags = IORESOURCE_BUS;
> bus_range = resource_size(&cfg->busr);
> - bus_range_max = resource_size(cfgres) >> ops->bus_shift;
> + bus_range_max = resource_size(cfgres) >> bus_shift;
> if (bus_range > bus_range_max) {
> bus_range = bus_range_max;
> cfg->busr.end = busr->start + bus_range - 1;
> dev_warn(dev, "ECAM area %pR can only accommodate %pR (reduced from %pR desired)\n",
> cfgres, &cfg->busr, busr);
> }
> - bsz = 1 << ops->bus_shift;
> + bsz = 1 << bus_shift;
>
> cfg->res.start = cfgres->start;
> cfg->res.end = cfgres->end;
> -----------------------------[cut here]-----------------------------
^ permalink raw reply
* Re: [PATCH v6 0/5] PCI: Unify ECAM constants in native PCI Express drivers
From: Vladimir Oltean @ 2020-12-09 21:20 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: kw, heiko, shawn.lin, Alexandru Marginean, paulus,
thomas.petazzoni, jonnyc, toan, will, robh, lorenzo.pieralisi,
michal.simek, linux-rockchip, bcm-kernel-feedback-list,
linux-arm-kernel, linux-pci, rjui, f.fainelli, linux-rpi-kernel,
Jonathan.Cameron, bhelgaas, jonathan.derrick, sbranden, wangzhou1,
Michael Walle, rrichter, linuxppc-dev, nsaenzjulienne
In-Reply-To: <20201209205913.GA2543692@bjorn-Precision-5520>
On Wed, Dec 09, 2020 at 02:59:13PM -0600, Bjorn Helgaas wrote:
> Yep, that's the theory. Thanks for testing it!
Testing what? I'm not following.
^ permalink raw reply
* Re: [RESEND v1 5/5] powerpc/platforms: Move files from 4xx to 44x
From: kernel test robot @ 2020-12-09 21:22 UTC (permalink / raw)
To: Christophe Leroy, Benjamin Herrenschmidt, Paul Mackerras,
Michael Ellerman
Cc: linuxppc-dev, kbuild-all, linux-kernel
In-Reply-To: <5e968da2216f4d2d8da521498dad6870fcaa4e11.1607519517.git.christophe.leroy@csgroup.eu>
[-- Attachment #1: Type: text/plain, Size: 7699 bytes --]
Hi Christophe,
I love your patch! Yet something to improve:
[auto build test ERROR on powerpc/next]
[also build test ERROR on next-20201209]
[cannot apply to robh/for-next linus/master mpe/next v5.10-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Christophe-Leroy/powerpc-40x-Remove-40x-platforms/20201209-211628
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc64-randconfig-m031-20201210 (attached as .config)
compiler: powerpc-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/27cc6cb808696f690aaad90722175809739de5bc
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Christophe-Leroy/powerpc-40x-Remove-40x-platforms/20201209-211628
git checkout 27cc6cb808696f690aaad90722175809739de5bc
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=powerpc64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> arch/powerpc/platforms/44x/uic.c:275:13: error: no previous prototype for 'uic_init_tree' [-Werror=missing-prototypes]
275 | void __init uic_init_tree(void)
| ^~~~~~~~~~~~~
>> arch/powerpc/platforms/44x/uic.c:320:14: error: no previous prototype for 'uic_get_irq' [-Werror=missing-prototypes]
320 | unsigned int uic_get_irq(void)
| ^~~~~~~~~~~
cc1: all warnings being treated as errors
--
>> arch/powerpc/platforms/44x/soc.c:193:6: error: no previous prototype for 'ppc4xx_reset_system' [-Werror=missing-prototypes]
193 | void ppc4xx_reset_system(char *cmd)
| ^~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
--
>> arch/powerpc/platforms/44x/msi.c:109:6: error: no previous prototype for 'ppc4xx_teardown_msi_irqs' [-Werror=missing-prototypes]
109 | void ppc4xx_teardown_msi_irqs(struct pci_dev *dev)
| ^~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
vim +/uic_init_tree +275 arch/powerpc/platforms/44x/uic.c
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 274
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 @275 void __init uic_init_tree(void)
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 276 {
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 277 struct device_node *np;
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 278 struct uic *uic;
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 279 const u32 *interrupts;
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 280
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 281 /* First locate and initialize the top-level UIC */
26cb7d8bbddc83 arch/powerpc/sysdev/uic.c Cyrill Gorcunov 2007-11-30 282 for_each_compatible_node(np, NULL, "ibm,uic") {
12d371a69e6df9 arch/powerpc/sysdev/uic.c Stephen Rothwell 2007-04-29 283 interrupts = of_get_property(np, "interrupts", NULL);
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 284 if (!interrupts)
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 285 break;
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 286 }
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 287
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 288 BUG_ON(!np); /* uic_init_tree() assumes there's a UIC as the
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 289 * top-level interrupt controller */
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 290 primary_uic = uic_init_one(np);
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 291 if (!primary_uic)
b7c670d673d118 arch/powerpc/platforms/4xx/uic.c Rob Herring 2017-08-21 292 panic("Unable to initialize primary UIC %pOF\n", np);
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 293
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 294 irq_set_default_host(primary_uic->irqhost);
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 295 of_node_put(np);
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 296
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 297 /* The scan again for cascaded UICs */
26cb7d8bbddc83 arch/powerpc/sysdev/uic.c Cyrill Gorcunov 2007-11-30 298 for_each_compatible_node(np, NULL, "ibm,uic") {
12d371a69e6df9 arch/powerpc/sysdev/uic.c Stephen Rothwell 2007-04-29 299 interrupts = of_get_property(np, "interrupts", NULL);
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 300 if (interrupts) {
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 301 /* Secondary UIC */
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 302 int cascade_virq;
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 303
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 304 uic = uic_init_one(np);
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 305 if (! uic)
b7c670d673d118 arch/powerpc/platforms/4xx/uic.c Rob Herring 2017-08-21 306 panic("Unable to initialize a secondary UIC %pOF\n",
b7c670d673d118 arch/powerpc/platforms/4xx/uic.c Rob Herring 2017-08-21 307 np);
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 308
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 309 cascade_virq = irq_of_parse_and_map(np, 0);
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 310
ec775d0e70eb6b arch/powerpc/sysdev/uic.c Thomas Gleixner 2011-03-25 311 irq_set_handler_data(cascade_virq, uic);
ec775d0e70eb6b arch/powerpc/sysdev/uic.c Thomas Gleixner 2011-03-25 312 irq_set_chained_handler(cascade_virq, uic_irq_cascade);
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 313
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 314 /* FIXME: setup critical cascade?? */
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 315 }
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 316 }
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 317 }
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 318
ef24ba7091517d arch/powerpc/sysdev/uic.c Michael Ellerman 2016-09-06 319 /* Return an interrupt vector or 0 if no interrupt is pending. */
e58923ed14370e arch/powerpc/sysdev/uic.c David Gibson 2007-04-18 @320 unsigned int uic_get_irq(void)
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 36177 bytes --]
^ permalink raw reply
* Re: [PATCH v6 0/5] PCI: Unify ECAM constants in native PCI Express drivers
From: Bjorn Helgaas @ 2020-12-09 21:34 UTC (permalink / raw)
To: Vladimir Oltean
Cc: kw, heiko, shawn.lin, Alexandru Marginean, paulus,
thomas.petazzoni, jonnyc, toan, will, robh, lorenzo.pieralisi,
michal.simek, linux-rockchip, bcm-kernel-feedback-list,
linux-arm-kernel, linux-pci, rjui, f.fainelli, linux-rpi-kernel,
Jonathan.Cameron, bhelgaas, jonathan.derrick, sbranden, wangzhou1,
Michael Walle, rrichter, linuxppc-dev, nsaenzjulienne
In-Reply-To: <20201209212017.vx7dps3jasjcwg6j@skbuf>
On Wed, Dec 09, 2020 at 11:20:17PM +0200, Vladimir Oltean wrote:
> On Wed, Dec 09, 2020 at 02:59:13PM -0600, Bjorn Helgaas wrote:
> > Yep, that's the theory. Thanks for testing it!
>
> Testing what? I'm not following.
You posted a patch that you said fixed the bug for you. The fix is
exactly the theory we've been discussing, so you have already verified
that the theory is correct.
I'm sure Krzysztof will update his patch, and we'll get this tidied up
in -next again.
Bjorn
^ permalink raw reply
* Re: [PATCH v6 0/5] PCI: Unify ECAM constants in native PCI Express drivers
From: Vladimir Oltean @ 2020-12-09 21:43 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: kw, heiko, shawn.lin, Alexandru Marginean, paulus,
thomas.petazzoni, jonnyc, toan, will, robh, lorenzo.pieralisi,
michal.simek, linux-rockchip, bcm-kernel-feedback-list,
linux-arm-kernel, linux-pci, rjui, f.fainelli, linux-rpi-kernel,
Jonathan.Cameron, bhelgaas, jonathan.derrick, sbranden, wangzhou1,
Michael Walle, rrichter, linuxppc-dev, nsaenzjulienne
In-Reply-To: <20201209213449.GA2546712@bjorn-Precision-5520>
On Wed, Dec 09, 2020 at 03:34:49PM -0600, Bjorn Helgaas wrote:
> On Wed, Dec 09, 2020 at 11:20:17PM +0200, Vladimir Oltean wrote:
> > On Wed, Dec 09, 2020 at 02:59:13PM -0600, Bjorn Helgaas wrote:
> > > Yep, that's the theory. Thanks for testing it!
> >
> > Testing what? I'm not following.
>
> You posted a patch that you said fixed the bug for you. The fix is
> exactly the theory we've been discussing, so you have already verified
> that the theory is correct.
>
> I'm sure Krzysztof will update his patch, and we'll get this tidied up
> in -next again.
If you were discussing this already, I missed it. I was copied to this
thread out of the blue two emails ago. I also looked at the full thread
on patchwork, I don't see anything being said about the culprit being
the size of the config space mapping.
^ permalink raw reply
* Re: [PATCH v6 0/5] PCI: Unify ECAM constants in native PCI Express drivers
From: Bjorn Helgaas @ 2020-12-09 22:05 UTC (permalink / raw)
To: Vladimir Oltean
Cc: kw, heiko, shawn.lin, Alexandru Marginean, paulus,
thomas.petazzoni, jonnyc, toan, will, robh, lorenzo.pieralisi,
michal.simek, linux-rockchip, bcm-kernel-feedback-list,
linux-arm-kernel, linux-pci, rjui, f.fainelli, linux-rpi-kernel,
Jonathan.Cameron, bhelgaas, jonathan.derrick, sbranden, wangzhou1,
Michael Walle, rrichter, linuxppc-dev, nsaenzjulienne
In-Reply-To: <20201209214359.gt4wisqh65oscd4i@skbuf>
On Wed, Dec 09, 2020 at 11:43:59PM +0200, Vladimir Oltean wrote:
> On Wed, Dec 09, 2020 at 03:34:49PM -0600, Bjorn Helgaas wrote:
> > On Wed, Dec 09, 2020 at 11:20:17PM +0200, Vladimir Oltean wrote:
> > > On Wed, Dec 09, 2020 at 02:59:13PM -0600, Bjorn Helgaas wrote:
> > > > Yep, that's the theory. Thanks for testing it!
> > >
> > > Testing what? I'm not following.
> >
> > You posted a patch that you said fixed the bug for you. The fix is
> > exactly the theory we've been discussing, so you have already verified
> > that the theory is correct.
> >
> > I'm sure Krzysztof will update his patch, and we'll get this tidied up
> > in -next again.
>
> If you were discussing this already, I missed it. I was copied to this
> thread out of the blue two emails ago. I also looked at the full thread
> on patchwork, I don't see anything being said about the culprit being
> the size of the config space mapping.
Oh, sorry, this was an IRC discussion on #linux-pci (OFTC):
10:51 AM <bjorn_> so the fault is on the first read for 00:00.1. forget my noise about extracting the device/func from the *virtual* address. the *physical* address is supposed to be aligned so you can do that, but not the virtual address
10:55 AM <bjorn_> kwilczynski: oh, i think i see it: pci_ecam_create() does "bsz = 1 << ops->bus_shift", but we removed .bus_shift for this case
10:55 AM <bjorn_> needs to default to 20 if it's not specified
10:56 AM <bjorn_> result is that we only map one page of the ECAM space, so we fault when we access the second page (which is where 00:00.1 starts)
Anyway, thanks very much again for fixing this and confirming the fix!
Bjorn
^ permalink raw reply
* Re: [PATCH v2 5/5] powerpc/cacheinfo: Print correct cache-sibling map/list for L2 cache
From: kernel test robot @ 2020-12-09 23:58 UTC (permalink / raw)
To: Gautham R. Shenoy, Srikar Dronamraju, Anton Blanchard,
Vaidyanathan Srinivasan, Michael Ellerman, Michael Neuling,
Nicholas Piggin, Nathan Lynch, Peter Zijlstra, Valentin Schneider
Cc: clang-built-linux, kbuild-all, linuxppc-dev
In-Reply-To: <1607533700-5546-6-git-send-email-ego@linux.vnet.ibm.com>
[-- Attachment #1: Type: text/plain, Size: 10557 bytes --]
Hi "Gautham,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on powerpc/next]
[also build test WARNING on v5.10-rc7 next-20201209]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Gautham-R-Shenoy/Extend-Parsing-ibm-thread-groups-for-Shared-L2-information/20201210-011226
base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc64-randconfig-r031-20201209 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 1968804ac726e7674d5de22bc2204b45857da344)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install powerpc64 cross compiling tool for clang build
# apt-get install binutils-powerpc64-linux-gnu
# https://github.com/0day-ci/linux/commit/61bd9b188793d5009b5cdf310149e498264e6d57
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Gautham-R-Shenoy/Extend-Parsing-ibm-thread-groups-for-Shared-L2-information/20201210-011226
git checkout 61bd9b188793d5009b5cdf310149e498264e6d57
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=powerpc64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:125:1: note: expanded from here
__do_insb
^
arch/powerpc/include/asm/io.h:556:56: note: expanded from macro '__do_insb'
#define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from arch/powerpc/kernel/cacheinfo.c:21:
In file included from arch/powerpc/include/asm/prom.h:21:
In file included from include/linux/of_address.h:7:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:45:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(insw, (unsigned long p, void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:127:1: note: expanded from here
__do_insw
^
arch/powerpc/include/asm/io.h:557:56: note: expanded from macro '__do_insw'
#define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from arch/powerpc/kernel/cacheinfo.c:21:
In file included from arch/powerpc/include/asm/prom.h:21:
In file included from include/linux/of_address.h:7:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:47:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(insl, (unsigned long p, void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:129:1: note: expanded from here
__do_insl
^
arch/powerpc/include/asm/io.h:558:56: note: expanded from macro '__do_insl'
#define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from arch/powerpc/kernel/cacheinfo.c:21:
In file included from arch/powerpc/include/asm/prom.h:21:
In file included from include/linux/of_address.h:7:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:49:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(outsb, (unsigned long p, const void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:131:1: note: expanded from here
__do_outsb
^
arch/powerpc/include/asm/io.h:559:58: note: expanded from macro '__do_outsb'
#define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from arch/powerpc/kernel/cacheinfo.c:21:
In file included from arch/powerpc/include/asm/prom.h:21:
In file included from include/linux/of_address.h:7:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:51:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(outsw, (unsigned long p, const void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:133:1: note: expanded from here
__do_outsw
^
arch/powerpc/include/asm/io.h:560:58: note: expanded from macro '__do_outsw'
#define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
~~~~~~~~~~~~~~~~~~~~~^
In file included from arch/powerpc/kernel/cacheinfo.c:21:
In file included from arch/powerpc/include/asm/prom.h:21:
In file included from include/linux/of_address.h:7:
In file included from include/linux/io.h:13:
In file included from arch/powerpc/include/asm/io.h:619:
arch/powerpc/include/asm/io-defs.h:53:1: warning: performing pointer arithmetic on a null pointer has undefined behavior [-Wnull-pointer-arithmetic]
DEF_PCI_AC_NORET(outsl, (unsigned long p, const void *b, unsigned long c),
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/include/asm/io.h:616:3: note: expanded from macro 'DEF_PCI_AC_NORET'
__do_##name al; \
^~~~~~~~~~~~~~
<scratch space>:135:1: note: expanded from here
__do_outsl
^
arch/powerpc/include/asm/io.h:561:58: note: expanded from macro '__do_outsl'
#define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
~~~~~~~~~~~~~~~~~~~~~^
arch/powerpc/kernel/cacheinfo.c:679:28: error: use of undeclared identifier 'thread_group_shares_l2'; did you mean 'thread_group_leader'?
if (cache->level == 2 && thread_group_shares_l2)
^~~~~~~~~~~~~~~~~~~~~~
thread_group_leader
include/linux/sched/signal.h:652:20: note: 'thread_group_leader' declared here
static inline bool thread_group_leader(struct task_struct *p)
^
>> arch/powerpc/kernel/cacheinfo.c:679:28: warning: address of function 'thread_group_leader' will always evaluate to 'true' [-Wpointer-bool-conversion]
if (cache->level == 2 && thread_group_shares_l2)
~~ ^~~~~~~~~~~~~~~~~~~~~~
arch/powerpc/kernel/cacheinfo.c:679:28: note: prefix with the address-of operator to silence this warning
if (cache->level == 2 && thread_group_shares_l2)
^
&
arch/powerpc/kernel/cacheinfo.c:680:11: error: implicit declaration of function 'cpu_l2_cache_mask' [-Werror,-Wimplicit-function-declaration]
return cpu_l2_cache_mask(cpu);
^
>> arch/powerpc/kernel/cacheinfo.c:680:11: warning: incompatible integer to pointer conversion returning 'int' from a function with result type 'const struct cpumask *' [-Wint-conversion]
return cpu_l2_cache_mask(cpu);
^~~~~~~~~~~~~~~~~~~~~~
14 warnings and 2 errors generated.
vim +679 arch/powerpc/kernel/cacheinfo.c
655
656 /*
657 * On big-core systems, each core has two groups of CPUs each of which
658 * has its own L1-cache. The thread-siblings which share l1-cache with
659 * @cpu can be obtained via cpu_smallcore_mask().
660 *
661 * On some big-core systems, the L2 cache is shared only between some
662 * groups of siblings. This is already parsed and encoded in
663 * cpu_l2_cache_mask().
664 *
665 * TODO: cache_lookup_or_instantiate() needs to be made aware of the
666 * "ibm,thread-groups" property so that cache->shared_cpu_map
667 * reflects the correct siblings on platforms that have this
668 * device-tree property. This helper function is only a stop-gap
669 * solution so that we report the correct siblings to the
670 * userspace via sysfs.
671 */
672 static const struct cpumask *get_shared_cpu_map(struct cache_index_dir *index, struct cache *cache)
673 {
674 #ifdef CONFIG_PPC64
675 if (has_big_cores) {
676 int cpu = index_dir_to_cpu(index);
677 if (cache->level == 1)
678 return cpu_smallcore_mask(cpu);
> 679 if (cache->level == 2 && thread_group_shares_l2)
> 680 return cpu_l2_cache_mask(cpu);
681 }
682 #endif
683
684 return &cache->shared_cpu_map;
685 }
686
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 37110 bytes --]
^ permalink raw reply
* Re: linux-next: build warning after merge of the akpm tree
From: Michael Ellerman @ 2020-12-10 0:19 UTC (permalink / raw)
To: Stephen Rothwell
Cc: Kees Cook, Mathieu Malaterre, Linux Kernel Mailing List,
Nicholas Piggin, Linux Next Mailing List, Andrew Morton, PowerPC
In-Reply-To: <20201209180703.404eb4cb@canb.auug.org.au>
Stephen Rothwell <sfr@canb.auug.org.au> writes:
> Hi Michael,
>
> On Wed, 09 Dec 2020 15:44:35 +1100 Michael Ellerman <mpe@ellerman.id.au> wrote:
>>
>> They should really be in DATA_DATA or similar shouldn't they?
>
> No other architecture appears t need them ...
Any arch with orphan-handling=warn should see them I thought?
cheers
^ permalink raw reply
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