From: Paul Walmsley <pjw@kernel.org>
To: Himanshu Chauhan <hchauhan@ventanamicro.com>
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 2/2] riscv: Introduce support for hardware break/watchpoints
Date: Wed, 26 Nov 2025 17:49:43 -0700 (MST) [thread overview]
Message-ID: <0b77ac0f-a18f-e577-ff92-98ddd1d2bed8@kernel.org> (raw)
In-Reply-To: <20250710125231.653967-3-hchauhan@ventanamicro.com>
On Thu, 10 Jul 2025, Himanshu Chauhan wrote:
> RISC-V hardware breakpoint framework is built on top of perf subsystem
> and uses SBI debug trigger extension to
> install/uninstall/update/enable/disable hardware triggers as specified
> in Sdtrig ISA extension.
>
> Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Talking with Anup, it sounds like you're planning an updated version of
this one, so will hold off on it.
- Paul
next prev parent reply other threads:[~2025-11-27 0:49 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-10 12:52 [PATCH v1 0/2] riscv: Introduce support for hardware break/watchpoints Himanshu Chauhan
2025-07-10 12:52 ` [PATCH v1 1/2] riscv: Add SBI debug trigger extension and function ids Himanshu Chauhan
2025-11-27 0:47 ` Paul Walmsley
2025-07-10 12:52 ` [PATCH v1 2/2] riscv: Introduce support for hardware break/watchpoints Himanshu Chauhan
2025-11-27 0:49 ` Paul Walmsley [this message]
2025-11-27 10:17 ` Himanshu Chauhan
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