Re: [PATCH] mtd: spi-nor: Add 4B_OPCODES flag to n25q256a

[<Tudor.Ambarus@microchip.com>]

Hi, Daniel,

On Friday, April 17, 2020 8:46:19 PM EEST Daniel Walker wrote:
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> 
> The n25q256a supports 4-byte opcodes so lets add the flag.

This is not true for all the n25q256a flashes. SPINOR_OP_PP_4B, 
SPINOR_OP_BE_4K_4B and SPINOR_OP_SE_4B are valid just for the part numbers 
N25Q256A83ESF40x, N25Q256A83E1240x, and N25Q256A83ESFA0F.

You need to differentiate between the aforementioned flashes and the rest in 
the n25q256a, in order to add the 4-byte opcodes flag.

Cheers,
ta

> Tested on Cisco IoT platform hardware using Marvell A7040 SoC.
> 
> This patch was base on one from Guo Yi <yi.guo@cavium.com>.
> 
> Cc: xe-linux-external@cisco.com
> Signed-off-by: Daniel Walker <danielwa@cisco.com>
> ---
>  drivers/mtd/spi-nor/micron-st.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/spi-nor/micron-st.c
> b/drivers/mtd/spi-nor/micron-st.c index 6c034b9718e2..471fe2bc2ba4 100644
> --- a/drivers/mtd/spi-nor/micron-st.c
> +++ b/drivers/mtd/spi-nor/micron-st.c
> @@ -37,7 +37,7 @@ static const struct flash_info st_parts[] = {
>                                SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>         { "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K |
>                               USE_FSR | SPI_NOR_DUAL_READ |
> -                             SPI_NOR_QUAD_READ) },
> +                             SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>         { "mt25qu256a",  INFO6(0x20bb19, 0x104400, 64 * 1024,  512,
>                                SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
>                                SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> --
> 2.17.1