From: Lin Ming <ming.m.lin@intel.com>
To: Ingo Molnar <mingo@elte.hu>
Cc: Stephane Eranian <eranian@google.com>,
Peter Zijlstra <a.p.zijlstra@chello.nl>,
Andi Kleen <andi@firstfloor.org>,
lkml <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 -tip] perf: x86, add SandyBridge support
Date: Mon, 28 Feb 2011 22:02:11 +0800 [thread overview]
Message-ID: <1298901731.2169.35.camel@localhost> (raw)
In-Reply-To: <20110228090833.GA7439@elte.hu>
On Mon, 2011-02-28 at 17:08 +0800, Ingo Molnar wrote:
> * Lin Ming <ming.m.lin@intel.com> wrote:
>
> > > In other words, bit 0-3 of the umask cannot be zero.
> >
> > I got the umask from "Table 30-20. PEBS Performance Events for Intel
> > microarchitecture code name Sandy Bridge".
> >
> > But from "Table A-2. Non-Architectural Performance Events In the Processor Core
> > for Intel Core Processor 2xxx Series", the combinations are needed as you show
> > above.
> >
> > Which one is correct?
>
> Since you have access to the hardware, could you please test and see it in practice
> which one is correct?
Stephane is right, need the combination.
Sorry that I may made mistake when I tested 0xd0 pebs events.
Re-test all PEBS events, now only below 2 events need more support to
work.
PEBS_EVENT_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
PEBS_EVENT_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORE*/
>
> Thanks,
>
> Ingo
next prev parent reply other threads:[~2011-02-28 14:02 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-02-28 7:22 [PATCH v2 -tip] perf: x86, add SandyBridge support Lin Ming
2011-02-28 8:20 ` Stephane Eranian
2011-02-28 8:51 ` Lin Ming
2011-02-28 9:02 ` Stephane Eranian
2011-02-28 14:03 ` Lin Ming
2011-02-28 14:28 ` Lin Ming
2011-02-28 9:08 ` Ingo Molnar
2011-02-28 14:02 ` Lin Ming [this message]
2011-02-28 14:13 ` Stephane Eranian
2011-02-28 9:15 ` Peter Zijlstra
2011-02-28 12:25 ` Stephane Eranian
2011-02-28 14:33 ` Lin Ming
2011-02-28 14:43 ` Stephane Eranian
2011-02-28 14:52 ` Lin Ming
2011-02-28 14:55 ` Stephane Eranian
2011-02-28 14:21 ` Lin Ming
2011-02-28 14:24 ` Peter Zijlstra
2011-02-28 14:45 ` Lin Ming
2011-02-28 14:46 ` Stephane Eranian
2011-02-28 14:56 ` Lin Ming
2011-02-28 15:11 ` Peter Zijlstra
2011-03-01 0:32 ` Lin Ming
2011-03-01 7:43 ` Stephane Eranian
2011-03-01 8:21 ` Lin Ming
2011-03-01 8:45 ` Lin Ming
2011-03-01 8:57 ` Stephane Eranian
2011-03-01 9:39 ` Stephane Eranian
2011-03-01 15:07 ` Lin Ming
2011-03-01 15:09 ` Stephane Eranian
2011-03-01 15:18 ` Lin Ming
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