From: Lin Ming <ming.m.lin@intel.com>
To: Stephane Eranian <eranian@google.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>,
Ingo Molnar <mingo@elte.hu>, Andi Kleen <andi@firstfloor.org>,
lkml <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 -tip] perf: x86, add SandyBridge support
Date: Mon, 28 Feb 2011 22:52:27 +0800 [thread overview]
Message-ID: <1298904747.2169.56.camel@localhost> (raw)
In-Reply-To: <AANLkTinDBPsUaNhTOv7fgz-u3TWur08-HA3SpLt9s=BV@mail.gmail.com>
On Mon, 2011-02-28 at 22:43 +0800, Stephane Eranian wrote:
> On Mon, Feb 28, 2011 at 3:33 PM, Lin Ming <ming.m.lin@intel.com> wrote:
> > On Mon, 2011-02-28 at 20:25 +0800, Stephane Eranian wrote:
> >> On Mon, Feb 28, 2011 at 10:15 AM, Peter Zijlstra <a.p.zijlstra@chello.nl> wrote:
> >> > On Mon, 2011-02-28 at 15:22 +0800, Lin Ming wrote:
> >> >> This patch adds basic SandyBridge support, including hardware cache
> >> >> events and PEBS events support.
> >> >>
> >> >> LLC-* hareware cache events don't work for now, it depends on the
> >> >> offcore patches.
> >> >
> >> > What's the status of those, Stephane reported some problems last I
> >> > remember?
> >> >
> >> >
> >> >> #define INTEL_EVENT_CONSTRAINT(c, n) \
> >> >> EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
> >> >> +#define INTEL_EVENT_CONSTRAINT2(c, n) \
> >> >> + EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
> >> >
> >> > That's a particularly bad name, how about something like
> >> >
> >> > INTEL_UEVENT_CONSTRAINT or somesuch.
> >> >
> >> >> @@ -702,7 +738,13 @@ static void intel_ds_init(void)
> >> >> printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
> >> >> x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
> >> >> x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
> >> >> - x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
> >> >> + switch (boot_cpu_data.x86_model) {
> >> >> + case 42: /* SandyBridge */
> >> >> + x86_pmu.pebs_constraints = intel_snb_pebs_events;
> >> >> + break;
> >> >> + default:
> >> >> + x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
> >> >> + }
> >> >> break;
> >> >>
> >> >> default:
> >> >
> >> > We already have this massive model switch right after this function,
> >> > might as well move the pebs constraint assignment there.
> >> >
> >> My PEBS patch was going to cleanup this part, though it was using
> >> it's own switch
> >> statement.
> >
> > Did you send out the patch? A link?
> >
> For what?
I mean your PEBS patch to do the cleanup.
>
> >
> >
next prev parent reply other threads:[~2011-02-28 14:52 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-02-28 7:22 [PATCH v2 -tip] perf: x86, add SandyBridge support Lin Ming
2011-02-28 8:20 ` Stephane Eranian
2011-02-28 8:51 ` Lin Ming
2011-02-28 9:02 ` Stephane Eranian
2011-02-28 14:03 ` Lin Ming
2011-02-28 14:28 ` Lin Ming
2011-02-28 9:08 ` Ingo Molnar
2011-02-28 14:02 ` Lin Ming
2011-02-28 14:13 ` Stephane Eranian
2011-02-28 9:15 ` Peter Zijlstra
2011-02-28 12:25 ` Stephane Eranian
2011-02-28 14:33 ` Lin Ming
2011-02-28 14:43 ` Stephane Eranian
2011-02-28 14:52 ` Lin Ming [this message]
2011-02-28 14:55 ` Stephane Eranian
2011-02-28 14:21 ` Lin Ming
2011-02-28 14:24 ` Peter Zijlstra
2011-02-28 14:45 ` Lin Ming
2011-02-28 14:46 ` Stephane Eranian
2011-02-28 14:56 ` Lin Ming
2011-02-28 15:11 ` Peter Zijlstra
2011-03-01 0:32 ` Lin Ming
2011-03-01 7:43 ` Stephane Eranian
2011-03-01 8:21 ` Lin Ming
2011-03-01 8:45 ` Lin Ming
2011-03-01 8:57 ` Stephane Eranian
2011-03-01 9:39 ` Stephane Eranian
2011-03-01 15:07 ` Lin Ming
2011-03-01 15:09 ` Stephane Eranian
2011-03-01 15:18 ` Lin Ming
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