Re: [PATCH v2 -tip] perf: x86, add SandyBridge support

[Lin Ming <ming.m.lin@intel.com>]

On Mon, 2011-02-28 at 20:25 +0800, Stephane Eranian wrote:
> On Mon, Feb 28, 2011 at 10:15 AM, Peter Zijlstra <a.p.zijlstra@chello.nl> wrote:
> > On Mon, 2011-02-28 at 15:22 +0800, Lin Ming wrote:
> >> This patch adds basic SandyBridge support, including hardware cache
> >> events and PEBS events support.
> >>
> >> LLC-* hareware cache events don't work for now, it depends on the
> >> offcore patches.
> >
> > What's the status of those, Stephane reported some problems last I
> > remember?
> >
> >
> >>  #define INTEL_EVENT_CONSTRAINT(c, n) \
> >>       EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
> >> +#define INTEL_EVENT_CONSTRAINT2(c, n)        \
> >> +     EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
> >
> > That's a particularly bad name, how about something like
> >
> > INTEL_UEVENT_CONSTRAINT or somesuch.
> >
> >> @@ -702,7 +738,13 @@ static void intel_ds_init(void)
> >>                       printk(KERN_CONT "PEBS fmt1%c, ", pebs_type);
> >>                       x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
> >>                       x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
> >> -                     x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
> >> +                     switch (boot_cpu_data.x86_model) {
> >> +                     case 42: /* SandyBridge */
> >> +                             x86_pmu.pebs_constraints = intel_snb_pebs_events;
> >> +                             break;
> >> +                     default:
> >> +                             x86_pmu.pebs_constraints = intel_nehalem_pebs_events;
> >> +                     }
> >>                       break;
> >>
> >>               default:
> >
> > We already have this massive model switch right after this function,
> > might as well move the pebs constraint assignment there.
> >
> My PEBS  patch was going to cleanup this part, though it was using
> it's own switch
> statement.

Did you send out the patch? A link?