From: David Miller <davem@davemloft.net>
To: suresh.b.siddha@intel.com
Cc: akpm@osdl.org, hugh@veritas.com, linux-kernel@vger.kernel.org,
asit.k.mallick@intel.com
Subject: Re: [patch] mm: fix a race condition under SMC + COW
Date: Wed, 27 Sep 2006 18:55:41 -0700 (PDT) [thread overview]
Message-ID: <20060927.185541.02300409.davem@davemloft.net> (raw)
In-Reply-To: <20060927172355.B12423@unix-os.sc.intel.com>
From: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
Date: Wed, 27 Sep 2006 17:23:55 -0700
> I am flushing the pte entry in ptep_clear_flush() and it is Ok not
> to do another TLB flush after doing set_pte_at().
>
> On Sparc64, this new set_pte_at() (after ptep_clear_flush) will not batch
> any TLB flush as the previous pte contents were zero.
>
> We are Ok with this patch, isn't it?
Ok, it seems PowerPC also has the "don't do anything if previous PTE
was zero" logic. So yes, it should be ok.
next prev parent reply other threads:[~2006-09-28 1:55 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2006-09-27 22:15 [patch] mm: fix a race condition under SMC + COW Siddha, Suresh B
2006-09-27 22:54 ` David Miller
2006-09-28 0:23 ` Siddha, Suresh B
2006-09-28 1:55 ` David Miller [this message]
2006-09-28 19:39 ` Hugh Dickins
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