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From: "Siddha, Suresh B" <suresh.b.siddha@intel.com>
To: David Miller <davem@davemloft.net>
Cc: suresh.b.siddha@intel.com, akpm@osdl.org, hugh@veritas.com,
	linux-kernel@vger.kernel.org, asit.k.mallick@intel.com
Subject: Re: [patch] mm: fix a race condition under SMC + COW
Date: Wed, 27 Sep 2006 17:23:55 -0700	[thread overview]
Message-ID: <20060927172355.B12423@unix-os.sc.intel.com> (raw)
In-Reply-To: <20060927.155442.71092068.davem@davemloft.net>; from davem@davemloft.net on Wed, Sep 27, 2006 at 03:54:42PM -0700

On Wed, Sep 27, 2006 at 03:54:42PM -0700, David Miller wrote:
> You can't really do a set_pte_at() in this code path because
> there isn't a subsequent flush_tlb_*().
> 
> This is needed because some architectures queue up all set_pte_at()
> calls until the next flush_tlb_*() in order to batch TLB flushes.
> PowerPC and Sparc64 both do this.
> 
> The pte_establish() in the existing code works fine because it takes
> care of the set_pte_at() and flush_tlb_*() work internally when
> necessary on a given platform.

I am flushing the pte entry in ptep_clear_flush() and it is Ok not
to do another TLB flush after doing set_pte_at().

On Sparc64, this new set_pte_at() (after ptep_clear_flush) will not batch
any TLB flush as the previous pte contents were zero.

We are Ok with this patch, isn't it?

thanks,
suresh

  reply	other threads:[~2006-09-28  0:41 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2006-09-27 22:15 [patch] mm: fix a race condition under SMC + COW Siddha, Suresh B
2006-09-27 22:54 ` David Miller
2006-09-28  0:23   ` Siddha, Suresh B [this message]
2006-09-28  1:55     ` David Miller
2006-09-28 19:39 ` Hugh Dickins

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