From: Ingo Molnar <mingo@elte.hu>
To: Jaswinder Singh Rajput <jaswinder@kernel.org>,
Paul Mackerras <paulus@samba.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Peter Zijlstra <peterz@infradead.org>,
x86 maintainers <x86@kernel.org>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH -tip] perf_counter: Add Generalized Hardware FPU support for AMD
Date: Wed, 1 Jul 2009 00:42:20 +0200 [thread overview]
Message-ID: <20090630224220.GI1241@elte.hu> (raw)
In-Reply-To: <1246368049.3026.11.camel@hpdv5.satnam>
* Jaswinder Singh Rajput <jaswinder@kernel.org> wrote:
> > Plus things like mmx-3dnow are AMD specific, sse-sse2 is x86
> > specific. We definitely want this general table, but the events
> > should be truly general.
>
> mmx and sse are available for both Intel and AMD. Thats why I
> added both of them. Is it OK.
'3dnow' is an AMD marketing term. (and is long obsolete)
Nor did you answer (or understand) my sentence above: 'sse' is an
x86 specific term.
I think a naming and enumeration scheme around the general concept
of 'vectored co-processor' would be far less x86 specific.
Mockup:
19583739 vec-adds ( 2.01x scaled)
20856051 vec-muls ( 2.01x scaled)
20856051 vec-divs ( 2.01x scaled)
25100224054 vec-idle-cycles ( 1.99x scaled)
12540131 vec-busy-cycles ( 1.99x scaled)
42286702 vec-ops ( 2.01x scaled)
Paulus: would this categorization fit PowerPC too?
Ingo
next prev parent reply other threads:[~2009-06-30 22:42 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-06-29 9:33 [PATCH -tip] perf_counter: Add Generalized Hardware FPU support for AMD Jaswinder Singh Rajput
2009-06-30 10:11 ` Ingo Molnar
2009-06-30 13:20 ` Jaswinder Singh Rajput
2009-06-30 14:56 ` Jaswinder Singh Rajput
2009-06-30 22:42 ` Ingo Molnar [this message]
2009-06-30 23:14 ` Alan Cox
2009-07-01 12:33 ` Paul Mackerras
2009-07-01 13:12 ` Ingo Molnar
2009-07-01 13:25 ` Jaswinder Singh Rajput
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